Low-voltage band-gap reference voltage source circuit without operational amplifier

Abstract

The invention discloses a low-voltage band-gap reference voltage source circuit without an operational amplifier, and belongs to the field of electronic circuits. The circuit comprises a positive temperature coefficient current generation module, a positive temperature coefficient voltage generation module and a reference voltage synthesis module. The positive temperature coefficient current generation module generates positive temperature coefficient current; the positive temperature coefficient voltage generation module generates a first voltage in direct proportion to the temperature; and the reference voltage synthesis module generates a second voltage in direct proportion to the temperature, and adds the second voltage with the negative temperature coefficient voltage to obtain a zero temperature coefficient band-gap reference voltage. Through the structure, the temperature coefficient is effectively reduced; and a cascode current mirror is adopted, so that the power supply rejection ratio of the circuit is improved. Compared with the prior art, an operational amplifier is not adopted, and noise and power supply complexity are reduced.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a low-voltage bandgap reference voltage source circuit without an operational amplifier. Background Art

[0002] As a bias voltage source, bandgap reference voltage source is widely used in analog and mixed analog and digital chips. In order to provide low temperature coefficient and high power supply rejection ratio, bandgap reference source often uses op amp, but this increases the power consumption and complexity of the circuit and introduces greater noise. But at the same time, most op amp-free bandgap references have a higher temperature coefficient.

[0003] Since the bandgap voltage of silicon is about 1.205 V, most bandgap reference voltage sources are around 1.205 V. However, many usage scenarios require the use of low-voltage reference voltage sources, which makes it difficult for conventional bandgap reference voltage sources to meet the requirements.

[0004] Therefore, there is an urgent need for a mature low-voltage bandgap reference voltage source without an op amp, so as to obtain a low-voltage bandgap reference with a low temperature coefficient, low noise, and high power supply rejection ratio without increasing excessive power consumption and circuit complexity. Summary of the invention

[0005] The object of the present invention is to provide a low-voltage bandgap reference voltage source circuit without an operational amplifier to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a low-voltage bandgap reference voltage source circuit without an operational amplifier, comprising:

[0007] A positive temperature coefficient current generation module generates a stable current proportional to the temperature required in a bandgap reference source;

[0008] The positive temperature coefficient voltage generation module uses V at different current densities BE The difference is proportional to the absolute temperature, generating a first positive temperature coefficient voltage;

[0009] The reference voltage synthesis module uses V at different current densities BE The difference is proportional to the absolute temperature, generating a second positive temperature coefficient voltage, which is superimposed on the first positive temperature coefficient voltage to form a third temperature coefficient voltage; wherein V BE is the voltage between the base and emitter of the transistor. BE A negative temperature coefficient voltage is obtained after resistor voltage division; a reference voltage source with a temperature coefficient close to zero is obtained by adding the third positive temperature coefficient voltage to the negative temperature coefficient voltage.

[0010] In one embodiment, the positive temperature coefficient current generating module includes PMOS transistors P1-P4, NMOS transistor N1, transistor Q1, transistor Q2, resistors R1-R3, and capacitor C1;

[0011] The positive temperature coefficient voltage generating module includes PMOS tubes P5-P6, PMOS tubes P13-P17, NMOS tube N2, NMOS tubes N6-N8, transistors Q5, transistors Q6, and capacitor C3;

[0012] The reference voltage synthesis module includes PMOS tubes P7-P12, NMOS tube N4, transistors Q3-Q4, resistors R3-R4, and capacitor C2;

[0013] The source of PMOS tube P1, the source of PMOS tube P2, the source of PMOS tube P5, the source of PMOS tube P7, the source of PMOS tube P8, the source of PMOS tube P9, the source of PMOS tube P11, the source of PMOS tube P12, the source of PMOS tube P16, the source of PMOS tube P17, the drain of NMOS tube N1, and the upper plate of capacitor C1 are all connected to the power supply; the drain of PMOS tube P1 is connected to the source of PMOS tube P2, the drain of PMOS tube P2 is connected to the gate of PMOS tube P1, the gate of PMOS tube P3, the gate of PMOS tube P5, the gate of PMOS tube P9, the gate of PMOS tube P11, the gate of PMOS tube P13, and the upper plate of capacitor C1. The lower electrode plate of the transistor Q1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the gate of the PMOS transistor P2, the gate of the PMOS transistor P4, the gate of the PMOS transistor P6, the gate of the PMOS transistor P10, the gate of the PMOS transistor P12, the gate of the PMOS transistor P18, the gate of the NMOS transistor N1, and the collector of the transistor Q1, and the emitter of the transistor Q1 is connected to the first end of the resistor R2; the base of the transistor Q1 is connected to the first end of the resistor R3, the drain of the PMOS transistor P3 is connected to the source of the PMOS transistor P4, the drain of the PMOS transistor P4 is connected to the collector and base of the transistor Q2, the source of the NMOS transistor N1, and the second end of the resistor R3; the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6 The drain of PMOS tube P6 is connected to the source and gate of NMOS tube N2, the gate of NMOS tube N4, and the gate of NMOS tube N7; the gate of PMOS tube P7 is connected to the drain of PMOS tube P7 and the drain of NMOS tube N3, and the source of NMOS tube N3 is connected to the drain of NMOS tube N4; the drain of PMOS tube P8 is connected to the base of transistor Q3, the base of transistor Q4, and the first end of resistor R4, the second end of resistor R4 is connected to the first end of resistor R5 and the output terminal VREF, the second end of resistor R5 is connected to the emitter of transistor Q4, the drain of NMOS tube N5, and the upper plate of capacitor C2; the drain of PMOS tube P9 is connected to the source of PMOS tube P10, and P The drain of MOS tube P10 is connected to the collector of transistor Q3, the emitter of transistor Q3 is connected to the source of NMOS tube N5, the emitter of transistor Q6, the upper plate of capacitor C3, and the drain of NMOS tube N8; the drain of PMOS tube P11 is connected to the source of PMOS tube P12, the drain of PMOS tube P12 is connected to the collector of transistor Q4; the drain of PMOS tube P13 is connected to the source of PMOS tube P14, the drain of PMOS tube P14 is connected to the gate of NMOS tube N6 and the collector of transistor Q5; the drain of PMOS tube P15 is connected to the gate of PMOS tube P15 and the drain of NMOS tube N6, the source of NMOS tube N6 is connected to the drain of NMOS tube N7;The drain of PMOS tube P16 is connected to the base of transistor Q5 and the base of transistor Q6; the drain of PMOS tube P17 is connected to the source of PMOS tube P18, the drain of PMOS tube P18 is connected to the collector of transistor Q6, the lower plate of capacitor C3, and the gate of NMOS tube N8; the second end of resistor R2, the emitter of transistor Q2, the emitter of transistor Q5, the source of NMOS tube N2, the source of NMOS tube N4, the source of NMOS tube N7, and the source of NMOS tube N8 are grounded.;

[0014] In one embodiment, the ratio of the number of transistors Q1 and Q2 is n1:1, the ratio of the number of transistors Q4 and Q3 is n2:1, the ratio of the number of transistors Q6 and Q5 is n3:1, the ratio of the common source and common gate current mirrors P1 to P3, and the ratio of P2 to P4 are both 1:1, the ratio of the common source and common gate current mirrors P9 to P11, and the ratio of P10 to P12 are both m1:1, the ratio of the common source and common gate current mirrors P13 to P17, and the ratio of P14 to P18 are both m2:1; wherein m1, m2, n1, n2, and n3 are positive integers.

[0015] In one implementation, the transistor Q1 , the transistor Q2 , the transistor Q3 , the transistor Q4 , the transistor Q5 , and the transistor Q6 are vertical bipolar transistors.

[0016] In one implementation, the NMOS transistor N3 and the NMOS transistor N6 are inverse ratio transistors; wherein the gate length of the inverse ratio transistor is greater than its gate width.

[0017] The present invention provides a low-voltage bandgap reference voltage source circuit without an op amp. The bandgap reference circuit is designed by combining a positive temperature coefficient current generation module, a positive temperature coefficient voltage generation module and a reference voltage synthesis module. The first and second positive temperature coefficient voltages are generated on the basis of the positive temperature coefficient current generation module. The third positive temperature coefficient voltage is superimposed on the negative temperature coefficient voltage to obtain a low-voltage bandgap reference voltage source. The temperature coefficient is effectively reduced by the structure. The common source and common gate current mirror is adopted to improve the power supply rejection ratio of the circuit. Compared with the prior art, no op amp is adopted, which reduces noise and power supply complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The circuit diagram of the low voltage bandgap reference source in the present invention.

[0019] Figure 2 This is the circuit diagram of the positive temperature coefficient current generating module.

[0020] Figure 3 An illustration of the synthesis of a low voltage bandgap reference voltage source. DETAILED DESCRIPTION

[0021] The following is a further detailed description of a low-voltage bandgap reference voltage source circuit without an operational amplifier proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] The present invention provides a low-voltage bandgap reference voltage source circuit without an operational amplifier, comprising a positive temperature coefficient current generating module, a positive temperature coefficient voltage generating module, and a reference voltage synthesis module; the positive temperature coefficient current generating module is used to generate a stable current proportional to temperature (i.e., a positive temperature coefficient current) required in a bandgap reference source; the positive temperature coefficient voltage generating module utilizes V BE The difference is proportional to the absolute temperature, generating a first positive temperature coefficient voltage; the reference voltage synthesis module uses V BE The difference is proportional to the absolute temperature, generating a second positive temperature coefficient voltage, which is superimposed on the first positive temperature coefficient voltage to form a third temperature coefficient voltage. BE is the voltage between the base and emitter of the transistor. BE A negative temperature coefficient voltage is obtained after resistor voltage division; a 510mV reference voltage source with a temperature coefficient close to zero is obtained by adding the third positive temperature coefficient voltage to the negative temperature coefficient voltage.

[0023] like Figure 1 As shown, the positive temperature coefficient current generating module includes PMOS tubes P1-P4, NMOS tube N1, transistor Q1, transistor Q2, resistors R1-R3, and capacitor C1;

[0024] The positive temperature coefficient voltage generating module includes PMOS tubes P5-P6, PMOS tubes P13-P17, NMOS tube N2, NMOS tubes N6-N8, transistors Q5, transistors Q6, and capacitor C3;

[0025] The reference voltage synthesis module includes PMOS tubes P7-P12, NMOS tube N4, transistors Q3-Q4, resistors R3-R4, and capacitor C2;

[0026] The source of PMOS tube P1, the source of PMOS tube P2, the source of PMOS tube P5, the source of PMOS tube P7, the source of PMOS tube P8, the source of PMOS tube P9, the source of PMOS tube P11, the source of PMOS tube P12, the source of PMOS tube P16, the source of PMOS tube P17, the drain of NMOS tube N1, and the upper plate of capacitor C1 are all connected to the power supply; the drain of PMOS tube P1 is connected to the source of PMOS tube P2, the drain of PMOS tube P2 is connected to the gate of PMOS tube P1, the gate of PMOS tube P3, the gate of PMOS tube P5, the gate of PMOS tube P9, the gate of PMOS tube P11, the gate of PMOS tube P13, and the upper plate of capacitor C1. The lower electrode plate of the transistor Q1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the gate of the PMOS transistor P2, the gate of the PMOS transistor P4, the gate of the PMOS transistor P6, the gate of the PMOS transistor P10, the gate of the PMOS transistor P12, the gate of the PMOS transistor P18, the gate of the NMOS transistor N1, and the collector of the transistor Q1, and the emitter of the transistor Q1 is connected to the first end of the resistor R2; the base of the transistor Q1 is connected to the first end of the resistor R3, the drain of the PMOS transistor P3 is connected to the source of the PMOS transistor P4, the drain of the PMOS transistor P4 is connected to the collector and base of the transistor Q2, the source of the NMOS transistor N1, and the second end of the resistor R3; the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6 The drain of PMOS tube P6 is connected to the source and gate of NMOS tube N2, the gate of NMOS tube N4, and the gate of NMOS tube N7; the gate of PMOS tube P7 is connected to the drain of PMOS tube P7 and the drain of NMOS tube N3, and the source of NMOS tube N3 is connected to the drain of NMOS tube N4; the drain of PMOS tube P8 is connected to the base of transistor Q3, the base of transistor Q4, and the first end of resistor R4, the second end of resistor R4 is connected to the first end of resistor R5 and the output terminal VREF, the second end of resistor R5 is connected to the emitter of transistor Q4, the drain of NMOS tube N5, and the upper plate of capacitor C2; the drain of PMOS tube P9 is connected to the source of PMOS tube P10, and P The drain of MOS tube P10 is connected to the collector of transistor Q3, the emitter of transistor Q3 is connected to the source of NMOS tube N5, the emitter of transistor Q6, the upper plate of capacitor C3, and the drain of NMOS tube N8; the drain of PMOS tube P11 is connected to the source of PMOS tube P12, the drain of PMOS tube P12 is connected to the collector of transistor Q4; the drain of PMOS tube P13 is connected to the source of PMOS tube P14, the drain of PMOS tube P14 is connected to the gate of NMOS tube N6 and the collector of transistor Q5; the drain of PMOS tube P15 is connected to the gate of PMOS tube P15 and the drain of NMOS tube N6, the source of NMOS tube N6 is connected to the drain of NMOS tube N7;The drain of PMOS tube P16 is connected to the base of transistor Q5 and the base of transistor Q6; the drain of PMOS tube P17 is connected to the source of PMOS tube P18, the drain of PMOS tube P18 is connected to the collector of transistor Q6, the lower plate of capacitor C3, and the gate of NMOS tube N8; the second end of resistor R2, the emitter of transistor Q2, the emitter of transistor Q5, the source of NMOS tube N2, the source of NMOS tube N4, the source of NMOS tube N7, and the source of NMOS tube N8 are grounded.;

[0027] Transistor Q1 , transistor Q2 , transistor Q3 , transistor Q4 , transistor Q5 , and transistor Q6 are vertical bipolar transistors.

[0028] See also Figure 2 When the positive temperature coefficient current generating module is powered on, the gate voltages of the two groups of common source and common gate current mirrors PMOS tubes P1 and PMOS tubes P3, PMOS tubes P2 and PMOS tubes P4 are the same, and the source voltages of PMOS tubes P1 and PMOS tubes P3 are the same, so that PMOS tubes P1, PMOS tubes P2, PMOS tubes P3, and PMOS tubes P4 are all in the saturation region, which makes the leakage currents of PMOS tubes P1 and PMOS tubes P2 the same. Since the number of transistors of transistors Q1 and transistors Q2 is n3:1, n3 is a positive integer; the V of the transistors with different currents flowing through them BE The difference is positively correlated with the temperature, so the voltage across the resistor R2 is:

[0029]

[0030] Where V BEQ1 is the base-emitter voltage difference of transistor Q1, V BEQ2 is the base-emitter voltage difference of transistor Q2, V T is the thermal voltage, n1 is the ratio of the number of transistors in transistor Q2 to that in transistor Q1, k is the Hertzmann constant, q is the charge, and T is the thermodynamic temperature. It can be seen that the current I flowing through resistor R2 is R2 Directly proportional to temperature.

[0031] The cascode current mirror PMOS tubes P5 and PMOS tubes P7 replicate the leakage current of PMOS tube P1 at a ratio of 1:1, so that I P7 =I R2 , I P7 is the current flowing through the PMOS tube P7; similarly, the current mirror NMOS tube N7 copies the leakage current of the NMOS tube N2 at a ratio of 1:1, making I N7 =I R2 , I N7 is the current flowing through NMOS tube N7. NMOS tube N6 is an inverse ratio tube, and the current IDN7 When it is larger, NMOS tube N6 will provide negative feedback to I DN7 The PMOS tube P16 copies the leakage current of the PMOS tube P15 at a ratio of 1:1, making I DP16 =I DN7 =I R2 , I P16 ,I P18 The base currents of transistors Q3 and Q4 are equal to each other, and the emitter currents of transistors Q5 and Q6 are controlled, so that transistors Q5 and Q6 are in the amplification area. The common source and common gate current mirrors PMOS tubes P17 and PMOS tubes P18 and the common source and common gate current mirrors PMOS tubes P13 and PMOS tubes P14 proportionally copy the leakage current of PMOS tube P1, so that I DP17 =m1*I DP13 ; m1 is a positive integer; since the number of transistors of transistor Q5 and transistor Q6 is n3:1, the current ratio of transistor Q5 and transistor Q6 is 1:m1, and the V BE The difference is positively correlated with the temperature, so the leakage voltage of resistor R2 is:

[0032]

[0033] V BEQ5 is the base-emitter voltage difference of transistor Q5, V BEQ6 is the base-emitter voltage difference of transistor Q6, m2 is a positive integer; the current mirror NMOS tube N4 copies the leakage current of NMOS tube N2 at a ratio of 1:1, so that I DN4 =I R2 . NMOS tube N3 is an inverse ratio tube, to the current I DN4 When it is larger, NMOS tube N6 will provide negative feedback to I DN4 The PMOS tube P8 copies the leakage current of the PMOS tube P15 at a ratio of 1:1, making I DP8 =I DN4 =I R2 , I DP18 The current flowing to the base of transistor Q3 and transistor Q4, resistor R4 and resistor R5 controls the emitter current of transistor Q5 and transistor Q6, making transistor Q5 and transistor Q6 in the amplification area. Since resistor R4 and resistor R5 are connected in series, the output port VREF is connected between resistor R4 and resistor R5, and transistor Q4 is connected in parallel with resistor R4 and resistor R5, so:

[0034]

[0035] The cascode current mirror PMOS tubes P17, PMOS tubes P18 and the cascode current mirror PMOS tubes P13, PMOS tubes P14 proportionally replicate the leakage current of the PMOS tube P1, so that I DP11 =m2*I DP9 Since the number of transistors of transistor Q3 and transistor Q4 is n2:1, n2 is a positive integer; the current ratio of transistor Q5 and transistor Q6 is 1:m2, the V of transistors with different currents flowing through them is BE The difference is positively correlated with the temperature, so the leakage voltage of resistor R2 is:

[0036]

[0037] Combining equations (3), (4), and (5), we can get VREF as:

[0038]

[0039] In formula (7) is a negative temperature coefficient voltage, For a positive temperature coefficient voltage, set When m1*m2*n2*n3 are appropriate values, a voltage with zero temperature coefficient can be obtained. The bandgap reference voltage value obtained in the present invention is 510mV. It is 0.52, n1, n2, n3 are all 9, m1 and m2 are all 5.

[0040] The present invention uses NMOS tubes N5 and NMOS tubes N8 to be equivalent to resistors, which not only reduces the area of ​​the layout, but also prevents the resistors from competing with the current source of the same branch for the control of the current; the resistor R1 is used to provide an appropriate bias for the common source and common gate current mirror, so that the MOS tube through which the current passes is in a saturation region, which not only improves the output power supply rejection ratio, but also reduces the circuit complexity and energy consumption of the circuit; the inverse ratio tube NMOS tube N3 and NMOS tube N6 are used to make the static operating point of the circuit more stable based on negative feedback; the appropriate capacitor C2 and capacitor C3 are used to compensate the negative feedback loop in the circuit to prevent the circuit from oscillating.

[0041] Based on the above analysis, it can be known that the present invention combines a positive temperature coefficient current generation module, a positive temperature coefficient voltage generation module and a reference voltage synthesis module to design a low-voltage bandgap reference circuit. After the positive temperature coefficient current generation module generates a positive temperature coefficient current, the positive temperature coefficient voltage generation module converts the current density difference into a positive temperature coefficient voltage difference, and the reference voltage synthesis module also converts the current density difference into a positive temperature coefficient voltage difference, and after adding it to the first positive temperature coefficient voltage, it is added to the negative temperature coefficient voltage to generate a low-voltage bandgap reference voltage with a low temperature coefficient. The present invention uses a common source and common gate current mirror to improve the output power supply rejection ratio; adopts an op amp-free structure to reduce circuit complexity and power consumption, and reduce output noise.

[0042] In addition, the present invention also provides an analog chip, which includes the above bandgap reference circuit.

[0043] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low-voltage bandgap reference voltage source circuit without an operational amplifier, characterized in that: include: A positive temperature coefficient current generation module generates a stable current proportional to the temperature required in a bandgap reference source; The positive temperature coefficient voltage generation module uses V at different current densities BE The difference is proportional to the absolute temperature, generating a first positive temperature coefficient voltage; The reference voltage synthesis module uses V at different current densities BE The difference is proportional to the absolute temperature, generating a second positive temperature coefficient voltage, which is superimposed on the first positive temperature coefficient voltage to form a third temperature coefficient voltage; wherein V BE is the voltage between the base and emitter of the transistor. BE A negative temperature coefficient voltage is obtained after resistor voltage division; a reference voltage source with a temperature coefficient close to zero is obtained by adding the third positive temperature coefficient voltage to the negative temperature coefficient voltage.

2. The low-voltage bandgap reference voltage source circuit without an operational amplifier as claimed in claim 1, characterized in that: The positive temperature coefficient current generating module includes PMOS tubes P1-P4, NMOS tube N1, transistor Q1, transistor Q2, resistors R1-R3, and capacitor C1; The positive temperature coefficient voltage generating module includes PMOS tubes P5-P6, PMOS tubes P13-P17, NMOS tube N2, NMOS tubes N6-N8, transistors Q5, transistors Q6, and capacitor C3; The reference voltage synthesis module includes PMOS tubes P7-P12, NMOS tube N4, transistors Q3-Q4, resistors R3-R4, and capacitor C2; The source of PMOS tube P1, the source of PMOS tube P2, the source of PMOS tube P5, the source of PMOS tube P7, the source of PMOS tube P8, the source of PMOS tube P9, the source of PMOS tube P11, the source of PMOS tube P12, the source of PMOS tube P16, the source of PMOS tube P17, the drain of NMOS tube N1, and the upper plate of capacitor C1 are all connected to the power supply; the drain of PMOS tube P1 is connected to the source of PMOS tube P2, the drain of PMOS tube P2 is connected to the gate of PMOS tube P1, the gate of PMOS tube P3, the gate of PMOS tube P5, the gate of PMOS tube P9, the gate of PMOS tube P11, the gate of PMOS tube P13, and the upper plate of capacitor C1. The lower electrode plate of the transistor Q1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the gate of the PMOS transistor P2, the gate of the PMOS transistor P4, the gate of the PMOS transistor P6, the gate of the PMOS transistor P10, the gate of the PMOS transistor P12, the gate of the PMOS transistor P18, the gate of the NMOS transistor N1, and the collector of the transistor Q1, and the emitter of the transistor Q1 is connected to the first end of the resistor R2; the base of the transistor Q1 is connected to the first end of the resistor R3, the drain of the PMOS transistor P3 is connected to the source of the PMOS transistor P4, the drain of the PMOS transistor P4 is connected to the collector and base of the transistor Q2, the source of the NMOS transistor N1, and the second end of the resistor R3; the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6 The drain of PMOS tube P6 is connected to the source and gate of NMOS tube N2, the gate of NMOS tube N4, and the gate of NMOS tube N7; the gate of PMOS tube P7 is connected to the drain of PMOS tube P7 and the drain of NMOS tube N3, and the source of NMOS tube N3 is connected to the drain of NMOS tube N4; the drain of PMOS tube P8 is connected to the base of transistor Q3, the base of transistor Q4, and the first end of resistor R4, the second end of resistor R4 is connected to the first end of resistor R5 and the output terminal VREF, the second end of resistor R5 is connected to the emitter of transistor Q4, the drain of NMOS tube N5, and the upper plate of capacitor C2; the drain of PMOS tube P9 is connected to the source of PMOS tube P10, and P The drain of MOS tube P10 is connected to the collector of transistor Q3, the emitter of transistor Q3 is connected to the source of NMOS tube N5, the emitter of transistor Q6, the upper plate of capacitor C3, and the drain of NMOS tube N8; the drain of PMOS tube P11 is connected to the source of PMOS tube P12, the drain of PMOS tube P12 is connected to the collector of transistor Q4; the drain of PMOS tube P13 is connected to the source of PMOS tube P14, the drain of PMOS tube P14 is connected to the gate of NMOS tube N6 and the collector of transistor Q5; the drain of PMOS tube P15 is connected to the gate of PMOS tube P15 and the drain of NMOS tube N6, the source of NMOS tube N6 is connected to the drain of NMOS tube N7;The drain of PMOS tube P16 is connected to the base of transistor Q5 and the base of transistor Q6; the drain of PMOS tube P17 is connected to the source of PMOS tube P18, the drain of PMOS tube P18 is connected to the collector of transistor Q6, the lower plate of capacitor C3, and the gate of NMOS tube N8; the second end of resistor R2, the emitter of transistor Q2, the emitter of transistor Q5, the source of NMOS tube N2, the source of NMOS tube N4, the source of NMOS tube N7, and the source of NMOS tube N8 are grounded.; 3. The low-voltage bandgap reference voltage source circuit without an operational amplifier as claimed in claim 2, characterized in that: The number ratio of the transistor Q1 to the transistor Q2 is n1:1, the number ratio of the transistor Q4 to the transistor Q3 is n2:1, the number ratio of the transistor Q6 to the transistor Q5 is n3:1, the ratio of the common source and common gate current mirror P1 to P3, and the ratio of P2 to P4 are both 1:1, the ratio of the common source and common gate current mirror P9 to P11, and the ratio of P10 to P12 are both m1:1, the ratio of the common source and common gate current mirror P13 to P17, and the ratio of P14 to P18 are both m2:1; wherein m1, m2, n1, n2, and n3 are positive integers.

4. The low-voltage bandgap reference voltage source circuit without an operational amplifier as claimed in claim 2, characterized in that: The transistor Q1 , the transistor Q2 , the transistor Q3 , the transistor Q4 , the transistor Q5 , and the transistor Q6 are vertical bipolar transistors.

5. The low-voltage bandgap reference voltage source circuit without an operational amplifier as claimed in claim 2, characterized in that: The NMOS transistor N3 and the NMOS transistor N6 are inverse ratio transistors, wherein the gate length of the inverse ratio transistor is greater than its gate width.

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