Shared Buffer Data Management Method and Storage System Based on Counting Information

Abstract

The present invention provides a method for managing data in a shared buffer based on count information and a storage system. The method includes: configuring a shared buffer in the memory of a host system, where a storage device is used to perform a preset operation based on data cached in the shared buffer; obtaining count information corresponding to at least one mapping entry cached in the shared buffer; and according to the count information, retaining a target mapping entry in the at least one mapping entry in the shared buffer, or removing the target mapping entry from the shared buffer. Thus, the performance of the storage device or the entire storage system can be effectively improved on the premise of minimizing the impact on the operation efficiency of the host system itself.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and more particularly to a method for managing data in a shared buffer based on count information and a storage system. Background Art

[0002] NAND flash is a non-volatile memory technology widely used in various storage devices. It stores charge by using floating-gate transistors, and each transistor represents a storage cell. NAND flash cells usually organize data in the form of pages, each page contains multiple bytes, and multiple pages form a block. Data is read and programmed in units of pages, while the erase operation is performed in units of blocks. This organization makes NAND flash very suitable for large-capacity storage and has a relatively high write speed.

[0003] However, as the storage capacity of storage devices continues to increase, the amount of management data used to manage the storage devices also continues to increase, resulting in insufficient use of the small-capacity memory of the storage devices themselves. Summary of the Invention

[0004] The present invention provides a method for managing data in a shared buffer based on count information and a storage system, which can effectively improve the performance of a storage device or the entire storage system on the premise of minimizing the impact on the operation efficiency of the host system.

[0005] An embodiment of the present invention provides a method for managing data in a shared buffer based on count information, which is used for a storage system. The storage system includes a host system and a storage device. The host system is connected to the storage device, and the method for managing data in the shared buffer based on count information includes: configuring a shared buffer in the memory of the host system, where the storage device is used to perform a preset operation based on the data cached in the shared buffer; obtaining count information corresponding to at least one mapping table entry cached in the shared buffer; and according to the count information, retaining the target mapping table entry in the at least one mapping table entry in the shared buffer, or removing the target mapping table entry from the shared buffer.

[0006] Another embodiment of the present invention provides a storage system, which includes a host system and a storage device. The storage device is connected to the host system. The host system is used to: configure a shared buffer in the memory of the host system, where the storage device is used to perform a preset operation based on the data cached in the shared buffer; obtain count information corresponding to at least one mapping table entry cached in the shared buffer; and according to the count information, retaining the target mapping table entry in the at least one mapping table entry in the shared buffer, or removing the target mapping table entry from the shared buffer.

[0007] Based on the above, a shared buffer can be configured in the memory of the host system, and the storage device can perform a preset operation based on the data cached in the shared buffer. When the storage system operates, the count information corresponding to at least one mapping entry cached in the shared buffer can be obtained. Then, according to the count information, the target mapping entry in the at least one mapping entry can be retained in the shared buffer or removed from the shared buffer. Thus, the performance of the storage device or the entire storage system can be effectively improved on the premise of minimizing the impact on the operation efficiency of the host system itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a storage system shown according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0011] Figure 4 is a flowchart of a method for managing data in a shared buffer based on count information shown according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Figure 1 is a schematic diagram of a storage system shown according to an embodiment of the present invention. Please refer to Figure 1 , the storage system (also referred to as a data storage system) 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed on a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0014] The host system 11 includes a processor 111 and a memory 112. The processor 111 is responsible for the overall or partial operation of the host system 11. For example, the processor 111 may include a Central Processing Unit (CPU), a Graphical Processing Unit (GPU), or other programmable general-purpose or special-purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices or combinations of these devices.

[0015] The memory 112 is connected to the processor 111 and is used to cache data. For example, the memory 112 may include a Random Access Memory (RAM) or a similar volatile storage device. It should be noted that the memory 112 is provided in the host system 11 (for example, on the motherboard of the host system 11 or directly in the processor 111), rather than in the storage device 12.

[0016] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCIExpress), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions, and / or data).

[0017] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0018] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0019] The memory controller 123 may send a sequence of instructions to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a sequence of read instructions to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send a sequence of erase instructions to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 may receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0020] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0022] In an embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0023] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0024] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0025] In one embodiment, a physical unit may include one or more physical erasure units. In addition, a physical unit may include a plurality of sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0026] In one embodiment, a physical programming unit may include a plurality of physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, both the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical requirements, which are not limited in the present invention. In one embodiment, a physical programming unit may be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a writing operation) on a physical programming unit to write data into this physical programming unit, multiple memory cells in this physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to this physical programming unit to change the threshold voltage of at least some of the memory cells in this physical programming unit. For example, the threshold voltage of a memory cell can reflect the bit data stored in this memory cell.

[0028] In one embodiment, an entity erasure unit may include multiple entity programming units. The multiple entity programming units in an entity erasure unit may be synchronously erased. For example, when performing an erasure operation on an entity erasure unit, an erasure voltage may be applied to the multiple entity programming units in this entity erasure unit to change the threshold voltages of at least some of the storage units in these entity programming units. By performing an erasure operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit may be regarded as an entity block.

[0029] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any one of the entity units in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0030] In one embodiment, if a certain entity unit does not store valid data, this entity unit may be associated with the idle area 32. In addition, the entity units in the idle area 32 may be erased to clear the data in this entity unit. In one embodiment, the entity units in the idle area 32 are also referred to as idle entity units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more entity units from the idle area 32 and instruct the memory module 122 to store the data in the selected entity units. After storing the data in this entity unit, this entity unit may be associated with the data area 31. In other words, one or more entity units may be alternately used between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may configure multiple logic units 302(1) to 302(C) to map the entity units (i.e., entity units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more entity units.

[0033] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in this physical unit includes valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that this physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as the logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may, according to the information in this management table (i.e., the logical-to-physical mapping table), instruct the memory module 122 to perform operations such as data reading, writing, or erasing.

[0035] In one embodiment, the processor 111 may configure a shared buffer 101 in the memory 112. By utilizing the memory resources of the host system 11 (such as the shared buffer 101), the processor 111 provides an efficient temporary data exchange space for the storage device 12, which not only reduces the latency caused by frequent access to the flash memory but also significantly improves the performance of random read and write operations. Specifically, based on the data in the shared buffer 101, the storage device 12 can perform preset operations related to the memory module 122, such as at least one of the following operations: ① Command scheduling optimization: allowing the memory control circuit 23 to temporarily store multiple I / O requests from the host system 11 in the shared buffer 101 in advance, thereby optimizing the execution order of these requests, reducing unnecessary addressing time and page switching, and improving the overall response speed. ② Address mapping management: The shared buffer 101 can be used to store and update the logical-to-physical address mapping table (L2P Mapping Table), accelerating the process of finding the data location, especially for random read operations, and greatly improving the efficiency. And performing sorting operations on multiple mapping table entries cached in the shared buffer 101 according to a sorting algorithm to obtain a sorted queue and other operations. ③ Data caching: When reading data from the memory module 122, if the data has been loaded into the shared buffer 101, it can be directly obtained from it, avoiding accessing the slower memory module 122 again, thereby accelerating the data reading speed. Similarly, when writing new data, the data can be temporarily saved in the shared buffer 101 first, and then it is decided when and how to persist it to the memory module 122 according to the background optimization strategy. ④ Metadata processing: In addition to user data, it can also be used to cache key metadata such as the file allocation table (FAT), wear leveling information, etc., to ensure efficient data management and access patterns even under high load conditions.

[0036] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12. For example, the memory control circuit 23 may perform a handshake operation with the host system 11. The handshake operation is used to exchange information related to the establishment of the connection between the host system 11 and the storage device 12, such as clock information and / or voltage information, etc.

[0037] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12 according to the execution result of the handshake operation. Thereafter, the memory control circuit 23 may access (also referred to as visit) the shared buffer 101 through the connection.

[0038] In one embodiment, the memory control circuit 23 may store management data in the shared buffer 101. During the access to the memory module 122, the memory control circuit 23 may query or update (i.e., modify) the management data in the shared buffer 101 accordingly. For example, the management data may include part of the data in the logical-to-physical mapping table (also referred to as mapping table entries). The mapping table entries may carry mapping information (such as logical-to-physical mapping information). The mapping information may reflect the mapping relationship between at least one logical unit and at least one physical unit.

[0039] In one embodiment, when the host system 11 desires to read data belonging to a certain logical unit (also referred to as the first logical unit) from the storage device 12, the processor 111 may store the read information corresponding to the first logical unit in the shared buffer 101. For example, the read information may include a read instruction indicating to read data belonging to the first logical unit. For example, the read instruction may include a random read instruction and / or a sequential read instruction. The random read instruction is used to indicate reading data from a single logical unit or multiple discontinuous logical units. The sequential read instruction is used to indicate reading data from multiple consecutive logical units. The memory control circuit 23 may access the shared buffer 101 to obtain the read information.

[0040] After obtaining the read information, the memory control circuit 23 may confirm whether the mapping table entry related to the first logical unit has been cached in the shared buffer 101. If the mapping table entry related to the first logical unit is not cached in the shared buffer 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 into the shared buffer 101.

[0041] If the mapping table entry related to the first logical unit has been cached in the shared buffer 101 (or after loading the mapping table entry from the memory module 122 into the shared buffer 101), the memory control circuit 23 can query the mapping table entry in the shared buffer 101 to obtain the mapping relationship between the first logical unit and the physical unit (also referred to as the first physical unit) in the memory module 122. Then, the memory control circuit 23 can read data (also referred to as the first data) from the first physical unit in the memory module 122 according to this mapping relationship. Then, the memory control circuit 23 can send the read first data back to the host system 11 to respond to the read information.

[0042] In an embodiment, when the host system 11 wants to store data (also referred to as the second data) belonging to a certain logical unit (also referred to as the second logical unit) in the storage device 12, the processor 111 can store the write information corresponding to the second logical unit in the shared buffer 101. For example, the write information may include a write instruction indicating an update to the data belonging to the second logical unit. For example, the write instruction may include a random write instruction and / or a sequential write instruction. The random write instruction is used to indicate an update to the data belonging to a single logical unit or multiple non - consecutive logical units. The sequential write instruction is used to indicate an update to the data belonging to multiple consecutive logical units. The memory control circuit 23 can access the shared buffer 101 to obtain the write information.

[0043] After obtaining the write information, the memory control circuit 23 can store the second data in the physical unit (also referred to as the second physical unit) in the memory module 122 according to the write information. On the other hand, the memory control circuit 23 can confirm whether the mapping table entry related to the second logical unit has been cached in the shared buffer 101. If the mapping table entry related to the second logical unit has not been cached in the shared buffer 101, the memory control circuit 23 can load the mapping table entry from the memory module 122 into the shared buffer 101. If the mapping table entry related to the second logical unit has been cached in the shared buffer 101 (or after loading the mapping table entry from the memory module 122 into the shared buffer 101), the memory control circuit 23 can update the mapping table entry in the shared buffer 101 to establish the mapping relationship between the second logical unit and the second physical unit. Then, the memory control circuit 23 can notify the host system 11 that the write operation is completed to respond to the write information.

[0044] In one embodiment, the memory control circuit 23 may also store other types of management data in the shared buffer 101 (e.g., loaded from the memory module 122 into the shared buffer 101). For example, the management data may include valid count management data, wear leveling management data, or bad block management data, etc., which are not limited in the present invention. The valid count management data is used to manage the valid data storage status of at least some physical units in the memory module 122. For example, the valid count management data may include valid counts corresponding to at least one physical unit in the memory module 122. The wear leveling management data is used to manage the wear status of at least some physical units in the memory module 122. For example, the wear leveling management data may include read counts, write counts, and / or erase counts corresponding to at least one physical unit in the memory module 122. The bad block management data is used to manage the damaged physical units (also referred to as bad blocks) in the memory module 122. For example, the bad block management data can be used to mark at least one physical unit in the memory module 122 as a bad block. Thereafter, the memory control circuit 23 can access or manage the memory module 122 according to the management data in the shared buffer 101.

[0045] It should be noted that the shared buffer 101 provided in the memory 112 occupies a part of the storage space of the memory 112, resulting in a reduction in the capacity of the memory 112 available for the host system 11 itself. For example, after the shared buffer 101 is set, the remaining capacity of the memory 112 after deducting the shared buffer 101 is the memory space available for the host system 11 itself. Therefore, if the capacity of the shared buffer 101 is larger, it may lead to a reduction in the operating efficiency of the host system 11 itself (due to the reduction in the memory space available for the host system 11 itself). However, if the capacity of the shared buffer 101 is too small, it may reduce the performance of the storage device 12 (due to the reduction in the memory space available for the storage device 12).

[0046] According to the technical solution provided by the embodiment of the present invention, it is possible to achieve fine management of the mapping table entries resident in the shared buffer 101, including but not limited to operations such as sorting, adding, and removing, while maintaining a relatively small capacity configuration of the shared buffer 101 (including but not limited to reducing its capacity requirements). In this way, on the basis of ensuring that the operating efficiency of the host system 11 is not disturbed, the performance of the storage device 12 and even the entire storage system 10 is further enhanced, achieving the best balance between the processing ability of the host system 11 and the response speed of the storage device 12, and ensuring that both can operate in an ideal state without affecting each other.

[0047] In particular, this solution is especially applicable to scenarios where random read and write performance needs to be improved. Traditionally, in order to maximize the efficiency of random read and write, in theory, all mapping table entries should be loaded into the cache memory 24. However, under the limitations of current product designs - for example, the cache memory 24 usually has a fixed capacity of 256 KB, while the data volume of the mapping table entries may reach 1 GB or more (taking a 1 TB capacity as an example), making it impossible to load all mapping table entries at once, resulting in the need to frequently load mapping table entries in batches, thus increasing latency and affecting the read speed of the storage device 12. By using the shared buffer 101 to efficiently manage these mapping table entries, not only is this challenge solved, but also independent and non-interfering optimization of the performance of the host system 11 and the storage device 12 is achieved.

[0048] Specifically, this solution allows the storage system 10 to maintain high-speed data access speed and low-latency characteristics when processing a large number of mapping table entries, thus ensuring the performance metrics of random read and write. At the same time, it also avoids the cost increase caused by adding additional hardware resources, as well as problems such as increased system complexity and decreased stability that may be caused. In short, this innovative technical solution provides a feasible and efficient way to address the challenges of high-performance storage systems.

[0049] In one embodiment, one or more mapping table entries can be cached in the shared buffer 101. After the memory control circuit 23 caches at least one mapping table entry in the shared buffer 101, the processor 111 can obtain the count information corresponding to the at least one mapping table entry. For example, the count information can reflect the number of times, frequency, or time points at which the at least one mapping table entry has been accessed (also known as read or written) in the past period of time. Subsequently, the processor 111 can, based on the count information, retain at least one mapping table entry (also known as the target mapping table entry) in the shared buffer 101, or remove the target mapping table entry from the shared buffer 101.

[0050] In one embodiment, the processor 111 can configure at least one counter for each mapping table entry in the shared buffer 101. The processor 111 can obtain the count information corresponding to each mapping table entry based on the output of the counter.

[0051] In one embodiment, the counting information includes counting information corresponding to a target mapping entry (also referred to as target counting information). For example, the target counting information may reflect the number of times, frequency, or time points at which the target mapping entry has been accessed over a past period of time. For example, the processor 111 may monitor the access status of the target mapping entry cached in the shared buffer 101 over a past period of time to obtain a monitoring result. For example, this monitoring result may reflect the access status of the target mapping entry cached in the shared buffer 101 over a past period of time. Then, the processor 111 may update the target counting information based on this monitoring result.

[0052] In one embodiment, in response to each access of the target mapping entry, the processor 111 may correspondingly update the target counting information. The updated target counting information may reflect the latest access status of the target mapping entry cached in the shared buffer 101 currently or over a past period of time (e.g., the latest number of times the target mapping entry has been accessed, the latest access frequency, or the latest access time point).

[0053] In one embodiment, the processor 111 may determine whether the target counting information meets a preset condition. If the target counting information meets the preset condition, the processor 111 may determine that the target mapping entry belongs to a certain type of mapping entry (also referred to as the first mapping entry). However, if the target counting information does not meet the preset condition, the processor 111 may determine that the target mapping entry belongs to another type of mapping entry (also referred to as the second mapping entry). Thereafter, when data is to be removed from the shared buffer 101, compared with the first mapping entry, the processor 111 may preferentially remove the second mapping entry from the shared buffer 101.

[0054] In one embodiment, the target counting information may include one or more count values. This count value may reflect the number of times, frequency, or time points at which the target mapping entry has been accessed over a past period of time. In one embodiment, this count value may be positively correlated with the number of times and / or frequency at which the target mapping entry has been accessed over a past period of time. That is, if this count value is larger, it indicates that the number of times the target mapping entry has been accessed and / or the frequency are higher over a past period of time. Alternatively, in one embodiment, this count value may also be negatively correlated with the number of times and / or frequency at which the target mapping entry has been accessed over a past period of time.

[0055] In one embodiment, this count value may be positively correlated with the time difference between the time point of the latest access of the target mapping entry over a past period of time and the current system time. That is, if this count value is larger, it indicates that the time point of the latest access of the target mapping entry over a past period of time is farther from the current system time. Alternatively, in one embodiment, this count value may also be negatively correlated with the time difference between the time point of the latest access of the target mapping entry over a past period of time and the current system time.

[0056] In one embodiment, the processor 111 may compare the count value with a preset value to obtain a comparison result. Then, the processor 111 may determine whether the target count information meets the preset condition according to the comparison result.

[0057] In one embodiment, assume that the count value is positively correlated with the number of times and / or frequency of access to the target mapping entry in the past period of time (or the count value is negatively correlated with the time difference between the time point of the last access to the target mapping entry and the current system time in the past period of time). If the comparison result indicates that the target count information is greater than the preset value (indicating that the number of times the target mapping entry has been accessed in the past period of time is relatively large, the frequency of access to the target mapping entry in the past period of time is relatively high, and / or the time point of the last access to the target mapping entry in the past period of time is relatively close to the current system time), then the processor 111 may determine that the target count information meets the preset condition. Conversely, if the comparison result indicates that the target count information is not greater than (e.g., less than or equal to) the preset value, the processor 111 may determine that the target count information does not meet the preset condition.

[0058] In one embodiment, assume that the count value is negatively correlated with the number of times and / or frequency of access to the target mapping entry in the past period of time (or the count value is positively correlated with the time difference between the time point of the last access to the target mapping entry and the current system time in the past period of time). If the comparison result indicates that the target count information is greater than the preset value (indicating that the number of times the target mapping entry has been accessed in the past period of time is relatively small, the frequency of access to the target mapping entry in the past period of time is relatively low, and / or the time point of the last access to the target mapping entry in the past period of time is relatively far from the current system time), then the processor 111 may determine that the target count information does not meet the preset condition. Conversely, if the comparison result indicates that the target count information is not greater than (e.g., less than or equal to) the preset value, then the processor 111 may determine that the target count information meets the preset condition.

[0059] In one embodiment, according to the counting information, the processor 111 may preferentially retain in the shared buffer 101 the mapping table entries (i.e., the first mapping table entries) that have been accessed relatively more times, have a relatively higher access frequency, and / or have a relatively smaller time difference between the time point of the most recent access and the current system time in the past period of time, and / or remove from the shared buffer 101 the mapping table entries (i.e., the second mapping table entries) that have been accessed relatively fewer times, have a relatively lower access frequency, and / or have a larger time difference between the time point of the most recent access and the current system time in the past period of time. Thus, even if the capacity of the shared buffer 101 is limited (or even reduced), the performance of the host system 11 and the storage device 12 can still be maintained (or even improved).

[0060] In one embodiment, the processor 111 may sort at least one mapping table entry currently cached in the shared buffer 101 according to the counting information to obtain a sorting result. Then, the processor 111 may, according to the sorting result, retain the target mapping table entry in the shared buffer 101 or remove the target mapping table entry from the shared buffer 101.

[0061] In one embodiment, the counting information includes first type of counting information, second type of counting information, and / or third type of counting information. The first type of counting information reflects the number of times the target mapping table entry has been accessed in the past period of time. The second type of counting information reflects the access frequency of the target mapping table entry in the past period of time. The third type of counting information reflects the time difference between the time point of the most recent access of the target mapping table entry and the current system time in the past period of time. In one embodiment, the processor 111 may bring at least one of the first type of counting information, the second type of counting information, and the third type of counting information into a sorting algorithm to obtain the sorting result. Thereafter, the processor 111 may, according to the sorting result, sequentially remove one or more mapping table entries from the shared buffer 101.

[0062] In one embodiment, the processor 111 may use a certain sorting algorithm (also referred to as the first sorting algorithm) to obtain the sorting result. For example, in the first sorting algorithm, the processor 111 may sort multiple mapping table entries in the shared buffer 101 according to the first type of counting information to obtain the sorting result. For example, this sorting result may reflect, from large to small or from small to large, the number of times each mapping table entry in the shared buffer 101 has been accessed in the past period of time. Thereafter, the processor 111 may, according to the sorting result, start from the mapping table entry with the fewest access times in the past period of time and sequentially remove one or more mapping table entries from the shared buffer 101.

[0063] In one embodiment, the processor 111 may adopt another sorting algorithm (also referred to as the second sorting algorithm) to obtain the sorting result. For example, in the second sorting algorithm, the processor 111 may sort multiple mapping entries in the shared buffer 101 according to the second type of count information to obtain the sorting result. For example, this sorting result may reflect, from low to high or from high to low, the access frequency of each mapping entry in the shared buffer 101 over a past period of time. Thereafter, the processor 111 may, according to the sorting result, sequentially remove one or more mapping entries from the shared buffer 101 starting from the mapping entry with the lowest access frequency over a past period of time.

[0064] In one embodiment, the processor 111 may adopt yet another sorting algorithm (also referred to as the third sorting algorithm) to obtain the sorting result. For example, in the third sorting algorithm, the processor 111 may sort multiple mapping entries in the shared buffer 101 according to the third type of count information to obtain the sorting result. For example, this sorting result may reflect, from large to small or from small to large, the time difference between the time point when each mapping entry in the shared buffer 101 was last accessed and the current system time over a past period of time. Thereafter, the processor 111 may, according to the sorting result, sequentially remove one or more mapping entries from the shared buffer 101 starting from the mapping entry with the largest time difference between the time point when it was last accessed and the current system time over a past period of time.

[0065] In one embodiment, in some sorting algorithms (also referred to as the fourth sorting algorithm), the processor 111 may also synchronously consider at least two of the first type of count information, the second type of count information, and the third type of count information to obtain the sorting result. In one embodiment, sorting each mapping entry in the shared buffer 101 by considering at least two of the first type of count information, the second type of count information, and the third type of count information can improve the accuracy of the sorting result.

[0066] In one embodiment, the processor 111 may configure a weight parameter (also referred to as the first weight parameter) for the first type of count information. In one embodiment, the processor 111 may configure a weight parameter (also referred to as the second weight parameter) for the second type of count information. In one embodiment, the processor 111 may configure a weight parameter (also referred to as the third weight parameter) for the third type of count information. The first weight parameter, the second weight parameter, and the third weight parameter may be used to allocate the influence of the first type of count information, the second type of count information, and the third type of count information on the sorting result respectively. For example, the sum of the first weight parameter, the second weight parameter, and the third weight parameter may be "1". For example, if it is desired to increase the influence of the first type of count information on the sorting result (equivalent to reducing the influence of the second type of count information and the third type of count information on the sorting result), the processor 111 may increase the value of the first weight parameter and correspondingly reduce the values of the second weight parameter and the third weight parameter. Then, the processor 111 may sort each mapping entry in the shared buffer 101 according to the first type of count information (and the first weight parameter), the second type of count information (and the second weight parameter), and / or the third type of count information (and the third weight parameter) to obtain the sorting result.

[0067] In one embodiment, the processor 111 may further determine the type of the target mapping entry. According to the type of the target mapping entry, the processor 111 may bring at least one of the first type of count information, the second type of count information, and the third type of count information into the sorting algorithm to obtain the sorting result. For example, when sorting multiple mapping entries belonging to a specific type, the processor 111 may, according to this specific type, bring at least one of the predetermined first type of count information, the second type of count information, and the third type of count information into the sorting algorithm to obtain the sorting result. Thus, the accuracy of the sorting result can be further improved.

[0068] In one embodiment, the processor 111 may obtain the identification information corresponding to the target mapping entry. The identification information may reflect the type of the target mapping entry. Then, the processor 111 may determine the type of the target mapping entry according to the identification information.

[0069] In one embodiment, the processor 111 may query the management table according to the identification information corresponding to the target mapping entry to obtain a query result. The management table may record multiple types (also referred to as candidate types) corresponding to multiple identification information (also referred to as candidate identification information) respectively. Then, the processor 111 may determine the type of the target mapping entry from the multiple candidate types according to the query result. For example, according to the query result, the processor 111 may determine the candidate type that matches the identification information in the management table as the type of the target mapping entry.

[0070] In one embodiment, the type of a mapping table entry may reflect that this mapping table entry belongs to at least one of an active foreground application, an inactive foreground application, and a background application. In one embodiment, assume that the current processor 111 is running applications A and B. Among them, application A is running in the foreground of the operating system (OS), while application B is running in the background of the operating system. At this time, the processor 111 may classify application A as an active foreground application and classify application B as a background application. It should be noted that those skilled in the art should know how the processor runs different application programs in the foreground and background of the operating system, and will not elaborate here.

[0071] In one embodiment, assume that another application C is switched to run in the foreground of the operating system. In response to application C being switched to run in the foreground of the operating system, the processor 111 may classify application C as an active foreground application. At the same time, the processor 111 may reclassify (for example, downgrade) application A, which was originally an active foreground application, as an inactive foreground application, and maintain application B as a background application.

[0072] In one embodiment, the identification information corresponding to the target mapping table entry may reflect that the target mapping table entry belongs to an active foreground application, an inactive foreground application, or a background application. In addition, when the type of the target mapping table entry changes, the processor 111 may correspondingly update the identification information of the target mapping table entry. The updated identification information may reflect the current type of the target mapping table entry. For example, when the target image table entry changes from originally belonging to an inactive foreground application to belonging to an active foreground application, the processor 111 may correspondingly update the identification information of the target mapping table entry so that the updated identification information reflects that the target mapping table entry currently belongs to an active foreground application.

[0073] It should be noted that in one embodiment, the type of at least one mapping table entry cached in the shared buffer 101 may also be configured or adjusted according to practical requirements, and is not limited to the above-mentioned active foreground application, inactive foreground application, and / or background application.

[0074] In one embodiment, the processor 111 may also configure multiple regions in the shared buffer 101 to classify and store mapping table entries of different types. Thus, the performance of the host system 11 and the storage device 12 can be effectively improved.

[0075] In one embodiment, the processor 111 may detect the data storage amount of at least one of the memory 112 and the shared buffer 101. For example, this data storage amount may reflect how much data has been stored in at least one of the current memory 112 and the shared buffer 101. In one embodiment, the processor 111 may detect whether the data storage amount reaches a critical value. When the data storage amount reaches the critical value, the processor 111 may, according to the counting information, retain the target mapping table entry in the shared buffer 101, or remove the target mapping table entry from the shared buffer 101. Alternatively, in one embodiment, when the data storage amount reaches the critical value, the processor 111 may perform the foregoing sorting operation according to the counting information to determine the priority order for each mapping table entry in the shared buffer 101 to be removed and / or retained. Then, the processor 111 may sequentially remove one or more mapping table entries from the shared buffer 101 according to the determined order. However, if the data storage amount does not reach the critical value, the processor 111 may temporarily not perform the foregoing operation of removing the mapping table entry from the shared buffer 101.

[0076] In one embodiment, when the data storage amount of at least one of the memory 112 and the shared buffer 101 is relatively large (e.g., reaches the critical value), preferentially removing the data with a relatively low hit rate according to the determined priority order can release additional memory space for the host system 11 (and the storage device 12) to use. Thereby, the performance of the host system 11 and the storage device 12 can be improved.

[0077] Figure 4 is a flowchart of a method for managing shared buffer data based on counting information shown in an embodiment of the present invention. Please refer to Figure 4 , in step S401, configure a shared buffer in the memory of the host system, where the storage device is used to perform a preset operation based on the data cached in the shared buffer. In step S402, obtain the counting information corresponding to at least one mapping table entry cached in the shared buffer. In step S403, according to the counting information, retain the target mapping table entry in the at least one mapping table entry in the shared buffer, or remove the target mapping table entry from the shared buffer.

[0078] However, Figure 4 each step has been described in detail above and will not be elaborated here. It should be noted that Figure 4 each step can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 4 the method of

[0079] In summary, the method and storage system for shared buffer data management based on count information proposed in the embodiments of the present invention can properly manage (such as sorting, adding, and / or removing) the mapping entries cached in the shared buffer when the capacity of the shared buffer available for storage devices within the host system is small (or even the capacity of the shared buffer can be reduced). Thus, the efficiency of the storage device or the entire storage system can be effectively improved on the premise of minimizing the impact on the operation efficiency of the host system itself.

[0080] In one embodiment, the aforementioned management and / or sorting mechanism for mapping entries can also be used to manage and / or sort other types of data. For example, in one embodiment, the aforementioned mapping entries can be replaced by various instructions, valid count management data, wear leveling management data, bad block management data, or other types of custom data, which will not be repeated here.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shared cache data management method based on counting information, characterized in that: Used in a storage system, the storage system includes a host system and a storage device, the host system is connected to the storage device, and the shared cache area data management method based on counting information includes: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Obtaining counting information corresponding to at least one mapping table entry cached in the shared cache area; and According to the counting information, retaining a target mapping table entry in the at least one mapping table entry in the shared cache area, or removing the target mapping table entry from the shared cache area, The step of retaining the target mapping table entry in the at least one mapping table entry in the shared cache area or removing the target mapping table entry from the shared cache area according to the counting information comprises: Determine the type of the target mapping table entry according to whether the target mapping table entry is an active foreground application, an inactive foreground application, or a background application, wherein if the application to which the target mapping table entry belongs is running in the foreground of the operating system, the target mapping table entry is determined to belong to the active foreground application; if the application is running in the background of the operating system, the target mapping table entry is determined to belong to the background application; if another application replaces the application to which the target mapping table entry belongs to run in the foreground of the operating system, the target mapping table entry is determined to belong to the inactive foreground application; According to the type of the target mapping table entry, at least one of the first type of counting information, the second type of counting information and the third type of counting information is brought into a sorting algorithm to obtain a sorting result for a plurality of mapping table entries belonging to a specific type, wherein the first type of counting information reflects the number of times the target mapping table entry has been accessed in a past period of time, the second type of counting information reflects the frequency of access to the target mapping table entry in the past period of time, and the third type of counting information reflects the time difference between a time point when the target mapping table entry was most recently accessed in the past period of time and a current system time; and According to the sorting result, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area.

2. According to the shared cache area data management method based on counting information according to claim 1, wherein the counting information includes target counting information corresponding to the target mapping table entry, and the target counting information reflects the number of times, frequency or time point when the target mapping table entry is accessed within a period of time in the past.

3. The shared cache data management method based on counting information according to claim 2 further comprises: In response to each time the target mapping table entry is accessed, the target count information is correspondingly updated.

4. The method for managing shared cache data based on counting information according to claim 1, wherein the step of retaining the target mapping table entry in the at least one mapping table entry in the shared cache or removing the target mapping table entry from the shared cache according to the counting information further comprises: Determining whether the target counting information corresponding to the target mapping table entry meets a preset condition; If the target counting information meets the preset condition, determining that the target mapping table entry belongs to the first mapping table entry; If the target counting information does not meet the preset condition, determining that the target mapping table entry belongs to the second mapping table entry; as well as When data is to be removed from the shared cache area, the second mapping table entry is removed from the shared cache area with priority compared to the first mapping table entry.

5. The method for managing shared cache data based on counting information according to claim 4, wherein the target counting information comprises a counting value, and the step of determining whether the target counting information corresponding to the target mapping table entry meets the preset condition comprises: Comparing the count value with a preset value to obtain a comparison result; as well as According to the comparison result, it is determined whether the target counting information meets the preset condition.

6. A storage system, characterized in that: include: Host system; as well as a storage device, connected to the host system, The host system is used to: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Obtaining counting information corresponding to at least one mapping table entry cached in the shared cache area; as well as According to the counting information, retaining a target mapping table entry in the at least one mapping table entry in the shared cache area, or removing the target mapping table entry from the shared cache area, The operation of retaining the target mapping table entry in the at least one mapping table entry in the shared cache area or removing the target mapping table entry from the shared cache area according to the counting information includes: Determine the type of the target mapping table entry according to whether the target mapping table entry is an active foreground application, an inactive foreground application, or a background application, wherein if the application to which the target mapping table entry belongs is running in the foreground of the operating system, the target mapping table entry is determined to belong to the active foreground application; if the application is running in the background of the operating system, the target mapping table entry is determined to belong to the background application; if another application replaces the application to which the target mapping table entry belongs to run in the foreground of the operating system, the target mapping table entry is determined to belong to the inactive foreground application; According to the type of the target mapping table entry, at least one of the first type of counting information, the second type of counting information and the third type of counting information is brought into a sorting algorithm to obtain a sorting result for a plurality of mapping table entries belonging to a specific type, wherein the first type of counting information reflects the number of times the target mapping table entry has been accessed in a past period of time, the second type of counting information reflects the frequency of access to the target mapping table entry in the past period of time, and the third type of counting information reflects the time difference between a time point when the target mapping table entry was most recently accessed in the past period of time and a current system time; and According to the sorting result, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area. 7 . The storage system according to claim 6 , wherein the counting information comprises target counting information corresponding to the target mapping table entry, and the target counting information reflects the number of times, frequency or time point at which the target mapping table entry is accessed within a past period of time.

8. The storage system according to claim 7, wherein the host system is further configured to: In response to each time the target mapping table entry is accessed, the target count information is correspondingly updated.

9. The storage system according to claim 6, wherein according to the counting information, the operation of retaining the target mapping table entry in the at least one mapping table entry in the shared cache area or removing the target mapping table entry from the shared cache area further comprises: Determining whether the target counting information corresponding to the target mapping table entry meets a preset condition; as well as If the target counting information meets the preset condition, determining that the target mapping table entry belongs to the first mapping table entry; If the target counting information does not meet the preset condition, determining that the target mapping table entry belongs to the second mapping table entry; as well as When data is to be removed from the shared cache area, the second mapping table entry is removed from the shared cache area with priority compared to the first mapping table entry.

10. The storage system according to claim 9, wherein the target count information comprises a count value, and the operation of determining whether the target count information corresponding to the target mapping table entry meets the preset condition comprises: Comparing the count value with a preset value to obtain a comparison result; as well as According to the comparison result, it is determined whether the target counting information meets the preset condition.

Images