Initialization method, electronic device and medium for LPDDR5

Abstract

The present application relates to the field of storage technology and provides an initialization method, electronic device and medium for LPDDR5. In order to deal with the problem of abnormal command recognition, an improvement is provided for the initialization process of low-power fifth-generation double-rate memory. Before command bus training, the operation steps of initializing the configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and chip selection mode are widened, and the clock signal after delay division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, which is conducive to ensuring that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to an initialization method, electronic device and medium for LPDDR5. Background Art

[0002] Double Data Rate 5 (DDR5) is a memory technology specification used to improve data flow channels and data transmission efficiency. Low Power Double Data Rate 5 (LPDDR5), or LPDDR5, adds low power (LP) to DDR5, which means lower power consumption and smaller size. LPDDR5 has the characteristics of DDR, that is, double data rate, which means that data is transmitted on both the rising and falling edges of the signal, that is, each clock cycle completes twice the amount of data transmission of synchronous dynamic random access memory (SDRAM). LPDDR5 is used in mobile devices such as smartphones and smart watches or in-vehicle intelligence and other applications that are sensitive to power consumption and size. The clock scheme of LPDDR5 adopts a dual clock signal design, which is different from the single clock signal design adopted by the clock scheme of DDR5. It can help improve the effective rate of the data bus, but it also brings challenges in state alignment and synchronization. In order to meet the requirements of the clock scheme of LPDDR5 for state alignment and synchronization, command bus training (CBT) is used to achieve alignment between signals. Before command bus training, refer to the protocol specification of LPDDR5 initialization process. After DRAM reset, it is necessary to initialize the configuration mode register write command (MRW), and then use the calibration reference signal (ZQ) signal to calibrate and latch through the calibration circuit. However, after configuring MRW and configuring the calibration circuit, and before CBT, there may be a large routing delay between the multiple links corresponding to the command address (CA) signal and the link corresponding to the chip select (CS) signal relative to the link corresponding to the clock (CK) signal. For example, there may be a situation where the timing diagram of MRW does not meet the timing requirements of DRAM particles, which may cause command recognition abnormalities. With the development of high-speed digital communication, the communication frequency is getting higher and higher, which further increases the risk of command recognition abnormalities.

[0003] To this end, the present application provides an initialization method, electronic device and medium for LPDDR5. By optimizing the initialization process of the low-power fifth-generation double-rate memory, the accuracy and stability of the mode register write command are increased, which is beneficial to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and is beneficial to ensure that the memory particles can be correctly configured and initialized before starting command bus training. Summary of the invention

[0004] In the first aspect, the present application provides an initialization method for LPDDR5. The initialization method includes: responding to the initialization instruction of the first memory, initializing the configuration mode register write command, then using the configured mode register write command to configure the particles of the first memory, and then, performing resistance calibration of the particles of the first memory through a calibration circuit, thereby initializing the particles of the first memory to perform command bus training, wherein the first memory is a low-power fifth-generation double-rate memory, wherein the initialization configuration mode register write command includes, through a delay training module, determining the routing delay of at least one command address signal link of the particles of the first memory relative to the clock signal link, when any command address in the at least one command address signal link When the routing delay of the signal link relative to the clock signal link exceeds half of the width of the command address pattern, the clock signal with a first frequency on the clock signal link is divided by multiples of a first value to obtain a divided clock signal with a second frequency, the command address pattern transmitted on all command address signal links in the at least one command address signal link is widened by multiples of the first value, and the chip selection pattern transmitted on the chip selection signal link of the particles of the first memory is widened by multiples of the first value, and then, the time of the unit interval of half the first value of the divided clock signal is delayed, and the width of the command address pattern and the time of the unit interval are both determined based on the first frequency.

[0005] Through the first aspect of the present application, in order to address the problem of abnormal command recognition, an improvement in the initialization process of a low-power fifth-generation double-rate memory is provided. Before command bus training, the operation steps of initializing the configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after division is delayed. The first numerical value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, which is beneficial to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0006] In a possible implementation of the first aspect of the present application, before the initialization configuration mode register write command, the maximum delay offset for avoiding command recognition exceptions is half of the width of the command address mode, and after the initialization configuration mode register write command, the maximum delay offset is a multiple of half of the first value of the width of the command address mode.

[0007] In a possible implementation of the first aspect of the present application, the initialization configuration mode register write command is used to: increase the first upper limit of the routing delay of each command address signal link in the at least one command address signal link relative to the clock signal link from half of the width of the command address mode to a multiple of half of the first value of the width of the command address mode, and the first upper limit is used to avoid command recognition abnormalities of the command address signal link.

[0008] In a possible implementation of the first aspect of the present application, the initialization configuration mode register write command is also used to: increase the second upper limit of the routing delay of the chip selection signal link relative to the clock signal link from half of the width of the command address mode to a multiple of half of the first value of the width of the command address mode, and the second upper limit is used to avoid command recognition abnormalities of the chip selection signal link.

[0009] In a possible implementation manner of the first aspect of the present application, the periods of the command address signals of any two command address signal links in the at least one command address signal link are the same, or different.

[0010] In a possible implementation manner of the first aspect of the present application, the first value is an even number greater than or equal to 2, and the first value is determined based on a frequency modulation requirement.

[0011] In a possible implementation manner of the first aspect of the present application, the first frequency is a multiple of the first value of the second frequency.

[0012] In a possible implementation manner of the first aspect of the present application, when the first frequency is 7500 MHz, the width of the command address mode is 533 picoseconds, and the first value is 8.

[0013] In a possible implementation manner of the first aspect of the present application, the initialization instruction of the first memory is issued based on resetting of particles of the first memory.

[0014] In a possible implementation manner of the first aspect of the present application, the command bus training is used to achieve alignment between command address signals and data signals of particles of the first memory.

[0015] In a possible implementation of the first aspect of the present application, the low-power fifth-generation double data rate memory is a dynamic random access memory that complies with the memory technical specifications of the low-power fifth-generation double data rate.

[0016] In a possible implementation manner of the first aspect of the present application, the chip select mode transmitted on the chip select signal link corresponds to the command address mode transmitted on all command address signal links in the at least one command address signal link.

[0017] In a possible implementation manner of the first aspect of the present application, the delay training module is independent of the first memory and is connected to the first memory.

[0018] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0019] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0020] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0021] In order to deal with the problem of abnormal command recognition, the beneficial technical effects of the present invention are: providing an improvement in the initialization process of a low-power fifth-generation double-rate memory, and optimizing the operation steps of initializing the configuration mode register write command before command bus training. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and chip selection mode are widened, and the clock signal after delay division is delayed. The first numerical value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, which is beneficial to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A flowchart of an initialization method for LPDDR5 provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of a timing diagram of a mode register write command before an initialization configuration mode register write command provided by an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a timing diagram of a mode register write command after an initialization configuration mode register write command is provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of a delay training module provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0030] Figure 1 A flowchart of an initialization method for LPDDR5 provided in an embodiment of the present application. Figure 1 As shown, the initialization method includes the following steps.

[0031] Step S101: In response to an initialization instruction of a first memory, a configuration mode register write command is initialized.

[0032] Step S103: Use the configured mode register write command to configure the particles of the first memory.

[0033] Step S105: performing resistance calibration of the particles of the first memory by means of a calibration circuit, thereby initializing the particles of the first memory to perform command bus training.

[0034] Figure 1 The initialization method for LPDDR5 shown in the figure, the first memory is a low-power fifth-generation double-rate memory. The initialization configuration mode register write command includes, through the delay training module, determining the routing delay of at least one command address signal link of the particles of the first memory relative to the clock signal link, when the routing delay of any command address signal link of the at least one command address signal link relative to the clock signal link exceeds half of the width of the command address mode, dividing the clock signal with a first frequency on the clock signal link by multiples of the first value to obtain a divided clock signal with a second frequency, widening the multiples of the first value of the command address mode transmitted on all command address signal links in the at least one command address signal link, and widening the multiples of the first value of the chip selection mode transmitted on the chip selection signal link of the particles of the first memory, and then delaying the unit interval time of half of the first value of the divided clock signal, the width of the command address mode and the unit interval time are both determined based on the first frequency.

[0035] refer to Figure 1, Double Data Rate 5 (DDR5) is a memory technology specification used to improve data flow channels and data transmission efficiency. Low Power Double Data Rate 5 (LPDDR5), that is, LPDDR5 adds low power (LP) to DDR5, which means lower power consumption and smaller size. LPDDR5 has the characteristics of DDR, that is, double data rate, which means that data is transmitted on both the rising and falling edges of the signal, that is, each clock cycle completes twice the amount of data transmission of synchronous dynamic random access memory (SDRAM). LPDDR5 is used in mobile devices such as smartphones and smart watches or in-vehicle intelligence and other application fields that are sensitive to power consumption and size. The clock scheme of LPDDR5 adopts a dual clock signal design, which is different from the single clock signal design adopted by the clock scheme of DDR5. It can help improve the effective rate of the data bus, but it also brings challenges in state alignment and synchronization. In order to meet the requirements of the clock scheme of LPDDR5 for state alignment and synchronization, command bus training (CBT) is used to achieve alignment between signals. Before command bus training, refer to the protocol specification of LPDDR5 initialization process. After DRAM reset, it is necessary to initialize the configuration mode register write command (MRW), and then use the calibration reference signal (ZQ) signal to calibrate and latch through the calibration circuit. However, after configuring MRW and configuring the calibration circuit, and before CBT, there may be a large routing delay between the multiple links corresponding to the command address (CA) signal and the link corresponding to the chip select (CS) signal relative to the link corresponding to the clock (CK) signal. For example, there may be a situation where the timing diagram of MRW does not meet the timing requirements of DRAM particles, which may cause command recognition abnormalities. With the development of high-speed digital communication, the communication frequency is getting higher and higher, which further increases the risk of command recognition abnormalities.

[0036] Continue to refer Figure 1In step S101, in response to the initialization instruction of the first memory, the configuration mode register write command is initialized. In step S103, the configured mode register write command is used to configure the particles of the first memory. In step S105, the resistance calibration of the particles of the first memory is performed through the calibration circuit, thereby initializing the particles of the first memory to perform command bus training. The calibration circuit uses the calibration reference signal, namely the ZQ signal, for calibration and locking. The ZQ calibration circuit outputs a standard voltage for output pull-up calibration to calibrate the internal resistance of the DRAM (affected by factors such as process angle, voltage, temperature, etc.), and is also used to output pull-down drive to terminate the resistance calibration. The ZQ calibration circuit is generally connected to an external reference resistor, and the reference resistor is considered to be unaffected by factors such as process angle, voltage, temperature, etc. For example, the reference resistor is 240 ohms. The resistance calibration inside the DRAM is based on the external reference resistor, and training and calibration are performed through the ZQ calibration circuit. Figure 1 The initialization method for LPDDR5 shown in the figure configures the chip through the MRW command, then calibrates the internal resistance of the DRAM through the calibration circuit, and finally performs command bus training. However, after configuring MRW, CA and CS may not be aligned in the middle of the differential clock signal CK, and there may be a large routing delay, that is, a large skew.

[0037] The command address signal includes multiple links, such as CA0 to CA6. When the offset between any CA link and CK exceeds half the width of the CA pattern (for example, half of 533 picoseconds (ps) is 266ps), command recognition abnormality may occur. For example, at a rate of 7500 megahertz (MHz), the width of a single CA pattern is approximately 533ps.

[0038] Continue to refer Figure 1, for the operation flow of the initialization method for low-power fifth-generation double data rate (LPDDR5), in order to ensure that before command bus training, the routing delay of the command address signal link relative to the clock signal link and the routing delay of the chip select signal link relative to the clock signal link are limited to an acceptable range, that is, the risk of abnormal control command recognition. Here, command recognition abnormality refers to the recognition of an incorrect command mode or recognition failure. For example, the command address mode that should have been recognized as corresponding to the command address signal link CA0 is mistakenly recognized as the command address mode corresponding to another command address signal link CA1. The multiple command address signal links associated with the first memory may use different cycles and different command address modes from each other. Therefore, in order to ensure business isolation and normal data transmission, it is necessary to ensure that the command address mode transmitted on each command address signal link is correctly recognized. When the timing diagram of the mode register write command does not meet the timing requirements of the memory particles, that is, when the routing delay of the command address signal link relative to the clock signal link exceeds half of the width of the command address mode, or when the routing delay of the chip selection signal link relative to the clock signal link exceeds half of the width of the command address mode, this may cause boundary judgment errors, positioning errors, etc. when sampling based on the clock signal, thereby causing command recognition abnormalities. In addition, in the field of high-speed digital communications, with the increase of communication frequency and the improvement of data processing performance, the maximum frequency of the clock signal may also increase. For example, when the clock frequency is 7500 MHz, the width of the command address mode is 533 picoseconds, which means that as long as any one of the command address signal links of the first memory particle relative to the clock signal link has a routing delay of more than half of the width of the command address mode (that is, more than half of 533 picoseconds), there is a high risk of command recognition abnormalities. Here, the routing of different command address signal links is affected by the transmission path, electronic device characteristics, etc., and there may be different degrees of delay. Therefore, the routing delays of different command address signal links relative to the clock signal link may also be different. In addition, different chip manufacturing processes, such as process corners, and chip operating conditions such as power supply voltage and operating temperature, that is, process corner voltage temperature (PVT), will also affect the overall routing delay, such as affecting the device driving capability, logic gate delay, chip speed, etc. For this reason, in the initialization process of LPDDR5, it is also necessary to consider the impact of PVT factors on the accuracy and stability of the mode register write command.

[0039] Continue to refer Figure 1 , Figure 1The initialization method for LPDDR5 shown in the figure optimizes the operation steps of the initialization configuration mode register write command. Specifically, through the delay training module, the routing delay of at least one command address signal link of the particles of the first memory relative to the clock signal link is determined, and it is judged whether the routing delay of any one of the at least one command address signal link relative to the clock signal link exceeds half of the width of the command address mode. Moreover, when the routing delay of any one of the at least one command address signal link relative to the clock signal link exceeds half of the width of the command address mode, it means that there is a risk of abnormal command recognition. Therefore, the clock signal with a first frequency on the clock signal link is divided by multiples of the first value to obtain a divided clock signal with a second frequency, and the multiples of the first value of the command address mode transmitted on all command address signal links in the at least one command address signal link are widened, and the multiples of the first value of the chip selection mode transmitted on the chip selection signal link of the particles of the first memory are widened, and then the unit interval time of half of the first value of the divided clock signal is delayed. In this way, there is no need to switch the input reference clock source, and only the original input reference clock source is used. By dividing the clock signal with the first frequency on the clock signal link by multiples of the first value, a divided clock signal with a second frequency is obtained, so that the divided clock signal with a reduced frequency can be output. In addition, by widening the command address mode and widening the chip selection mode, and on the basis of frequency division and widening, the time of the unit interval (Unit Interval, UI) of half the number of the first value of the divided clock signal is delayed, that is, the divided clock signal is delayed to output the time of the unit interval of half the number of the first value. Here, the multiple command address signal links associated with the first memory may use different cycles and different command address modes. The command address mode transmitted on each command address signal link is widened in the same proportion, that is, the multiples of the first value are widened. Here, the first value is an even number and an adjustable parameter, which can be adjusted based on the frequency modulation requirements. In this way, through the frequency division operation, the widening operation and the delay operation, it is equivalent to making the command address and the chip selection move closer to the middle position of the clock signal. Therefore, through a mechanism similar to circuit rectification or waveform correction, when there is a routing delay of the command address signal link relative to the clock signal link and a routing delay of the chip selection signal link relative to the clock signal link, the system fault tolerance is increased, which helps to improve the overall stability of the system.In addition, the routing delays of different command address signal links relative to the clock signal link may also be different. PVT factors may affect device driving capabilities, logic gate delays, chip speeds, etc. Here, by proportionally widening the command address modes transmitted by different command address signal links, that is, widening the multiples of the first value, this helps to increase the accuracy and stability of mode register write commands under different chip processes and routing conditions.

[0040] In conclusion, Figure 1 The initialization method for LPDDR5 shown in the figure provides an improvement on the initialization process of the low-power fifth-generation double-rate memory in order to deal with the problem of abnormal command recognition. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, which is conducive to ensuring that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training. In addition, there is no need to switch the input reference clock source, only the original input reference clock source is used, and the clock signal with a first frequency on the clock signal link is divided by a multiple of the first value to obtain a divided clock signal with a second frequency. In this way, the divided clock signal with a reduced frequency can be output, saving the loss of switching the clock source, which is conducive to adapting to the technical specifications and frequency modulation requirements of various memories.

[0041] Figure 2 A schematic diagram of a timing diagram of a mode register write command before an initialization configuration mode register write command is provided in an embodiment of the present application. Figure 2 As shown, a plurality of command address signal links associated with the first memory each transmits a corresponding command address mode. Figure 2 201 , command address mode A201 , command address mode B203 , command address mode C205 , and command address mode D207 are exemplarily shown. Figure 2The clock signal 211 before frequency division is also shown as an example. It can be seen that when the timing diagram of the mode register write command does not meet the timing requirements of the memory particles, that is, when the routing delay of the command address signal link relative to the clock signal link exceeds half of the width of the command address mode, or when the routing delay of the chip selection signal link relative to the clock signal link exceeds half of the width of the command address mode, this may cause boundary judgment errors, positioning errors, etc. when sampling based on the clock signal, thereby causing command recognition abnormalities. For example, the command address mode (for example, the command address mode corresponding to the command address signal link CA0) that should have been identified Figure 2 The command address mode A201 in the command address signal link is mistakenly identified as the command address mode corresponding to another command address signal link CA1 (for example Figure 2 For example, when the clock frequency is 7500 MHz, the width of the command address mode is 533 picoseconds, which means that as long as the routing delay of any one of the at least one command address signal link of the particles of the first memory relative to the clock signal link exceeds half of the width of the command address mode (that is, exceeds half of 533 picoseconds), there is a high risk of abnormal command recognition. In the field of high-speed digital communication, with the increase of communication frequency and the improvement of data processing performance, the maximum frequency of the clock signal may also increase, which means that half of the width of the command address mode will be reduced, while the routing delay may be basically maintained, which further increases the risk of abnormal command recognition.

[0042] Figure 3 A schematic diagram of a timing diagram of a mode register write command after an initialization configuration mode register write command is provided in an embodiment of the present application. Figure 3 As shown, a plurality of command address signal links associated with the first memory each transmits a corresponding command address mode. Figure 3 FIG. 2 exemplarily shows two command address modes: command address mode E301 and command address mode F303. Figure 1The initialization method for LPDDR5 shown in the figure optimizes the operation steps of the initialization configuration mode register write command, including: when the routing delay of any one of the at least one command address signal link relative to the clock signal link exceeds half of the width of the command address mode, the clock signal with the first frequency on the clock signal link is divided by multiples of the first value to obtain a divided clock signal 311 with a second frequency, the multiples of the first value of the command address mode transmitted on all command address signal links in the at least one command address signal link are widened, and the multiples of the first value of the chip selection mode transmitted on the chip selection signal link of the particles of the first memory are widened, and then the time of the unit interval of half of the first value of the divided clock signal 311 is delayed. Here, it is assumed that the routing delay exceeds half of the width of the command address mode. For this purpose, the clock signal on the clock signal link is divided by the delay training module, the command address mode and the chip selection mode are widened, and the divided clock signal 311 is delayed. Assume that the first value is 8, that is, the command address mode is widened by 8 times. Therefore, after the command address mode E301 is expanded by 8 times, Figure 3 In the example, the command address pattern E301 is represented as 8 boxes of the same 8 command address patterns. For the purpose of simplicity, the command address pattern F303 is expanded 8 times. Figure 3 Only three boxes of command address mode F303 are schematically shown in FIG. In this way, through the frequency division operation, widening operation and delay operation, it is equivalent to making the command address and chip selection move closer to the middle position of the clock signal. Therefore, through a similar mechanism to circuit rectification or waveform correction, in the case of a routing delay of the command address signal link relative to the clock signal link and a routing delay of the chip selection signal link relative to the clock signal link, the system fault tolerance is increased, which helps to improve the overall stability of the system. In addition, there is no need to switch the input reference clock source, only the original input reference clock source is used, and the divided clock signal 311 with a second frequency is obtained by dividing the clock signal with a first frequency on the clock signal link by a multiple of the first value. In this way, the divided clock signal with a reduced frequency can be output, saving the loss of switching the clock source, which is conducive to adapting to the technical specifications and frequency modulation requirements of various memories.

[0043] Figure 4 A schematic diagram of a delay training module provided in an embodiment of the present application. Figure 4 As shown, the delay training module 401 is connected to the first memory 403 and exchanges relevant information about the clock 411 , the chip selection 413 and the command address 415 . Figure 4 Delay training module 401, reference Figure 1The initialization method for LPDDR5 shown in the figure performs an initialization process after optimization design on the particles of the first memory 403, including optimizing the operation steps of the initialization configuration mode register write command. Specifically, through the delay training module 401, the routing delay of at least one command address signal link of the particles of the first memory 403 relative to the clock signal link is determined, and it is determined whether the routing delay of any command address signal link in the at least one command address signal link relative to the clock signal link exceeds half of the width of the command address mode. Furthermore, when the routing delay of any one of the at least one command address signal links relative to the clock signal link exceeds half of the width of the command address pattern, this means that there is a risk of abnormal command recognition. Therefore, the clock signal with a first frequency on the clock signal link is divided by multiples of a first value to obtain a divided clock signal with a second frequency, and the multiples of the first value of the command address pattern transmitted on all command address signal links in the at least one command address signal link are widened, and the multiples of the first value of the chip selection pattern transmitted on the chip selection signal link of the particles of the first memory 403 are widened, and then the time of the unit interval of half the first value of the divided clock signal is delayed. In this way, before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module 401, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, which is conducive to ensuring that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training. In addition, there is no need to switch the input reference clock source, and only the original input reference clock source is used. By dividing the clock signal with a first frequency on the clock signal link by a multiple of the first value, a divided clock signal with a second frequency is obtained. In this way, a divided clock signal with a reduced frequency can be output, which saves the loss of switching the clock source and is conducive to adapting to the technical specifications and frequency modulation requirements of various memories.

[0044] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4In one possible implementation, before the initialization configuration mode register write command, the maximum delay offset for avoiding command recognition exceptions is half of the width of the command address mode, and after the initialization configuration mode register write command, the maximum delay offset is a multiple of half of the first value of the width of the command address mode. Command recognition exception refers to the recognition of an incorrect command mode or recognition failure. For example, the command address mode that should have been recognized as corresponding to the command address signal link CA0 is mistakenly recognized as the command address mode corresponding to another command address signal link CA1. The multiple command address signal links associated with the first memory may use different cycles and different command address modes. Therefore, in order to ensure business isolation and normal data transmission, it is necessary to ensure that the command address mode transmitted on each command address signal link is correctly recognized. When the timing diagram of the mode register write command does not meet the timing requirements of the memory particles, that is, when the routing delay of the command address signal link relative to the clock signal link exceeds half of the width of the command address mode, or when the routing delay of the chip selection signal link relative to the clock signal link exceeds half of the width of the command address mode, this may cause boundary judgment errors, positioning errors, etc. when sampling based on the clock signal, thereby causing command recognition abnormalities. In the field of high-speed digital communications, with the increase of communication frequency and the improvement of data processing performance, the maximum frequency of the clock signal may also increase. For example, when the clock frequency is 7500 MHz, the width of the command address mode is 533 picoseconds, which means that as long as any one of the command address signal links of the first memory particle has a routing delay relative to the clock signal link that exceeds half of the width of the command address mode (that is, more than half of 533 picoseconds), there is a high risk of command recognition abnormalities. Here, the routing of different command address signal links is affected by the transmission path, electronic device characteristics, etc., and there may be different degrees of delay. Therefore, the routing delays of different command address signal links relative to the clock signal link may also be different. In this way, by optimizing the operation steps of the initialization configuration mode register write command, the clock signal on the clock signal link is divided through the delay training module, the command address mode and chip selection mode are widened, and the clock signal after the division is delayed, the first value is used as an adjustable parameter, and the maximum delay offset for avoiding command recognition abnormalities is equivalently increased.Assuming that the first value is 8, before the initialization configuration mode register write command, as long as the routing delay of any one of the at least one command address signal link of the particles of the first memory relative to the clock signal link exceeds half of the width of the command address mode (for example, more than half of 533 picoseconds), there is a risk of abnormal command recognition. After the initialization configuration mode register write command, the maximum delay offset is increased to a multiple of half of the first value of the width of the command address mode (for example, half of 8 times of 533 picoseconds, that is, four times of 533 picoseconds). In this way, through the frequency division operation, widening operation and delay operation, it is equivalent to making the command address and chip selection move closer to the middle position of the clock signal. Therefore, through a similar mechanism to circuit rectification or waveform correction, in the case of routing delay of the command address signal link relative to the clock signal link and routing delay of the chip selection signal link relative to the clock signal link, the system fault tolerance is increased, which helps to improve the overall stability of the system.

[0045] In a possible implementation, the initialization configuration mode register write command is used to: increase the upper limit (first upper limit, the first upper limit is used to avoid command recognition abnormality of the command address signal link) of the routing delay of each command address signal link in the at least one command address signal link relative to the clock signal link from half of the width of the command address mode to a multiple of half of the first value of the width of the command address mode. Command recognition abnormality refers to the recognition of an incorrect command mode or recognition failure, for example, the command address mode that should have been recognized as corresponding to the command address signal link CA0 is mistakenly recognized as the command address mode corresponding to another command address signal link CA1. The multiple command address signal links associated with the first memory may use different cycles and different command address modes from each other. Therefore, in order to ensure business isolation and normal data transmission, it is necessary to ensure that the command address mode transmitted on each command address signal link is correctly recognized. When the timing diagram of the mode register write command does not meet the timing requirements of the memory particles, that is, when the routing delay of the command address signal link relative to the clock signal link exceeds half of the width of the command address mode, or when the routing delay of the chip select signal link relative to the clock signal link exceeds half of the width of the command address mode, this may lead to boundary judgment errors, positioning errors, etc. when sampling based on the clock signal, and thus cause command recognition abnormalities. In this way, by optimizing the operation steps of the initialization configuration mode register write command, the clock signal on the clock signal link is divided through the delay training module, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, and the upper limit of the routing delay of each command address signal link in the at least one command address signal link relative to the clock signal link is equivalently increased from half of the width of the command address mode (for example, half of 533 picoseconds) to a multiple of half of the first value of the width of the command address mode (for example, half of 8 times of 533 picoseconds, that is, four times of 533 picoseconds). In this way, through the frequency division operation, the widening operation and the delay operation, it is equivalent to making the command address and the chip selection move closer to the middle position of the clock signal. Therefore, through a similar mechanism to circuit rectification or waveform correction, in the case of the routing delay of the command address signal link relative to the clock signal link and the routing delay of the chip selection signal link relative to the clock signal link, the system fault tolerance is increased, which helps to improve the overall stability of the system.

[0046] In some embodiments, the initialization configuration mode register write command is also used to: increase the upper limit (second upper limit, the second upper limit is used to avoid command recognition abnormality) of the routing delay of the chip selection signal link relative to the clock signal link from half of the width of the command address mode to a multiple of half of the first value of the width of the command address mode. In this way, through the frequency division operation, widening operation and delay operation, it is equivalent to making the command address and chip selection move closer to the middle position of the clock signal. Therefore, through a mechanism similar to circuit rectification or waveform correction, in the presence of routing delay of the command address signal link relative to the clock signal link and routing delay of the chip selection signal link relative to the clock signal link, the system fault tolerance is increased, which helps to improve the overall stability of the system.

[0047] In a possible implementation, the periods of the command address signals of any two command address signal links in the at least one command address signal link are the same, or different. The routing delays of different command address signal links relative to the clock signal link may also be different. PVT factors may affect the device driving capability, logic gate delay, chip speed, etc. Thus, by expanding the command address modes transmitted by different command address signal links in the same proportion, that is, expanding the multiples of the first value, it is helpful to increase the accuracy and stability of the mode register write command under different chip processes and routing conditions.

[0048] In a possible implementation, the first value is an even number greater than or equal to 2, and the first value is determined based on the frequency modulation requirement. The first value is an even number and is an adjustable parameter that can be adjusted based on the frequency modulation requirement. The first value can be determined in combination with the frequency modulation requirement, for example, set to 8, 12 or a higher multiple. A higher first value means using a higher multiple for frequency division and a higher multiple for widening, and also means delaying more unit time intervals. In this way, through the frequency division operation, the widening operation and the delay operation, it is equivalent to making the command address and the chip selection move closer to the middle position of the clock signal, so through a similar mechanism to circuit rectification or waveform correction, in the presence of a routing delay of the command address signal link relative to the clock signal link and a routing delay of the chip selection signal link relative to the clock signal link, the system fault tolerance is increased, which helps to improve the overall stability of the system. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, which is conducive to ensuring that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training. In addition, there is no need to switch the input reference clock source, only the original input reference clock source is used, and the clock signal with the first frequency on the clock signal link is divided by a multiple of the first value to obtain a divided clock signal with a second frequency. In this way, a divided clock signal with a reduced frequency can be output, which saves the loss of switching the clock source and is conducive to adapting to the technical specifications and frequency modulation requirements of various memories.

[0049] In a possible implementation, the first frequency is a multiple of the first value of the second frequency. Thus, an improvement is provided to the initialization process of the low-power fifth-generation double-rate memory. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, helps to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0050] In a possible implementation, when the first frequency is 7500 MHz, the width of the command address mode is 533 picoseconds, and the first value is 8. Thus, an improvement is provided to the initialization process of the low-power fifth-generation double-rate memory. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, helps to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0051] In a possible implementation manner, the initialization instruction of the first memory is issued based on the reset of the particles of the first memory, so as to adapt to the reset requirements of the memory.

[0052] In a possible implementation, the command bus training is used to achieve alignment between the command address signal and the data signal of the particles of the first memory. In this way, an improvement is provided to the initialization process of the low-power fifth-generation double-rate memory. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, helps to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0053] In a possible implementation, the low-power fifth-generation double-rate memory is a dynamic random access memory that complies with the low-power fifth-generation double-rate memory technical specifications. In this way, an improvement is provided to the initialization process of the low-power fifth-generation double-rate memory. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, helps to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0054] In a possible implementation, the chip selection mode transmitted on the chip selection signal link corresponds to the command address mode transmitted on all command address signal links in the at least one command address signal link. In this way, an improvement is provided to the initialization process of the low-power fifth-generation double-rate memory. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, helps to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0055] In a possible implementation, the delay training module is independent of the first memory and connected to the first memory. In this way, an improvement is provided to the initialization process of the low-power fifth-generation double-rate memory. Before the command bus training is performed, the operation steps of the initialization configuration mode register write command are optimized and designed. Through the delay training module, the clock signal on the clock signal link is divided, the command address mode and the chip selection mode are widened, and the clock signal after the frequency division is delayed. The first value is used as an adjustable parameter, which increases the accuracy and stability of the mode register write command, helps to ensure that the timing diagram of the mode register write command meets the timing requirements of the memory particles, and helps to ensure that the memory particles can be correctly configured and initialized before starting the command bus training.

[0056] Figure 5: is a structural diagram of a computing device provided in an embodiment of the present application, and the computing device 500 includes: one or more processors 510, a communication interface 520 and a memory 530. The processor 510, the communication interface 520 and the memory 530 are interconnected via a bus 540. Optionally, the computing device 500 may also include an input / output interface 550, and the input / output interface 550 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 500 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 510 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the computing device 500 performing various operations can refer to the specific details in the above-mentioned embodiments, such as the processor 510 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 500 may be used to implement part or all of the functions of one or more components in the above-mentioned device embodiment. In addition, the communication interface 520 may be specifically used to perform the communication functions necessary to implement the functions of these devices and components, and the processor 510 may be specifically used to perform the processing functions necessary to implement the functions of these devices and components.

[0057] It should be understood that Figure 5 The computing device 500 may include one or more processors 510, and the multiple processors 510 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 510 may form a processor sequence or a processor array, or the multiple processors 510 may be divided into a main processor and an auxiliary processor, or the multiple processors 510 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 500 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 500 may include Figure 5 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0058] The processor 510 may have a variety of specific implementation forms. For example, the processor 510 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 510 may also be a single-core processor or a multi-core processor. The processor 510 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 510 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 520 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0059] The memory 530 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 530 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 530 may also be used to store program codes and data, so that the processor 510 calls the program codes stored in the memory 530 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Figure 5 Show more or fewer components, or have different component configurations.

[0060] The bus 540 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 540 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 540 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0061] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0062] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0063] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0064] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0065] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. An initialization method for LPDDR5, characterized in that: The initialization method comprises: In response to the initialization instruction of the first memory, step 1: initializing a configuration mode register write command; Step 2: Use the configured mode register write command to configure the particles of the first memory; Step 3: Performing resistance calibration of the particles of the first memory by means of a calibration circuit, thereby initializing the particles of the first memory to perform command bus training, wherein the first memory is a low-power fifth-generation double rate memory, Wherein, in the step 1, the initialization configuration mode register write command includes, through a delay training module, determining the routing delay of at least one command address signal link of the particles of the first memory relative to the clock signal link, when the routing delay of any one of the at least one command address signal link relative to the clock signal link exceeds half of the width of the command address mode, dividing the clock signal with a first frequency on the clock signal link by multiples of a first value to obtain a divided clock signal with a second frequency, widening the multiples of the first value of the command address mode transmitted on all command address signal links in the at least one command address signal link, and widening the multiples of the first value of the chip selection mode transmitted on the chip selection signal link of the particles of the first memory, and then delaying the time of the unit interval of half the first value of the divided clock signal, the width of the command address mode and the time of the unit interval are both determined based on the first frequency.

2. The initialization method according to claim 1, characterized in that: Before the initialization configuration mode register write command, the maximum delay offset for avoiding command recognition exceptions is half the width of the command address mode, and after the initialization configuration mode register write command, the maximum delay offset is a multiple of half of the first value of the width of the command address mode.

3. The initialization method according to claim 1, characterized in that: The initialization configuration mode register write command is used to increase the first upper limit of the routing delay of each command address signal link in the at least one command address signal link relative to the clock signal link from half of the width of the command address mode to a multiple of half of the first value of the width of the command address mode, and the first upper limit is used to avoid command recognition abnormalities of the command address signal link.

4. The initialization method according to claim 3, characterized in that: The initialization configuration mode register write command is also used to increase the second upper limit of the routing delay of the chip selection signal link relative to the clock signal link from half the width of the command address mode to a multiple of half the first value of the width of the command address mode, and the second upper limit is used to avoid command recognition abnormalities of the chip selection signal link.

5. The initialization method according to claim 1, characterized in that: The periods of the command address signals of any two command address signal links in the at least one command address signal link are the same or different.

6. The initialization method according to claim 1, characterized in that: The first value is an even number greater than or equal to 2, and the first value is determined based on frequency modulation requirements.

7. The initialization method according to claim 1, characterized in that: The first frequency is a multiple of the first value of the second frequency.

8. The initialization method according to claim 1, characterized in that: When the first frequency is 7500 MHz, the width of the command address pattern is 533 picoseconds, and the first value is 8.

9. The initialization method according to claim 1, characterized in that: The initialization instruction of the first memory is issued based on the reset of the particles of the first memory.

10. The initialization method according to claim 1, characterized in that: The command bus training is used to achieve alignment between command address signals and data signals of particles of the first memory.

11. The initialization method according to claim 1, characterized in that: The low-power fifth-generation double data rate memory is a dynamic random access memory that complies with the low-power fifth-generation double data rate memory technical specifications.

12. The initialization method according to claim 1, characterized in that: The chip select pattern transmitted on the chip select signal link corresponds to the command address pattern transmitted on all command address signal links in the at least one command address signal link.

13. The initialization method according to claim 1, characterized in that: The delay training module is independent of the first memory and connected to the first memory.

14. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 13 when executing the computer program.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 13.

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