Support of multiple peripheral components in synchronous serial communication system using single chip select line

Abstract

The invention relates to supporting multiple peripheral components in a synchronous serial communication system with a single chip select line. A synchronous serial communication controller, a synchronous serial communication peripheral component, and a computer-implemented method of enabling synchronous serial communication between the synchronous serial communication controller and the synchronous serial communication peripheral component are provided. An example synchronous serial communication controller includes a serial communication interface configured with a clock logic line, a data output logic line, a data input logic line, and a shared select line logic line. The shared select line logic line is electrically connected to the plurality of peripheral components. Chip identification data transmitted over the data output logic line indicates a selected one of the plurality of peripheral components.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to synchronous serial communication systems, and more particularly, to supporting multiple peripheral components using a single chip select line in a synchronous serial communication system. Background Art

[0002] Electronic systems are often composed of numerous interconnected electrical components. The interconnected electrical components often utilize a synchronous serial communication protocol (such as a serial peripheral interface (SPI) protocol) to enable communication between the interconnected electrical components. In some cases, a serial communication system can utilize a controller to communicate with multiple peripheral components.

[0003] Applicants have recognized that there are many technical challenges and difficulties in supporting communication with multiple peripheral components in a synchronous serial communication system. Applicants, through hard work, ingenuity and innovation, have solved the problems associated with communication with multiple peripheral components in a serial communication system by developing solutions embodied in the present disclosure, which are described in detail below. Summary of the invention

[0004] Various embodiments relate to an example synchronous serial communication controller, an example synchronous serial communication peripheral component, and a computer-implemented method for synchronous serial communication between a synchronous serial communication controller and a plurality of synchronous serial communication peripheral components. In one embodiment, an example synchronous serial communication controller is provided. The example synchronous serial communication controller includes a serial communication interface, which includes a clock logic line, a data output logic line, a data input logic line, and a shared selection line logic line. In some embodiments, the shared selection line logic line is electrically connected to a plurality of peripheral components. In addition, a peripheral component selected from the plurality of peripheral components is indicated by chip identification data transmitted on the data output logic line.

[0005] In some embodiments, the voltage on the shared select line logic line is driven low to indicate the transmission of chip identification data to the selected peripheral device.

[0006] In some embodiments, the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.

[0007] In some embodiments, the shared select line logic line is a chip select logic line.

[0008] In some embodiments, the serial communication interface also includes a dedicated chip select logic line electrically connected to the legacy peripheral component.

[0009] In some embodiments, a legacy peripheral component is selected by driving an electrical signal on a dedicated chip select logic line low.

[0010] In some embodiments, a notification opcode is transmitted on the data output logic line, indicating the transmission of chip identification data.

[0011] An example synchronous serial communication peripheral component is also provided. In at least one embodiment, the example synchronous serial communication peripheral component includes a serial communication interface, the serial communication interface including a clock logic line, a data output logic line, a data input logic line, and a shared selection line logic line. In some embodiments, the shared selection line logic line is electrically connected to a plurality of peripheral components, so that a selected peripheral component among the plurality of peripheral components is indicated by chip identification data received on the shared selection line logic line.

[0012] In some embodiments, the shared select line logic line is activated to indicate the transmission of chip identification data to the selected peripheral component.

[0013] In some embodiments, the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.

[0014] In some embodiments, the shared select line logic line is a chip select logic line.

[0015] In some embodiments, a notification opcode is received on a data output logic line indicating the transmission of chip identification data.

[0016] In some embodiments, in the event that the notification opcode is not recognized by the synchronous serial communication peripheral component, the synchronous serial communication peripheral component is configured to perform one or more actions according to the operation opcode.

[0017] In some embodiments, the serial communication peripheral component further includes a local chip identifier, wherein the local chip identifier is compared to the chip identification data to determine receipt of subsequent operation opcodes and data bytes.

[0018] The present invention also provides a computer-implemented method for synchronous serial communication between a serial communication controller and a plurality of peripheral components. In some embodiments, the computer-implemented method includes transmitting chip identification data on a data output logic line of a serial communication interface. The serial communication interface includes a clock logic line, a data output logic line, a data input logic line, and a shared selection line logic line. The shared selection line logic line is electrically connected to a plurality of peripheral components, and the chip identification data identifies a selected peripheral component of the plurality of peripheral components. In some embodiments, the computer-implemented method also includes transmitting an operation opcode indicating an operation associated with the selected peripheral component.

[0019] In some embodiments, the computer-implemented method further includes activating a shared select line logic line to indicate transmission of a notification opcode to the plurality of peripheral components.

[0020] In some embodiments, the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.

[0021] In some embodiments, the shared select line logic line is a chip select logic line.

[0022] In some embodiments, the serial communication interface also includes a dedicated chip select logic line electrically connected to the legacy peripheral component.

[0023] In some embodiments, the computer-implemented method further comprises exchanging one or more data bytes with the selected peripheral component.

[0024] In some embodiments, the computer-implemented method further includes transmitting a notification opcode on a data output logic line indicating transmission of the chip identification data. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Reference will now be made to the drawings. The components shown in the drawings may or may not be present in certain embodiments described herein. According to example embodiments of the present disclosure, some embodiments may include fewer (or more) components than shown in the drawings.

[0026] Figure 1 An example serial communication system is illustrated in which a chip select logic line is utilized for each connected peripheral component.

[0027] Figure 2 An example serial communication system is illustrated that utilizes a single shared select line logic line to support synchronous serial communications between a controller and multiple peripheral components according to an example embodiment of the present disclosure.

[0028] Figure 3 A block diagram of an example controller according to an example embodiment of the present disclosure is shown.

[0029] Figure 4 An example of a legacy serial communication operation data sequence on a data output logic line is shown.

[0030] Figure 5 An example serial communication flow utilizing a single shared select line logic line to communicate with multiple peripheral components of a serial communication system is shown according to an example embodiment of the present disclosure.

[0031] Figure 6 An example serial communication system supporting synchronous serial communications between a serial communication controller, a legacy peripheral component, and a plurality of peripheral components configured in accordance with an example embodiment of the present disclosure is illustrated.

[0032] Figure 7A flow chart illustrating an example process of performing synchronous serial communications between a serial communication controller and a plurality of peripheral components according to an example embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Example embodiments will be described more fully below with reference to the accompanying drawings, in which some but not all embodiments of the invention of the present disclosure are shown. In fact, the embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals throughout the text represent like elements.

[0034] As used herein, the term "high" when referring to a logic line indicates that the voltage on the logic line is above some minimum voltage threshold of the electronic device, generally between 1.8 volts and 3.6 volts. Similarly, the term "low" when referring to a logic line indicates that the voltage is below some voltage threshold of the electronic device, generally at or near 0 volts. As used herein, the term "assertion" refers to switching a signal to an active state, whether a voltage below some maximum threshold on an active low logic line or a voltage above some minimum threshold on an active high logic line.

[0035] Various example embodiments solve technical problems associated with synchronous serial communication with multiple peripheral components on a serial communication system. As those skilled in the art understand, there are many example scenarios in which a serial communication system can benefit from communicating with multiple peripheral devices in a space and power efficient manner.

[0036] For example, electronic systems often consist of many interconnected electrical components. Generally speaking, an electronic system may include a central electronic component or controller that is responsible for controlling and / or interacting with multiple peripheral components (such as memory, sensors, control devices, and other similar electronic components). The controller typically interacts with the connected peripheral components using synchronous serial communication. In order to support synchronous serial communication between electrical components, communication protocols such as the Serial Peripheral Interface (SPI) protocol have been designed. The SPI protocol enables synchronous serial communication between devices using four logic signals transmitted on the following logic lines: clock (CLK), data output (DO), data input (DI), peripheral input controller output (PICO), and chip select (CS).

[0037] In an SPI communication system, a clock is generated by the controller and transmitted to various peripheral components along with the data. The transmitted clock enables synchronous transmission of data between the controller and any connected peripheral components. On an SPI communication system, the controller can only communicate with one peripheral component at a time. The chip select logic line is used to indicate the peripheral component that is communicating. In general, the chip select logic line is a low-active logic line, which means that when the voltage on the chip select logic line is low or grounded, the signal is activated or asserted. During operation, the low-active chip select logic line for the target peripheral component is driven low to wake up the target peripheral component and indicate the transmission of data on the data output logic line. Once the target peripheral component is notified, the operation opcode indicating the operation to be performed is transmitted to the target peripheral component, followed by any data bytes associated with the transaction.

[0038] Reference now Figure 1 , a legacy serial communication system 100 (eg, SPI) is provided. Figure 1 As shown in , the legacy serial communication system 100 includes a serial communication controller 102 electrically connected to a serial communication interface 114, which has a clock logic line 106, a master output slave input (MOSI) line 108, and a master input slave output (MISO) line 110. The illustrated serial communication interface 114 shows that the MISO line 110 electrically connects the data input pin of the serial communication controller 102 to the data output pin of the legacy peripheral components 104a-104n; the MOSI line 108 electrically connects the data output pin of the serial communication controller 102 to the data input pin of the legacy peripheral components 104a-104n, and the clock logic line 106 electrically connects the clock pin of the serial communication controller 102 to the clock pin on the legacy peripheral components 104a-104n. In addition, the example serial communication system 100 includes separate chip select logic lines 112a-112n electrically connected to each legacy peripheral component 104a-104n. As shown Figure 1 As shown in FIG. 1 , each of the legacy peripheral components 104 a - 104 n shares a clock logic line 106 , a MOSI line 108 , and a MISO line 110 , but has separate chip select logic lines 112 a - 112 n for each legacy peripheral component 104 a - 104 n .

[0039] Since each of the plurality of legacy peripheral components 104a-104n requires a separate chip select logic line 112a-112n, Figure 1The example legacy serial communication system 100 shown in FIG. 1 uses three logic lines plus one additional line for each legacy peripheral component 104 a-104 n. As the number of legacy peripheral components 104 a-104 n increases, the number of logic lines also increases. The increase in logic lines increases the number of input / output (I / O) pins at the controller, thereby increasing the size and cost of the controller. In addition, the routing of the chip select logic lines for each legacy peripheral component 104 a-104 n can be complicated, thereby increasing the cost and overall complexity of the serial communication system.

[0040] Various example embodiments described herein utilize a variety of techniques to support multiple peripheral components in a serial communication system using one or more shared select line logic lines. For example, in some embodiments, the serial communication system described herein can manage communication between multiple peripheral components using a single chip select logic line electrically connected to the multiple peripheral components.

[0041] To support synchronous serial communication with multiple peripheral components, the serial communication system described herein can utilize chip identification data in conjunction with shared selection line logic lines to communicate with the connected peripheral components.

[0042] In addition, in some embodiments, a serial communication system that supports both traditional SPI peripheral components and multiple peripheral components using a single shared select line logic line can be used. In such embodiments, the controller can distinguish between peripheral components that share the shared select line logic line and peripheral components with dedicated chip select logic lines. Therefore, when communicating with peripheral components that share the shared select line logic line, the controller can transmit chip identification data. However, for peripheral components with dedicated chip select logic lines, the controller can communicate with the peripheral components according to the traditional serial communication system protocol.

[0043] As a result of the example embodiments described herein and in some examples, the effectiveness of synchronous serial communication systems can be greatly improved. In addition, the cost, size, and complexity of designing and manufacturing serial communication systems with multiple peripheral components can be greatly improved.

[0044] Reference now Figure 2 , an example shared selection line serial communication system 220 is provided. Figure 2As shown in , the example shared selection line serial communication system 220 includes a shared selection line serial communication controller 222, which is electrically connected to a plurality of shared selection line peripheral components 224a-224n via a shared selection line serial communication interface 228. The illustrated shared selection line serial communication interface 228 shows: a MISO line 210, which electrically connects a data input pin of the shared selection line serial communication controller 222 to a data output pin of the shared selection line peripheral components 224a-224n; a MOSI line 208, which electrically connects a data output pin of the shared selection line serial communication controller 222 to a data input pin of the shared selection line peripheral components 224a-224n; and a clock logic line 206, which electrically connects a clock pin of the shared selection line serial communication controller 222 to a clock pin on the shared selection line peripheral components 224a-224n.

[0045] like Figure 2 As shown in , the example serial communication system includes a shared selection line serial communication controller 222. The shared selection line serial communication controller 222 can be any circuit system or device including hardware, software and / or firmware, including at least four I / O interfaces electrically connected to the shared selection line serial communication interface 228. The shared selection line serial communication controller 222 is also configured to generate a clock signal on the clock logic line 206 for transmission to each of the connected shared selection line peripheral components 224a-224n to support synchronous serial communication. In addition, the shared selection line serial communication controller 222 is configured to utilize the shared selection line logic line 226 to support communication with multiple shared selection line peripheral components 224a-224n, which are configured to share the shared selection line logic line 226, as described with respect to Figure 5 In some embodiments, the shared select line serial communication controller 222 may also be configured to utilize chip select logic lines, transmit operation opcodes, and transmit data bytes to facilitate communication with one or more shared select line peripheral components 224a-224n according to the SPI protocol.

[0046] As about Figure 2As further shown, the example serial communication interface 220 includes a plurality of shared selection line peripheral components 224a-224n. The shared selection line peripheral components 224a-224n are any electronic devices configured to interface with the shared selection line serial communication interface 228 and to transmit and / or receive operational data with the shared selection line serial communication controller 222 based on a clock signal provided by the shared selection line serial communication controller 222 on the clock logic line 206. In addition, the shared selection line peripheral components 224a-224n are configured to transmit and receive operational data utilizing the shared selection line logic lines 226 (as described herein) with the shared selection line serial communication controller 222 communicating on the shared selection line logic lines 226. In some embodiments, the shared selection line peripheral components 224a-224n can be configured to transmit and receive operational data according to a legacy SPI protocol, for example, utilizing as described with respect to Figure 1 Dedicated chip select logic lines 112a-112b are depicted.

[0047] like Figure 2 As further shown in FIG. 1 , the example shared select line serial communication system 220 includes a shared select line serial communication interface 228. The shared select line serial communication interface 228 includes four signals transmitted on the clock logic line 206, the MOSI line 208, the MISO line 210, and the shared select line logic line 226.

[0048] The clock logic line 206 transmits a clock signal generated by the shared select line serial communication controller 222. The clock logic line 206 synchronizes the transmission of operational data between the shared select line serial communication controller 222 and the selected shared select line peripheral components 224a-224n. Compared to asynchronous serial communication protocols, the use of a clock to synchronize transactions simplifies configuration and enables the use of much higher clock frequencies.

[0049] The MOSI line 208 (e.g., data output logic line) enables data to be transmitted from the shared select line serial communication controller 222 to the shared select line peripheral components 224a-224n. The MISO line 210 (e.g., data input logic line) enables data to be transmitted from the shared select line peripheral components 224a-224n to the shared select line serial communication controller 222. According to the SPI protocol, data can be sent on both the MOSI line 208 and the MISO line 210 at the same time.

[0050] like Figure 2As further shown in FIG. 1 , the example shared selection line serial communication interface 228 includes a shared selection line logic line 226. The shared selection line logic line 226 is any conductive wire, cable, cord, or other conduit configured to provide an electrical connection between the shared selection line serial communication controller 222 and the plurality of shared selection line peripheral components 224a-224n. Figure 5 As described, the shared selection line logic line 226 is used in conjunction with the MOSI line 208 to support synchronous serial communication with multiple shared selection line peripheral components 224a-224n using only a single shared selection line logic line 226. Asserting the shared selection line logic line 226 (e.g., driving the voltage below a certain maximum threshold on the low active logic line) indicates that all electrically connected shared selection line peripheral components 224a-224n are ready to receive chip identification data, indicating that the selected shared selection line peripheral components 224a-224n are transmitting data. The shared selection line peripheral components 224a-224n that match the chip identification data can then exchange data bytes with the shared selection line serial communication controller 222.

[0051] The shared selection line serial communication controller 222 can be used by, for example, Figure 3 The invention may be implemented by one or more computing systems such as the apparatus 300 shown in FIG.

[0052] Figure 3 An example device 330 is illustrated in accordance with at least some example embodiments of the present disclosure. Example device 330 includes a processor 332, input / output circuitry 334, data storage medium 336, communication circuitry 338, and peripheral communication circuitry 339. In some embodiments, device 330 is configured to use one or more sets of circuitry 332, 334, 336, 338, and / or 339 to perform the operations described herein.

[0053] Although components are described in terms of functional limitations, it should be understood that specific implementations necessarily include the use of specific computing hardware. It should also be understood that, in some embodiments, certain components described herein include similar or common hardware. For example, both sets of circuit systems can make full use of the same (one or more) processors, (one or more) network interfaces, and / or (one or more) storage media, etc. to perform their associated functions, so that no duplicate hardware is required for each set of circuit systems. Therefore, the use of the term "circuit system" used herein with respect to components of the apparatus described herein should be understood to include specific hardware configured to perform functions associated with the specific circuit system described herein.

[0054] In particular, the term "circuitry" should be broadly understood to include hardware, and in some embodiments, software for configuring hardware. For example, in some embodiments, "circuitry" includes processing circuitry, storage media, network interfaces, and / or input / output devices, etc. Alternatively or additionally, in some embodiments, other elements of device 330 provide or supplement the functionality of other specific groups of circuitry. For example, in some embodiments, processor 332 provides processing functionality for any group of circuitry, data storage medium 336 provides storage functionality for any group of circuitry, and / or communication circuitry 338 provides network interface functionality for any group of circuitry, etc.

[0055] In some embodiments, the processor 332 (and / or a coprocessor or any processing circuitry assisting or otherwise associated with the processor) communicates with the data storage medium 336 via a bus for passing information between components of the device 330. In some embodiments, for example, the data storage medium 336 is non-transitory and may include, for example, one or more volatile and / or non-volatile memories. In other words, for example, in some embodiments, the data storage medium 336 includes or implements an electronic storage device (e.g., a computer-readable storage medium). In some embodiments, the data storage medium 336 is configured to store information, data, content, applications, instructions, etc., to enable the device 330 to perform various functions according to example embodiments of the present disclosure.

[0056] The processor 332 can be implemented in a variety of different ways. For example, in some example embodiments, the processor 332 includes one or more processing devices configured to execute independently. Additionally or alternatively, in some embodiments, the processor 332 includes one or more processors configured in tandem via a bus to enable independent execution of instructions, pipelining, and / or multithreading. The use of the terms "processor" and "processing circuit system" should be understood to include a single-core processor, a multi-core processor, multiple processors within the device 330, and / or one or more remote or "cloud" processors outside the device 330.

[0057] In an example embodiment, the processor 332 is configured to execute instructions stored in the data storage medium 336 or otherwise accessible to the processor. Alternatively or additionally, in some embodiments, the processor 332 is configured to execute hard-coded functionality. Therefore, whether configured by hardware or software methods, or by a combination of the two, the processor 332 represents an entity (e.g., physically implemented in a circuit system) that is capable of performing operations according to embodiments of the present disclosure when configured accordingly. Alternatively or additionally, as another example in some example embodiments, when the processor 332 is implemented as an executor of software instructions, the instructions specifically configure the processor 332 to perform an algorithm implemented in a specific operation described herein when executing the instructions.

[0058] As a specific example embodiment, the processor 332 is configured to perform various operations associated with enabling synchronous communication with multiple shared select line peripheral components (e.g., shared select line peripheral components 224a-224n) utilizing a single shared select line logic line (e.g., shared select line logic line 226). In some embodiments, the processor 332 includes hardware, software, firmware, and / or a combination thereof that drives a voltage on a multi-peripheral chip select logic line low to indicate a transmission of chip identification data to the selected peripheral component. Additionally or alternatively, in some embodiments, the processor 332 includes hardware, software, firmware, and / or a combination thereof that transmits a notification opcode on a data output logic line (e.g., MOSI line 208) indicating a transmission of chip identification data. Additionally or alternatively, in some embodiments, the processor 332 includes hardware, software, firmware, and / or a combination thereof to transmit chip identification data on a data output logic line of a serial communication interface, wherein the serial communication interface includes: a clock logic line; a data output logic line; a data input logic line (e.g., MISO line 210); and a shared selection line logic line; wherein the shared selection line logic line is electrically connected to a plurality of peripheral components, and wherein the chip identification data identifies a selected peripheral component of the plurality of peripheral components. Additionally or alternatively, in some embodiments, the processor 332 includes hardware, software, firmware, and / or a combination thereof to transmit an operation opcode associated with one or more data bytes. Additionally or alternatively, in some embodiments, the processor 332 includes hardware, software, firmware, and / or a combination thereof to transmit one or more data bytes to a selected peripheral component.

[0059] In some embodiments, the device 330 includes an input / output circuit system 334 that provides output to the user and receives an indication of user input in some embodiments. In some embodiments, the input / output circuit system 334 communicates with the processor 332 to provide such functionality. The input / output circuit system 334 may include one or more user interfaces (e.g., user interfaces), and in some embodiments includes a display, which includes an interface presented as a network (web) user interface, an application user interface, a user device, or a back-end system, etc. The processor 332 and / or the input / output circuit system 334 including the processor may be configured to control one or more functions of one or more user interface elements by computer program instructions (e.g., software and / or firmware) stored on a processor-accessible memory (e.g., a data storage medium 336, etc.). In some embodiments, the input / output circuit system 334 includes or utilizes a user-oriented application to provide input / output functionality to a client device and / or other displays associated with a user.

[0060] In some embodiments, the device 330 includes a communication circuit system 338. The communication circuit system 338 includes any component configured to receive and / or transmit data to a network and / or any other device, circuit system or module that communicates with the device 330, such as a device or circuit system implemented in the form of hardware or a combination of hardware and software. In this regard, for example, in some embodiments, the communication circuit system 338 includes a network interface for enabling communication with a wired or wireless communication network. Additionally or alternatively, in some embodiments, the communication circuit system 338 includes one or more network interface cards, antennas, buses, switches, routers, modems, and supporting hardware, firmware and / or software, or any other device suitable for enabling communication via one or more communication networks. Additionally or alternatively, the communication circuit system 338 includes a circuit system for interacting with (one or more) antennas and / or other hardware or software to transmit signals via (one or more) antennas or handle signals received via (one or more) antennas. In some embodiments, the communication circuit system 338 enables data to be transmitted to and / or received from a client device that communicates with the device 330.

[0061] In some embodiments, the device 330 includes a peripheral communication circuit system 339. The peripheral communication circuit system 339 includes hardware, software, firmware, and / or a combination thereof that supports various functionalities associated with performing synchronous serial communications with one or more electrically connected peripheral components (e.g., legacy peripheral components 104a-104n, shared selection line peripheral components 224a-224n). The various functionalities performed by the peripheral communication circuit system 339 may include: driving a clock voltage on a clock logic line (e.g., clock logic line 106, 206), driving a voltage on a chip select line (e.g., chip select logic lines 112a-112n, shared selection line logic line), driving a voltage on a data output logic line (e.g., MOSI line 208) to transmit a data byte to a selected peripheral component, receiving data from a selected peripheral component on a data input logic line (e.g., MISO line 210), and other functionalities associated with synchronous serial communications.

[0062] Additionally or alternatively, in some embodiments, one or more sets of circuit systems 332-339 are combinable. Additionally or alternatively, in some embodiments, one or more groups of circuit systems 332-339 perform some or all of the functionality described in association with another component. For example, in some embodiments, one or more sets of circuit systems 332-339 are combined into a single module implemented in hardware, software, firmware, and / or a combination thereof. Similarly, in some embodiments, one or more sets of circuit systems (e.g., peripheral communication circuit system 339) are combined so that processor 332 performs one or more of the above operations for each of these circuit systems individually.

[0063] Reference now Figure 4 , an example serial communication operation data sequence 440 is provided that complies with synchronous serial communication on a legacy serial communication system (eg, legacy serial communication system 100). Figure 4 As shown in , the example serial communication operation data sequence 440 conforms to the legacy SPI protocol. The example serial communication operation data sequence 440 includes a selected mode 446 during which an operation opcode 442 followed by a plurality of data bytes 444a-444n is transmitted.

[0064] like Figure 4As shown in , during the selected mode 446, the example serial communication operation data sequence 440 is transmitted on the data output logic line (e.g., MOSI line 208). The selected mode 446 is such a period during which the peripheral component is selected to exchange data with the serial communication controller on the data input logic line (e.g., MISO line 210) and the data output logic line. For example, the peripheral component (e.g., the legacy peripheral component 104a-104n) is selected by asserting the chip select logic line associated with the peripheral component (e.g., chip select logic line 112a-112n). Since the legacy SPI protocol includes a dedicated chip select logic line for each peripheral component, in order to select the peripheral component, the chip select logic line for the selected peripheral component is asserted (e.g., driven to a low voltage), and the chip select logic lines for all other peripheral components are de-asserted (e.g., the voltage remains high). The dedicated chip select logic line for each peripheral component increases the number of input / output (I / O) pins at the controller, thereby increasing the size and cost of the legacy serial communication controller. Additionally, routing chip select logic lines for each legacy peripheral component increases the complexity and overall cost of the serial communication system.

[0065] like Figure 4 As further shown in FIG. 4 , an exemplary serial communication operation data sequence 440 includes an operation opcode 442, followed by zero or more data bytes 444a-444n transmitted on a data output logic line. The operation opcode 442 is an arbitrary sequence of data transmitted indicating an operation to be performed by and / or on a selected peripheral component. The data bytes 444a-444n are any sequence of electronic data required to perform the operation indicated by the operation opcode 442. For example, in some embodiments, the operation opcode 442 may indicate a write operation to be performed on the selected peripheral component. In this case, the operation opcode 442 may be followed by a plurality of data bytes 444a-444n, indicating a memory location to write data and / or providing data to be stored on the selected peripheral component. In another example, the operation opcode 442 may indicate a read operation, such as the reading of a specific memory or sensor value. In this case, the operation opcode 442 may not be followed by any data bytes 444a-444n. However, the selected peripheral component can transmit one or more data bytes on the data input logic line that provides the requested data. In some embodiments, the operation opcode 442 can include two bytes or 16 bits of data. The operation indicated by the operation opcode 442 can vary based on the specific peripheral component. Some example operations indicated by the operation opcode 442 can include read operations, write operations, write enable operations, status register read operations, status register write operations, serial number / device ID read operations, etc.

[0066] In some embodiments, the shared selection line peripheral component (e.g., the shared selection line peripheral component 224a-224n) can receive the serial communication operation data sequence 440. In this case, the shared selection line peripheral component can recognize that there is no notification operation code (e.g., as shown in the reference Figure 5 The described operation code 442) and perform the operation indicated by the operation code 442.

[0067] Reference now Figure 5 , an example serial communication operation data sequence 550 is provided for a serial communication system (eg, shared select line serial communication system 220) utilizing shared select line logic lines (eg, shared select line logic lines 226). Figure 5 As shown in FIG. 5 , an example serial communication operation data sequence 550 transmitted on a data output logic line (e.g., MOSI line 208) includes a select mode 556 and a selected mode 546. During the select mode 556, a shared select line serial communication controller (e.g., shared select line serial communication controller 222) transmits a notification opcode 552 and chip identification data 554 on the data output logic line. During the selected mode 546, the shared select line serial communication controller transmits an operation opcode 542 on the data output logic line followed by a plurality of data bytes 544a-544n.

[0068] like Figure 5 As shown in FIG. 5 , during the select mode 556, the shared select line serial communication controller transmits a notification opcode 552 and chip identification data 554 on the MOSI line 208. During the select mode 556 of the shared select line serial communication system, the shared select line logic line is asserted. Therefore, all shared select line peripheral components using the shared select line logic line are ready to receive incoming data on the data output logic line. During the select mode 556, the selected peripheral component is identified by the transmission of the notification opcode 552 and chip identification data 554.

[0069] The notification opcode 552 may be any data sequence, including bits, bytes, numbers, characters, or other data representations, that indicates that the chip select line connected to the peripheral component is a shared select line logic line and also indicates the subsequent transmission of chip identification data 554. In some embodiments, the notification opcode 552 may include one byte (or 8 bits) of data. A peripheral component (e.g., a shared select line peripheral component) configured to support a shared select line serial communication system may be configured to recognize the notification opcode 552. For example, a shared select line serial communication controller may be configured to transmit 8'b01100110 as the notification opcode 552. The shared select line peripheral component may be configured to recognize the 8'b01100110 notification opcode 552 and prepare to receive subsequent chip identification data 554. In some embodiments, the notification opcode 552 may include an opcode that is not used in the SPI protocol standard.

[0070] The chip identification data 554 can be any data sequence, including bits, bytes, numbers, characters, or other data representations, that identifies one or more shared selection line peripheral components as the selected peripheral components for serial communication operations. An identifier is assigned to the shared selection line peripheral component, for example, a bit sequence, a serial number, a universally unique identifier (UUID), a string, or other identification data. The identifier can be hardwired in an external pin, stored in a non-volatile memory, or otherwise accessible to the peripheral component. In the event that the received chip identification data 554 matches the identifier of the peripheral component, the peripheral component is selected and operated as if the dedicated chip selection logic line had been asserted. Peripheral components that contain identifiers that do not match the received chip identification data 554 operate as if the dedicated chip selection logic line was de-asserted.

[0071] like Figure 5 As further shown in FIG. 5 , the shared select line serial communication controller transmits an operation opcode 542 and zero or more data bytes 544a during a selected mode 546. Figure 4 As described, during a selected mode 546 of the shared select line serial communication system, an operation is identified by an operation opcode 542, and the associated data bytes 544a-544n required to perform the operation are transmitted. During the selected mode 546, peripheral components that are not identified as selected peripheral components operate as if the shared select line logic line is de-asserted and awaits re-assertion of the shared select line logic line.

[0072] Reference now Figure 6 , an example hybrid serial communication system 660 is provided. Figure 6As shown in , the example hybrid serial communication system 660 includes multiple legacy peripheral components 604a-604n and multiple shared selection line peripheral components 624a-624n. The illustrated hybrid serial communication system 660 shows a MISO line 610 (e.g., a data input logic line) that electrically connects a data input pin of a hybrid serial communication controller 662 to data output pins of the shared selection line peripheral components 624a-624n and data output pins of the legacy peripheral components 604a-604n. The illustrated hybrid serial communication system 660 also shows a MOSI line 608 (e.g., a data output logic line) that electrically connects a data output pin of the hybrid serial communication controller 662 to data input pins of the shared selection line peripheral components 624a-624n and data input pins of the legacy peripheral components 604a-604n. As shown Figure 6 As further shown in FIG. 6 , clock logic line 606 electrically connects a clock pin of hybrid serial communication controller 662 to clock pins on shared select line peripheral components 624 a - 624 n and to clock pins on legacy peripheral components 604 a - 604 n .

[0073] The chip select pin of each legacy peripheral component 604a-604n is electrically connected to the hybrid serial communication controller 662 using dedicated chip select logic lines 612a-612n. However, the chip select pin of each shared select line peripheral component 624a-624n is electrically connected to the shared select line logic line 626 at the chip select shared pin.

[0074] like Figure 6 As shown in , the hybrid serial communication controller 662 is configured to interface with a serial communication interface 664, which includes a shared MISO line 610, a shared MOSI line 608, a shared clock logic line 606, a shared selection line logic line 626, and a plurality of chip selection logic lines 612a-612n. As described herein, the hybrid serial communication controller 662 is configured to generate and transmit a clock on the clock logic line 606 to support synchronous communication. In addition, the hybrid serial communication controller 662 generates electronic signals to transmit data on the shared MOSI line 608 and is configured to receive electronic data on the shared MISO line 610.

[0075] To support serial communications when the serial communications interface 664 includes both legacy peripheral components 604a-604n and shared select line peripheral components 624a-624n, the hybrid serial communications controller 662 operates according to a standard synchronous serial communications protocol. For example, the hybrid serial communications controller 662 can assert (e.g., pull the voltage low) the chip select logic lines 612a-612n associated with the selected legacy peripheral components 604a-604n and de-assert (e.g., keep the voltage high) on all other select logic lines (e.g., other chip select logic lines 612a-612n and shared select line logic lines 626). Once a legacy peripheral component 604a-604n is selected, the hybrid serial communications controller 662 can communicate with the selected legacy peripheral component 604a-604n, as described with respect to FIG. Figure 4 as described.

[0076] In the event that the hybrid serial communication controller 662 utilizes the shared selection line logic line 626 to initiate communication with the shared selection line peripheral components 624a-624n, the hybrid serial communication controller 662 can assert (e.g., pull the voltage low) the shared selection line logic line 626 and de-assert (e.g., keep the voltage high) the chip selection logic lines 612a-612n associated with the legacy peripheral components 604a-604n. The hybrid serial communication controller 662 can then transmit a notification opcode (e.g., notification opcode 552) and chip identification data (e.g., chip identification data 554) indicating the selected shared selection line peripheral components 624a-624n. Once the selected shared selection line peripheral components 624a-624n are indicated, the hybrid serial communication controller 662 can initiate one or more operations, such as regarding Figure 5 as described.

[0077] In the case where the shared selection line peripheral components 624a-624n are electrically connected to the serial communication controller (e.g., serial communication controller 102, shared selection line serial communication controller 222, hybrid serial communication controller 662) via dedicated chip select logic lines (e.g., chip select logic lines 612a-612n), the shared selection line peripheral components 624a-624n can continue to operate as legacy peripheral components. For example, in the case where the chip select line is asserted and data is received on the shared MOSI line 608, if the received data does not match the notification opcode, then the shared selection line peripheral components 624a-624n can interpret the received data as an operation opcode and perform according to the received operation.

[0078] Reference now Figure 7, an example process 770 is provided for performing synchronous serial communication between a serial communication controller (e.g., a shared selection line serial communication controller 222, a hybrid serial communication controller 662) and a plurality of peripheral components (e.g., legacy peripheral components 104a-104n, 604a-604n, shared selection line peripheral components 224a-224n, 624a-624n) using a shared selection line logic line (e.g., the shared selection line logic line 226, 626). At block 772, the serial communication controller activates the shared selection line logic line to indicate the transmission of chip identification data (e.g., chip identification data 554) to the plurality of peripheral components. As described herein, the shared selection line logic line may be activated or asserted by driving a voltage on the shared selection line logic line low in an active low configuration, or by driving a voltage on the shared selection line logic line high in an active high configuration. Activating the shared select line logic line alerts all connected peripheral components to the subsequent transmission of electronic data on the data MOSI line (eg, MOSI lines 108, 208, 608).

[0079] At block 774, the serial communication controller transmits a notification opcode (e.g., notification opcode 552) on a data output logic line (e.g., MOSI line 208, 608) indicating the transmission of chip identification data. Figure 5 As described, the notification opcode is transmitted to all shared selection line peripheral components (e.g., shared selection line peripheral components 224a-224n, 624a-624n). The notification opcode is a uniquely identifiable opcode that indicates that the shared selection line logic line can be shared by multiple shared selection line peripheral components, and therefore, the chip identification data indicating the selected shared selection line peripheral component is transmitted. In the case where the notification opcode is not transmitted but data matching the operation opcode (e.g., operation opcode 542) is transmitted instead, the shared selection line peripheral components can be configured as described above. Figure 4 The conventional serial communication operation described above operates on a data sequence.

[0080] At box 776, the serial communication controller transmits chip identification data on a data output logic line of a serial communication interface, wherein the serial communication interface includes: a clock logic line; a data output logic line; a data input logic line (e.g., MISO line 210, 610); and a shared selection line logic line; wherein the shared selection line logic line is electrically connected to a plurality of peripheral components, and wherein the chip identification data identifies a selected peripheral component among the plurality of peripheral components. As described herein, each shared selection line peripheral component is assigned an identifier, such as a bit sequence, a serial number, a universally unique identifier (UUID), a string, or other identification data. The identifier may be hardwired in an external pin, stored in a non-volatile memory, or otherwise accessible to the peripheral component. Each peripheral component compares the transmitted chip identification data with an identifier assigned to the peripheral component. In the event that the received chip identification data matches the identifier of the peripheral component, the peripheral component is selected and operated as if the dedicated chip selection logic line had been asserted. A peripheral component assigned an identifier that does not match the received chip identification data operates as if the dedicated chip selection logic line is de-asserted.

[0081] At block 778, the serial communication controller transmits an operation opcode indicating an operation associated with the selected peripheral component. The operation opcode indicates to the selected peripheral component an operation to be performed on or by the selected peripheral component. For example, the operation opcode may indicate a memory write, a specific register read, or other operation.

[0082] At block 780, the serial communication controller exchanges one or more data bytes with the selected peripheral component. In some embodiments, the operation indicated by the operation opcode may include one or more data bytes transmitted by the serial communication controller on a data output logic line. For example, a memory write operation may include the transmission of a memory address and the data to be written. In some embodiments, the operation indicated by the operation opcode may include one or more data bytes transmitted by the selected peripheral component to the serial communication controller on a data input logic line. For example, a memory read operation may require the transmission of a data byte containing data read from the indicated memory location. Also, some operations indicated by the operation opcode may require that additional data bytes not be transmitted through the serial communication interface.

[0083] Although this detailed description has set forth some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements. For example, those skilled in the art will recognize that these principles can be applied to any electronic device that utilizes a synchronous serial communication system. For example, any electronic device including a memory component, a sensor, or a control device that communicates via an SPI protocol. In the appended claims, unless the specific term "means for" or "step for" is used in a given claim, it is not intended to be interpreted under 35 U.S.C. 112, paragraph 6.

[0084] The use of broader terms such as "comprising," "including," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "consisting substantially of." The use of the terms "optionally," "may," "perhaps," "might," and the like with respect to any element of an embodiment means that the element is not required, or, alternatively, the element may also be required, both of which alternatives are within the scope of the embodiment. Moreover, references to examples are provided for illustrative purposes only, and are not intended to be exclusive.

Claims

1. A synchronous serial communication controller, comprising: Serial communication interfaces, including: Clock logic line; Data output logic line; data input logic lines; and Shared selection line logic line, wherein the shared selection line logic line is electrically connected to a plurality of peripheral components, and The selected peripheral component among the plurality of peripheral components is indicated by chip identification data transmitted on the data output logic line.

2. The serial communication controller of claim 1, wherein the voltage on the shared select line logic line is driven low to indicate transmission of chip identification data to the selected peripheral component.

3. The serial communication controller as claimed in claim 1, wherein the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.

4. The serial communication controller of claim 3, wherein the shared select line logic line is a chip select logic line.

5. The serial communication controller of claim 1, wherein the serial communication interface further comprises a dedicated chip select logic line electrically connected to the legacy peripheral component.

6. The serial communications controller of claim 5, wherein the legacy peripheral component is selected by driving an electrical signal on a dedicated chip select logic line low.

7. The serial communication controller of claim 1, wherein a notification operation code is transmitted on the data output logic line to indicate the transmission of the chip identification data.

8. A synchronous serial communication peripheral component comprising: Serial communication interfaces, including: Clock logic line; Data output logic line; data input logic lines; and Shared selection line logic line, wherein the shared selection line logic line is electrically connected to a plurality of peripheral components, and The selected peripheral component among the plurality of peripheral components is indicated by chip identification data received on a shared selection line logic line.

9. The synchronous serial communication peripheral component of claim 8, wherein the shared select line logic line is activated to indicate the transmission of the chip identification data to the synchronous serial communication peripheral component.

10. The synchronous serial communication peripheral assembly of claim 8, wherein the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.

11. The synchronous serial communications peripheral component of claim 10, wherein the shared select line logic line is a chip select logic line.

12. The synchronous serial communication peripheral component of claim 8, wherein a notification opcode is received on the data output logic line indicating the transmission of chip identification data.

13. The synchronous serial communication peripheral component of claim 12, wherein in the event that the notification opcode is not recognized by the synchronous serial communication peripheral component, the synchronous serial communication peripheral component is configured to perform one or more actions according to the operation opcode.

14. The synchronous serial communications peripheral component of claim 8, further comprising a local chip identifier, wherein the local chip identifier is compared to the chip identification data to determine receipt of subsequent operation opcodes and data bytes.

15. A computer-implemented method for synchronous serial communication between a serial communication controller and a plurality of peripheral components, the computer-implemented method comprising: Transmit chip identification data on the data output logic line of the serial communication interface, The serial communication interfaces include: Clock logic line; Data output logic line; data input logic lines; and Shared selection line logic line; wherein the shared selection line logic line is electrically connected to the plurality of peripheral components, and wherein the chip identification data identifies a selected peripheral component from among the plurality of peripheral components; and An operation opcode indicating an operation associated with the selected peripheral component is transmitted.

16. The computer-implemented method of claim 15, further comprising: The shared selection line logic line is activated to indicate the transmission of the notification operation code to the plurality of peripheral components.

17. The computer implemented method of claim 15, wherein the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.

18. The computer implemented method of claim 15, wherein the serial communication interface further comprises a dedicated chip select logic line electrically connected to the legacy peripheral component.

19. The computer-implemented method of claim 15, further comprising: Exchanges one or more data bytes with the selected peripheral component.

20. The computer-implemented method of claim 15, further comprising: A notification operation code is transmitted on the data output logic line to indicate the transmission of chip identification data.

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