Processor cache structure, processor and data cache method

Abstract

The embodiment of the present application provides a processor cache structure, a processor and a data cache method, which relates to the field of computer technology. The processor cache structure includes: a first-level data cache, a first-level instruction cache, a second-level private cache, a second-level private pre-fetch cache, and a cache consistency control unit; the first-level data cache is used to store data accessed multiple times by the current core of the processor; the first-level instruction cache is used to store instructions executed multiple times by the current core; the second-level private cache is used to store data read from the main memory or a high-level cache by the current core; the second-level private pre-fetch cache is used to calculate the pre-fetch address using a preset algorithm and send a pre-fetch request to the second-level private cache, so that the second-level private cache pre-fetches the cache line according to the pre-fetch address; the cache consistency control unit is used to monitor the cache operations of each core of the processor. This solution does not need to wait for other cores to release cache resources, significantly reduces data access latency, and improves the overall performance of the processor.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor cache structure, a processor, and a data cache method. Background Art

[0002] With the rapid development of computer technology, memory, as a key component for storing data and instructions required for program execution, has been increasingly used in various processors. Among them, modern high-performance multi-core processors need to be equipped with a secondary cache to meet the needs of high-performance computing, multi-threaded applications, and data-intensive tasks. Therefore, in order to improve the performance and data access efficiency of multi-core processors, how to set the secondary cache structure is particularly important.

[0003] At present, in the related technology, a shared cache approach is often used in multi-core processor structures. However, this design will cause competition among multiple cores when accessing the cache. For example, when multiple cores need to access data in the cache at the same time, they may have to wait in line, thereby increasing data access latency and reducing the overall performance of the processor. Summary of the invention

[0004] Embodiments of the present application provide a processor cache structure, a processor, and a data cache method.

[0005] A first aspect of an embodiment of the present application provides a processor cache structure, including:

[0006] A first-level data cache, a first-level instruction cache, a second-level private cache, a second-level private prefetch cache, and a cache consistency control unit; the second-level private cache is respectively connected to the first-level data cache, the first-level instruction cache, the second-level private prefetch cache, and the cache consistency control unit;

[0007] The first-level data cache is used to: store data that is accessed multiple times by the current core of the processor;

[0008] The first-level instruction cache is used to: store instructions executed multiple times by the current core;

[0009] The second-level private cache is used to: store data read by the current core from the main memory or the high-level cache; the high-level cache is a cache with a higher level than the second-level private cache;

[0010] The secondary private prefetch cache is used to: calculate a prefetch address using a preset algorithm and send a prefetch request to the secondary private cache, so that the secondary private cache prefetches a cache line according to the prefetch address;

[0011] The cache consistency control unit is used to monitor the cache operations of each core of the processor.

[0012] In an optional embodiment of the present application, the secondary private cache includes a plurality of cache lines, and the data in the cache lines includes at least one of the following data states: shared-dirty, unique-dirty, invalid, shared-clean, unique-clean;

[0013] The shared-dirty is used to characterize that the data in the cache line exists in the caches of multiple cores and has been modified; the unique-dirty is used to characterize that the data in the cache line only exists in the cache of the current core and has been modified; the invalid is used to characterize that the data in the cache line is invalid; the shared-clean is used to characterize that the data in the cache line exists in the caches of multiple cores and has not been modified; the unique-clean is used to characterize that the data in the cache line only exists in the cache of the current core and has not been modified.

[0014] In an optional embodiment of the present application, the secondary private cache includes a shadow tag memory, a register configuration unit, a plurality of line buffers, and a cache;

[0015] The shadow tag memory is used to: store data states corresponding to all cache lines in the secondary private cache;

[0016] The register configuration unit is used to: configure parameters in the secondary private cache;

[0017] Each of the row buffers is used to: temporarily store data read from or written to the buffer;

[0018] The cache is used to store data read by the current core from the main memory or the high-level cache.

[0019] In an optional embodiment of the present application, the secondary private cache is specifically used for:

[0020] Receiving and responding to a cache operation request, acquiring target cache line data and sending it to the cache coherence control unit, and updating a data state of the target cache line data;

[0021] Among them, the cache operation request is that the cache consistency control unit checks the shadow tag memory in the secondary private cache, obtains the data status of all cache lines in the secondary private cache from the shadow tag memory, and sends it to the secondary private cache according to the data status; the cache operation request includes a data shared read request and a data exclusive read request.

[0022] In an optional embodiment of the present application, the secondary private cache is further used for:

[0023] receiving a data exclusive read request sent by a cache consistency control unit, and allocating the data exclusive read request to a row buffer; the data exclusive read request carries a data read address;

[0024] querying the shadow tag memory through the row buffer and searching whether there is target data corresponding to the data read address in the cache;

[0025] When the data state of the target data in the shadow tag memory is valid, sending the data exclusive read request to the primary data cache to obtain the target data, and updating the data state of the target data to an invalid state;

[0026] When the data state of the target data in the cache is valid, acquiring the target data and sending it to the row buffer, and updating the data state of the target data to an invalid state;

[0027] The target data is sent to the cache coherence control unit through the row buffer.

[0028] In an optional embodiment of the present application, the secondary private cache is further used for:

[0029] receiving a data exclusive read request sent by the primary data cache, and allocating the data exclusive read request to a row cache; the data exclusive read request carries a data read address;

[0030] querying, through the row buffer, whether there is a cache line corresponding to the data read address in the cache of the secondary private cache;

[0031] When the cache line exists, sending a data exclusive read request to the cache consistency control unit, marking the copies of other cores as invalid, acquiring the target data and sending it to the first-level data cache; the other cores are the cores of all the cores of the processor except the current core;

[0032] When the cache line does not exist, the data exclusive read request is sent to the cache consistency control unit, data is obtained from other cores or the next level cache, and the copies in the other cores are marked as invalid, and the target data is obtained and sent to the first level data cache.

[0033] In an optional embodiment of the present application, the secondary private cache is further used for:

[0034] When receiving a data write-back request sent by the primary data cache, allocating the data write-back request to the row cache; the data write-back request includes write-back data and a data write address;

[0035] Writing the write-back data into a cache in the secondary private cache through the row cache;

[0036] When other cache lines are replaced in the secondary private cache, check whether there is a cache line with the same address as the data write address in the primary data cache; if so, read the cache line from the primary data cache and update the data state to an invalid state, and write the replaced data back to the cache consistency control unit;

[0037] When no other cache line in the secondary private cache is replaced, the operation ends.

[0038] A second aspect of the embodiments of the present application provides a processor, including the processor cache structure provided in the above embodiments.

[0039] A third aspect of the embodiments of the present application provides a data cache method, which is applied to the processor cache structure as described in any one of the above items, and the method includes:

[0040] The first-level private prefetch cache calculates a prefetch address using a preset prefetch algorithm and sends a prefetch request to the second-level private cache; the prefetch request includes the prefetch address;

[0041] The secondary private cache receives and responds to the prefetch request, and prefetches a cache line according to the prefetch address.

[0042] The processor cache structure in the embodiment of the present application includes: a first-level data cache, a first-level instruction cache, a second-level private cache, a second-level private prefetch cache, and a cache consistency control unit; the second-level private cache is connected to the first-level data cache, the first-level instruction cache, the second-level private prefetch cache, and the cache consistency control unit respectively; the first-level data cache is used to: store data accessed multiple times by the current core of the processor; the first-level instruction cache is used to: store instructions executed multiple times by the current core; the second-level private cache is used to: store data read by the current core from the main memory or a high-level cache; the high-level cache is a cache with a higher level than the second-level private cache; the second-level private prefetch cache is used to: use a preset algorithm to calculate the prefetch address and send a prefetch request to the second-level private cache, so that the second-level private cache prefetches the cache line according to the prefetch address; the cache consistency control unit is used to: monitor the cache operations of each core of the processor. The technical solution in the present application can effectively reduce the mutual interference in cache access between the cores by independently allocating a second-level private cache to each core on the basis of setting a first-level data cache and a first-level instruction cache, so that each core can quickly access its own second-level private cache without waiting for other cores to release cache resources, thereby significantly reducing data access latency. The second-level private prefetch cache uses a preset algorithm to calculate the prefetch address, so that the second-level private cache prefetches data to the cache line in advance according to the prefetch address, reducing data acquisition time. The cache operations of each core of the processor are monitored by the cache consistency control unit to ensure the consistency of data cache operations, thereby improving the overall performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0044] Figure 1 A schematic diagram of a processor cache structure provided for one embodiment of the present application;

[0045] Figure 2 A schematic diagram of the structure of a secondary private cache provided for an embodiment of the present application;

[0046] Figure 3 A flowchart of a data caching method provided by an embodiment of the present application;

[0047] Figure 4 A schematic diagram of the structure of a computer device provided for one embodiment of the present application.

[0048] Description of reference numerals:

[0049] Level 1 data cache-10; Level 1 instruction cache-20; Level 2 private cache-30; Shadow tag memory-31; Register configuration unit-32; Line cache-33; Cache-34; Level 2 private prefetch cache-40; Cache coherence control unit-50. DETAILED DESCRIPTION

[0050] In the process of implementing the present application, the inventors discovered that the existing shared cache may cause competition among multiple cores when accessing the cache, thereby increasing data access latency and reducing the overall performance of the processor.

[0051] Based on the above-mentioned defects, the embodiments of the present application provide a processor cache structure, a processor and a data cache method. By independently allocating a second-level private cache to each core on the basis of setting a first-level data cache and a first-level instruction cache, the mutual interference between the cores in cache access can be effectively reduced, so that each core can quickly access its own second-level private cache without waiting for other cores to release cache resources, thereby significantly reducing data access latency. The second-level private prefetch cache uses a preset algorithm to calculate the prefetch address, so that the second-level private cache prefetches data to the cache line in advance according to the prefetch address, reducing data acquisition time. The cache operations of each core of the processor are monitored by the cache consistency control unit to ensure the consistency of data cache operations, thereby improving the overall performance of the processor.

[0052] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0053] See also Figure 1 As shown, Figure 1 A structural schematic diagram of a processor cache structure provided in an embodiment of the present application, the processor cache structure: a first-level data cache 10, a first-level instruction cache 20, a second-level private cache 30, a second-level private prefetch cache 40, and a cache consistency control unit 50; the second-level private cache 30 is connected to the first-level data cache 10, the first-level instruction cache 20, the second-level private prefetch cache 40, and the cache consistency control unit 50, respectively.

[0054] The first-level data cache 10 is used to store data that is accessed multiple times by the current core of the processor; the first-level instruction cache 20 is used to store instructions that are executed multiple times by the current core; the second-level private cache 30 is used to store data that the current core reads from the main memory or a high-level cache; a high-level cache is a cache at a higher level than the second-level private cache; the second-level private prefetch cache 40 is used to calculate a prefetch address using a preset algorithm and send a prefetch request to the second-level private cache, so that the second-level private cache prefetches a cache line according to the prefetch address; the cache consistency control unit 50 is used to monitor the cache operations of each core of the processor.

[0055] It should be noted that in a multi-core processor architecture, the processor includes multiple cores, and each core has its own independent L2 cache, which is called a private L2 cache. In contrast to a shared L2 cache, a private L2 cache is only used by the current core and cannot be used by other cores.

[0056] Specifically, the first-level data cache 10 is also called L1 dcache, which is used to store data recently used by the processor. It is a cache level close to the processor core, and the data access speed is extremely fast. For example, the data variables accessed in a loop body will be stored in the first-level data cache 10, so that when the processor needs these data again, it can be quickly obtained from L1 dcache without having to read from a slower storage level (such as main memory), which greatly improves the efficiency of data reading.

[0057] The first level instruction cache 20 is also called L1 icache, which is used to store instructions that are executed multiple times by the processor. During program execution, the processor will extract instructions from L1 icache in sequence for execution. The first level instruction cache is located close to the core and can quickly provide instructions to the processor to ensure efficient operation of the program. For example, when executing a complex function call, the instructions of the function will be pre-loaded into L1 icache so that the processor can quickly obtain and execute these instructions.

[0058] Among them, in modern processors, the instruction pipeline is an important means to improve performance. L1 icache can provide a stable instruction stream for the instruction pipeline, ensuring that instructions at different stages can be obtained in a timely manner. For example, in a five-stage instruction pipeline (fetch, decode, execute, access, write back), L1 icache is responsible for providing instructions for the instruction fetch stage to ensure the smooth operation of the pipeline.

[0059] The above-mentioned second-level private cache 30 is also called private L2 cache, abbreviated as PL2, which is a cache structure of a higher level than the first-level data cache and the first-level instruction cache in the processor. PL2 and the first-level data cache L1 dcache are inclusive, that is, if a cache line exists in L1 dcache, then it must also exist in PL2.

[0060] In this embodiment, by setting up the secondary private cache 30, it is possible to reduce the competition for cache resources between cores and reduce cache access latency, thereby improving the performance of a single core. In addition, since PL2 and the primary data cache L1 dcache are included, the frequency of the cache consistency control unit snooping the primary data cache L1 dcache can be reduced, and the secondary private cache PL2 can be directly checked to obtain some required information, thereby reducing the occupancy of the primary data cache L1 dcache bandwidth and improving system performance.

[0061] The above-mentioned secondary private prefetch cache 40 is also called PL2 prefetch, and its main function is to predict the data that the processor may need in the future, and extract these data from the main memory or other hierarchical storage to PL2 (private secondary cache) in advance. Specifically, the secondary private prefetch cache 40 uses a preset prefetch algorithm to calculate the prefetch address, and then encapsulates the prefetch address into a prefetch request, and sends the prefetch request to the secondary private cache 30, so that the secondary private cache 30 prefetches the cache line into the secondary private cache 30 according to the prefetch address.

[0062] In this embodiment, by setting up a secondary private prefetch cache 40, the required data can be acquired in advance according to the data processing mode, so that when the processor really needs these data, they are already in PL2, which greatly improves the cache hit rate and reduces the data acquisition delay. In addition, PL2 prefetch can reduce the time the processor waits for data to be transmitted from the main memory. In modern processor systems, the main memory access speed is relatively slow, and the prefetch operation can effectively use the time when the processor performs other tasks to acquire data in advance. For example, when processing large data sets (such as image processing, data mining and other applications), PL2 prefetch can acquire the next batch of required data in advance according to the data processing mode, thereby improving the processing efficiency of the entire system.

[0063] The cache consistency control unit 50 is also called a snoop control unit (SCU). The main function of the SCU is to ensure the consistency of data in the cache of each core. It achieves this goal by snooping the cache operations of each core. For example, when a core modifies the data in its cache, the SCU will detect the modification and notify other cores to update or invalidate the corresponding data in their caches according to the cache consistency protocol, which can be, for example, the MESI protocol.

[0064] Optionally, the SCU is also used to monitor the cache line status of each core of the processor. For example, cache line status information can be obtained by checking the shadow tagram in the second-level private cache (PL2). Based on these states, the SCU can initiate different types of snooping transactions (such as readshared, readunique, etc.) to ensure that data is correctly shared and updated between different cores.

[0065] In the embodiment of the present application, by setting up SCU, cache consistency issues can be discovered and handled in a timely manner, reducing such risks. For example, in a multi-threaded application, different threads may run on different cores and may access the same data. SCU can ensure that the data seen by these threads is consistent, avoiding program exceptions caused by inconsistent data.

[0066] It can be understood that the first-level data cache (L1 dcache) and the first-level instruction cache (L1 icache) are first-level caches closer to the core. When a data load operation needs to be performed, if the required data is not available in the first-level data cache, the data will be requested from the second-level private cache (PL2). When the required data is not available in the second-level private cache (PL2), a read data request read transaction will be sent to the cache consistency control unit (SCU) to obtain the required data from the cache consistency control unit. In other words, during the data loading operation, the cache system searches for data level by level. Starting from the L1 cache closest to the core, search PL2 and SCU in turn to ensure that the data can be correctly loaded to the location required by the core.

[0067] The processor cache structure in the embodiment of the present application includes: a first-level data cache, a first-level instruction cache, a second-level private cache, a second-level private prefetch cache, and a cache consistency control unit; the second-level private cache is connected to the first-level data cache, the first-level instruction cache, the second-level private prefetch cache, and the cache consistency control unit respectively; the first-level data cache is used to: store data accessed multiple times by the current core of the processor; the first-level instruction cache is used to: store instructions executed multiple times by the current core; the second-level private cache is used to: store data read by the current core from the main memory or a high-level cache; the high-level cache is a cache with a higher level than the second-level private cache; the second-level private prefetch cache is used to: use a preset algorithm to calculate the prefetch address and send a prefetch request to the second-level private cache, so that the second-level private cache prefetches the cache line according to the prefetch address; the cache consistency control unit is used to: monitor the cache operations of each core of the processor. The technical solution in the present application can effectively reduce the mutual interference in cache access between the cores by independently allocating a second-level private cache to each core on the basis of setting a first-level data cache and a first-level instruction cache, so that each core can quickly access its own second-level private cache without waiting for other cores to release cache resources, thereby significantly reducing data access latency. The second-level private prefetch cache uses a preset algorithm to calculate the prefetch address, so that the second-level private cache prefetches data to the cache line in advance according to the prefetch address, reducing data acquisition time. The cache operations of each core of the processor are monitored by the cache consistency control unit to ensure the consistency of data cache operations, thereby improving the overall performance of the processor.

[0068] In an optional embodiment of the present application, the secondary private cache 30 includes a plurality of cache lines, and the data in the cache lines includes at least one of the following data states: shared-dirty, unique-dirty, invalid, shared-clean, unique-clean;

[0069] shared-dirty is used to indicate that the data in a cache line exists in the caches of multiple cores and has been modified; unique-dirty is used to indicate that the data in a cache line only exists in the cache of the current core and has been modified; invalid is used to indicate that the data in a cache line is invalid; shared-clean is used to indicate that the data in a cache line exists in the caches of multiple cores and has not been modified; unique-clean is used to indicate that the data in a cache line only exists in the cache of the current core and has not been modified.

[0070] It should be noted that the secondary private cache can store both data and instructions, and can store data that the processor has recently used and instructions to be executed. For example, in applications that process large data sets, frequently accessed data will be stored in the secondary private cache to facilitate the processor to quickly obtain and process it. The above multiple cache lines can be arranged according to preset rules, and the data in each cache line has a corresponding state, which can be updated in real time according to the data flow.

[0071] In this embodiment, different data states determine the operation mode when reading, writing and accessing data by other cores. When data needs to be read or written, the appropriate operation mode can be quickly determined according to these data states. For example, for data in the "shared - clean" state, the read operation can be performed directly because the data is shared and has not been modified, and cache consistency issues will not be caused. For data in the "unique - dirty" state, when other cores need to read, data synchronization operations must be performed first to ensure data consistency. This precise state-based operation can avoid unnecessary operations and improve the efficiency of data processing.

[0072] In this embodiment, by setting corresponding different data states for the data in the cache line, it is helpful to carefully monitor and manage the flow and modification of the data in the cache line, and provide basic guidance information for subsequent cache operations. The cache operation may include, for example, a read operation, a pre-fetch operation, and an SCU snoop operation, which facilitates the execution of corresponding operations on the data and improves data processing efficiency.

[0073] In an optional embodiment of the present application, see Figure 2 As shown, Figure 2 The schematic diagram of the structure of the second-level private cache provided in the embodiment of the present application is as follows: The second-level private cache 30 includes a shadow tag memory 31 , a register configuration unit 32 , a plurality of line buffers 33 , and a cache 34 .

[0074] The shadow tag memory 31 is used to store the data status corresponding to all cache lines in the secondary private cache 30; the register configuration unit 32 is used to configure the parameters in the secondary private cache 30; each line cache 33 is used to temporarily store data read from or written to the cache; the cache 34 is used to store data read by the current core from the main memory or the high-level cache.

[0075] It should be noted that the shadow tag memory 31 is also called shadow tag ram, which is used to store tag information of cache lines. The tag information facilitates fast positioning and identification of data in the cache.

[0076] The register configuration unit 32 is also called configure, which is used to configure the parameters in the cache system, for example, the cache size, line size, replacement strategy, prefetch strategy, etc. can be set. The replacement strategy can be, for example, Least Recently Used LRU, First In First Out FIFO, etc. Multiple line buffers 33 are also called: line buffers, which are used to temporarily store data read from or written to the cache. These buffers play a role of cache in the data transmission process, which helps to improve the efficiency of data transmission. Cache 34 refers to the actual cache storage area in the secondary private cache, which is used to store data frequently accessed by the processor to reduce the number of accesses to the main memory, thereby improving system performance. Among them, cache 34 can store data read by the current core from the main memory or high-level cache. The high-level cache refers to a cache structure with a higher level than the secondary private cache, such as a three-level cache structure, a four-level cache structure, etc.

[0077] It is understandable that the row buffer 33 is widely used for data transmission between caches at all levels. For example, between the first-level data cache and the second-level private cache, the row buffer can coordinate the read and write operations of data to improve the overall performance of the cache system. The shadow tag memory stores the data status corresponding to all cache lines in the second-level private cache.

[0078] In the present embodiment, shadow tag memory is set in the secondary private cache to help locate data in the cache, cache parameters can be adjusted to optimize performance by setting the register configuration unit, and row cache is set to facilitate coordination of data transmission between the cache and other components. The shadow tag memory, register configuration unit, row cache and cache are coordinated with each other so that the entire cache system can run efficiently, improve cache hit rate, reduce data access delay, and thus improve the overall performance of the processor.

[0079] In an optional embodiment of the present application, the secondary private cache 30 is specifically used for:

[0080] Receive and respond to a cache operation request, obtain target cache line data and send it to a cache coherence control unit, and update the data state of the target cache line data;

[0081] Among them, the cache operation request is that the cache consistency control unit checks the shadow tag memory in the secondary private cache, obtains the data status of all cache lines in the secondary private cache from the shadow tag memory, and sends it to the secondary private cache according to the data status; the cache operation request includes a data sharing read request and a data exclusive read request.

[0082] It should be noted that the above-mentioned target cache line data refers to data whose data status meets the data requirements. When the cache consistency control unit 50 performs cache consistency control operations, it needs to first check the shadow tag memory shadow tagram from the secondary private cache, and obtain the data status of all cache lines cacheline in the secondary private cache 30 from the shadow tag memory shadow tagram, and then generate a cache operation request according to the data status, and send a corresponding cache operation request snoop transaction to the secondary private cache 30. The cache operation request may include, for example, two types, namely, a data shared read request readshared and a data exclusive read request readunique.

[0083] After receiving the cache operation request, the L2 private cache 30 may obtain the target cache line data according to the address information and data status in the cache operation request, and send the target cache line data to the cache coherence control unit 50. Furthermore, the data status of the target cache line data is updated.

[0084] In this embodiment, the secondary private cache receives and responds to cache operation requests, obtains target cache line data and sends it to the cache consistency control unit, which can help to achieve data sharing and synchronization between different cores, and update the data status of the target cache line data, so as to accurately track changes in cache line data.

[0085] In an optional embodiment of the present application, the secondary private cache 30 is further used for:

[0086] Receive a data exclusive read request sent by a cache consistency control unit, and allocate the data exclusive read request to a row cache; the data exclusive read request carries a data read address; query the shadow tag memory through the row cache, and simultaneously search whether there is target data corresponding to the data read address in the cache; when the data state of the target data in the shadow tag memory is valid, send a data exclusive read request to the primary data cache to obtain the target data, and update the data state of the target data to an invalid state;

[0087] When the data state of the target data in the cache is valid, the target data is acquired and sent to the row buffer, and the data state of the target data is updated to an invalid state; and the target data is sent to the cache consistency control unit through the row buffer.

[0088] It should be noted that, taking the data exclusive read request as readunique as an example, after the L2 private cache 30 (PL2) receives the data exclusive read request readunique from the L1 data cache L1 dcache, the data exclusive read request carries a data read address, which is used to uniquely represent the address information for obtaining data. Readunique is assigned to a line buffer in a certain L2 private cache 30, and then the shadow tag memory shadow tagram in PL2 is queried, and at the same time, the cache is queried whether there is target data corresponding to the data read address.

[0089] If the shadow tag memory shadow tagram is valid, a read unique is initiated to the first-level data cache L1dcache to obtain the corresponding target data. At the same time, the first-level data cache dcache will also change the corresponding cache line cacheline from a valid state to an invalid state.

[0090] If the data status of the target data in the cache is valid, the cache will return the target data to the line buffer, and change the corresponding cacheline from valid to invalid. And send the target data to the cache consistency control unit.

[0091] It can be understood that the above-mentioned target data is data corresponding to the data reading address, and can be represented in any form, for example, in a table form, in a picture form, or in a text form. This embodiment does not impose any limitation on the form of expression of the target data.

[0092] In this embodiment, the secondary private cache receives the data exclusive read request sent by the cache consistency control unit, and queries the shadow tag memory while searching whether there is target data corresponding to the data read address in the cache. It can accurately send the target data to the cache consistency control unit, thereby improving data processing efficiency.

[0093] In an optional embodiment of the present application, the secondary private cache is also used for:

[0094] Receive a data exclusive read request sent by the first-level data cache, and distribute the data exclusive read request to the row cache; the data exclusive read request carries a data read address; query the cache of the second-level private cache through the row cache whether there is a cache line corresponding to the data read address; when the cache line exists, send a data exclusive read request to the cache consistency control unit, mark the copies of other cores as invalid, obtain target data and send it to the first-level data cache; other cores are all cores of the processor except the current core; when the cache line does not exist, send a data exclusive read request to the cache consistency control unit, obtain data from other cores or the next-level cache, mark the copies in other cores as invalid, obtain target data and send it to the first-level data cache.

[0095] It should be noted that when the first-level data cache L1 dcache needs to obtain data, it can send a data exclusive read request readunique to the second-level private cache PL2. After receiving the readunique sent by the first-level data cache L1 dcache, the second-level private cache allocates readunique to a line buffer linebuffer, and then queries whether there is a cache line cacheline corresponding to the data read address in the second-level private cache PL2. If the cache line cacheline exists in the second-level private cache PL2, it sends a data exclusive read request cleanunique to the cache consistency control unit, changes the copy in other cores to invalid state, obtains the target data and sends it to the first-level data cache; other cores core are all cores of the processor except the current core.

[0096] When there is no cache line cacheline, a data exclusive read request readunique is sent to the cache consistency control unit to obtain data from other cores or the next level cache, and the copies in other cores are marked as invalid, and the target data is obtained and sent to the first level data cache L1 dcache.

[0097] In this embodiment, the second-level private cache receives the data exclusive read request sent by the first-level data cache, and queries through the row cache whether there is a cache line corresponding to the data read address in the cache of the second-level private cache, and returns the corresponding target data to the first-level data cache according to the existence result, which can save cache bandwidth, effectively handle exclusive data changes, and improve system performance and efficiency.

[0098] In an optional embodiment of the present application, the secondary private cache is also used for:

[0099] When receiving a data write back request sent by the first-level data cache, the data write back request is allocated to the row cache; the data write back request includes write-back data and a data write address; the write-back data is written to the cache in the second-level private cache through the row cache; when other cache lines in the second-level private cache are replaced, check whether there is a cache line with the same data write address in the first-level data cache; if so, read the cache line from the first-level data cache and update the data status to an invalid status, and write the replaced data back to the cache consistency control unit; when no other cache lines in the second-level private cache are replaced, end the operation.

[0100] It should be noted that when the first-level data cache L1 dcache needs to write back data, it can send a data writeback request writeback to the second-level private cache PL2. After receiving the writeback sent by the first-level data cache L1 dcache, the second-level private cache allocates the writeback to a linebuffer line cache and directly writes the data to the cache of the second-level private cache PL2 according to the data write address.

[0101] After writing the data into the cache, you can continue to determine whether other cache lines are replaced. If other cache lines are replaced, in order to ensure the inclusive property, you need to snoop the first-level data cache L1 dcache, obtain the cache line cacheline with the same address as the data write address, read the cache line from the first-level data cache dcache and update it to the invalid state, and then write the replaced data to the cache consistency control unit SCU; if no other cache lines are replaced, the operation ends.

[0102] In this embodiment, by receiving a data write back request sent by the first-level data cache and distributing the data write back request to the row cache, the cache can be efficiently managed in a multi-core environment, ensuring data consistency and high performance.

[0103] On the other hand, an embodiment of the present application further provides a processor, which includes the processor cache structure of the above-mentioned embodiment, wherein the solution in the embodiment of the present application can be implemented using various computer languages, for example, object-oriented programming language Java and interpreted scripting language JavaScript.

[0104] The processor provided in the embodiment of the present application can be applied to a computer device, see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 3 As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), an operating system and a computer program, etc. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data reading and writing processing method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0105] The processor provided in this embodiment includes the above-mentioned processor cache structure. By independently allocating a second-level private cache to each core on the basis of setting a first-level data cache and a first-level instruction cache, the mutual interference in cache access between the cores can be effectively reduced, so that each core can quickly access its own second-level private cache without waiting for other cores to release cache resources, thereby significantly reducing data access latency, and using a preset algorithm to calculate the prefetch address through the second-level private prefetch cache, so that the second-level private cache prefetches data to the cache line in advance according to the prefetch address, thereby reducing data acquisition time, and monitoring the cache operations of each core of the processor through the cache consistency control unit to ensure the consistency of data cache operations, thereby improving the overall performance of the processor.

[0106] See also Figure 4 The following embodiments take the above-mentioned computer device as the execution subject, and apply the data caching method provided in the embodiments of the present application to the above-mentioned computer device to perform instruction processing as an example for specific description. The computer device includes the above-mentioned processor cache structure, and the data caching method provided in the embodiments of the present application is applied to the processor cache structure as described in any of the above items, and the method includes the following steps 201-202:

[0107] Step 201: The secondary private prefetch cache calculates a prefetch address using a preset prefetch algorithm and sends a prefetch request to the secondary private cache; the prefetch request includes the prefetch address.

[0108] Step 202: The L2 private cache receives and responds to the prefetch request, and prefetches a cache line according to the prefetch address.

[0109] It should be noted that the above-mentioned private L2 cache PL2 (private L2 cache) is a core-private L2 cache, which means that each core has its own independent L2 cache and will not be shared with other cores. The above-mentioned private L2 prefetch cache private L2 prefetch can pre-calculate the prefetch address using a prefetch algorithm.

[0110] Specifically, when the processor executes a program, the prefetch algorithm predicts future memory access requirements based on the current memory access pattern. The prefetch algorithm needs to consider multiple factors, such as historical access patterns, program behavior characteristics, etc., to determine which data blocks are most likely to be accessed in the near future. Once the locations of these data blocks are determined, their addresses will be used as prefetch addresses.

[0111] After determining the prefetch address, the secondary private prefetch cache sends a prefetch request to the secondary private cache. The prefetch request includes the prefetch address. The prefetch request is used to indicate that a specific data block needs to be obtained from the main memory.

[0112] After receiving the prefetch request, the L2 private cache retrieves the data from the slower storage level (usually the main memory) according to the provided prefetch address and stores the data in the cache. In this way, when the processor actually needs the data, it can be quickly obtained directly from the L2 cache without accessing the slower main memory again.

[0113] In this embodiment, by pre-fetching data into the secondary private cache, the delay caused by waiting for data to be transferred from the main memory to the processor can be reduced, which significantly improves the overall performance of the system and makes more efficient use of system resources. Especially in a multi-core processor environment, each core can have its own secondary private cache, thereby reducing competition for shared resources.

[0114] In an optional embodiment of the present application, the above method further includes:

[0115] The second-level private cache receives and responds to cache operation requests, obtains target cache line data and sends it to the cache consistency control unit, and updates the data status of the target cache line data; wherein, the cache operation request is that the cache consistency control unit checks the shadow tag memory in the second-level private cache, obtains the data status of all cache lines in the second-level private cache from the shadow tag memory, and sends it to the second-level private cache according to the data status; the cache operation request includes a data sharing read request and a data exclusive read request.

[0116] It should be noted that the cache consistency control unit SCU can first obtain the shadow tag memory of the secondary private cache, which stores the data status of each cache line, and the data status includes: shared-dirty, unique-dirty, invalid, shared-clean, unique-clean; then encapsulate the data according to the data status to generate a cache operation request and send it to the secondary private cache, and the cache operation request includes a data shared read request and a data exclusive read request.

[0117] Among them, when a processor or core needs to read a data item but does not intend to modify it, a data sharing read request is issued. This means that multiple processors or cores can hold copies of the data item at the same time, and all copies remain consistent. It is mainly used in read-only scenarios, allowing multiple processors or cores to access the same data concurrently without interfering with each other. When processing such a request, if the data item is already in the cache of a processor and its state allows sharing, a copy of the data item can be distributed to the requester, and its cache state is updated to reflect the new shared state.

[0118] Exclusive Read Requests are issued when a processor or core wants not only to read a data item but also intends to modify it subsequently. This type of request ensures that only the requester has access to the data item and that no other processor or core can hold a copy of the data item at the same time. The purpose is to ensure data consistency and correctness, especially before write operations. By obtaining exclusive access to data items, data contention and inconsistency issues can be avoided. When processing such a request, if the data item is currently in a shared state, the system must first invalidate the copies of all other processors or cores (i.e., remove them from their caches), then convert the state of the data item to an exclusive state, and finally provide the data item to the requester.

[0119] The secondary private cache receives and responds to the cache operation request, parses and processes the cache operation request, obtains the target cache line data and sends it to the cache consistency control unit, and then updates the data status of the target cache line data.

[0120] In this embodiment, the secondary private cache receives and responds to cache operation requests, obtains target cache line data and sends it to the cache consistency control unit, so that the multi-processor system can effectively manage the data in the cache, support high-concurrency reading, and ensure data consistency and integrity.

[0121] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0122] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0123] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0126] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0127] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A processor cache structure, characterized in that: The processor cache structure comprises: A first-level data cache, a first-level instruction cache, a second-level private cache, a second-level private prefetch cache, and a cache consistency control unit; the second-level private cache is respectively connected to the first-level data cache, the first-level instruction cache, the second-level private prefetch cache, and the cache consistency control unit; The first-level data cache is used to: store data that is accessed multiple times by the current core of the processor; The first-level instruction cache is used to: store instructions executed multiple times by the current core; The second-level private cache is used to: store data read by the current core from the main memory or the high-level cache; the high-level cache is a cache with a higher level than the second-level private cache; The secondary private prefetch cache is used to: calculate a prefetch address using a preset algorithm and send a prefetch request to the secondary private cache, so that the secondary private cache prefetches a cache line according to the prefetch address; The cache consistency control unit is used to: monitor the cache operations of each core of the processor; The secondary private cache includes a plurality of cache lines, and the data in the cache lines includes at least one of the following data states: shared-dirty, unique-dirty, invalid, shared-clean, and unique-clean; The shared-dirty is used to characterize that the data in the cache line exists in the caches of multiple cores and has been modified; the unique-dirty is used to characterize that the data in the cache line only exists in the cache of the current core and has been modified; the invalid is used to characterize that the data in the cache line is invalid; the shared-clean is used to characterize that the data in the cache line exists in the caches of multiple cores and has not been modified; the unique-clean is used to characterize that the data in the cache line only exists in the cache of the current core and has not been modified.

2. The processor cache structure according to claim 1, characterized in that: The secondary private cache includes a shadow tag memory, a register configuration unit, a plurality of line buffers, and a cache; The shadow tag memory is used to: store data states corresponding to all cache lines in the secondary private cache; The register configuration unit is used to: configure parameters in the secondary private cache; Each of the row buffers is used to: temporarily store data read from or written to the buffer; The cache is used to store data read by the current core from the main memory or the high-level cache.

3. The processor cache structure according to claim 1, characterized in that: The secondary private cache is specifically used for: Receiving and responding to a cache operation request, acquiring target cache line data and sending it to the cache coherence control unit, and updating a data state of the target cache line data; Among them, the cache operation request is that the cache consistency control unit checks the shadow tag memory in the secondary private cache, obtains the data status of all cache lines in the secondary private cache from the shadow tag memory, and sends it to the secondary private cache according to the data status; the cache operation request includes a data shared read request and a data exclusive read request.

4. The processor cache structure according to claim 3, characterized in that: The secondary private cache is also used for: receiving a data exclusive read request sent by a cache consistency control unit, and allocating the data exclusive read request to a row buffer; the data exclusive read request carries a data read address; querying the shadow tag memory through the row buffer and searching whether there is target data corresponding to the data read address in the cache; When the data state of the target data in the shadow tag memory is valid, sending the data exclusive read request to the primary data cache to obtain the target data, and updating the data state of the target data to an invalid state; When the data state of the target data in the cache is valid, acquiring the target data and sending it to the row buffer, and updating the data state of the target data to an invalid state; The target data is sent to the cache coherence control unit through the row buffer.

5. The processor cache structure according to claim 3, characterized in that: The secondary private cache is also used for: receiving a data exclusive read request sent by the primary data cache, and allocating the data exclusive read request to a row cache; the data exclusive read request carries a data read address; querying, through the row buffer, whether there is a cache line corresponding to the data read address in the cache of the secondary private cache; When the cache line exists, sending a data exclusive read request to the cache consistency control unit, marking the copies of other cores as invalid, acquiring the target data and sending it to the first-level data cache; The other cores are cores other than the current core among all the cores of the processor; When the cache line does not exist, the data exclusive read request is sent to the cache consistency control unit, data is obtained from other cores or the next level cache, and the copies in the other cores are marked as invalid, and the target data is obtained and sent to the first level data cache.

6. The processor cache structure according to claim 3, characterized in that: The secondary private cache is also used for: When receiving a data write-back request sent by the primary data cache, allocating the data write-back request to the row cache; the data write-back request includes write-back data and a data write address; Writing the write-back data into a cache in the secondary private cache through the row cache; When other cache lines in the secondary private cache are replaced, checking whether there is a cache line in the primary data cache that is the same as the data write address; If it exists, read the cache line from the first-level data cache and update the data state to an invalid state, and write the replaced data back to the cache consistency control unit; When no other cache line in the secondary private cache is replaced, the operation ends.

7. A processor, characterized in that: The processor comprises a processor cache structure as described in any one of claims 1 to 6 above.

8. A data caching method, characterized in that: Applied to the processor cache structure as described in any one of claims 1 to 6 above, the data cache method comprises: The secondary private prefetch cache calculates a prefetch address using a preset prefetch algorithm, and sends a prefetch request to the secondary private cache; the prefetch request includes the prefetch address; The secondary private cache receives and responds to the prefetch request, and prefetches a cache line according to the prefetch address.

9. The data caching method according to claim 8, characterized in that: The method further comprises: The secondary private cache receives and responds to the cache operation request, obtains the target cache line data and sends it to the cache consistency control unit, and updates the data state of the target cache line data; Among them, the cache operation request is that the cache consistency control unit checks the shadow tag memory in the secondary private cache, obtains the data status of all cache lines in the secondary private cache from the shadow tag memory, and sends it to the secondary private cache according to the data status; the cache operation request includes a data shared read request and a data exclusive read request.

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