Method, device, electronic device and storage medium for generating high-speed serial signals

Abstract

The embodiments of the present application relate to a method, device, electronic device and storage medium for generating a high-speed serial signal, and relate to the field of signal source technology. The method for generating a high-speed serial signal includes: obtaining a mode selection signal, the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode; if the first selection control information is control-on information and the second selection control information is control-off information, then determining the intermediate sampling rate according to the expected bit rate set by the user, and determining the first output sampling rate according to the intermediate sampling rate; generating a high-speed serial signal according to the first output sampling rate. The embodiments of the present application calculate and use an intermediate sampling rate, which can effectively reduce the amount of calculation at low bit rates and effectively improve the calculation accuracy and quality of high-speed serial signals at high bit rates, and support multiple modes at the same time, and users can flexibly choose.

Description

Technical Field

[0001] The present application relates to the field of signal source technology, and in particular to a method, device, electronic device, and storage medium for generating a high-speed serial signal. Background Art

[0002] The high-speed serial signal option in the AWG (Arbitrary Waveform Generator) signal source allows users to set any bit rate to generate high-speed serial signals. When the bit rate is set very low or very high, the following drawbacks may occur: If the bit rate is very low, each symbol duration may contain too many sampling points, resulting in a very large amount of calculation for each symbol and, if the symbol length is very long, the required storage space will be very large. If the bit rate is very high, the number of sampling points may be too small, making it difficult to accurately construct the edges of each symbol, resulting in low-quality high-speed serial signals. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a method, apparatus, electronic device, and storage medium for generating a high-speed serial signal to solve at least one problem existing in the background technology.

[0004] In a first aspect, an embodiment of the present application provides a method for generating a high-speed serial signal, comprising:

[0005] Acquire a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0006] If the first selection control information is control-on information and the second selection control information is control-off information, determining an intermediate sampling rate according to a desired bit rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate;

[0007] A high-speed serial signal is generated according to the first output sampling rate.

[0008] In conjunction with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to the expected bit rate set by the user includes:

[0009] Determine the reference sampling rate according to the expected bit rate set by the user;

[0010] An intermediate sampling rate is determined according to the reference sampling rate.

[0011] In combination with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to the reference sampling rate includes:

[0012] An intermediate sampling rate is determined according to a multiple relationship between the reference sampling rate and the maximum sampling rate.

[0013] In conjunction with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to a multiple relationship between the reference sampling rate and the maximum sampling rate includes:

[0014] If the reference sampling rate is greater than or equal to the maximum sampling rate, determining an integer executable decimation multiple based on the reference sampling rate and the maximum sampling rate;

[0015] An intermediate sampling rate is determined based on the executable decimation factor.

[0016] In conjunction with the first aspect, in an optional implementation manner, determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0017] Determining a reference decimation multiple according to the reference sampling rate and the maximum sampling rate;

[0018] An integer executable decimation factor that satisfies a first condition is determined based on the reference decimation factor, where the first condition is that a first deviation between the reference decimation factor and the executable decimation factor is within a first preset deviation range.

[0019] In conjunction with the first aspect, in an optional implementation manner, determining the intermediate sampling rate based on a multiple relationship between the reference sampling rate and the maximum sampling rate further includes:

[0020] If the reference sampling rate is less than the maximum sampling rate, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0021] An intermediate sampling rate is determined according to the executable interpolation factor.

[0022] In combination with the first aspect, in an optional implementation manner, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0023] Determining a reference interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0024] An integer executable interpolation multiple that satisfies a second condition is determined according to the reference interpolation multiple, where the second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

[0025] In conjunction with the first aspect, in an optional implementation manner, the method further includes:

[0026] If the first selection control information is control-on information and the second selection control information is control-on information, determining an intermediate sampling rate according to a desired bit rate set by a user, and determining the second output sampling rate as a maximum sampling rate according to the intermediate sampling rate;

[0027] A high-speed serial signal is generated according to the second output sampling rate.

[0028] In conjunction with the first aspect, in an optional implementation manner, the method further includes:

[0029] If the first selection control information is control-off information and the second selection control information is control-on information, determining the intermediate sampling rate as the maximum sampling rate and determining the third output sampling rate as the maximum sampling rate;

[0030] A high-speed serial signal is generated according to the third output sampling rate.

[0031] In a second aspect, an embodiment of the present application provides a device for generating a high-speed serial signal, comprising:

[0032] An acquisition unit, configured to generate a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0033] a first mode unit, configured to determine an intermediate sampling rate according to a desired bit rate set by a user, and determine a first output sampling rate according to the intermediate sampling rate, if the first selection control information is control-on information and the second selection control information is control-off information;

[0034] The first high-speed serial signal generating unit is configured to generate a high-speed serial signal according to the first output sampling rate.

[0035] In a third aspect, an embodiment of the present application provides an electronic device, including:

[0036] processor; and

[0037] A memory stores computer-executable instructions, which are used by the processor to execute the method for generating a high-speed serial signal.

[0038] In a fourth aspect, an embodiment of the present application provides a storage medium having computer-executable instructions stored thereon, wherein the computer-executable instructions are executed by a processor to execute the above-mentioned method for generating a high-speed serial signal.

[0039] The beneficial effects brought about by the technical solution provided by the embodiment of the present application include: by using the first selection control information of the intermediate sampling rate mode as the control-on information and the second selection control information of the fixed output sampling rate mode as the control-off information, the intermediate sampling rate is determined according to the expected code rate set by the user, and the first output sampling rate is determined according to the intermediate sampling rate, so that the sampling rate corresponding to the expected code rate set by the user is adjusted to the intermediate sampling rate, the intermediate sampling rate is reasonably selected, and then the output sampling rate can be reasonably selected. In other words, when the expected code rate is very low or very high, the number of sampling points is more reasonable, which can effectively reduce the amount of calculation, save calculation time, and improve the accuracy of the code element edge construction, effectively improving the quality of the generated high-speed serial signal.

[0040] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the embodiments of the present application and constitute a part of the embodiments of the present application. The illustrative embodiments of the embodiments of the present application and their descriptions are used to explain the embodiments of the present application and do not constitute an improper limitation on the embodiments of the present application. In the drawings:

[0042] Figure 1 A flowchart of a specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0043] Figure 2 This is a flowchart of another specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0044] Figure 3 This is a flowchart of another specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0045] Figure 4 This is a flowchart of another specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0046] Figure 5 A block diagram showing a specific example of a process for generating a high-speed serial signal in an embodiment of the present application;

[0047] Figure 6 This is a principle block diagram of a specific example of a device for generating a high-speed serial signal in an embodiment of the present application;

[0048] Figure 7 This is a principle block diagram of a specific example of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0049] To make the technical solutions and beneficial effects of the embodiments of the present application more clearly understood, the following detailed description is given by way of enumerating specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly illustrate the details of the local features. Unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which the embodiments of the present application belong.

[0050] It should be noted that the terms "first", "second", etc. may be used in this document to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. When describing "first", it does not necessarily mean that there is a "second"; and when discussing "second", it does not mean that there is necessarily a "first" in this application. The singular forms "one", "an" and "said / the" may also be intended to include plural forms, unless the context clearly indicates otherwise. The term "includes" is used to determine the existence of the included features, but does not exclude the existence or addition of one or more other features. The term "and / or" includes any and all combinations of the relevant listed items.

[0051] It should be noted that the high-speed serial signal option in an AWG signal source allows users to set any bit rate within a wide range, such as from 500Kbps to the maximum sampling rate Fs (typically, the maximum sampling rate of an AWG signal source is up to 5GSa / s, 10GSa / s, or even exceeding 100GSa / s). Furthermore, users can set the bit rate with high precision and resolution, for example, setting the high-speed serial signal bit rate to 1.1235Mbps.

[0052] As a result, the following situations are usually encountered:

[0053] 1. The bit rate is very low, far less than the maximum sampling rate. When generating a high-speed serial signal, the duration of each symbol will be many times the sampling period corresponding to the maximum sampling rate, and each symbol duration will contain many sampling points. For example, when generating a high-speed serial signal with a bit rate of 1Mbps, assuming a maximum sampling rate of 5GSa / s, each symbol duration will contain 5000 sampling points, resulting in a very large amount of computation for each symbol.

[0054] If the symbol length is very long, the required storage space will often be very large. For example, if a 100Mbit symbol generates a high-speed serial signal with a bit rate of 1Mbps, assuming a maximum sampling rate of 5GSa / s, the memory required will be able to store approximately 500G sample points. However, AWGs are rarely equipped with such a large storage space.

[0055] 2. The bit rate is very high, close to the maximum sampling rate. When generating high-speed serial signals, the number of sampling points within each symbol duration is too small. For example, when generating a high-speed serial signal with a bit rate of 2500Mbps, assuming a maximum sampling rate of 5GSa / s, each symbol duration will contain only two sampling points. This small number of sampling points makes it difficult to accurately construct the edges of each symbol, resulting in low-quality high-speed serial signals.

[0056] 3. Because arbitrary bit rate settings and high-precision settings are supported, there is usually a non-integer multiple relationship between the bit rate and the maximum sampling rate. Each code element duration contains a non-integer multiple of sampling points, affecting the accuracy of the generated high-speed serial signal.

[0057] The present invention provides a method for generating a high-speed serial signal, which can be applied to instruments such as AWG signal sources, such as Figure 1 As shown, the method for generating a high-speed serial signal includes:

[0058] S100, obtaining a mode selection signal, where the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0059] S200: If the first selection control information is control-on information and the second selection control information is control-off information, determining an intermediate sampling rate according to a desired bit rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate;

[0060] S300 , generating a high-speed serial signal according to a first output sampling rate.

[0061] In an embodiment of the present application, the first selection control information is used to indicate whether to turn on the intermediate sampling rate mode, and the second selection control information is used to indicate whether to turn on the fixed output sampling rate mode. If the first selection control information is the control on information (ON), it indicates that the intermediate sampling rate mode is turned on. If the first selection control information is the control off information (OFF), it indicates that the intermediate sampling rate mode is turned off. If the second selection control information is the control on information (ON), it indicates that the fixed output sampling rate mode is turned on. If the second selection control information is the control off information (OFF), it indicates that the fixed output sampling rate mode is turned off. The expected bit rate set by the user can be an integer bit rate or a small bit rate of arbitrary precision. The maximum sampling rate is the DAC (digital to analog) sampling rate set by the user. The intermediate sampling rate is used to control the number of sampling points within a reasonable range, thereby reducing the amount of calculation and the required storage space, and also improving the quality of the generated high-speed serial signal. By setting the first selection control information of the intermediate sampling rate mode as control-on information and the second selection control information of the fixed output sampling rate mode as control-off information, the intermediate sampling rate is determined according to the expected bit rate set by the user, and the first output sampling rate is determined according to the intermediate sampling rate, so that the sampling rate corresponding to the expected bit rate set by the user is adjusted to the intermediate sampling rate, the intermediate sampling rate is reasonably selected, and then the output sampling rate can be reasonably selected. In this way, when the expected bit rate is very low or very high, the number of sampling points is more reasonable, which can effectively reduce the amount of calculation, save calculation time, and improve the accuracy of the code element edge construction, thereby effectively improving the quality of the generated high-speed serial signal.

[0062] In an alternative embodiment, if Figure 2 As shown, determining the intermediate sampling rate according to the desired bit rate set by the user includes:

[0063] S201, determining a reference sampling rate according to an expected bit rate set by a user;

[0064] S202: Determine an intermediate sampling rate according to a reference sampling rate.

[0065] In an optional implementation, determining the intermediate sampling rate according to the reference sampling rate includes:

[0066] S202-1. Determine an intermediate sampling rate according to a multiple relationship between a reference sampling rate and a maximum sampling rate.

[0067] Preferably, according to the multiple relationship between the reference sampling rate and the maximum sampling rate, the intermediate sampling rate is determined as follows:

[0068] S202-11, if the reference sampling rate is greater than or equal to the maximum sampling rate, determining an integer executable decimation multiple based on the reference sampling rate and the maximum sampling rate;

[0069] S202-12, determining an intermediate sampling rate according to the executable decimation multiple;

[0070] S202-13, if the reference sampling rate is less than the maximum sampling rate, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0071] S202-14: Determine an intermediate sampling rate according to the executable interpolation multiple.

[0072] In an embodiment of the present application, as a preferred method, the reference sampling rate can be obtained by multiplying the desired bit rate set by the user. Alternatively, the reference sampling rate can be obtained by multiplying the desired bit rate set by the user. The multiplier of the multiplication and the multiplier of the reduction can be set according to actual needs. It can be a user-settable value or an empirical value within the instrument. The value is used to adjust the reference sampling rate to achieve control of the amount of calculation, storage space, or quality of the generated high-speed serial signal.

[0073] Since the expected bit rate may be a small bit rate, by obtaining an executable decimation multiple and an executable interpolation multiple that are both integers, and based on the executable decimation multiple and the executable interpolation multiple, the intermediate sampling rate obtained is an integer, and the relationship between the intermediate sampling rate and the maximum sampling rate is an integer multiple, which meets the requirement that the sampling rate is an integer.

[0074] In an optional embodiment, determining an integer executable decimation factor based on the reference sampling rate and the maximum sampling rate includes:

[0075] S202-111, determining a reference decimation multiple according to a reference sampling rate and a maximum sampling rate;

[0076] S202-112: Determine an integer executable decimation multiple that satisfies a first condition based on the reference decimation multiple, where the first condition is that a first deviation between the reference decimation multiple and the executable decimation multiple is within a first preset deviation range.

[0077] In an optional embodiment, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0078] S202-131, determining a reference interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0079] S202-132: Determine an integer executable interpolation multiple that satisfies a second condition based on the reference interpolation multiple, where the second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

[0080] As a specific example, the calculation formula of the reference sampling rate RefVFs is:

[0081] RefVFs=Rs×RefTimes (1)

[0082] Where Rs represents the expected bit rate, and RefTimes represents the reference multiplication factor.

[0083] If the reference sampling rate is greater than or equal to the maximum sampling rate, the reference interpolation multiple interpTimes is 1, and the calculation formula for the reference decimation multiple decTimes is:

[0084] decTimes=RefVFs / MaxFs (2)

[0085] Wherein, RefVFs represents the reference sampling rate, and MaxFs represents the maximum sampling rate.

[0086] An integer executable decimation multiple realDecTimes that satisfies a first condition is determined according to the reference decimation multiple decTimes.

[0087] The calculation formula for the intermediate sampling rate VFs is:

[0088] VFs=MaxFs / realInterpTimes×realDecTimes

[0089] =MaxFs×realDecTimes (3)

[0090] Among them, MaxFs represents the maximum sampling rate, realDecTimes represents the executable decimation multiple, realInterpTimes represents the executable interpolation multiple, and realInterpTimes=interpTimes=1.

[0091] If the reference sampling rate is less than the maximum sampling rate, the reference decimation multiple decTimes is 1, and the calculation formula for the reference interpolation multiple interpTimes is:

[0092] interpTimes=MaxFs / RefVFs (4)

[0093] Wherein, RefVFs represents the reference sampling rate, and MaxFs represents the maximum sampling rate.

[0094] An integer executable interpolation time realInterpTimes satisfying a second condition is determined according to the reference interpolation time interpTimes.

[0095] The calculation formula for the intermediate sampling rate VFs is:

[0096] VFs=MaxFs / realInterpTimes×realDecTimes

[0097] =MaxFs / realInterpTimes (5)

[0098] Among them, MaxFs represents the maximum sampling rate, realInterpTimes represents the executable interpolation multiple, realDecTimes represents the executable decimation multiple, and realDecTimes=decTimes=1.

[0099] In an embodiment of the present application, the first preset deviation range is used to control the degree to which the executable decimation multiple is close to the reference decimation multiple. The smaller the first preset deviation range, the closer the executable decimation multiple of the obtained integer is to the reference decimation multiple. The first deviation indicates that the corresponding executable decimation multiple is the integer closest to the reference decimation multiple within the first preset range. Similarly, the second preset deviation range is used to control the degree to which the executable interpolation multiple is close to the reference interpolation multiple. The smaller the second preset deviation range, the closer the executable interpolation multiple of the obtained integer is to the reference interpolation multiple. The second deviation indicates that the corresponding executable interpolation multiple is the integer closest to the reference interpolation multiple within the second preset range. This eliminates the influence that the reference decimation multiple and the reference interpolation multiple may be a decimal, thereby ensuring that the intermediate sampling rate meets the requirements.

[0100] As a specific example, the calculation formula of the first output sampling rate Fs1 is:

[0101] Fs1=VFs / realDecTimes (6)

[0102] Where VFs represents the intermediate sampling rate and realDecTimes represents the executable decimation multiple.

[0103] In the embodiment of the present application, the first output sampling rate can be adjusted based on the intermediate sampling rate. Thus, the output sampling rate can be flexibly selected based on the user-set bit rate, maximum sampling rate, storage depth, and other factors. This effectively reduces the amount of algorithm computation required and saves computation time when dealing with low-bit rate signals. When dealing with high-bit rate signals, the algorithm can be calculated based on an intermediate sampling rate that exceeds the maximum sampling rate, effectively improving computational accuracy, enhancing the output quality of high-speed serial signals, and effectively reducing the storage requirements for signal waveforms.

[0104] In an alternative embodiment, if Figure 3 As shown, the method for generating a high-speed serial signal further includes:

[0105] S400: If the first selection control information is control-on information and the second selection control information is control-on information, determining an intermediate sampling rate according to a desired bit rate set by the user, and determining the second output sampling rate as the maximum sampling rate according to the intermediate sampling rate;

[0106] S500 , generating a high-speed serial signal according to a second output sampling rate.

[0107] In an embodiment of the present application, the second output sampling rate is determined as the maximum sampling rate based on the intermediate sampling rate. Thus, although the maximum sampling rate output set by the user is still maintained, multiple intermediate calculation steps are calculated at an appropriate intermediate sampling rate. Finally, the second output sampling rate is determined to be the maximum sampling rate based on the intermediate sampling rate. When faced with low bit rate signals, the algorithm calculation amount can be effectively reduced, saving calculation time. When faced with high bit rate signals, the calculation can be based on the intermediate sampling rate that exceeds the maximum sampling rate, effectively improving the calculation accuracy and improving the output quality of the high-speed serial signal. The step of determining the intermediate sampling rate based on the expected bit rate set by the user in step S400 is the above-mentioned steps S201-S202.

[0108] As a specific example, the calculation formula of the second output sampling rate Fs2 is:

[0109] Fs2=VFs×realInterpTimes / realDecTimes (7)

[0110] Where VFs represents the intermediate sampling rate, realInterpTimes represents the executable interpolation times, and realDecTimes represents the executable decimation times.

[0111] In an alternative embodiment, if Figure 4 As shown, the method for generating a high-speed serial signal further includes:

[0112] S600: If the first selection control information is control-off information and the second selection control information is control-on information, determining the intermediate sampling rate as the maximum sampling rate and determining the third output sampling rate as the maximum sampling rate;

[0113] S700 : Generate a high-speed serial signal according to a third output sampling rate.

[0114] In the embodiment of the present application, when the first selection control information for the intermediate sampling rate mode is control-off information, the intermediate sampling rate VFs and the third output sampling rate Fs3 are both the DAC sampling rate (maximum sampling rate) set by the user. As a preferred embodiment, when the bit rate is too low or the bit stream is too long, causing the storage requirement to exceed the instrument's storage space, an alarm is issued when a high-speed serial signal is generated according to the third output sampling rate. By controlling the three mode selection signals, users can flexibly implement multiple mode combinations to meet the application requirements of different scenarios.

[0115] like Figure 5As shown in the figure, the high-speed serial signal generation process involves three signal sampling rates. In step (1): User-set bit rate, the signal sampling rate is equal to the user-set desired bit rate Rs. This step involves processing the signal's bit stream, pattern encoding, and modulation. Bit stream settings include PRBS (pseudo-random bit sequence), COLCK (clock), and file-imported bit streams. Pattern encoding and modulation settings include NRZ (non-return-to-zero), NRZ-I (non-return-to-zero inverted), RZ (return-to-zero), RZPolar (polarity return-to-zero), 8B / 10B, PAM (pulse amplitude modulation) 4 / 5 / 8 / 10 / 12 / 16, and scrambling.

[0116] Step (2): In the intermediate sampling rate, the signal sampling rate = intermediate sampling rate VFs is involved. This step can be applied to the embodiment of the present application when the first selection control information for the intermediate sampling rate mode is control-on information and the second selection control information for the fixed output sampling rate mode is control-off information, or when the first selection control information for the intermediate sampling rate mode is control-on information and the second selection control information for the fixed output sampling rate mode is control-on information, and determines the intermediate sampling rate according to the desired bit rate set by the user. The intermediate sampling rate VFs is automatically calculated internally according to certain rules to achieve the conversion from bit rate to intermediate sampling rate VFs and the corresponding functions, such as serial signal function blocks, filtering and interference, and sampling rate conversion. The serial signal function block settings include PWM (pulse width) modulation, periodic jitter injection, SSC (spread spectrum clock), random jitter injection, DCD (duty cycle distortion), and edge construction. The filtering and interference settings include Low-Pass Filter (low-pass filtering), ISI (inter-symbol interference), band-limited noise interference, and single-tone noise interference. The sampling rate conversion settings include interpolation filtering and decimation filtering.

[0117] Step (3): In the output sampling rate, the signal sampling rate = output sampling rate is involved. This step can be applied to the embodiment of the present application, where the first selection control information for the intermediate sampling rate mode is control-on information and the second selection control information for the fixed output sampling rate mode is control-off information, and the first output sampling rate is determined according to the intermediate sampling rate; or when the first selection control information for the intermediate sampling rate mode is control-on information and the second selection control information for the fixed output sampling rate mode is control-on information, the second output sampling rate is determined as the maximum sampling rate according to the intermediate sampling rate. At this time, the first output sampling rate or the second output sampling rate is automatically calculated according to certain rules, and the signal is interpolated or extracted from the intermediate sampling rate VFs to the first output sampling rate or the second output sampling rate, and then the signal is output from the AWG. For example, sampling rate conversion is performed. The sampling rate conversion setting also includes linear interpolation and linear decimation.

[0118] Several specific examples are introduced below to illustrate the method for generating a high-speed serial signal according to an embodiment of the present application.

[0119] When the intermediate sampling rate mode is on and the fixed output sampling rate mode is on:

[0120] Case 1: User-set expected bit rate Rs = 1.0000000000000 Mbps

[0121] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0122] Reference multiplication factor RefTimes = 24.000000000000

[0123] Reference sampling rate RefVFs = 0.024000000000GSa / s

[0124] Executable interpolation times realInterpTimes = 250.0

[0125] Executable decimation multiple realDecTimes = 1.0

[0126] Intermediate sampling rate VFs = 0.020000000000GSa / s

[0127] Second output sampling rate Fs2=5.0000000000000GSa / s

[0128] Case 2: User-set desired bitrate Rs = 1.511287427978 Mbps

[0129] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0130] Reference multiplication factor RefTimes = 24.000000000000

[0131] Reference sampling rate RefVFs = 0.036270898271GSa / s

[0132] Executable interpolation times realInterpTimes = 160.0

[0133] Executable decimation multiple realDecTimes = 1.0

[0134] Intermediate sampling rate VFs = 0.031250000000GSa / s

[0135] Second output sampling rate Fs2=5.0000000000000GSa / s

[0136] Case 3: User-set expected bit rate Rs = 125.0000000000000 Mbps Maximum sampling rate MaxFs = 5.0000000000000 GSa / s

[0137] Reference multiplication factor RefTimes = 24.000000000000

[0138] Reference sampling rate RefVFs = 3.0000000000000GSa / s

[0139] Executable interpolation times realInterpTimes = 2.0

[0140] Executable decimation multiple realDecTimes = 1.0

[0141] Intermediate sampling rate VFs = 2.5000000000000GSa / s

[0142] Second output sampling rate Fs2 = 5.0000000000000GSa / s

[0143] Case 4: User-set expected bit rate Rs = 325.001983654685Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0144] Reference multiplication factor RefTimes = 24.000000000000

[0145] Reference sampling rate RefVFs = 7.800047607712GSa / s

[0146] Executable interpolation times realInterpTimes = 1.0

[0147] Executable decimation multiple realDecTimes = 2.0

[0148] Intermediate sampling rate VFs = 10.0000000000000GSa / s

[0149] Second output sampling rate Fs2=5.0000000000000GSa / s

[0150] Case 5: User-set expected bit rate Rs = 1250.0000000000000Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0151] Reference multiplication factor RefTimes = 24.000000000000

[0152] Reference sampling rate RefVFs = 30.0000000000000GSa / s

[0153] Executable interpolation times realInterpTimes = 1.0

[0154] Executable extraction multiple realDecTimes = 5.0

[0155] Intermediate sampling rate VFs = 25.0000000000000GSa / s

[0156] Second output sampling rate Fs2=5.0000000000000GSa / s

[0157] When the intermediate sampling rate mode is ON and the fixed output sampling rate mode is OFF:

[0158] Case 6: User-set expected bitrate Rs = 1.0000000000000Mbps

[0159] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0160] Reference multiplication factor RefTimes = 24.000000000000

[0161] Reference sampling rate RefVFs = 0.024000000000GSa / s

[0162] Executable interpolation times realInterpTimes = 250.0

[0163] Executable decimation multiple realDecTimes = 1.0

[0164] Intermediate sampling rate VFs = 0.020000000000GSa / s

[0165] First output sampling rate Fs1=0.020000000000GSa / s

[0166] Case 7: User-set desired bitrate Rs = 1.511287427978 Mbps

[0167] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0168] Reference multiplication factor RefTimes = 24.000000000000

[0169] Reference sampling rate RefVFs = 0.036270898271GSa / s

[0170] Executable interpolation times realInterpTimes = 160.0

[0171] Executable decimation multiple realDecTimes = 1.0

[0172] Intermediate sampling rate VFs = 0.031250000000GSa / s

[0173] First output sampling rate Fs1=0.031250000000GSa / s

[0174] Case 8: User-set expected bit rate Rs = 125.0000000000000 Mbps Maximum sampling rate MaxFs = 5.0000000000000 GSa / s

[0175] Reference multiplication factor RefTimes = 24.000000000000

[0176] Reference sampling rate RefVFs = 3.0000000000000GSa / s

[0177] Executable interpolation times realInterpTimes = 2.0

[0178] Executable decimation multiple realDecTimes = 1.0

[0179] Intermediate sampling rate VFs = 2.5000000000000GSa / s

[0180] First output sampling rate Fs1=2.5000000000000GSa / s

[0181] Case 9: User-set expected bit rate Rs = 325.001983654685Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0182] Reference multiplication factor RefTimes = 24.000000000000

[0183] Reference sampling rate RefVFs = 7.800047607712GSa / s

[0184] Executable interpolation times realInterpTimes = 1.0

[0185] Executable decimation multiple realDecTimes = 2.0

[0186] Intermediate sampling rate VFs = 10.0000000000000GSa / s

[0187] First output sampling rate Fs1=5.0000000000000GSa / s

[0188] Case 10: User-set expected bitrate Rs = 1250.0000000000000 Mbps

[0189] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0190] Reference multiplication factor RefTimes = 24.000000000000

[0191] Reference sampling rate RefVFs = 30.0000000000000GSa / s

[0192] Executable interpolation times realInterpTimes = 1.0

[0193] Executable extraction multiple realDecTimes = 5.0

[0194] Intermediate sampling rate VFs = 25.0000000000000GSa / s

[0195] First output sampling rate Fs1=5.0000000000000GSa / s

[0196] It can be seen that the method for generating a high-speed serial signal in the embodiment of the present application, by calculating and using an intermediate sampling rate, can effectively reduce the amount of calculation and the required storage space at low bit rates while ensuring that no loss of accuracy is achieved; at high bit rates, it can effectively improve the calculation accuracy and quality of the high-speed serial signal, while supporting multiple modes, allowing users to flexibly choose. However, in some AWG signal sources, in order to reduce the amount of calculation at low bit rates, the low bit rate is usually directly multiplied by a multiple and used as the output sampling rate to generate a high-speed serial signal. For example, the TekAWG5200 directly generates a high-speed serial signal at a low bit rate using 6 times the bit rate as the output sampling rate. This lacks the user's ability to select a mode independently and may result in loss of accuracy. When the required storage space exceeds the maximum storage space of the AWG signal source, there is no way to normally generate a high-speed serial signal. For example, the Keysight M8195A will calculate the final required storage space in real time based on parameters such as the bit rate and symbol length. If the maximum storage space is exceeded, an error message will be displayed, requiring the user to re-modify parameters such as the symbol length or bit rate, lacking the ability to autonomously adjust the sampling rate.

[0197] The embodiment of the present application provides a device for generating a high-speed serial signal, which corresponds to the method for generating a high-speed serial signal in the above embodiment. Figure 6 As shown, the high-speed serial signal generating device 100 includes:

[0198] An acquiring unit 101 is configured to acquire a mode selection signal, the mode selection signal including first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0199] The first mode unit 102 is configured to determine an intermediate sampling rate according to a desired bit rate set by a user, and determine a first output sampling rate according to the intermediate sampling rate if the first selection control information is control-on information and the second selection control information is control-off information;

[0200] The first high-speed serial signal generating unit 103 is configured to generate a high-speed serial signal according to a first output sampling rate.

[0201] In an embodiment of the present application, the first selection control information of the intermediate sampling rate mode is used as control-on information and the second selection control information of the fixed output sampling rate mode is used as control-off information, the intermediate sampling rate is determined according to the expected bit rate set by the user, and the first output sampling rate is determined according to the intermediate sampling rate, so that the sampling rate corresponding to the expected bit rate set by the user is adjusted to the intermediate sampling rate, the intermediate sampling rate is reasonably selected, and then the output sampling rate can be reasonably selected. In this way, when the expected bit rate is very low or very high, the number of sampling points is more reasonable, which can effectively reduce the amount of calculation, save calculation time, and improve the accuracy of the code element edge construction, thereby effectively improving the quality of the generated high-speed serial signal.

[0202] In an optional implementation, the first mode unit 102 includes:

[0203] A reference sampling rate determining unit, configured to determine a reference sampling rate according to a desired bit rate set by a user;

[0204] The first intermediate sampling rate determining unit is configured to determine the intermediate sampling rate according to the reference sampling rate.

[0205] In an optional implementation manner, the first intermediate sampling rate determining unit includes:

[0206] The second intermediate sampling rate determining unit is configured to determine the intermediate sampling rate according to a multiple relationship between the reference sampling rate and the maximum sampling rate.

[0207] In an optional implementation manner, the second intermediate sampling rate determining unit includes:

[0208] a first multiple determination unit, configured to determine an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate if the reference sampling rate is greater than or equal to the maximum sampling rate;

[0209] The third intermediate sampling rate determining unit is configured to determine the intermediate sampling rate according to the executable decimation multiple.

[0210] In an optional implementation manner, the first multiple determination unit includes:

[0211] A reference decimation multiple determining unit, configured to determine a reference decimation multiple based on a reference sampling rate and a maximum sampling rate;

[0212] The executable decimation factor determining unit is configured to determine an integer executable decimation factor that satisfies a first condition based on the reference decimation factor. The first condition is that a first deviation between the reference decimation factor and the executable decimation factor is within a first preset deviation range.

[0213] In an optional implementation manner, the second intermediate sampling rate determining unit further includes:

[0214] a second multiple determination unit, configured to determine an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate if the reference sampling rate is less than the maximum sampling rate;

[0215] The fourth intermediate sampling rate determining unit is configured to determine the intermediate sampling rate according to the executable interpolation multiple.

[0216] In an optional implementation manner, the second multiple determination unit includes:

[0217] A reference interpolation multiple determining unit, configured to determine a reference interpolation multiple according to a reference sampling rate and a maximum sampling rate;

[0218] The executable interpolation multiple determining unit is configured to determine an integer executable interpolation multiple that satisfies a second condition according to the reference interpolation multiple. The second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

[0219] In an optional embodiment, the high-speed serial signal generating device further includes:

[0220] a second mode unit, configured to determine an intermediate sampling rate according to a desired bit rate set by a user, and determine the second output sampling rate as a maximum sampling rate according to the intermediate sampling rate, if the first selection control information is control-on information and the second selection control information is control-on information;

[0221] The second high-speed serial signal generating unit is configured to generate a high-speed serial signal according to a second output sampling rate.

[0222] In an optional embodiment, the high-speed serial signal generating device further includes:

[0223] a third mode unit, configured to determine the intermediate sampling rate as the maximum sampling rate and the third output sampling rate as the maximum sampling rate if the first selection control information is control-off information and the second selection control information is control-on information;

[0224] The third high-speed serial signal generating unit is configured to generate a high-speed serial signal according to a third output sampling rate.

[0225] The present application also provides an electronic device, such as Figure 7 As shown, the electronic device 200 includes a processor 201 and a memory 202; the memory 202 stores computer executable instructions, and when the computer executable instructions are executed by the processor 201, the high-speed serial signal generation method is executed.

[0226] The processor 201 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0227] The memory 202 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 201 may execute the program instructions to implement the steps in the above-described method for generating a high-speed serial signal and / or other desired functions.

[0228] In one example, the electronic device 200 may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown in the figure).

[0229] In addition, the input device may also include, for example, a keyboard, a mouse, a microphone, etc. The output device may output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output devices, etc.

[0230] Of course, to simplify, Figure 7 Only a portion of the components of the electronic device 200 related to the embodiment of the present application is shown, omitting components such as a bus, input device / output interface, etc. In addition, the electronic device 200 may further include any other appropriate components depending on the specific application.

[0231] An embodiment of the present application further provides a storage medium having computer executable instructions stored thereon. When the computer executable instructions are executed by a processor, the method for generating a high-speed serial signal is executed.

[0232] The present application embodiment can be system, method and / or computer program product.Computer program product can comprise computer-readable storage medium, and it is loaded with the computer-readable program instruction for making processor realize the various aspects of the present application embodiment.Computer program product can be written in any combination of one or more programming languages ​​for executing the program code of embodiment operation of the present application, and programming language comprises object-oriented programming language, such as Java, C++ etc., also comprises conventional procedural programming language, such as " C " language or similar programming language.Program code can be executed completely on user computing device, partially on user device, executed as an independent software package, partly on user computing device, partly on remote computing device, or completely on remote computing device or server.In the case of relating to remote computer, remote computer can be connected to user computer by any kind of network-including local area network (LAN) or wide area network (WAN), or, can be connected to external computer (for example, utilizing Internet service provider to connect by Internet). In some embodiments, by utilizing the status information of computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions, thereby realizing various aspects of the embodiments of the present application.

[0233] Computer-readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. A computer-readable storage medium is a tangible device that can maintain and store the instructions used by the instruction execution device. The readable storage medium can, for example, include but is not limited to a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. The computer-readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0234] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0235] Various aspects of the embodiments of the present application are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0236] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0237] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0238] It should be noted that the embodiments of the high-speed serial signal generation method, high-speed serial signal generation device, computer-readable storage medium, and electronic device provided in the embodiments of the present application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0239] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations of the claims. Various modifications and variations may be made to the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments merely illustrate several implementations of the present application and do not limit the scope of protection of the patent application.

Claims

1. A method for generating a high-speed serial signal, characterized in that: include: Acquire a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode; If the first selection control information is control-on information and the second selection control information is control-off information, determining an intermediate sampling rate according to a desired bit rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate; generating a high-speed serial signal according to the first output sampling rate; Determining the intermediate sampling rate according to the expected bit rate set by the user includes: Determine the reference sampling rate according to the expected bit rate set by the user; determining an intermediate sampling rate according to the reference sampling rate; Determining the intermediate sampling rate according to the reference sampling rate includes: Determining an intermediate sampling rate based on a multiple relationship between the reference sampling rate and the maximum sampling rate; Determining the intermediate sampling rate according to the multiple relationship between the reference sampling rate and the maximum sampling rate includes: If the reference sampling rate is greater than or equal to the maximum sampling rate, determining an integer executable decimation multiple based on the reference sampling rate and the maximum sampling rate; determining an intermediate sampling rate according to the executable decimation factor; Determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate includes: Determining a reference decimation multiple according to the reference sampling rate and the maximum sampling rate; Determining an integer executable decimation factor that satisfies a first condition based on the reference decimation factor, wherein the first condition is that a first deviation between the reference decimation factor and the executable decimation factor is within a first preset deviation range; The determining of the intermediate sampling rate according to the multiple relationship between the reference sampling rate and the maximum sampling rate further comprises: If the reference sampling rate is less than the maximum sampling rate, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate; An intermediate sampling rate is determined according to the executable interpolation factor.

2. The method for generating a high-speed serial signal according to claim 1, wherein: Determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate includes: Determining a reference interpolation multiple according to the reference sampling rate and the maximum sampling rate; An integer executable interpolation multiple that satisfies a second condition is determined according to the reference interpolation multiple, where the second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

3. The method for generating a high-speed serial signal according to claim 1, wherein: Also includes: If the first selection control information is control-on information and the second selection control information is control-on information, determining an intermediate sampling rate according to a desired bit rate set by a user, and determining the second output sampling rate as a maximum sampling rate according to the intermediate sampling rate; A high-speed serial signal is generated according to the second output sampling rate.

4. The method for generating a high-speed serial signal according to claim 1, wherein: Also includes: If the first selection control information is control-off information and the second selection control information is control-on information, determining the intermediate sampling rate as the maximum sampling rate and determining the third output sampling rate as the maximum sampling rate; A high-speed serial signal is generated according to the third output sampling rate.

5. A high-speed serial signal generating device, characterized in that: include: An acquisition unit, configured to generate a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode; a first mode unit, configured to determine an intermediate sampling rate according to a desired bit rate set by a user, and determine a first output sampling rate according to the intermediate sampling rate, if the first selection control information is control-on information and the second selection control information is control-off information; a first high-speed serial signal generating unit, configured to generate a high-speed serial signal according to the first output sampling rate; The first mode unit includes: A reference sampling rate determining unit, configured to determine a reference sampling rate according to a desired bit rate set by a user; a first intermediate sampling rate determining unit, configured to determine an intermediate sampling rate according to a reference sampling rate; The first intermediate sampling rate determining unit includes: a second intermediate sampling rate determining unit, configured to determine an intermediate sampling rate according to a multiple relationship between the reference sampling rate and the maximum sampling rate; The second intermediate sampling rate determining unit includes: a first multiple determination unit, configured to determine an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate if the reference sampling rate is greater than or equal to the maximum sampling rate; a third intermediate sampling rate determining unit, configured to determine the intermediate sampling rate according to the executable decimation multiple; The first multiple determination unit includes: A reference decimation multiple determining unit, configured to determine a reference decimation multiple based on a reference sampling rate and a maximum sampling rate; an executable decimation factor determining unit, configured to determine an executable decimation factor that satisfies a first condition as an integer based on the reference decimation factor, wherein the first condition is that a first deviation between the reference decimation factor and the executable decimation factor is within a first preset deviation range; The second intermediate sampling rate determining unit further includes: a second multiple determination unit, configured to determine an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate if the reference sampling rate is less than the maximum sampling rate; The fourth intermediate sampling rate determining unit is configured to determine the intermediate sampling rate according to the executable interpolation multiple.

6. An electronic device, characterized in that: include: processor; as well as A memory storing computer executable instructions, wherein the computer executable instructions are executed by the processor to execute the method for generating a high-speed serial signal according to any one of claims 1 to 4.

7. A storage medium, characterized in that: The storage medium stores computer-executable instructions, which, when executed by a processor, execute the method for generating a high-speed serial signal according to any one of claims 1 to 4.

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