Method for synchronizing internal signals of multi-core chip

Abstract

The invention discloses a method for synchronizing internal signals of a multi-core chip, which comprises the following steps of: defining an IO (Input / Output) interface as a system time synchronization signal receiving interface for each core of the multi-core chip, and automatically aligning the working cycle of each core to a system synchronization signal after each core receives the system synchronization signal so as to ensure that the data resolving cycle between the cores is synchronous with the system; meanwhile, a core is arranged in the multi-core chip as a synchronizing signal management core, and when the core does not receive a system time synchronizing signal in a plurality of system periods, the core is used as a multi-core chip synchronizing source to send IPC interrupt to each core to replace the system synchronizing signal, so that normal operation of functions such as resolving output among the cores is ensured. According to the invention, each core manages an intra-core synchronization signal by receiving an external clock synchronization signal or a synchronization signal, so that the signal synchronization requirement of a weapon system is met.

Description

Technical Field

[0001] The present invention belongs to the field of weapon system electrical architecture, and in particular relates to a multi-core chip internal signal synchronization method in multi-core processor information processing. Background Art

[0002] In the design of new weapon systems, it is necessary to reduce the size and weight of the system structure as much as possible. However, since each molecular system in the electrical architecture of the weapon system uses a large number of electrical solver boards, the total volume of the electrical box will be large and the system power consumption will be high. If the data solver board functions such as optoelectronics, fire control, and follow-up position control in the traditional weapon electrical system are integrated into a multi-core processor, a large amount of electrical box structure space will be saved and the system weight will be reduced. These data solver functions need to be based on the sampling and solver synchronization of the system sensors. Therefore, a multi-core processor internal signal synchronization method is needed, which can not only meet the time synchronization between the cores of the multi-core processor and the weapon system, but also complete the self-synchronization function of each core without the input of external time synchronization signal. For this reason, the use of a reliable multi-core processor internal signal synchronization method is of great significance in the integration of new weapon electrical systems. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiency of synchronization between cores in the existing multi-core processor data solution board, and provide a method for signal synchronization between cores in a multi-core chip. In the present invention, each core manages the internal synchronization signal of the core by receiving an external clock synchronization signal or a synchronization signal to meet the signal synchronization requirements with the weapon system.

[0004] The technical solutions to the above problems are as follows:

[0005] A method for synchronizing internal signals of a multi-core chip, characterized in that an IO interface is designated for each core of the multi-core chip as a system time synchronization signal receiving interface. After receiving the system synchronization signal, each core automatically aligns its own working cycle with it to ensure that the data solution cycle between the cores is synchronized with the system. At the same time, a core is set in the multi-core chip as a synchronization signal management core. When this core does not receive the system time synchronization signal within multiple system cycles, this core, as a synchronization source of the multi-core chip, sends an IPC interrupt to each core to replace the system synchronization signal, thereby ensuring the normal operation of functions such as solution output between the cores.

[0006] Furthermore, the multi-core chip is an octa-core chip, core 0 is set as a synchronization signal management core, and cores 1 to 7 all achieve internal chip signal synchronization by receiving external clock synchronization signals or synchronization signals within the synchronization signal management core.

[0007] Furthermore, the system clock synchronization signal is input into the 8 GPIO interfaces of the multi-core chip through the system synchronization bus. Cores 0 to 7 respectively set a GPIO interface as an external interrupt interface. When the system clock synchronization signal is received, the external interrupt of each core is triggered at the same time. After each core triggers the synchronous interrupt, the delay calculation flag and the data output flag are set through the interrupt callback function software interface to realize the weapon system control synchronization function.

[0008] Furthermore, after core 0 completes software initialization, it times the interval of each received synchronization interrupt; if the time interval of N consecutive system synchronization interrupts does not match the weapon system clock synchronization signal period, or no synchronization interrupt is received for M consecutive seconds, it is judged that the weapon system clock synchronization signal reception failure.

[0009] The advantages of the present invention are:

[0010] The internal inter-core signal synchronization method of the core chip involved in the present invention not only satisfies the time synchronization between the cores inside the multi-core processor and the weapon system, but also can complete the self-synchronization function of the cores itself without external time synchronization signal input. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flowchart of the workflow of the present invention. DETAILED DESCRIPTION

[0012] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0013] The present invention discloses a method for synchronizing internal signals of a multi-core chip. The method of the present invention is as follows: by defining an IO interface for each core of the multi-core chip as a system time synchronization signal receiving interface, each core automatically aligns its own working cycle with the system synchronization signal after receiving the system synchronization signal to ensure that the data solution cycle between the cores is synchronized with the system. At the same time, a core is set in the multi-core chip as a synchronization signal management core. When this core does not receive the system time synchronization signal within multiple system cycles, this core acts as a synchronization source of the multi-core chip to send an IPC interrupt to each core to replace the system synchronization signal, thereby ensuring the normal operation of functions such as solution output between the cores.

[0014] Example

[0015] This embodiment is an application example of the present invention in a certain high-mobility project on a vehicle. Figure 1 Each core manages the internal synchronization signal by receiving an external clock synchronization signal or synchronization signal to meet the synchronization requirements with the weapon system signal.

[0016] The specific implementation steps are as follows:

[0017] The multi-core chip in this embodiment adopts TMS320C6678, core 0 is set as the synchronization signal management core, and cores 1 to 7 all achieve chip internal signal synchronization by receiving external clock synchronization signals or synchronization signals within the synchronization signal management core.

[0018] 1. External clock synchronization

[0019] The weapon system clock synchronization signal is input into the 8 GPIO interfaces of the TMS320C6678 multi-core chip through the system synchronization bus. Cores 0 to 7 set a GPIO interface as an external interrupt interface. When the system clock synchronization signal is received, the external interrupt of each core is triggered at the same time. After each core triggers the synchronization interrupt, the delay calculation flag and data output flag are set through the interrupt callback function software interface to realize the weapon system control synchronization function.

[0020] 2. Internal clock self-synchronization

[0021] After completing software initialization, core 0 will time the interval of each received synchronization interrupt. If the time interval of the system synchronization interrupt for 5 consecutive cycles does not match the cycle of the weapon system clock synchronization signal, or if no synchronization interrupt is received for 1 second, it is judged that the weapon system clock synchronization signal reception fails. At this time, core 0 starts to enable the internal timer of the chip. When the timer interrupt is triggered, it sends an IPC interrupt to the remaining cores as an internal self-synchronization signal.

[0022] After receiving the synchronous IPC interrupt, cores 1 to 7 will no longer respond to the external synchronization signal triggered by the system synchronous bus, and all flags in the original external synchronous interrupt callback function will be set in the synchronous IPC interrupt callback function. This ensures that when the system clock synchronization signal reception fails, each core can still maintain normal operation.

[0023] In practical applications, the present invention can also adjust the judgment basis of the system clock synchronization signal reception failure according to actual needs, and the corresponding internal self-synchronization signal sending period also needs to be adjusted according to actual conditions.

[0024] Finally, it should be noted that the above-described implementation mode is only a preferred embodiment of the present invention to illustrate the technical solution of the present invention, and does not limit it, let alone limit the protection scope of the present invention; although the invention is described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the protection scope of the claims.

Claims

1. A method for synchronizing internal signals of a multi-core chip, characterized in that: By designating an IO interface as the system time synchronization signal receiving interface for each core of the multi-core chip, each core automatically aligns its own working cycle with the system synchronization signal after receiving the system synchronization signal to ensure that the data solution cycle between the cores is synchronized with the system. At the same time, a core is set in the multi-core chip as a synchronization signal management core. When this core does not receive the system time synchronization signal within multiple system cycles, this core acts as a synchronization source for the multi-core chip to send an IPC interrupt to each core to replace the system synchronization signal, thereby ensuring the normal operation of functions such as solution output between the cores.

2. A method for synchronizing internal signals of a multi-core chip according to claim 1, characterized in that: The multi-core chip is an octa-core chip, core 0 is set as a synchronization signal management core, and cores 1 to 7 all achieve chip internal signal synchronization by receiving external clock synchronization signals or synchronization signals within the synchronization signal management core.

3. A method for synchronizing internal signals of a multi-core chip according to claim 2, characterized in that: The system clock synchronization signal is input into the 8 GPIO interfaces of the multi-core chip through the system synchronization bus. One GPIO interface is set as the external interrupt interface for cores 0 to 7 respectively. When the system clock synchronization signal is received, the external interrupt of each core is triggered at the same time. After each core triggers the synchronous interrupt, the delay calculation flag and data output flag are set through the interrupt callback function software interface to realize the weapon system control synchronization function.

4. A method for synchronizing internal signals of a multi-core chip according to claim 2, characterized in that: After core 0 completes software initialization, it times the interval of each received synchronization interrupt; if the time interval of N consecutive system synchronization interrupts does not match the weapon system clock synchronization signal period, or no synchronization interrupt is received for M consecutive seconds, it is judged that the weapon system clock synchronization signal reception failure.

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