An integrated sensing, computing and macro cell circuit, system and analog-to-digital conversion method

Abstract

The present application discloses a sense-in-memory macrocell circuit, system, and analog-to-digital conversion method, including the steps: a tag module reads an analog signal from the iSC bus; the tag module traverses and compares the read analog signal with a plurality of reference analog signals; according to the comparison result, a corresponding digital signal is obtained; the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship. This method does not require a dedicated ADC circuit and utilizes the existing circuits of the PE to implement the conversion function.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits and signal processing, and in particular to a sensing-in-memory macro unit circuit, system, and analog-to-digital conversion method. Background Art

[0002] With the development of the industrial Internet, higher requirements are put forward for video acquisition and processing technologies. In traditional vision application systems, an image sensor collects image information, converts the optical signal into an electrical signal, and after analog-to-digital conversion, it becomes a digital signal. Then, the image data is processed by an image signal processing unit, and finally, it needs to be output to the processor in the system through a special video interface, and then the processor performs data analysis and makes corresponding control and operations.

[0003] In applications such as image processing and laser ranging, as Figure 1 shown, the sensing-in-memory chip integrates sensing, storage, and computing functions to achieve efficient and low-power data processing. Among them, in the middle is an array of processing macro units (PE) 1, where the PEs are closely arranged in an array form, for example, with a scale of 1024*1024. Since each PE includes a basic sensing-in-memory unit, all the PEs in the PE array can simultaneously process the data within each unit in parallel. Such a method is also often referred to as the single instruction multiple data mode, i.e., SIMD, which is more common in GPUs. A row control module 5 and a column control module 6 are respectively designed in the horizontal and vertical directions of the PE array. The row control module 5 is used to perform row selection and related control on the PE array, and the corresponding column mode control module is used to perform column selection and related control on the PE array, as well as data readout selection. An external digital module 4, an INS bus 41, an external analog module 3, and an interface module 7 are also included outside the PE array.

[0004] As Figure 2 shown, the PE unit includes a sensing unit (SU), an analog signal operator arithmetic unit (AOP), an analog memory-computation unit (AREG Bank), a digital memory-computation unit (DREG bank), a tag module (TAG), and an adjacent PE communication unit (AdjacentIF). Among them, the analog memory-computation unit includes several analog signal memories AREG0, AREG1..., and the analog signal memory itself is also an arithmetic unit. Similarly, the digital memory-computation unit includes several digital signal memories DREG0, DREG1..., and the digital signal memory can perform logical operations in addition to storing digital signals. The output of the tag unit serves as a judgment signal to control whether the current PE executes the current SIMD instruction.

[0005] For the conventional conversion of analog signals to digital signals, dedicated ADC chips or ADC circuits are required to achieve the conversion. For traditional image sensors, it has evolved from a single ADC in the early stage to column-level ADCs and then to the latest pixel-level ADC designs. However, this will increase the chip area and the energy consumption required for conversion, and pixel-level ADCs require more advanced process technologies such as stacking processes. Due to the size limitations of ADC designs and the frequency characteristic requirements of ADCs, in the traditional data transfer process, high latency and high power consumption are caused.

[0006] Especially for the sense-compute-in-memory chips, the analog and digital memory units in the PE face significant problems when signals interact or flow between the analog and digital domains. Either an ADC circuit is designed in the PE, but this brings problems such as circuit area and power consumption. Or serial conversion is performed through a single ADC circuit, which brings efficiency problems and delays and power consumption issues in data flow. Summary of the Invention

[0007] The present invention proposes a sense-compute-integrated macrocell circuit, system, and data processing method, which can achieve the conversion function through special modules and the control of the PE mode.

[0008] The present invention proposes an analog-to-digital conversion method for a sense-compute-integrated macrocell circuit, including the steps of:

[0009] The tag module reads the analog signal from the iSC bus;

[0010] The tag module traverses and compares the read analog signal with a plurality of reference analog signals;

[0011] Obtain the corresponding digital signal according to the comparison result;

[0012] The plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship.

[0013] Optionally, the reference analog signals increase or decrease gradually with the number of times according to a linear function, exponential function, logarithmic function, power function, or trigonometric function relationship.

[0014] Optionally, the analog signal increases or decreases gradually with the number of times according to a linear function, exponential function, logarithmic function, power function, or trigonometric function relationship.

[0015] Optionally, the coding rule of the digital signal is standard binary code, Gray code, Hamming code, or Huffman coding.

[0016] Optionally, obtaining the corresponding digital signal according to the comparison result further includes the steps of:

[0017] The initial value of the digital memory unit is 0;

[0018] When the comparison result of the tag module indicates that the analog signal is less than the reference analog signal, each time a comparison is made, the digital signal stored in the digital memory and computing unit changes by one value according to the encoding rule until the analog signal is greater than or equal to the reference analog signal, at which point the digital memory and computing unit outputs the stored digital signal.

[0019] Optionally, it further includes the step of: the tag module determines whether the current sensing, memory, and computing integrated macro cell circuit executes the instruction sent by the INS bus based on the stored identification data.

[0020] Optionally, it further includes the step of: in the digital-to-analog conversion mode, the tag module consists of a comparator circuit and a latch circuit. The comparator circuit is used to compare the analog signal with several reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction; when the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

[0021] Optionally, in the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator into the subsequent latch; when the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction; when the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

[0022] Optionally, the digital signal is a 3-bit binary signal.

[0023] Optionally, it further includes the step of: the DAC unit outside the sensing, memory, and computing integrated macro cell circuit sends the reference analog signal.

[0024] The present invention also provides a sensing, memory, and computing integrated macro cell circuit, including:

[0025] The iSC bus, used to connect each module, for transmitting sensing signals and computing signals between modules;

[0026] The INS bus, used to connect each module;

[0027] The digital memory and computing unit, used for simultaneously storing data and performing data operations, where the data includes digital signals;

[0028] The analog memory and computing unit, used for simultaneously storing data and performing data operations, where the data includes analog signals;

[0029] The tag module, used to read the analog signal from the iSC bus; traversing and comparing the read analog signal with several reference analog signals;

[0030] The output module, used to obtain the digital signal according to the comparison result;

[0031] A first control module for providing reference analog signals to a tag module, where the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship.

[0032] Optionally, the reference analog signals increase or decrease gradually according to a linear function, an exponential function, a logarithmic function, a power function, or a trigonometric function relationship with the number of times.

[0033] Optionally, an encoding module for corresponding the reference analog signals and digital signals according to a certain encoding rule, and the encoding rule of the digital signals is a standard binary code, a Gray code, a Hamming code, or a Huffman code.

[0034] Optionally, it further includes: a second control module for initializing the value of the digital memory and computing unit to 0;

[0035] When the comparison result of the tag module is that the analog signal is less than the reference analog signal, then for each comparison, the digital signal stored in the digital memory and computing unit changes by one value according to the encoding rule until the analog signal is greater than or equal to the reference analog signal.

[0036] Optionally, the sensing unit, the analog memory and computing unit, the digital memory and computing unit, the iSC bus, the INS bus, and the tag module are integrally integrated on the same chip.

[0037] Optionally, the tag module determines whether to execute the instruction sent by the INS bus for the current sensing, memory, and computing integrated macro cell circuit based on the stored identification data.

[0038] Optionally: In the digital-to-analog conversion mode, the tag module consists of a comparator circuit and a latch circuit. The comparator circuit is used to compare the analog signal with a plurality of reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

[0039] Optionally: In the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator into the subsequent latch; when the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

[0040] Optionally, the analog memory and computing unit includes a plurality of analog signal memories, and the analog signal memories also serve as analog computing units. By connecting the plurality of analog memory and computing units to the same iSC bus for reading and writing operations, analog signals can directly perform addition, subtraction, multiplication, and division operations in the analog signal memories.

[0041] Optionally, the digital memory and computing unit includes a plurality of digital signal memories, and the digital signal memories have both storage and logical operation capabilities.

[0042] Optionally, a DREG BANK is provided in the digital memory and computing unit. The DREG BANK includes a plurality of digital signal memories, a digital read bus iSC RD DBUS, and a digital write bus iSC WR DBUS. The digital signal memories are digital registers DREG. A plurality of digital registers DREG are connected in parallel between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS. Among them, the input terminal IN of the digital register DREG is connected to the digital write bus iSC WR DBUS, and the output terminal OUT of the digital register DREG is connected to the digital read bus iSC RD DBUS. A multiplexer MUX is also connected between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS. The digital read bus iSC RD DBUS of the digital register DREG is also connected to the iSC bus through a switch.

[0043] Optionally, the digital signal memory is implemented using 3T DRAM, 6T DRAM, or SRAM.

[0044] Optionally, the digital signal memory is implemented using Flash. Further, it includes: a plurality of FLASH memories, a read / write control circuit, a digital read bus iSC RD DBUS, and a multiplexer MUX. Among them, the input terminal IN of the FLASH memory is connected to the read / write control circuit, the output terminals of the FLASH are connected in parallel to the digital read bus iSC RD DBUS, and a multiplexer MUX is connected between the digital read bus iSC RD DBUS and the read / write control circuit.

[0045] The present invention also provides a sensing, memory, and computing integrated macro cell system, including:

[0046] A plurality of sensing, memory, and computing integrated macro cell circuits are arranged in an array structure, where:

[0047] The sensing, memory, and computing integrated macro cell circuit includes:

[0048] An iSC bus for connecting each module to transfer sensing signals and computing signals between modules;

[0049] INS bus, used to connect each module;

[0050] Digital memory - computing unit, used to perform data storage and data operation simultaneously, and the data includes digital signals;

[0051] Analog memory - computing unit, used to perform data storage and data operation simultaneously, and the data includes analog signals;

[0052] Tag module, used to read analog signals from the iSC bus; traverse and compare the read analog signals with several reference analog signals;

[0053] Output module, used to obtain digital signals according to the comparison result;

[0054] First control module, used to provide reference analog signals to the tag module, and the several reference analog signals are data that gradually increase or decrease according to a functional relationship, and the external DAC unit serves as the first control module.

[0055] Optionally, the memory - in - computing macro - cell circuit arrays are located on the same chip,

[0056] The external DAC is located inside or outside the chip.

[0057] The present invention utilizes the existing PE resources, realizes the principle of ADC through a control method, and further realizes a method for parallel analog - to - digital domain signal conversion, which conforms to the characteristics of the memory - in - computing system - on - chip SIMD, and simultaneously realizes ADC conversion for the entire PE array. It enables seamless conversion between analog - domain signals and digital - domain signals.

[0058] The present invention utilizes existing components in the PE, such as comparators, to convert analog signals such as Pixel signals and AREG current signals into digital signals, which are stored in the DREG in the PE. Without the need to add special conversion circuits, a method for parallel analog - to - digital domain signal conversion is realized. This method does not require a dedicated ADC circuit, and utilizes the existing circuits in the PE to achieve the conversion function. This parallel conversion is equivalent to signal conversion at the pixel level or the PE level, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion. Description of the Drawings

[0059] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0060] Figure 1 It is a schematic diagram of the architecture of a memory - in - computing macro - cell system;

[0061] Figure 2 is a schematic diagram of the architecture of a sense-storage-computation integrated macro cell circuit;

[0062] Figure 3 is a schematic diagram of the DREG architecture of a sense-storage-computation integrated macro cell circuit;

[0063] Figure 4 is a schematic diagram of the SRAM circuit of a sense-storage-computation integrated macro cell circuit;

[0064] Figure 5 is a schematic diagram of the TAG circuit of a sense-storage-computation integrated macro cell circuit;

[0065] Figure 6 is a schematic diagram of the analog-to-digital conversion method of a sense-storage-computation integrated macro cell circuit according to an embodiment of the present application;

[0066] Figure 7 is a flowchart of the analog-to-digital conversion method of a sense-storage-computation integrated macro cell circuit according to an embodiment of the present application;

[0067] Figure 8 is a schematic diagram of the analog-to-digital conversion method of a sense-storage-computation integrated macro cell circuit according to another embodiment of the present application;

[0068] Figure 9 is a schematic diagram of the encoding of the analog-to-digital conversion method of a sense-storage-computation integrated macro cell circuit according to an embodiment of the present application;

[0069] Figure 10 is a schematic diagram of the encoding of the analog-to-digital conversion method of a sense-storage-computation integrated macro cell circuit according to another embodiment of the present application. Detailed implementation manners

[0070] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention. Obviously, the embodiments described in the present invention are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0071] In this application, unless otherwise stated, the use of "or" means "and / or". In addition, the use of terms such as "comprising", "including", and other forms of "including" is not restrictive. Additionally, unless specifically stated otherwise, terms such as "element" or "component" cover both elements and components including one unit and elements and components including more than one unit.

[0072] The present invention provides a sensing, storage, and computing integrated macrocell system, which includes a plurality of the above-mentioned sensing, storage, and computing integrated macrocell circuits, and the plurality of sensing, storage, and computing integrated macrocell circuits are arranged in an array structure;

[0073] The sensing, storage, and computing integrated macrocell circuit includes:

[0074] An iSC bus for connecting each module to transfer sensing signals and computing signals between modules;

[0075] An INS bus for connecting each module;

[0076] A digital storage and computing unit for simultaneously storing and computing data, where the data includes digital signals;

[0077] An analog storage and computing unit for simultaneously storing and computing data, where the data includes analog signals;

[0078] A tag module for reading analog signals from the iSC bus; traversing and comparing the read analog signals with a plurality of reference analog signals;

[0079] An output module for obtaining digital signals according to the comparison result;

[0080] A first control module for providing reference analog signals to the tag module, where the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship, and the external DAC unit serves as the first control module.

[0081] In one embodiment, it further includes: a DAC unit arranged outside the array structure, and the external DAC unit serves as the first control module.

[0082] In one embodiment, the sensing, storage, and computing integrated macrocell circuit array is located on the same chip, and the external DAC is located inside or outside the chip.

[0083] As Figure 1 shown, in this embodiment, the sensing, storage, and computing integrated macrocell system is specifically designed in a pixel-level sensing, storage, and computing integrated chip. In the middle is an array of processing macrocells (PEs), with PE1 closely arranged in an array form, for example, with a scale of 1024*1024. The internal structure of the PE will be described in detail with reference to the specific embodiments of the sensing, storage, and computing integrated macrocell circuit and the sensing, storage, and computing integrated macrocell circuit. Here, only the overall architecture of the sensing and storage integrated macrocell system is described.

[0084] Since each PE includes the basic unit of sensing, storage, and computing, all the PEs in the PE array can simultaneously and parallelly process the data within each unit. Such a method is also often referred to as the single instruction multiple data mode, i.e., SIMD, which is relatively common in GPUs. A row control module and a column control module are respectively designed in the horizontal and vertical directions of the PE array. The row control module is used to perform row selection and related control on the PE array, and the corresponding column mode control module is used to perform column selection and related control on the PE array, as well as data readout selection. Therefore, in addition to the PE array, the integrated sensing and computing circuit system also includes an analog-to-digital conversion unit (ADC) 2, a peripheral analog module 3, a peripheral digital module 4, a row control module 5, a column control module 6, an interface module 7, etc., arranged around the PE array, as well as the INS bus 41.

[0085] In one embodiment, the integrated sensing, storage, and computing macro unit system includes a plurality of integrated sensing, storage, and computing macro unit circuits arranged in an array structure. Specifically, it can be the integrated sensing, storage, and computing macro unit circuit of a distance measurement sensor, such as Figure 2 As shown, the PE unit includes a sensing unit SU, an analog signal operator arithmetic unit AOP, an analog storage and computing unit AREG bank, a digital storage and computing unit DREG bank, a tag module TAG, an adjacent PE communication unit adjacent IF, an iSC bus, and an INS bus. The above units and modules are all connected to the iSC bus and the INS bus. The iSC bus is used to transmit sensing signals and arithmetic signals, and both the sensing unit and the storage and computing unit are connected to the iSC bus; the INS bus is used to transmit instructions. The tag module is used to read the analog signal from the iSC bus; traverse and compare the read analog signal with several reference analog signals, and output the comparison result; the output module is used to output a digital signal according to the comparison result and the reference analog signal; the first control module is used to provide the reference analog signal to the tag module, and the several reference analog signals are data that gradually increase or decrease according to a functional relationship.

[0086] In one embodiment, the reference analog signals increase or decrease gradually with the number of times according to a linear function, an exponential function, a logarithmic function, a power function, or a trigonometric function relationship.

[0087] In one embodiment, the encoding module is used to correspond the reference analog signal and the digital signal according to a certain encoding rule. The encoding rule of the digital signal is a standard binary code, a Gray code, a Hamming code, or a Huffman code.

[0088] In one embodiment, according to the comparison result and the reference analog signal, outputting the corresponding digital signal further includes the steps of:

[0089] The initial value of the digital storage and computing unit is 0;

[0090] When the comparison result of the tag module indicates that the analog signal is less than the reference analog signal, each time a comparison is made, the digital signal stored in the digital memory and computing unit changes by one value according to the coding rule until the analog signal is greater than or equal to the reference analog signal, at which point the digital memory and computing unit outputs the stored digital signal.

[0091] In one embodiment, the sensing unit, analog memory and computing unit, digital memory and computing unit, iSC bus, INS bus, and tag module are integrated on the same chip.

[0092] In one embodiment, the analog memory and computing unit includes multiple analog signal memories. The analog signal memories also serve as analog computing units. By connecting the multiple analog memory and computing units to the same iSC bus for read and write operations, analog signals can directly perform addition, subtraction, multiplication, and division operations in the analog signal memories.

[0093] In one embodiment, the digital memory and computing unit includes several digital signal memories, and the digital signal memories have both storage and logical operation capabilities.

[0094] In one embodiment, a DREG BANK is provided in the digital memory and computing unit. The DREG BANK includes multiple digital signal memories, a digital read bus iSC RD data bus, and a digital write bus iSC WR data bus. The digital signal memories are digital registers DREG. A plurality of digital registers DREG are connected in parallel between the digital read bus iSC RD data bus and the digital write bus iSC WR data bus. Among them, the input terminal IN of the digital register DREG is connected to the iSC WR data bus, the output terminal OUT of the digital register DREG is connected to the iSC RD data bus, a multiplexer MUX is also connected between the digital read bus iSC RD data bus and the digital write bus iSC WR data bus, and the digital read bus iSC RD data bus of the digital register DREG is also connected to the iSC bus through a switch.

[0095] In one embodiment, the digital signal memory is implemented using 3T DRAM, 6T DRAM, or SRAM.

[0096] In one embodiment, the digital signal memory is implemented using Flash. Further included are: multiple FLASH memories, a read and write control circuit, a read data iSC RD data bus, and a multiplexer MUX. Among them, the input terminal IN of the FLASH memory is connected to the read and write control circuit, the output terminals of the FLASH are connected in parallel to the iSC RD data bus, and a multiplexer MUX is connected between the iSC RD data bus and the read and write control circuit.

[0097] In one embodiment, it further includes: identification data is stored in the tag module, and based on the stored identification data, it is determined whether the current sense computing integrated macrocell circuit executes the instruction sent by the INS bus.

[0098] In one embodiment, during operation, one or more digital register DREG signals read out from the digital read bus iSC RD data bus are written back to the digital write bus iSC WR data bus through a multiplexer MUX and then written into the corresponding one or more digital registers DREG to implement the operation.

[0099] In one embodiment, each tag module corresponds to a processing unit, which is used to determine whether the current processing unit PE executes the current INS instruction according to the comparison result stored in the tag module, that is, the identification data; when the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction, and when the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

[0100] In one embodiment, the analog computing unit includes several analog signal memories AREG0, AREG1..., and the analog signal memory itself is also an arithmetic unit. Signals can perform addition, subtraction, multiplication, and division operations through the analog memory. For example, 5 registers can be designed to meet the basic arithmetic requirements. Similarly, a DREG BANK is provided in the digital computing unit, and the DREG BANK includes multiple digital signal memories, and the digital signal memories are digital registers DREG; a dedicated digital read bus iSC RD bus and a digital write bus iSC WR bus are designed in the DREGBANK. By simultaneously turning on multiple DREG read control signals RD to the read bus, the wire-and operation of storing digital signals can be realized. The digital read bus can transfer the signal to the iSC bus through a strobe tube for further operations. A multiplexer MUX is designed between the two buses to write the read signal of the read bus back to the write bus and then write it into the corresponding DREG. The written-back signal can be the same as the original signal or can be selected to be written back in an inverted form. This is the function of the multiplexer MUX. Refer to Figure 3, a plurality of digital registers DREG0, DREG1,... are connected in parallel between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS. In addition to storing digital signals, the digital signal memory can also perform logical operations. Among them, the input end IN of the digital register DREG is connected to the iSC WRDBUS, the output end OUT of the digital register DREG is connected to the digital read bus iSC RD DBUS, a multiplexer MUX is also connected between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS, and the digital read bus iSC RD DBUS of the digital register DREG is also connected to the iSC bus through a switch.

[0101] The digital signal memory is implemented by 3T DRAM, 6T DRAM, or SRAM. 6T SRAM is used as the circuit for storing digital signals in the DREG of the PE. Compared with the previous DRAM, the storage is more stable, but it will increase the cell size of the DREG. Data is written through the MWR transistor, WR is valid, and the IN input valid signal is used to complete the write operation. Correspondingly, data is read through the MRD transistor, RD is valid, and the OUT output valid signal is used to complete the read operation. The specific RAM in this embodiment refers to Figure 4 .

[0102] In one embodiment, in addition to performing conventional operations through analog registers, the analog signal operator operation unit AOP can be designed with an efficient special operator according to the particularity of the application scenario to implement special operations, such as square operation, log operation, square root operation, etc.

[0103] During the operation, one or more digital register DREG signals read from the digital read bus iSC RD DBUS are written back to the digital write bus iSC WR DBUS through the multiplexer MUX and then written to the corresponding one or more digital registers DREG to implement the operation.

[0104] In one embodiment, the tag module determines whether the current sensing, computing, and integrating macro unit circuit executes the instruction sent by the INS bus based on the stored identification data.

[0105] In one embodiment, refer to Figure 5 , the tag unit includes a comparator for reading an analog signal from the iSC bus; traversing and comparing the read analog signal with a plurality of reference analog signals, and outputting a digital signal according to the comparison result.

[0106] In one embodiment, the output of the tag module serves as a judgment signal or an enable signal to control whether the current PE executes the global SIMD instruction. For a PE designed with a TAG module, when the TAG output status is "invalid", the current PE does not execute the current instruction. Conversely, when the TAG output status is "valid", the current PE executes the current instruction. The signals affecting the TAG tag module come from the operation process of the analog register, such as signal overflow after operation, numerical judgment of digital signals "0" and "1", and other operation results. The TAG tag module is designed to consist of a comparator circuit and a latch circuit. The comparator circuit is used to compare the signals on the iSC bus with the reference input signals, and then stores the output result of the comparator into the subsequent latch. The TAG tag module controls the internal sensing unit, analog memory-computation unit, digital memory-computation unit, and adjacent PE communication module in the PE, and controls the read-write operations or working states of the above unit circuits through an enable circuit. The control range of the TAG tag module is only the current PE. The chip restores the TAG to its initial state through a global TAG reset signal.

[0107] In this embodiment, in the digital-to-analog conversion mode, the comparator circuit of the tag module is used to compare the analog signal with several reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current instruction.

[0108] In the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator into the subsequent latch. When the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current instruction.

[0109] The communication interface between adjacent PEs is also designed in the PE, such as Figure 2 the adjacent PE communication unit (Adjacent IF) in it, which can provide the information of the 8 PEs surrounding the current PE to the current PE. The above module units are connected together through a specially designed sense-memory-computation bus, the iSC bus. The analog signal can be a voltage or a current signal. In addition to the iSC bus, a global instruction bus, the INS bus, is also designed in the PE to perform overall operation control on each functional module in the PE. Since the INS bus of each PE is controlled by the same global signal, in this way, the integration of memory and computation (SIMD) is achieved.

[0110] In one embodiment, the original signal can come from the SU unit, or be written into the PE from outside the chip as shown in the IO access, or be the signal of an adjacent PE, and be transmitted to the bus of this PE through the adjacent IF. The SU, IO or adjacent IF transmits the sensed signal to the analog register AREG BANK or the AOP unit through the iSC bus. Storage and operations can be performed inside the AREG, and the specific implementation will be described in detail below. The analog signal is converted into a digital signal and then stored in the DREGBANK, where digital operations and storage can be carried out. The operation result can be stored in the AREG or DREG of the PE and then output to the outside of the chip through the iSC bus or other buses and transmission lines to achieve a certain application function.

[0111] In one embodiment, it further includes: a DAC unit arranged outside the array structure, and the external DAC unit serves as the first control module.

[0112] In one embodiment, the sensing, storage and computing integrated macro cell circuit array is located on the same chip, and the external DAC is located inside or outside the chip.

[0113] In one embodiment, the sensing, storage and computing integrated macro cell circuit further includes: a second control module for initializing the value of the digital storage and computing unit to 0; when the comparison result of the tag module is that the analog signal is less than the reference analog signal, then every time a comparison is made, the digital signal stored in the digital storage and computing unit changes by one value according to the coding rule until the analog signal is greater than or equal to the reference analog signal, and the digital signal obtained by the digital storage and computing unit.

[0114] The following further explains in combination with the sensing, storage and computing integrated macro cell circuit and its analog-to-digital conversion method.

[0115] Reference Figure 6 , the analog-to-digital conversion method of the sensing, storage and computing integrated macro cell circuit in this embodiment includes the steps of:

[0116] The tag module reads the analog signal from the iSC bus;

[0117] The tag module traverses and compares the read analog signal with a plurality of reference analog signals;

[0118] Obtain the corresponding digital signal according to the comparison result;

[0119] The plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship.

[0120] Among them, the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship.

[0121] In one embodiment, the reference analog signal gradually increases or decreases with the number according to a linear function, exponential function, logarithmic function, power function, or trigonometric function relationship.

[0122] In one embodiment, the encoding rule of the digital signal is standard binary code, Gray code, Hamming code, or Huffman code.

[0123] The present invention realizes the conversion from the PE analog domain to the digital domain, that is, converts the analog signal in the PE into the corresponding digital signal. The following example converts the analog signal of AREG in the PE, such as a current signal, into a 3-bit precision digital signal. In actual use, a 5-bit precision or even higher 8-bit digital signal can be used and stored in the digital memory DREG.

[0124] In this embodiment, the original signal can come from the SU unit, or be written into the PE from outside the chip, or come from the analog register AREG BANK, or the AOP unit, and then be sent to the iSC bus. The TAG unit receives the analog signal from the iSC bus. Thus, according to the magnitude of the AREG analog current signal and the magnitude of the voltage input to the negative input terminal, the converted digital signal can be obtained, and then stored in the DREG BANK, where digital operations and storage can be performed. The operation result can be stored in the DREG of the PE and then output to the outside of the chip through the iSC bus to achieve a certain application function. In the analog-to-digital conversion step, the analog memory and computing unit sends the analog signal to the iSC bus.

[0125] All of the above data transmissions and signal acquisitions require INS instruction control. The INS bus connects the components in each PE. The INS can come from instructions issued by a system outside the chip, or be issued by the internal MCU module of the chip, or the chip itself generates INS for specific applications. The tag module determines whether the current sensing memory and computing integrated macrocell circuit executes the instruction sent by the INS bus based on the stored identification data.

[0126] Specifically, in this embodiment, the storage current range of AREG is -8uA to 8uA, and the voltage output to the iSC bus will also change correspondingly, from 0.2V to 0.9V.

[0127] Specifically, the output of the tag module serves as a judgment signal or an enable signal to control whether the current PE executes the global SIMD instruction. For a PE designed with a TAG module, when the TAG output status is "invalid", the current PE does not execute the current instruction. Conversely, when the TAG output status is "valid", the current PE executes the current instruction. The signals affecting the TAG tag module come from the operation process of the analog register, such as signal overflow after operation, numerical judgment of digital signals "0" and "1", and other operation results. The TAG tag module is designed with a comparator circuit such asFigure 5 It consists of the comparator circuit and the latch circuit as shown. The comparator circuit is used to compare the signals on the iSC bus with the reference input signal, and then stores the output result of the comparator into the subsequent latch. The TAG controls the internal sensing unit, analog computing unit, digital computing unit, and adjacent PE communication module of the PE, and controls the read / write operations or working states of the above unit circuits through the enable circuit. The control range of the TAG label module is only the current PE. The chip restores the TAG to its initial state through the global TAG reset signal.

[0128] In one embodiment, it further includes the step: the label module determines whether the current sense-compute-in-one macrocell circuit executes the instruction sent by the INS bus based on the stored identification data.

[0129] In one embodiment, it further includes the step: in the analog-to-digital conversion mode, the comparator circuit is used to compare the analog signal with several reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the label module is the first value, the corresponding processing unit executes the current instruction. When the comparison result stored in the label module is the second value, the corresponding processing unit does not execute the current instruction.

[0130] In one embodiment, it further includes the step: in the non-analog-to-digital conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator into the subsequent latch; when the comparison result stored in the label module is the first value, the corresponding processing unit executes the current instruction. When the comparison result stored in the label module is the second value, the corresponding processing unit does not execute the current instruction.

[0131] Specifically, the analog-to-digital conversion mode and the non-analog-to-digital conversion mode can be achieved by connecting a multiplexer to the reference signal input terminal of the comparator. For example, in the analog-to-digital conversion mode, the input reference analog signal is selected, and in the non-analog-to-digital conversion mode, the comparison reference signal with the identification data is selected. Additionally, a multiplexer can also be set at the positive input terminal of the comparator to select to read the analog signal from the iSC bus in the corresponding mode.

[0132] Because the main circuit of the TAG module is the comparator circuit, the characteristics of the TAG comparator are utilized to implement the ADC function in the PE, that is, to achieve the mutual conversion of analog domain signals to digital domain signals in the PE. Specifically, the iSC bus is connected to the positive terminal of the comparator in the TAG. The negative terminal of the comparator in the TAG inputs the reference analog signal.

[0133] Specifically, the AREG or SU can send analog signals to the iSC bus. The TAG internally includes a comparator circuit, which is used to compare the magnitudes of the two signals: the analog signal obtained from the iSC and the reference analog signal. As Figure 5As shown, the gate of MOS transistor M171 inputs voltage signal A, the gate of MOS transistor M172 inputs voltage signal B, the drain of MOS transistor M172 serves as the output terminal, and the comparator circuit is used to compare the magnitudes of the two signals. When A is less than B, the output of TAG will become 0, or the output terminal of analog register AREG is input to terminal B, and the reference analog signal voltage is input to terminal A to determine whether the value of AREG exceeds the given reference analog signal voltage. If it exceeds, it is 0; if it is lower than the threshold, it becomes 1.

[0134] For example, in this embodiment, the DAC unit peripheral to the PE array is used to connect to the negative terminal of the comparator in TAG to provide the reference analog signal. According to Figure 8 and Figure 9 , the DAC module on the chip can be used to generate a ramp staircase voltage and output it to the negative terminal of the comparator. The output range corresponds to the signal range stored in AREG. The change of the ramp staircase output voltage is related to the quantization accuracy. For example, for 3-bit quantization accuracy, 8 staircase voltage values are required. This correspondence is a linear relationship, and the size of the encoding is linearly related to the quantized voltage.

[0135] In this embodiment, the encoding rule for digital signals is the standard binary code. In other embodiments, it can also be in accordance with Gray code, Hamming code, Huffman code, etc., all within the protection scope of the present invention. The reference analog signal increases or decreases gradually with the number of times according to a linear function, exponential function, logarithmic function, power function, or trigonometric function relationship. In another embodiment of the present invention, another non-linear quantization method is adopted to adjust the output characteristics of the DAC to make its output non-linear, such as a LOG curve, and corresponding linear digital encoding, which can achieve a quantization conversion method with a higher dynamic range, especially for data conversion in optical imaging.

[0136] In one embodiment, as Figure 7 shown, the control flow, through instruction control, the chip performs operations according to the instructions, and the entire PE array operates in SIMD mode. The conversion of analog signals to digital signals, the specific operation process and steps are as follows:

[0137] S10: Reset the TAG unit, and the TAG value becomes "0".

[0138] S20: Initialize DREGs to 0, and store DREG1, DREG2, and DREG3 as initial values, such as 000.

[0139] S30: The TAG unit compares the analog signal and the reference analog signal.

[0140] The TAG unit receives the analog signal from the iSC bus, and the external DAC provides the analog reference signal to the TAG unit, such as 0.2v.

[0141] S40: Assign a TAG value according to the comparison result; if the analog signal of the TAG unit is less than the reference analog signal, then TAG = 0, and step S50 is executed.

[0142] Otherwise, TAG = 1, and step S60 is executed.

[0143] S50: DREGs change a value according to the coding rule, for example, increment by 1, the values of the corresponding 3-bit DREG1, DREG2, and DREG3 change, and the external DAC provides an analog reference signal to the TAG unit to increase by a fixed value, for example, 0.1v, and the reference analog signal increases to 0.3v, then return to execute step S30.

[0144] S60: DREGs are locked to complete one digital-to-analog conversion.

[0145] Therefore, in steps S30 and S40, it loops continuously until one digital-to-analog conversion is completed.

[0146] The specific corresponding relationship is as follows:

[0147] If the analog signal is less than 0.2V, DREGs are set to 000;

[0148] If the analog signal is between 0.2V and 0.3V, DREG is set to 001;

[0149] If the analog signal is between 0.3V and 0.3V, DREG is set to 010;

[0150] If the analog signal is between 0.4V and 0.5V, DREG is set to 011;

[0151] If the analog signal is between 0.5V and 0.6V, DREG is set to 100;

[0152] If the analog signal is between 0.6V and 0.7V, DREG is set to 101;

[0153] If the analog signal is between 0.7V and 0.8V, DREG is set to 110;

[0154] If the analog signal is between 0.8V and 0.9V, DREG is set to 111;

[0155] The counter function is implemented by controlling multiple DREGs through global instructions. For example, 3-bit precision conversion requires 3 DREGs, DREG0 / DREG1 / DREG2. Let DREG0 / DREG1 / DREG2 change from "000" to "111", and at the same time, each time the value changes, the voltage corresponding to the negative input of the comparator is input. When the voltage at the negative input of the comparator is equal to or greater than the iSC bus voltage, the output of the comparator in the TAG changes from 0 to 1, and the TAG value becomes 1. At this time, the current PE does not respond to the global instruction, the values in DREG0 / DREG1 / DREG2 are not output, the current value is locked, and it no longer changes with the INS control. At this time, the value corresponds to the magnitude of the analog signal. The DREG locks the current value and no longer responds to the global DREG operation, that is, a digital-to-analog conversion is completed.

[0156] In another embodiment, as shown in the figure, the reference analog signal can increase gradually according to the logarithmic function relationship with the number of times.

[0157] In another embodiment, refer to Figure 10 , the encoding rule of the digital signal is to use Gray code. Using the Gray code method can improve the quantization efficiency because the change between natural number sequences involves multiple bits changing simultaneously, which requires multiple instructions to achieve the corresponding value change. If the Gray code method is used, only one bit changes between each number, that is, only one instruction is needed to achieve the change of the corresponding numerical sequence. As follows Figure 3 bit sequence and 4-bit numerical sequence change.

[0158] The specific correspondence is as follows:

[0159] When the analog signal is less than 0.2V, the DREG is set to 000;

[0160] When the analog signal is between 0.2V and 0.3V, the DREG is set to 001;

[0161] When the analog signal is between 0.3V and 0.3V, the DREG is set to 011;

[0162] When the analog signal is between 0.4V and 0.5V, the DREG is set to 010;

[0163] When the analog signal is between 0.5V and 0.6V, the DREG is set to 110;

[0164] When the analog signal is between 0.6V and 0.7V, the DREG is set to 111;

[0165] When the analog signal is between 0.7V and 0.8V, the DREG is set to 101;

[0166] When the analog signal is between 0.8V and 0.9V, DREG is set to 100.

[0167] In another embodiment, 4-bit encoding can also be used, that is, the precision of DREG is 4 bits.

[0168] The specific correspondence is as follows:

[0169] When the analog signal is less than 0.2V, DREG is set to 0000;

[0170] When the analog signal is between 0.2V and 0.25V, DREG is set to 0001;

[0171] When the analog signal is between 0.25V and 0.3V, DREG is set to 0011;

[0172] When the analog signal is between 0.3V and 0.35V, DREG is set to 0010;

[0173] When the analog signal is between 0.35V and 0.4V, DREG is set to 0110;

[0174] When the analog signal is between 0.4V and 0.45V, DREG is set to 0111;

[0175] When the analog signal is between 0.45V and 0.5V, DREG is set to 0101;

[0176] When the analog signal is between 0.5V and 0.55V, DREG is set to 0100;

[0177] When the analog signal is between 0.55V and 0.6V, DREG is set to 1100;

[0178] When the analog signal is between 0.6V and 0.65V, DREG is set to 1101;

[0179] When the analog signal is between 0.65V and 0.7V, DREG is set to 1111;

[0180] When the analog signal is between 0.7V and 0.75V, DREG is set to 1010;

[0181] When the analog signal is between 0.75V and 0.8V, DREG is set to 1011;

[0182] When the analog signal is between 0.8V and 0.85V, DREG is set to 1001;

[0183] When the analog signal is between 0.85V and 0.9V, DREG is set to 1000.

[0184] For the conventional conversion of analog signals to digital signals, a dedicated ADC chip or ADC circuit is required to achieve the conversion. For traditional image sensors, it has evolved from a single ADC in the early stage to column-level ADCs and then to the latest pixel-level ADC design. However, this requires advanced process requirements due to the size limitation of ADC design and the frequency characteristics requirements of ADCs. In this traditional way, the data transfer process results in high latency and high power consumption during processing.

[0185] Especially for the sense-compute chip, there are analog signal operation and storage units and digital signal operation and storage units in the PE. When signals interact or flow between the analog domain and the digital domain, significant problems are faced. Either an ADC circuit is designed in the PE, which brings problems of circuit area and power consumption, or serial conversion is performed through a single ADC circuit, which brings efficiency problems and delays and power consumption problems in data flow.

[0186] In the present invention, the quantized digital signals are stored in DREGs and can be used for calculations in the digital domain or as the final operation result. The present invention provides a method for parallel analog-to-digital signal conversion in the PE. This method does not require a dedicated ADC circuit and utilizes the existing circuits in the PE to achieve the conversion function. This parallel conversion is equivalent to pixel-level or PE-level signal conversion, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion. It is output to the digital system at the rear stage of the chip, such as an MCU.

[0187] Utilize components in the existing PE, such as a comparator, to convert analog signals such as Pixel signals and AREG current signals into digital signals and store them in the DREG in the PE. A method for parallel analog-to-digital signal conversion is realized without the need to add special conversion circuits. This method does not require a dedicated ADC circuit and utilizes the existing circuits in the PE to achieve the conversion function. This parallel conversion is equivalent to pixel-level signal conversion, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion.

[0188] It conforms to the SIMD execution mode of the sense-compute chip. This conversion method only circulates within the PE and does not need to be transmitted outside the PE, thus reducing data flow, significantly reducing latency, and the power consumption caused by data transfer.

[0189] The embodiments of the mechanism disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of this application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0190] Program code can be applied to the input instructions to perform the various functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner.

[0191] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. When needed, the program code can also be implemented in assembly language or machine language. In fact, the mechanisms described in this application are not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0192] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried or stored on one or more transient or non-transitory machine-readable (e.g., computer-readable) storage media, which can be read and executed by one or more processors. For example, the instructions can be distributed via a network or via other computer-readable media. Thus, machine-readable media can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to, floppy disks, optical disks, optical discs, compact discs read-only memory (CD-ROMs), magneto-optical discs, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) in electrical, optical, acoustic, or other forms using the Internet. Thus, machine-readable media includes any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0193] In the drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or ordering may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Additionally, including a structural or method feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0194] It should be noted that each unit / module mentioned in the device embodiments of the present application is a logical unit / module. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or can be implemented as a combination of multiple physical units / module. The physical implementation manner of these logical units / modules themselves is not the most important. The combination of the functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application. This does not mean that there are no other units / modules in the above device embodiments.

[0195] It should be noted that in the examples and descriptions of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising an" does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0196] Although the present application has been illustrated and described by reference to some preferred embodiments of the present application, those of ordinary skill in the art should understand that various changes can be made in form and detail without departing from the spirit and scope of the present application.

Claims

1. An analog-to-digital conversion method for a sense-storage-and-computation integrated macrocell circuit, characterized in that Including steps: The tag module reads an analog signal from the iSC bus; The tag module traverses and compares the read analog signal with a number of reference analog signals; According to the comparison result, the corresponding digital signal is obtained; The number of reference analog signals is data that gradually increases or decreases according to a functional relationship; Obtaining the corresponding digital signal according to the comparison result further includes the steps of: The initial value of the digital memory and computing unit is 0; When the comparison result of the tag module is that the analog signal is less than the reference analog signal, each time a comparison is made, the digital signal stored in the digital memory and computing unit changes by one value according to the coding rule until the analog signal is greater than or equal to the reference analog signal, the tag state changes, and at the same time, the digital signal in the digital memory and computing unit is locked.

2. The analog-to-digital conversion method of a sense-storage-and-computation integrated macrocell circuit according to claim 1, characterized in that The reference analog signal gradually increases or decreases with the number of times according to a linear function, exponential function, logarithmic function, power function or trigonometric function relationship.

3. The analog-to-digital conversion method of a sense-storage-and-computation integrated macrocell circuit according to claim 1, wherein The coding rule of the digital signal is standard binary code, Gray code, Hamming code or Huffman coding.

4. The analog-to-digital conversion method of a sense-storage-computation integrated macro cell circuit according to claim 1, wherein It further includes the step of: the tag module determines whether the current sense memory and computing integrated macro cell circuit executes the instruction sent by the INS bus based on the stored identification data.

5. The analog-to-digital conversion method of a sense-in-memory-and-compute integrated macrocell circuit according to claim 4, wherein It further includes the step of: The tag module consists of a comparator circuit and a latch circuit. In the digital-to-analog conversion mode, the comparator circuit is used to compare the analog signal with a number of reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current instruction.

6. The analog-to-digital conversion method of a sense-storage-and-computation integrated macrocell circuit according to claim 5, characterized in that In the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator into the subsequent latch; when the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current instruction.

7. The analog-to-digital conversion method of a sense-storage-computation integrated macrocell circuit according to claim 3, characterized in that, The digital signal is a 3-bit binary signal.

8. The analog-to-digital conversion method of a sense-storage-and-computation integrated macrocell circuit according to claim 1, characterized in that It further includes the step of: The DAC unit outside the sense memory and computing integrated macro cell circuit sends a reference analog signal.

9. A sense, storage, and computing integrated macrocell circuit using the analog-to-digital conversion method described in claim 1, characterized in that, Including: The iSC bus is used to connect each module and transfer sensing signals and operation signals between modules; The INS bus is used to connect each module; The digital memory and computing unit is used to simultaneously store and operate data, and the data includes digital signals; The analog memory and computing unit is used to simultaneously store and operate data, and the data includes analog signals; The tag module is used to read an analog signal from the iSC bus; traverse and compare the read analog signal with a number of reference analog signals; The output module is used to obtain a digital signal according to the comparison result; The first control module is used to provide a reference analog signal to the tag module, and the number of reference analog signals is data that gradually increases or decreases according to a functional relationship.

10. The sense-in-memory-and-computation integrated macrocell circuit according to claim 9, characterized in that, The reference analog signal gradually increases or decreases with the number of times according to a linear function, exponential function, logarithmic function, power function or trigonometric function relationship.

11. A sense-in-memory-and-compute integrated macrocell circuit according to claim 9, characterized in that, An encoding module for corresponding a reference analog signal and a digital signal according to a certain encoding rule, and the encoding rule of the digital signal is standard binary code, Gray code, Hamming code or Huffman coding.

12. A sense-in-memory-and-computation integrated macrocell circuit according to claim 9, wherein, It further includes: A second control module for initializing the value of the digital memory and computing unit to 0; When the comparison result of the tag module is that the analog signal is less than the reference analog signal, then for each comparison, the digital signal stored in the digital memory and computing unit changes by one value according to the encoding rule until the analog signal is greater than or equal to the reference analog signal.

13. The sense-in-memory-and-computation integrated macrocell circuit according to claim 9, wherein The analog memory and computing unit, digital memory and computing unit, iSC bus, INS bus and tag module are integrated on the same chip.

14. A sense-in-memory-and-computation integrated macrocell circuit according to claim 9, wherein The tag module determines whether the current sensing and computing integrated macro cell circuit executes the instruction sent by the INS bus based on the stored identification data.

15. A sense-in-memory computing integrated macrocell circuit according to claim 14, characterized in that, The tag module consists of a comparator circuit and a latch circuit. In the digital-to-analog conversion mode, the comparator circuit is used to compare the analog signal with several reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

16. A sense-in-memory-and-compute integrated macrocell circuit according to claim 15, characterized in that, In the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator into the subsequent latch; when the comparison result stored in the tag module is the first value, the corresponding processing unit executes the current INS instruction. When the comparison result stored in the tag module is the second value, the corresponding processing unit does not execute the current INS instruction.

17. The sense-in-memory-and-computation integrated macrocell circuit according to claim 9, wherein The analog memory and computing unit includes multiple analog signal memories, and the analog signal memories also serve as analog operation units. By connecting the multiple analog signal memories of the analog memory and computing unit to the same iSC bus for reading and writing operations, the analog signal can directly perform addition, subtraction, multiplication and division operations in the analog signal memory.

18. A sense-in-memory-in-computation integrated macrocell circuit according to claim 9, wherein The digital memory and computing unit includes multiple digital signal memories, and the digital signal memories have both storage and logical operation capabilities.

19. The sense-in-memory-and-compute integrated macrocell circuit according to claim 9, characterized in that, A DREG BANK is provided in the digital memory and computing unit, and the DREG BANK includes multiple digital signal memories, as well as a digital read bus iSCRD DBUS and a digital write bus iSC WR DBUS. The digital signal memories are digital registers DREG; Multiple digital registers DREG are connected in parallel between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS. Among them, the input end IN of the digital register DREG is connected to the iSC WR DBUS, the output end OUT of the digital register DREG is connected to the data read bus iSC RD DBUS, and a multiplexer MUX is also connected between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS. The digital read bus iSC RD DBUS of the digital register DREG is also connected to the iSC bus through a switch.

20. The sense-in-memory-and-computation integrated macrocell circuit according to claim 19, wherein The digital signal memory is implemented using 3T DRAM, 6T DRAM, or SRAM.

21. The sense-in-memory-and-compute integrated macro cell circuit according to claim 19, characterized in that, The digital signal memory is implemented using Flash, and further includes: a plurality of FLASH memories, a read / write control circuit, a digital read bus iSC RD DBUS, and a multiplexer MUX. The input end IN of the FLASH memory is connected to the read / write control circuit, the output ends of the FLASH are connected in parallel to the digital read bus iSC RD DBUS, and a multiplexer MUX is connected between the digital read bus iSC RD DBUS and the read / write control circuit.

22. A sense-in-memory-in-computation integrated macrocell system comprising the sense-in-memory-in-computation integrated macrocell circuit of any one of claims 9 to 21, characterized in that, Comprising: A plurality of sense-compute-in-one macro cell circuits are arranged in an array structure, where: The sense-compute-in-one macro cell circuit includes: An iSC bus for connecting each module to transfer sensing signals and computing signals between modules; An INS bus for connecting each module; A digital memory and computing unit for simultaneously storing and computing data, where the data includes digital signals; An analog memory and computing unit for simultaneously storing and computing data, where the data includes analog signals; A tag module for reading analog signals from the iSC bus; traversing and comparing the read analog signals with a plurality of reference analog signals; An output module for obtaining digital signals according to the comparison results; A first control module for providing reference analog signals to the tag module, and the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship; An external DAC unit is further included and serves as the first control module.

23. The sense-storage-computation integrated macro cell system according to claim 22, characterized in that, The sense-compute-in-one macro cell circuit array is located on the same chip. The external DAC is located inside or outside the chip.

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