High computing power application oriented pipeline processor architecture
By designing a pipeline processor architecture in a multi-core processor, connecting the arithmetic logic units and registers of adjacent pipeline processors, and introducing instruction locking units, the problem of low data transfer efficiency between processors is solved, and efficient large-scale Data calculation.
Patent Information
- Application Number
- CN202411587755.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-14
AI Technical Summary
In multi-core processors, the arithmetic logic units of each processor are relatively independent, resulting in the large instruction overhead of data transmission during complex calculations, and the processor's computing power cannot be used to maximize the calculation power, affecting the computing efficiency.
Design a pipeline processor architecture for high computing power applications, and connect the arithmetic logic units of adjacent pipeline processors to registers and add instruction locking units to achieve efficient data calculation and effective instructions locking.
By reducing the impact of memory access process and instruction cycles when data is passed between processors, the computing units of each processor are maximized, and the computing efficiency of large-scale data operations is significantly improved.
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Figure CN119441135A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of hardware system architecture, and in particular relates to a pipeline processor architecture for high computing power applications. Background Art
[0002] With the rapid development of artificial intelligence and large models, reasoning calculations are widely used in scene applications. At the same time, since the calculation process is accompanied by a large number of logical calculations, higher requirements are placed on the computing power of the processor. Therefore, for a processor, whether it can efficiently run large-scale calculations in this scenario has become one of the criteria for measuring the performance of the processor.
[0003] In a multi-core processor, each processor can perform various types of calculations, but the arithmetic logic unit of each processor is still relatively independent. For a complex calculation, when each processor needs to process it at the same time, data transfer between processors still requires a large instruction overhead, resulting in the arithmetic logic unit of each processor cannot be fully utilized, greatly affecting the computing efficiency of the processor. Therefore, how to make each processor transfer data with the highest efficiency when processing the same set of calculations has become a top priority for improving the computing power of the processor. Summary of the invention
[0004] The present invention provides a pipeline processor architecture for high computing power applications, which designs each processor pipeline level, adds a data interface between an arithmetic logic unit and a register in a pipeline sequence, and adds an instruction lock unit to achieve efficient data calculation, so that multiple CPUs can simultaneously perform various parts of a complete calculation in a pipeline form.
[0005] The present invention adopts the following technical solution: a pipeline processor architecture for high computing power applications, comprising:
[0006] n CPUs are arranged in sequence according to the pipeline structure. The i-th CPU is the i-th level pipeline processor, i=0, ..., n-1; CPU0 is the first level pipeline processor, which is used to read data and send data to the next level processor; the last level processor is used to process the data from the previous level processor and write the data back to the main memory;
[0007] The CPU includes an arithmetic logic unit; the i-th CPU sends the data obtained by the internal arithmetic logic unit to the general register of the i+1-th CPU, the i+1-th CPU sends the data from the general register to the internal arithmetic logic unit for calculation through instructions, and then sends the data calculated by the arithmetic logic unit of the i+1-th CPU to the general register of the i+2-th CPU processor.
[0008] The CPU comprises:
[0009] A control unit is used to control the CPU instruction execution process;
[0010] Arithmetic logic unit, used to execute the arithmetic logic of the arithmetic instructions;
[0011] Data registers are used to store data generated during CPU operation;
[0012] Data access unit, used for CPU to access external memory.
[0013] The control unit comprises:
[0014] Instruction register, used to store instructions during CPU operation;
[0015] The instruction lock unit is used to lock the instruction logic in the arithmetic logic unit or the data access unit when the CPU loads instructions;
[0016] Instruction counter, used to count the CPU program running process;
[0017] The instruction lock unit is used to lock logical operation instructions and data access instructions. When a lock occurs, the corresponding CPU works with the locked instruction logic until the next new instruction is generated, then the instruction logic of the corresponding CPU is replaced.
[0018] The pipeline structure arranges the CPUs in sequence, and the calculation result of each CPU is directly sent to the next pipeline CPU for calculation; wherein the first pipeline processor is used for data reading and memory access, and the last pipeline processor is used for data writing back and memory access.
[0019] Each CPU starts running one pipeline cycle later in the pipeline sequence to ensure that when the previous pipeline CPU finishes calculation and sends data to the next pipeline processor, the next pipeline processor is ready to start processing data from the previous pipeline processor.
[0020] A pipeline processor method for high computing power applications includes the following steps:
[0021] CPU0, as the main control core, divides the received data into several single instruction calculations and distributes them to each CPU according to the CPU pipeline structure;
[0022] CPU0 is responsible for synchronizing each CPU. After all CPUs are ready, it issues a unified execution command, and each CPU starts calculating in sequence according to the pipeline level.
[0023] Each CPU controls whether the instruction decoding logic is locked in the corresponding instruction register, instruction counter or instruction decoding according to the instruction lock signal, until a new instruction appears and the new logic is locked;
[0024] Each CPU performs arithmetic logic and data access functions according to the decoding of instructions, and each CPU runs the corresponding operations according to the pipeline level until all calculations are completed.
[0025] A method for implementing a pipeline processor for high computing power applications includes the following steps:
[0026] CPU0 starts to calculate and starts to fetch the mth instruction in the kth clock cycle. At this time, other CPUs are in suspended state.
[0027] In the k+1th clock cycle, CPU1 starts fetching the mth instruction, and CPU0 performs instruction decoding of the mth instruction;
[0028] In the k+2th clock cycle, CPU0 starts executing the mth instruction and processes the data. At this time, CPU1 decodes the mth instruction and CPU2 fetches the mth instruction.
[0029] In the k+3th clock cycle, CPU0 starts executing the m+1th instruction, CPU1 executes the mth instruction, and its execution data comes from the data obtained by CPU0's execution of the mth instruction. CPU2 decodes the mth instruction, and CPU3 fetches the mth instruction.
[0030] In the k+4th clock cycle, CPU0 starts to execute the m+2th instruction, CPU1 executes the m+1th instruction, and its execution data comes from the m+1th instruction of CPU0, CPU2 executes the mth instruction, and its execution data comes from the mth instruction of CPU1, CPU3 decodes the mth instruction, and CPU4 fetches the mth instruction;
[0031] CPU0, CPU1, CPU2, CPU3, and CPU4 execute in their respective order of instruction fetching, instruction decoding, and execution;
[0032] When CPU4 completes the execution of the mth instruction, it indicates that the data calculation of the current CPU pipeline stage is completed. Within a certain clock cycle, CPU4 starts the memory access function to store the data back to the main memory. At the same time, CPU4 executes the m+1th instruction, and its data comes from the m+1th instruction of CPU3.
[0033] For the data access part, CPU0 and CPU4 serve as the first pipeline processor and the last pipeline processor respectively; the first pipeline processor is used to preprocess the data, load the input feature data and the input weight data, and fix the logical operation instructions of the data preprocessing in the logical operation unit, and only update the data loading instructions each time;
[0034] For the last pipeline processor, it is used to perform bias processing on the data and write the output layer data back to the main memory. The logic operation instructions for bias processing are fixed in the logic operation unit, and only the data storage instructions are updated each time; until all the output layer data calculations are completed, that is, the entire calculation is completed.
[0035] The present invention has the following beneficial effects and advantages:
[0036] The present invention connects the arithmetic logic units of adjacent pipeline processors with registers so that no additional memory access process is required when data is calculated and transferred between processors. At the same time, an instruction locking function is added to reduce the impact of repeated instructions on instruction cycles, maximize the use of the computing units of each processor, and greatly improve the computing efficiency during large-scale data operations. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 This is the pipeline processor architecture diagram;
[0038] Figure 2 It is a schematic diagram of the inter-processor pipeline;
[0039] Figure 3 This is a schematic diagram of the pipeline hardware;
[0040] Figure 4 Flowchart of the method for high computing power implementation;
[0041] Figure 5 This is a schematic diagram of the splitting and allocation of the computing structure. DETAILED DESCRIPTION
[0042] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0043] A pipeline processor architecture for high-computing applications (such as Figure 1 ), contains multiple high-efficiency processors (CPU0, CPU1, ..., CPUn), and arranged in a pipeline structure (CPU0 is the first-level pipeline processor, CPU1 is the second-level pipeline processor, and so on), where:
[0044] Each processor, based on the traditional general-purpose processor, adds an instruction lock unit, which is used to lock the instruction logic in the arithmetic logic unit or the data access unit when the processor loads instructions.
[0045] Each processor (except CPU0) is based on the traditional general-purpose processor and adds an interface for outputting the calculation results of the arithmetic logic unit of the previous pipeline processor to the data register of the next pipeline processor, which is used to connect data between two adjacent processors.
[0046] The processors are arranged in a pipeline structure, and the processors are arranged in sequence. The calculation result of each processor can be directly sent to the next pipeline processor for calculation. Among them, the first pipeline processor is also responsible for data reading and memory access, and the last pipeline processor is also responsible for data writing back to memory access.
[0047] The first pipeline processor is usually CPU0, and the last pipeline processor is the last CPU according to the number of processors actually required for the calculation. When the number of processors required for the calculation is small, multiple groups of calculations can be calculated on the same pipeline of processors. At this time, the intermediate processor can be selected in sequence according to the pipeline order as the first pipeline processor of the next group of calculations.
[0048] The processor pipeline structure is arranged so that when the entire system starts calculating, each processor starts running one pipeline cycle later in the order of the processor pipeline, so as to ensure that when the previous pipeline processor finishes the calculation and sends the data to the next pipeline processor, the next pipeline processor is ready to start processing the data from the previous pipeline processor (such as Figure 2 ).
[0049] The arrangement of the processor pipeline structure does not affect the original pipeline structure of each processor. On this basis, a pipeline structure is formed between processors (such as Figure 3 ), decomposes a complex large-scale calculation into calculations that can be completed by a single processor, and sends each calculation instruction to the corresponding pipeline processor for calculation according to the calculation order and the processor pipeline order.
[0050] Break down a complex large-scale calculation into calculations that can be completed by a single processor. The calculation that can be completed by a single processor is the calculation that can be completed in one pipeline cycle through a single instruction, so that when the calculation is completed in the previous processor pipeline stage, the next processor pipeline stage can be ready before the calculation starts.
[0051] The instruction locking unit can lock logical operation instructions and data access instructions. When the lock occurs, the corresponding hardware unit will work with the locked logic until the next new instruction is generated, and then the logic of the corresponding hardware unit will be replaced.
[0052] The communication interface between the two adjacent processors will arbitrate the data from the previous pipeline processor and the calculation results generated by the logic operation unit of the current processor through the control signal of CPU0 in the next pipeline processor to ensure expansion without affecting the hardware function of the original processor.
[0053] A method for implementing a pipeline processor architecture for high computing power applications, comprising the following steps (eg Figure 4 ):
[0054] CPU0, as the main control core, is responsible for identifying the calculation structure, dividing it into several single instruction calculations, and distributing them to each CPU according to the pipeline structure of the processor.
[0055] CPU0 is responsible for synchronizing each CPU. After all CPUs are ready, it issues an execution command at the same time, and each processor starts calculating in sequence according to the pipeline level.
[0056] Each CPU controls whether the instruction decoding logic is locked in the corresponding hardware unit according to the instruction locking signal until a new instruction appears and the new logic is locked.
[0057] Each CPU executes the hardware arithmetic logic and data access functions according to the decoding of the instructions, and each CPU runs the corresponding operations at high speed according to the pipeline level until all calculations are completed.
[0058] The present invention connects the in-core general registers of each processor in a multi-core processor with the arithmetic logic unit of an adjacent processor to form the fastest data transmission between cores, reduces the process of data synchronization between cores through the main memory, makes the most efficient use of the arithmetic logic unit of each processor, and improves the computing efficiency of the entire multi-core processor.
[0059] In the original general-purpose processors, in the multi-core architecture, each processor runs its own program relatively independently. When there is a relatively large computing demand, it is usually necessary to divide the calculation into several parts and hand them over to each processor for processing respectively. Due to the close connection between these data, data transmission between processors is often involved. Although for homogeneous processors, data coordination between processors can be achieved through data cache and hardware management of cache consistency between multi-cores, a long clock cycle is still required when data is transmitted from the general register inside the processor to the cache and the cache consistency between data is synchronized. This greatly reduces the computing power of the entire processor. Therefore, the present invention proposes that for large-scale calculations, by synchronizing data between processors at the general register level and introducing an instruction locking function, pipeline-level calculation of large-scale data can be achieved, the cycle delay caused by data coordination between processors can be reduced, and the computing power performance of the processor can be improved.
[0060] The original general-purpose processor includes a control unit, an arithmetic logic unit, a data register, and a data access unit. The main memory is used to store the code and data for program operation. The present invention makes improvements on this basis. The present invention arranges the multi-core processors in order. When the function of efficient calculation is triggered, the data will be directly sent from the arithmetic logic unit of the previous pipeline processor to the data register of the next pipeline processor. The next level register will send the data sent from the previous level to the arithmetic logic unit of the current processor for processing according to the current instruction according to the decoding logic, and send it to the data register of the next level processor after the processing is completed, until the calculation of the last level processor is completed, and the data is returned to the main memory according to the instruction; when the function of efficient calculation is not triggered, each processor will run the code stored in its main memory relatively independently.
[0061] In a multi-core processor, we select CPU0 as the main core to control whether the entire multi-core processor performs efficient calculations. At the same time, as the first level of the entire processor pipeline under efficient calculations, it is used to read data and send data to the next level processor. For the last level processor, it is used to process data from the previous level processor and write the data back to the main memory. Here, the regulations for the last level processor need to be determined comprehensively based on the division level of a set of complete calculations and the number of processors in the multi-core processor. When the number of division levels of a set of complete calculations is greater than the number of processors in the multi-core processor, the set of complete calculations needs to be cut again until the number of processors required for calculation does not exceed the number of processors contained in the current multi-core processor; when the number of division levels of a set of complete calculations is not greater than the number of processors in the multi-core processor, the reorganized calculation can be directly placed in the multi-core processor for calculation. At this time, CPU0 is used as the main core to perform the first level of data calculation; at this time, when the remaining processors can still support a complete set of complete calculations, CPU0 can control the first remaining processor arranged in the pipeline level as the first pipeline processor of the next group of calculations to read and calculate data.
[0062] For a processor, according to the pipeline mechanism of the processor, the entire processing process is usually divided into the following processes: instruction fetching, which is used to read the program from the main memory; instruction decoding, which is used to decode the instruction according to the processor's instruction set and convert it into the corresponding data processing behavior; data execution, which is used to read the data from the register according to the instruction and send it to the arithmetic logic unit for calculation; memory access, which is used to read the data from the main memory to the general register, or write the data from the general register to the main memory; write back, which is used to write the calculated data back to the general register. In the whole process, when there is no efficient calculation function, the data needs to be read from the main memory through memory access, and then written back to the register, and then the data is sent to the arithmetic logic unit for calculation, and the calculated data is written back to the general register again, and then the data is sent from the general register to the main memory through memory access. At this point, a complete calculation process ends, and another processor repeats the above process for calculation. Under efficient computing, the entire process will be shortened to the previous pipeline-level processor sending the data obtained from the arithmetic logic unit to the general register of the next pipeline-level processor. The next pipeline-level processor sends the data from the general register to the arithmetic logic unit for calculation through instructions, and then sends the data calculated by the arithmetic logic unit of the current-level processor to the general register of the next pipeline-level processor, and the cycle continues.
[0063] The first and last stages of the processor pipeline are often accompanied by data reading and data writing. These two processes usually require additional instructions to be performed, which results in the processor being unable to perform data calculation functions during the process, thereby reducing processing efficiency. In actual CPU hardware, the logic operation unit and the data access unit are two independent hardware units, and in the pipeline structure of a single CPU, the execution process and the memory access process belong to two different pipeline stages. In the currently involved efficient computing structure, the overall computing data structure is usually relatively neat and does not require frequent instruction changes. Therefore, the present invention is based on the original An instruction locking unit is added to the processor. For the logic operation unit and the data access unit, when they are read out in the form of instruction locking, the CPU can lock the logic operation logic and data access logic obtained by decoding the part of the instructions in the corresponding hardware unit. Only when it is necessary to change the logic of this part is re-decoded, and when re-decoding, only changing the logic operation logic or only changing the data access logic does not affect the operation of another locked logic, thereby reducing the problem of occupying the pipeline of a single CPU during data transfer, resulting in a decrease in the operating efficiency of the processor, and retaining the flexibility of the processor to handle different operations.
[0064] Here, the present invention takes the case where the number of multi-core processors is 5 and the pipeline level of each processor is 5 as an example to illustrate the execution process and pipeline of the processor. For a complex calculation, CPU0 first identifies the structure of the data calculation, and divides it into several calculations that can be performed by a single instruction according to the calculation order and the number of CPUs, and sends the complex calculation of each CPU to the corresponding CPU.
[0065] Here we take a typical CNN (convolutional neural network, commonly used in large models) as an example for splitting (such as Figure 5 ), for a complete output layer data, it is necessary to carry out preprocessing, filtering operation, convolution operation, nonlinear operation and bias processing in sequence. Each calculation logic can complete the calculation for a set of local data through a single instruction. According to the pipeline order of the CPU, each part is assigned to CPU0, CPU1, CPU2, CPU3 and CPU4 respectively. Each CPU identifies the calculation it is responsible for and starts to execute the program in sequence according to the order specified by the pipeline. Here, in order to ensure that each CPU starts to execute according to its corresponding pipeline order, it is necessary to synchronize each CPU through CPU0 as the main core to ensure that each CPU is at its corresponding pipeline level.
[0066] When entering the efficient computing of multi-core processors, CPU0 starts computing first, and starts fetching the first instruction in the first cycle, while other processors are in suspended state; in the next clock cycle, CPU1 starts fetching the first instruction, while CPU0 performs instruction decoding of the first instruction; in the next clock cycle, CPU0 starts executing the first instruction and processes the data, while CPU1 performs instruction decoding of the first instruction, while CPU2 performs instruction fetching of the first instruction; in the next clock cycle, CPU0 starts executing the second instruction, while CPU1 executes the first instruction, and the data for execution comes from the data obtained by the execution of the first instruction of CPU0, while CPU2 performs instruction decoding of the first instruction, while CPU3 performs instruction fetching of the first instruction; in the next clock cycle, CPU0 starts executing the third instruction, while CPU1 executes the second instruction, and the data for execution comes from the second instruction of CPU0, while CPU2 executes the first instruction, and the data for execution comes from the first instruction of CPU1, while CPU3 performs instruction decoding of the first instruction, while CPU4 performs instruction fetching of the first instruction. And so on.
[0067] When CPU4 completes the execution of the first instruction, the data calculation of the current processor pipeline stage is completed. In the next clock cycle, CPU4 will start the memory access function to store the data back to the main memory. At the same time, CPU4 executes the second instruction, and its data comes from the second instruction of CPU3, and so on. When the five processors and five pipeline stages are working at full capacity, based on the pipeline characteristics of the processor level of the entire multi-core processor, the arithmetic logic unit of each processor can process data at the same time, maximizing the computing power of the entire processor.
[0068] For the data access part, CPU0 and CPU4 serve as the first pipeline processor and the last pipeline processor respectively. For the first pipeline processor, in addition to data preprocessing, it is also necessary to load input feature data and input weight data. Since the calculation form of data preprocessing is consistent for each group of data, the logical operation instructions of data preprocessing are fixed in the logical operation unit, and only the data loading instructions are updated each time. For the last pipeline processor, in addition to data bias processing, it is also necessary to write the output layer data back to the main memory. Similarly, the logical operation instructions of bias processing are fixed in the logical operation unit, and only the data storage instructions are updated each time. Until all the output layer data calculations are completed, the entire calculation is completed.
Claims
1. A pipeline processor architecture for high computing power applications, characterized in that: include: n CPUs are arranged in sequence according to the pipeline structure, the i-th CPU is the i-th level pipeline processor, i=0,…,n-1; CPU0 is the first-level pipeline processor, which is used to read data and send data to the next-level processor; for the last-level processor, it is used to process data from the previous-level processor and write the data back to the main memory; The CPU includes an arithmetic logic unit; the i-th CPU sends the data obtained by the internal arithmetic logic unit to the general register of the i+1-th CPU, the i+1-th CPU sends the data from the general register to the internal arithmetic logic unit for calculation through instructions, and then sends the data calculated by the arithmetic logic unit of the i+1-th CPU to the general register of the i+2-th CPU processor.
2. A pipeline processor architecture for high computing power applications according to claim 1, characterized in that: The CPU comprises: A control unit is used to control the CPU instruction execution process; Arithmetic logic unit, used to execute the arithmetic logic of the arithmetic instructions; Data registers are used to store data generated during CPU operation; Data access unit, used for CPU to access external memory.
3. A pipeline processor architecture for high computing power applications according to claim 2, characterized in that: The control unit comprises: Instruction register, used to store instructions during CPU operation; The instruction lock unit is used to lock the instruction logic in the arithmetic logic unit or the data access unit when the CPU loads instructions; Instruction counter, used to count the CPU program running process; The instruction lock unit is used to lock logical operation instructions and data access instructions. When a lock occurs, the corresponding CPU works with the locked instruction logic until the next new instruction is generated, then the instruction logic of the corresponding CPU is replaced.
4. The pipeline processor architecture for high computing power applications according to claim 1, characterized in that: The pipeline structure arranges the CPUs in sequence, and the calculation result of each CPU is directly sent to the next pipeline CPU for calculation; wherein the first pipeline processor is used for data reading and memory access, and the last pipeline processor is used for data writing back and memory access.
5. The pipeline processor architecture for high computing power applications according to claim 1, characterized in that: Each CPU starts running one pipeline cycle later in the pipeline sequence to ensure that when the previous pipeline CPU finishes calculation and sends data to the next pipeline processor, the next pipeline processor is ready to start processing data from the previous pipeline processor.
6. A method for implementing a pipeline processor for high computing power applications, characterized in that: The following steps are involved: CPU0, as the main control core, divides the received data into several single instruction calculations and distributes them to each CPU according to the CPU pipeline structure; CPU0 is responsible for synchronizing each CPU. After all CPUs are ready, it issues a unified execution command, and each CPU starts calculating in sequence according to the pipeline level. Each CPU controls whether the instruction decoding logic is locked in the corresponding instruction register, instruction counter or instruction decoding according to the instruction lock signal, until a new instruction appears and the new logic is locked; Each CPU performs arithmetic logic and data access functions according to the decoding of instructions, and each CPU runs the corresponding operations according to the pipeline level until all calculations are completed.
7. A method for implementing a pipeline processor for high computing power applications according to claim 6, characterized in that: The following steps are involved: CPU0 starts to calculate and starts to fetch the mth instruction in the kth clock cycle. At this time, other CPUs are in suspended state. In the k+1th clock cycle, CPU1 starts fetching the mth instruction, and CPU0 performs instruction decoding of the mth instruction; In the k+2th clock cycle, CPU0 starts executing the mth instruction and processes the data. At this time, CPU1 decodes the mth instruction and CPU2 fetches the mth instruction. In the k+3th clock cycle, CPU0 starts executing the m+1th instruction, CPU1 executes the mth instruction, and its execution data comes from the data obtained by CPU0's execution of the mth instruction. CPU2 decodes the mth instruction, and CPU3 fetches the mth instruction. In the k+4th clock cycle, CPU0 starts to execute the m+2th instruction, CPU1 executes the m+1th instruction, and its execution data comes from the m+1th instruction of CPU0, CPU2 executes the mth instruction, and its execution data comes from the mth instruction of CPU1, CPU3 decodes the mth instruction, and CPU4 fetches the mth instruction; CPU0, CPU1, CPU2, CPU3, and CPU4 execute in their respective order of instruction fetching, instruction decoding, and execution; When CPU4 completes the execution of the mth instruction, it indicates that the data calculation of the current CPU pipeline stage is completed. Within a certain clock cycle, CPU4 starts the memory access function to store the data back to the main memory. At the same time, CPU4 executes the m+1th instruction, and its data comes from the m+1th instruction of CPU3.
8. The method for implementing a pipeline processor for high computing power applications according to claim 6, characterized in that: For the data access part, CPU0 and CPU4 serve as the first pipeline processor and the last pipeline processor respectively; the first pipeline processor is used to preprocess the data, load the input feature data and the input weight data, and fix the logical operation instructions of the data preprocessing in the logical operation unit, and only update the data loading instructions each time; For the last pipeline processor, it is used to perform bias processing on the data and write the output layer data back to the main memory. The logic operation instructions for bias processing are fixed in the logic operation unit, and only the data storage instructions are updated each time; until all the output layer data calculations are completed, that is, the entire calculation is completed.