Data processing device, computer-readable recording medium storing data processing program, and data processing method

Abstract

The invention discloses a data processing apparatus, a computer-readable recording medium storing a data processing program, and a data processing method. The data processing apparatus includes: a memory that stores a plurality of values at a first point in time, the plurality of values including: a value of a state variable at the first point in time and included in an evaluation function of a combinatorial optimization problem having a constraint condition; a value of a first local field at a first point in time and for specifying an amount of change in a value of an evaluation function by a change in a value of a state variable; and a value of a second local field at the first point in time, and the second local field specifying an amount of value to be added to the evaluation function when the constraint condition is not satisfied; and a control circuit configured to restore the plurality of state variables, the first local field, and the second local field to values at the first point in time when the determination circuit determines that the change is not accepted.

Description

Technical Field

[0001] The embodiments discussed herein relate to a data processing apparatus, a non-transitory computer-readable recording medium storing a data processing program, and a data processing method. Background Art

[0002] There is the method that combinatorial optimization problem is transformed into the Ising model representing the spin behavior of magnetic body when searching the solution of combinatorial optimization problem.Then, utilize Markov chain Monte Carlo method to search the following state of Ising model, in which the value of Ising type evaluation function (that is, the value corresponding to the energy of Ising model) is locally minimized.The state of the minimum value of the local minimum value of evaluation function wherein is reached is regarded as the optimal solution.The state variable included in the Ising type evaluation function is a binary variable taking the value 0 or 1.The state variable can be represented as a bit.Note that the state where the value of evaluation function is locally maximized can also be searched by changing the sign of evaluation function.

[0003] In the following, the Markov chain Monte Carlo method will be referred to as the MCMC method. In addition, the processing based on the MCMC method is sometimes also referred to as the MCMC processing. For example, in the MCMC processing, the state transition is accepted with the acceptance probability of the state transition defined by the Metropolis method or the Gibbs method. Exemplary types of MCMC methods include simulated annealing and replica exchange methods.

[0004] There is a conventional process in which it is assumed that the number of bits that allow a change (hereinafter, referred to as a transition) of a state variable in one trial of a process performed by an MCMC process is one (hereinafter, referred to as a single-bit transition process). However, in the single-bit transition process, when a solution falls into a local solution, it is difficult to escape from the local solution, and the search speed may decrease in some cases.

[0005] Therefore, there is a proposed process for determining whether the conversion of multiple bits is possible based on the calculation result of the change amount of the value of the evaluation function in the case where the conversion of multiple bits occurs, and making the multiple bits convert if the conversion is allowed. Hereinafter, such a process will be referred to as a multi-bit conversion process. Through the multi-bit conversion process, the solution is promoted to escape from the local solution, and the search range can be expanded.

[0006] By the way, some combinatorial optimization problems have constraints that are assumed to be satisfied by the solution. For example, the knapsack problem, which is one of the discrete optimization problems, has a constraint that the total capacity of the luggage loaded into the knapsack is equal to or less than the capacity of the knapsack.

[0007] Japanese Laid-Open Patent Publication No. 2020-021209, Japanese Laid-Open Patent Publication No. 2020-064536, Japanese Laid-Open Patent Publication No. 2021-157361, and Japanese Laid-Open Patent Publication No. 2021-165965 are disclosed as related arts. Summary of the invention

[0008] Technical issues

[0009] In the conventional multi-bit conversion process, the configuration for calculating the amount of change in the value of the evaluation function when the conversion of multiple bits occurs, the configuration of propagation data, etc. become complicated. Therefore, it is not easy to implement.

[0010] In one aspect, an embodiment aims to provide a data processing device, a data processing program and a data processing method capable of realizing a multi-bit conversion process for searching for a solution to a combinatorial optimization problem with constraints.

[0011] Solution to the problem

[0012] According to one aspect of the embodiment, a data processing device is provided, comprising: a memory configured to store a plurality of values ​​at a first point in time, the plurality of values ​​comprising: values ​​of a plurality of state variables at the first point in time, the plurality of state variables being included in an evaluation function of a combinatorial optimization problem with constraints; a value of a first local field at the first point in time, the first local field being used to specify an amount of change in the value of the evaluation function associated with a change in the values ​​of each of the plurality of state variables; and a value of a second local field at the first point in time, the second local field being used to specify an amount of constraint violation of the value to be added to the evaluation function when the constraints are not satisfied; a conversion candidate designation circuit configured to calculate the amount of change by using the value of the first local field at the first point in time, and to designate a candidate for conversion one by one based on the amount of change. A candidate whose value is to be changed among a plurality of state variables is determined; an update circuit configured to update the value of the candidate and the values ​​of the first local field and the second local field each time the candidate is specified, and further update the value of the first local field at a second time point by using the value of the second local field at the first time point and the value at the second time point; a cumulative value calculation circuit configured to calculate a cumulative value of the change amount when the value of the candidate is changed; a determination circuit configured to determine whether to accept a change in the value of a first number of candidates equal to or greater than two based on the cumulative value; and a control circuit configured to restore each of the values ​​of the plurality of state variables, the value of the first local field, and the value of the second local field to a plurality of values ​​at the first time point when the determination circuit determines that the change in the value of the first number of candidates is not accepted.

[0013] Advantageous Effects of the Invention

[0014] In one aspect, embodiments may enable implementation of a multi-bit conversion process that searches for a solution to a combinatorial optimization problem with constraints. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram showing an example of a relationship between a state variable and a second local field;

[0016] Figure 2 is a diagram showing an example of the amount of change in the value of the penalty function due to a change in the value of the state variable;

[0017] Figure 3 is a diagram showing an example of a data processing device according to the first embodiment;

[0018] Figure 4 It is shown in x j Figure 1 shows an example of updating a first local field and a second local field when a value of a local field changes;

[0019] Figure 5 is a diagram showing a circuit example of a memory, an update circuit, and a conversion candidate specifying circuit;

[0020] Figure 6 is a flowchart showing the flow of an example of a data processing method according to the first embodiment;

[0021] Figure 7 is a flowchart showing the flow of an example of a single-bit conversion process;

[0022] Figure 8 is a flowchart showing the flow of an example of multi-bit conversion processing of the data processing method according to the first embodiment;

[0023] Fig. 9 is a flowchart showing the flow of another example of the multi-bit conversion process of the data processing method according to the first embodiment;

[0024] Fig.10 is a diagram (part 1) showing a first example of pipeline processing of the data processing method according to the first embodiment;

[0025] Fig.11 is a diagram (part 2) showing a first example of pipeline processing of the data processing method according to the first embodiment;

[0026] Fig.12 is a diagram (part 1) showing a second example of pipeline processing according to the data processing method of the first embodiment;

[0027] Fig.13is a diagram (part 2) showing a second example of pipeline processing according to the data processing method of the first embodiment;

[0028] Fig.14 is a diagram showing an example of a data processing device according to a second embodiment (part 1);

[0029] Fig.15 is a diagram showing an example of a data processing device according to a second embodiment (part 2);

[0030] Fig.16 is a flowchart showing the flow of an example of multi-bit conversion processing of the data processing method according to the second embodiment;

[0031] Fig.17 is a flowchart showing the flow of another example of multi-bit conversion processing of the data processing method according to the second embodiment;

[0032] Fig.18 is a diagram showing an example of pipeline processing of the data processing method according to the second embodiment (part 1);

[0033] Fig.19 is a diagram showing an example of pipeline processing of the data processing method according to the second embodiment (part 2);

[0034] Fig. 20 is a diagram showing a hardware example of an example of a data processing device; and

[0035] Fig.21 is a diagram showing an example of hardware of a computer. DETAILED DESCRIPTION

[0036] Hereinafter, modes for carrying out the embodiments will be described with reference to the drawings.

[0037] A data processing apparatus according to each of the embodiments described below searches for a solution to a combinatorial optimization problem with constraints using an MCMC method such as a simulated annealing method or a replica exchange method, and outputs a solution found by the search.

[0038] The evaluation function of the combinatorial optimization problem with constraints is represented by the following formula, for example.

[0039] [Mathematical formula 1]

[0040]

[0041] The first and second terms on the right are Ising-type evaluation functions. The first term on the right is used to integrate the product of the values ​​of two state variables (0 or 1) and the weighting factor (indicating the strength of the correlation between the two state variables) for all combinations of state variables that are neither omitted nor repeated. D represents the set of identification numbers of the state variables. i represents a state variable with identification number i, and x j W represents the state variable with identification number j. ij represents a weighting factor indicating the magnitude of the correlation between the state variables having identification numbers i and j. The second term on the right side is obtained by adding the product of the bias coefficient and the state variable for each identification number. b i Indicates the bias coefficient for identification number i.

[0042] The third item on the right side is a constraint item having a value according to the presence or absence of violation of the constraint item. k represents the identification number of the constraint item, and A represents the identification number set of the constraint item. In addition, γ k represents the proportionality coefficient associated with the constraint with identification number = k. k represents the weight of the constraint item with identification number = k. For each constraint item, we can k Assign different values. g(h k ) represents a function of the type of constraint. In the following, g(h k ) is sometimes also called a penalty function. k h represents a local field (LF) for specifying a constraint violation amount, which is a value added to the evaluation function when the constraint condition with identification number = k is not satisfied. The following formula (2) represents h k Note that in the following, h k It will also sometimes be referred to as the second local field to be used in conjunction with the first local field (sometimes also represented as h) for specifying the amount of change in the value of the evaluation function associated with the change in the value of each of the plurality of state variables. i ) to be distinguished.

[0043] [Mathematical formula 2]

[0044]

[0045] In formula (2), W ki Indicates x i The coefficient (weighting factor) of the weight relative to the constraint with identification number k. b k represents the coefficient associated with the constraint with identification number = k.

[0046] Figure 1 is a diagram showing an example of a relationship between a state variable and a second local field.

[0047] exist Figure 1 In the figure, arrows indicate multiple state variables ( Figure 1 In the example of x1, x i and x N ) and each of the plurality of state variables and the plurality of second local fields ( Figure 1 In the example of h p 、h k and h r ). The magnitude of these correlations corresponds to W ij or W ki .

[0048] In the case where the constraint with identification number = k is an inequality constraint, g(h k ) can be expressed by the following formula (3).

[0049] [Mathematical formula 3]

[0050] g(h k )=max[0,h k ] (3)

[0051] In formula (3), max[0, h k ] is the output 0 and h k In the case where the constraints are inequality constraints, h k It can be expressed by the following formula (4).

[0052] [Mathematical formula 4]

[0053]

[0054] R k represents the consumption (also called resource quantity) of the constraint item with identification number k, and U k The first term on the right side of the above formula (2) corresponds to R in formula (4). k , and +b in formula (2) k Corresponding to -U in formula (4) k . R k with U k The difference between is the constraint violation amount.

[0055] Note that another function (such as a step function, for example) may also be used as g(h k ).

[0056] In the following, the Ising-type evaluation function in the first and second terms on the right side of formula (1) is sometimes also expressed as E(x). In addition, the constraint term in the third term on the right side of formula (1) is sometimes also expressed as P(x). Using E(x) and P(x), the evaluation function of the combinatorial optimization problem with constraints can be expressed as H(x)=E(x)+P(x).

[0057] Note that the penalty function can be expressed by the following formula (5) for a certain state variable (x i The change in the value of the evaluation function when the value of ) changes (ΔH i ).

[0058] [Mathematical formula 5]

[0059]

[0060] In formula (5), g(h k +W ki Δx i )-g(h k ) means that in a certain state variable (x i ) changes (which can also be called the change in the constraint term).

[0061] Figure 2 : is a diagram showing an example of the amount of change in the value of the penalty function due to a change in the value of the state variable. k ), and the horizontal axis represents h k .

[0062] exist Figure 2 In, g(h k )=max[0,h k ] is used as an example of a penalty function. When h k With x i The change in the value of h k +W ki Δx i When , the change in the value of the penalty function is expressed as g(h k +W ki Δx i )-g(h k ).

[0063] As the first local field for specifying the amount of change in the value of the evaluation function represented by the formula (5), a variable (h) represented by the following formula (6) can be used. i ).

[0064] [Mathematical formula 6]

[0065]

[0066] In formula (6), Δg(h k , W ki Δx i ) is expressed by the following formula (7).

[0067] [Mathematical formula 7]

[0068] Δg(h k , W ki Δx i )=Δx i [g(h k +W ki Δx i )-g(h k )] (7)

[0069] As shown in formula (7), Δg(h k , W ki Δx i ) can be based on x i 、h k and W ki The amount calculated.

[0070] By using h as in formula (6) i , ΔH i It can be expressed as ΔH i =-h i Δx i .

[0071] The data processing apparatus according to each of the embodiments described below uses the first local field (h i ) is used to perform multi-bit conversion processing to search for solutions to combinatorial optimization problems with constraints. Note that in the following description, it is assumed that the number of state variables included in the evaluation function shown in formula (1) is N, and the number of constraints is assumed to be M.

[0072] (First Embodiment)

[0073] Figure 3 is a diagram showing an example of a data processing device according to the first embodiment.

[0074] The data processing device 10 includes a weighting factor memory 11, a memory 12, a conversion candidate designation circuit 13, an update circuit 14, a cumulative value calculation circuit 15, a determination circuit 16, a control circuit 17, an evaluation function value update and holding circuit 18, a comparison circuit 19 and a minimum value update and holding circuit 20.

[0075] The weighting factor memory 11 stores the weighting factor information about h. i The calculation formula of formula (6) includes Wij N×N instances and W ki M×N instances of . Note that since W ki =W ik , so the weighting factor memory 11 does not need to store W ik In addition, the weighting factor memory 11 does not need to store W whose value is zero. ki For example, the weighting factor memory 11 may be formed of a volatile storage device as an electronic circuit such as a dynamic random access memory (DRAM), a nonvolatile storage device as an electronic circuit such as a flash memory, etc. The weighting factor memory 11 may be a storage device such as a hard disk drive (HDD).

[0076] Note that the weighting factor memory 11 may store the bias coefficients (b i ), proportionality coefficient (γ k ), coefficients related to constraints (b k ), other calculation condition data, and W ij and W ki .

[0077] The memory 12 stores N state variables (x1 to x2) included in the evaluation function. N ) (hereinafter, sometimes also referred to as state) and the first local field (h1 to h2) of each of the N state parameters. N ). In addition, the memory 12 stores the values ​​of the N state variables at the first time point of the solution search and the values ​​of the N first local fields at the first time point. In addition, the memory 12 stores the M second local fields (h k ) and the values ​​of the M second local fields at the first time point.

[0078] Here, the first time point is, for example, a time point when the multi-bit conversion process is started (hereinafter, referred to as a starting point). Figure 3 In the example, the values ​​of the N state variables at the starting point are represented as the starting point state, and the values ​​of the N first local fields at the starting point are represented as the starting point first local fields. In addition, the values ​​of the M second local fields at the starting point are represented as the starting point second local fields.

[0079] A memory having a smaller storage capacity than that of the weighting factor memory 11 may be used as the memory 12. For example, the memory 12 may be formed of a volatile storage device as an electronic circuit such as a static random access memory (SRAM) or a register, etc. However, the memory 12 is not limited to these storage devices.

[0080] The conversion candidate specifying circuit 13 calculates the amount of change in the value of the evaluation function associated with the change in the value of each of the N state variables using the values ​​of the N first local fields. i The change in the value of i ) can be expressed as ΔH i =-h i Δx i Therefore, the conversion candidate specifying circuit 13 can be realized by setting h i Multiply by -Δx i To calculate ΔH i The conversion candidate specifying circuit 13 can calculate ΔH in parallel. i In addition, the conversion candidate specifying circuit 13 is based on ΔH i N instances of , starting from the starting point, specify x1 to x one by one N Among them, the candidates whose values ​​are to be changed (hereinafter, referred to as conversion candidates).

[0081] In the following example, a description will be given based on the assumption that the data processing device 10 performs multi-bit conversion processing of n (an integer equal to or greater than two) bits. n may also be referred to as a conversion bit depth. The conversion candidate specifying circuit 13 specifies n of the above conversion candidates one by one.

[0082] The conversion candidate specifying circuit 13 outputs the identification number of the state variable specified as the conversion candidate and the amount of change in the value of the evaluation function when the value of the conversion candidate is changed. An example of a method for specifying a conversion candidate and an example of the conversion candidate specifying circuit 13 will be described later (see Figure 5 ).

[0083] Each time a conversion candidate is specified, the update circuit 14 updates the value of the conversion candidate stored in the memory 12 and also updates the values ​​of the N first partial fields and the values ​​of the M second partial fields. In the following example, it is assumed that the update circuit 14 performs such an update until n conversion candidates are specified.

[0084] For example, in x j When it is designated as a candidate for conversion, the update circuit 14 sets Δh i =W ij Δx j Add to h i Each of the N instances updates h i . Note that when i=j, W ii = 0 and h i If there is no change, no update is involved.

[0085] In addition, when x jWhen it is designated as a candidate for conversion, the update circuit 14 sets Δh k =W kj Δx j Add to h k Each of the M instances of h is updated k . Note that with W kj = 0 h k Does not change, and therefore does not involve updating.

[0086] Figure 4 It is shown in x j Figure 2 is an example of updating a first local field and a second local field when the value of is changed. Figure 4 In the example, h1 to h N indicates N first partial fields, and h N+1 to h N+M Indicates M second partial fields. Such calculation can be performed by parallel calculation with a parallel degree of N+M.

[0087] In addition, at the second time point, the update circuit 14 further updates the value of the first partial field using the value of the second partial field at the first time point and the value at the second time point. The second time point may be the time when the second partial field is updated. That is, each time a conversion candidate is specified, the values ​​of the N first partial fields may be updated using the updated second partial field. Alternatively, the second time point may be a time point when the conversion candidate is specified multiple times. For example, the second time point may be a time point when the conversion candidate is specified n-1 times.

[0088] Use h at the second time point k For h i The update of can be expressed by, for example, the following formula (8).

[0089] [Mathematical formula 8]

[0090]

[0091] In formula (8), h k (old) represents the second partial field at the first time point stored in the memory 12. Note that in the case of i=j, h i does not change, and therefore does not involve updating. In the following, -γ in formula (8) k [Δg(h k , W ki Δx i )-Δg(h k (old) , W ki Δx i )] is sometimes also expressed as δhi .

[0092] Note that in the update process described above, the state at the first time point (starting point state), the value of the first partial field (starting point first partial field), and the value of the second partial field (starting point second partial field) are not updated. The update here is a temporary update, and the updated state and the values ​​of the first partial field and the second partial field will be restored to the starting point state and the values ​​of the starting point first partial field and the starting point second partial field by the process described later in some cases. The update circuit 14 performs the above update process under the control of the control circuit 17.

[0093] The cumulative value calculation circuit 15 calculates the cumulative value of the amount of change in the value of the evaluation function when the value of the conversion candidate is changed. For example, the cumulative value calculation circuit 15 can be formed using an adder, a register, or the like.

[0094] The determination circuit 16 determines whether to accept the change in the value of the n conversion candidates based on the cumulative value of the change amount of the value of the evaluation function by MCMC processing. For example, when the cumulative value of the change amount is expressed as ΔE i When ΔE is caused by i The acceptance probability A of a change in the value of the state variable i It can be expressed by formula (9).

[0095] [Mathematical formula 9]

[0096]

[0097] β represents the inverse (β=1 / t) of the parameter T (T>0) indicating temperature, and is called the inverse temperature. In the following, β and T are sometimes also called temperature values. The min operator indicates the minimum value of the selected parameter. The upper right side of formula (9) corresponds to the Metropolis method. The lower right side of formula (9) corresponds to the Gibbs method.

[0098] The determination circuit 16 makes a determination so that, for example, the acceptance probability A in formula (9) i The determination circuit 16 that makes such a determination may be formed using a comparator or the like that determines the value of the n conversion candidates based on, for example, a uniform random number having a value from 0 to 1 and A i Output the value based on the comparison result between them.

[0099] In the case where the determination circuit 16 determines that the change in the value of the n conversion candidates is accepted, the control circuit 17 causes the update circuit 14 to update the values ​​of the N state variables and the values ​​of the first local field and the second local field stored in the memory 12 to the values ​​in the case where the value of the n-th conversion candidate is changed. In addition, in the case where the determination circuit 16 determines that the change in the value of the n conversion candidates is not accepted, the control circuit 17 restores each of the updated values ​​of the N state variables and the values ​​of the first local field and the second local field to the value at the first time point.

[0100] In addition, the control circuit 17 has Figure 1 The operation of each element shown performs a control function.

[0101] For example, the control circuit 17 controls so that the updating circuit 14 reads the weighting factor memory 11 corresponding to the identification number output by the conversion candidate specifying circuit 13. ij or W ki . In addition, the control circuit 17 controls the temperature value (T or β) used in the determination processing by the determination circuit 16. For example, in the case where the simulated annealing method is used as the MCMC method, the control circuit 17 gradually reduces the value of T according to a predetermined plan. In the case where the replica exchange method is used as the MCMC method, the control circuit 17 performs control so that the processing of each of the above-mentioned circuits is performed independently of each other for multiple replicas of the Ising model. The control circuit 17 sets a different temperature value in each of the multiple replicas, and exchanges the temperature values ​​between the replicas at a predetermined exchange probability in a predetermined cycle.

[0102] Furthermore, the control circuit 17 may switch whether to cause the conversion candidate designation circuit 13 to perform the single-bit conversion process or the multi-bit conversion process based on the determination result output by the determination circuit 16. For example, when the determination result indicating that a change in value is not accepted continues for a predetermined period of time at the time of solution search in the single-bit conversion process, the control circuit 17 switches the single-bit conversion process to the multi-bit conversion process.

[0103] In the single-bit conversion process, the conversion candidate designation circuit 13 performs a process of determining whether to allow a value change for each of the N state variables based on the amount of change in the value of the evaluation function. Similar to the determination circuit 16, the determination at this time is performed according to the MCMC method. In the multi-bit conversion process, the conversion candidate designation circuit 13 performs a process of designating conversion candidates one by one from the starting point.

[0104] When a determination result indicating that a change in value is not accepted continues for a predetermined period of time at the time of searching for a solution by the multi-bit conversion process, the control circuit 17 may increase the value of n in the multi-bit conversion process. In the case where a determination result indicating that a change in value is accepted is obtained at the time of searching for a solution by the multi-bit conversion process, or in the case where such a determination result continues for a predetermined period of time, the control circuit 17 may switch the multi-bit conversion process to the single-bit conversion process.

[0105] Furthermore, in the case where the determination circuit 16 determines that the change in the values ​​of the n conversion candidates is not accepted, the control circuit 17 may control the conversion candidate specifying circuit 13 so that the same n conversion candidates are not selected again.

[0106] The evaluation function value update holding circuit 18 includes, for example, a holding circuit such as a register, and holds the value of the evaluation function. In the case where the determination circuit 16 determines to accept the change in the value of the n conversion candidates, the evaluation function value update holding circuit 18 acquires the cumulative value of the change amount of the value of the evaluation function calculated by the cumulative value calculation circuit 15, updates the value of the evaluation function using the acquired cumulative value, and outputs the updated value.

[0107] The comparison circuit 19 compares the value of the evaluation function held in the evaluation function value update-hold circuit 18 with the minimum value of the evaluation function held in the minimum value update-hold circuit 20 .

[0108] The minimum value update hold circuit 20 includes, for example, a holding circuit such as a register, and holds the minimum value of the evaluation function obtained until then. In the case where the comparison circuit 19 outputs a comparison result indicating that the value of the evaluation function held in the evaluation function value update hold circuit 18 is less than the minimum value obtained until then, the minimum value update hold circuit 20 updates the minimum value using the value of the evaluation function. In addition, when the minimum value is obtained, the minimum value update hold circuit 20 holds the values ​​of the N state variables. For example, the values ​​of the N state variables held when a predetermined end condition is satisfied are then output as a solution to the combinatorial optimization problem.

[0109] Figure 5 is a diagram showing a circuit example of a memory, an update circuit, and a conversion candidate specifying circuit. Note that Figure 5 It is also shown that the weighting factor (W ij , W ki and W ik ) is an example stored in the weighting factor memory 11.

[0110] The memory 12 includes a status storage area 12a, a starting point status storage area 12b, a first local field storage area 12c, a starting point first local field storage area 12d, a second local field storage area 12e, a starting point second local field storage area 12f and access control circuits 12g and 12h.

[0111] The values ​​of the N state variables are stored in the state storage area 12a, and the values ​​of the N state variables at the first time point of the solution search (hereinafter, assumed to be the above-mentioned starting point) are stored in the starting point state storage area 12b. The values ​​of the N first local fields are stored in the first local field storage area 12c, and the values ​​of the N first local fields at the starting point are stored in the starting point first local field storage area 12d. The values ​​of the M second local fields are stored in the second local field storage area 12e, and the values ​​of the M second local fields at the starting point are stored in the starting point second local field storage area 12f.

[0112] The access control circuit 12g is Figure 3 The control circuit 17 shown controls the reading and writing of states between the state storage area 12a, the starting point state storage area 12b and the state update holding circuit 14a of the update circuit 14. For example, under the control of the control circuit 17, the following operations are performed.

[0113] In the case where the state variable is updated, the access control circuit 12g overwrites the value of the state variable stored in the state storage area 12a with the value of the updated state variable.

[0114] exist Figure 3 In the case where the determination circuit 16 shown determines to accept the change of the values ​​of the n conversion candidates, the access control circuit 12g rewrites the starting point state in the starting point state storage area 12b with the values ​​of the N state variables in the state storage area 12a. Note that the values ​​of the N state variables in the state storage area 12a are values ​​obtained by updating n values ​​among the values ​​of the N state variables at the starting point.

[0115] In the case where the determination circuit 16 determines that the change of the values ​​of the n conversion candidates is not accepted, the access control circuit 12g overwrites the values ​​of the N state variables in the state storage area 12a with the values ​​of the N state variables at the starting point in the starting point state storage area 12b.

[0116] The access control circuit 12h controls the first local field storage area 12c, the starting point first local field storage area 12d and the update circuit 14h under the control of the control circuit 17. i In addition, the access control circuit 12h controls the reading and writing of the first local field storage area 12e, the starting point second local field storage area 12f and the update circuit 14h under the control of the control circuit 17. k The reading and writing of the second partial field between the holding circuits 14g are performed. For example, under the control of the control circuit 17, the operation described below is performed.

[0117] When the process of the conversion candidate specifying circuit 13 is executed, the access control circuit 12h writes the values ​​of the N first partial fields in the first partial field storage area 12c into the h i Holding circuit 14f.

[0118] In a case where the value of the first partial field is updated, the access control circuit 12h overwrites the value of the partial field in the first partial field storage area 12c with the updated value of the first partial field.

[0119] When the determination circuit 16 determines to accept the change of the values ​​of the n conversion candidates, the access control circuit 12h overwrites the values ​​of the N first local fields at the starting point in the starting point first local field storage area 12d with the values ​​of the N first local fields in the first local field storage area 12c.

[0120] When the determination circuit 16 determines that the change of the values ​​of the n conversion candidates is not accepted, the access control circuit 12h overwrites the values ​​of the N first local fields in the first local field storage area 12c with the values ​​of the N first local fields at the starting point in the starting point first local field storage area 12d.

[0121] In the case where the processing of the conversion candidate specifying circuit 13 is executed, the access control circuit 12h writes the values ​​of the M auxiliary variables in the second local field storage area 12e into the h k Holding circuit 14g.

[0122] In a case where the value of the second partial field is updated, the access control circuit 12h overwrites the value of the second partial field in the second partial field storage area 12e with the updated value of the second partial field.

[0123] When the determination circuit 16 determines to accept the change of the values ​​of the n conversion candidates, the access control circuit 12h overwrites the values ​​of the M second local fields at the starting point in the second local field storage area 12f using the values ​​of the M second local fields in the second local field storage area 12e.

[0124] When the determination circuit 16 determines that the change of the values ​​of the n conversion candidates is not accepted, the access control circuit 12h overwrites the values ​​of the M second local fields in the second local field storage area 12e with the values ​​of the M second local fields at the starting point in the starting point second local field storage area 12f.

[0125] For example, at the second time point when the first partial field is updated using the value of the second partial field, the access control circuit 12h writes the values ​​of the M second partial fields in the starting point second partial field storage area 12f into the first partial field.k Holding circuit 14g.

[0126] The conversion candidate specifying circuit 13 includes a ΔH calculating circuit 13 a , a ΔH holding circuit 13 b , a flip-flop (FF) 13 c , an acceptance determining circuit 13 d , and a selecting circuit 13 e .

[0127] The ΔH calculation circuit 13a calculates the amount of change in the value of the evaluation function associated with the change in the value of each of the N state variables using the values ​​of the N first local fields. i The change in the value of i ) can be expressed as ΔH i =-h i Δx i . Δx i The state storage area 12a can be used to store the data x1 to x2. N The value of is obtained.

[0128] Note that the ΔH calculation circuit 13a may not calculate the ΔH of the state variable that has become the conversion candidate when n conversion candidates are specified. i This is to prevent a state variable that was once a transition candidate from becoming a transition candidate again, and to prevent the value of the state variable from returning to its original state.

[0129] The ΔH holding circuit 13b holds the ΔH calculated by the ΔH calculation circuit 13a. i N instances of .

[0130] FF 13c hold h k The value of and delay output h k The timing of h k (old) The h supplied to the update circuit 14 k Contribution amount calculation circuit 14e.

[0131] The acceptance determination circuit 13d accepts the change in the value of at least one state variable. For example, the acceptance determination circuit 13d outputs a change that causes ΔH i The identification number of the state variable and the ΔH i , in ΔH i When the value is changed, the value of the evaluation function becomes the lowest. For example, the acceptance determination circuit 13d may output a value that makes ΔH i The identification numbers of the multiple state variables that are less than the predetermined threshold and ΔH i The acceptance determination circuit 13d may accept a change in the value of one or more state variables according to a predetermined rule.

[0132] Note that in the case of performing a single-bit conversion process, the acceptance determination circuit 13d accepts a change in the value of each state variable with the acceptance probability indicated by formula (9).

[0133] In the case where the acceptance determination circuit 13d accepts the change in the values ​​of the plurality of state variables, the selection circuit 13e selects one of the plurality of state variables whose value change is accepted, and outputs the identification number of the selected state variable and ΔH associated with the change in the value of the selected state variable. i For example, the selection circuit 13e may select a state variable at random, or may select a state variable according to a predetermined rule.

[0134] The identification number of the state variable selected by the selection circuit 13e is supplied to Figure 3 The control circuit 17 shown, and the ΔH associated with the change in the value of the selected state variable i is supplied to the cumulative value calculation circuit 15 .

[0135] The updating circuit 14 includes a state updating and holding circuit 14a, a k Holding circuit 14b, h i h k Update circuit 14c,h k Update detection circuit 14d,h k Contribution calculation circuit 14e,h i Holding circuit 14f and h k Holding circuit 14g.

[0136] The state update holding circuit 14a holds the values ​​of the N state variables. In addition, the state update holding circuit 14a updates the value of the state variable selected by the selection circuit 13e under the control of the control circuit 17.

[0137] x k Holding circuit 14b holds x k M values ​​of . For example, x k It can be used to check whether the constraint with identification number = k is satisfied. In the case of inequality constraints, such as Figure 2 As shown in h k >0 satisfies g(h k )>0, and a constraint violation occurs. So, for example, x k The holding circuit 14b can be k >0 when x is kept k =1, and can satisfy h k Keep x when ≤0 k = 0. However, the data processing device 10 of this embodiment does not necessarily use x k In this case, x is not involvedk Holding circuit 14b.

[0138] Under the control of the control circuit 17, h i h k The updating circuit 14c updates the first local field (h i ) and the second local field (h k ). For example, in x j If h is a candidate for conversion, i Updated to h i =h i +W ij Δx j In addition, at x j When h is designated as a conversion candidate, i h k The updating circuit 14c will k Updated to h k =h k +W kj Δx j The value of .

[0139] h k The update detection circuit 14d detects h k Updates. kj = 0, no h is detected for the constraint with identification number = k k Updates.

[0140] h k The contribution calculation circuit 14e reads a non-zero W from the weighting factor memory 11. ki , in order to calculate the h detected due to its update k The change in the value of h i The change in (δh i ). In addition, h k The contribution amount calculation circuit 14e uses h k The holding circuit 14g obtains h k , and get h from FF 13c k (old) Then, h k The contribution calculation circuit 14e calculates δh i , and by changing δh i Add to original h i To update h i .

[0141] Based on h k Update the value of h iIn the case where the second time point of the value of is the time point when n-1 conversion candidates are specified, the value of the second partial field at the start point is used as h k (old) .

[0142] h i The holding circuit 14f holds the values ​​of the N first partial fields.

[0143] h k The holding circuit 14g holds the values ​​of the M second partial fields.

[0144] Each of the circuits in the data processing device 10 described above may be formed using, for example, an electronic circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). In addition, at least a portion of each circuit in the data processing device 10 may also be formed by software processing by a processor that executes a program. Examples of the processor include a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and the like.

[0145] Next, the flow of the data processing method (solution search) performed by the data processing device 10 as described above will be described with reference to a flowchart.

[0146] Figure 6 is a flowchart showing the flow of an example of a data processing method according to the first embodiment.

[0147] First, initialization is performed under the control of the control unit 17 (step S10). In the process of step S10, the initial values ​​of N state variables, the initial value of the evaluation function, the initial values ​​of N first local fields, and the initial values ​​of M second local fields are set, and the end condition of the solution search is set, etc. In addition, in the case of performing the simulated annealing method, for example, the start value and the end value of the temperature value, the value by which the temperature value is multiplied for each predetermined temperature change cycle, etc. are set. In the case of performing the replica exchange method, the temperature value is set in each replica, the replica exchange cycle, etc. are set.

[0148] The control circuit 17 determines whether to start the multi-bit conversion process (step S11). For example, the control circuit 17 starts the single-bit conversion process at the time of starting the solution search, and starts the multi-bit conversion process if the determination result indicating that the change of value is not accepted continues for a predetermined period.

[0149] In the case where the control circuit 17 determines not to start the multi-bit conversion process, the process in step S12 is performed. In the process in step S12, the single-bit conversion process is performed. The flow of the single-bit conversion process will be described later (see Figure 7 ). After the processing in step S12, the processing in step S18 is performed.

[0150] When the control circuit 17 determines to start the multi-bit conversion process, the process in step S13 is executed. In the process in step S13, various multi-bit conversion parameters used when performing the multi-bit conversion process are set. The various multi-bit conversion parameters include n as the above-mentioned conversion bit depth, and the number of repetitions L of the repeated trials as the number of times of the multi-bit conversion process. The user can input n and L to the data processing device 10, or n and L can be preset in a holding circuit such as a register in the data processing device 10. In addition, the control circuit 17 sets the flag variable Mflip_flag to 0, and the flag variable Mflip_flag has 1 when allowing the values of multiple conversion candidates to change.

[0151] After the process in step S13, for k = 1 to k < L, the process of the multi-bit conversion trial loop (steps S14 to S17) is repeated.

[0152] In the multi-bit conversion trial loop, the multi-bit conversion process is executed (step S15). The flow of the multi-bit conversion process will be described later (see Figure 8 ).

[0153] After the process in step S15, the control circuit 17 determines whether Mflip_flag has 0 (step S16). When the control circuit 17 determines that Mflip_flag has 0, the control circuit 17 repeats the process starting from step S15 by incrementing k by 1 when k < L.

[0154] When the control circuit 17 determines that Mflip_flag does not have 0 or when k reaches L, the control circuit 17 executes the process in step S18.

[0155] In the process in step S18, the control circuit 17 determines whether to end the solution search. For example, when a predetermined end condition is satisfied, the control circuit 17 determines to end the solution search, outputs the solution of the combinatorial optimization problem as the result of the solution search (step S19), and ends the process. For example, in the process in step S19, when it is determined to end the solution search, the values of the N state variables held in the minimum value update holding circuit 20 are output as the solution of the combinatorial optimization problem. The control circuit 17 can cause a display device (not shown) to display the solution, or can cause a communication circuit (not shown) to send the solution to an external device.

[0156] When the control circuit 17 determines not to end the solution search, the control circuit 17 repeats the process starting from step S11.

[0157] Figure 7 is a flowchart showing an example of the process of the single-bit conversion process.

[0158] The conversion candidate specifying circuit 13 calculates ΔH with respect to each of the N state variables using the current values ​​of the N first local fields. i (Step S20).

[0159] Then, the conversion candidate specifying circuit 13 performs acceptance determination (step S21). For example, the conversion candidate specifying circuit 13 determines the conversion candidate based on ΔH with respect to each of the N state variables. i and the temperature value supplied from the control circuit 17, accepts the change in the value of each state variable with the acceptance probability indicated by the formula (9).

[0160] In the case of accepting changes in the values ​​of a plurality of state variables, the conversion candidate specifying circuit 13 selects one state variable to be updated (step S22).

[0161] After that, the conversion candidate specifying circuit 13 determines whether updating is permitted (step S23). For example, in the case where a change in value is not accepted for any state variable in the processing in step S21, it is determined that updating is not permitted.

[0162] When the conversion candidate specifying circuit 13 determines that updating is permitted, the updating circuit 14 performs an updating process (step S24). In the updating process, the value of the state variable permitted to be updated changes. Then, based on the change, the values ​​of the first partial field and the second partial field are updated.

[0163] At this time, the evaluation function value update holding circuit 18 updates the value of the state variable allowed to be updated based on ΔH associated with the change in the value of the state variable. i When the updated evaluation function value is less than the minimum value of the evaluation function held in the minimum value update hold circuit 20, the minimum value is updated and held in the minimum value update hold circuit 20 together with the current values ​​of the N state variables.

[0164] In the case where it is determined that updating is not permitted in the process in step S23, or after the process in step S24, the process of the data processing device 10 returns to Figure 6 The processing in step S18 is shown.

[0165] Figure 8 : is a flowchart showing the flow of an example of a multi-bit conversion process of the data processing method according to the first embodiment.

[0166] The memory 12 stores the state at the starting point and h i and h k value (step S30).

[0167] Thereafter, for i = 0 to i < n, the processing of the n-bit conversion trial loop described below is repeated (Steps S31 to S48).

[0168] In the n-bit conversion trial loop, the conversion candidate designating circuit 13 selects its ΔH i object to be calculated (Step S32). When designating n conversion candidates, state variables that have once been conversion candidates are excluded from the objects whose ΔH i is to be calculated. The conversion candidate designating circuit 13 uses h stored in the memory 12 i to calculate the ΔH of the object selected as the object to be calculated i (Step S33).

[0169] Then, the conversion candidate designating circuit 13 performs acceptance determination (Step S34). The conversion candidate designating circuit 13 accepts a change in the value of at least one state variable.

[0170] In the case of accepting changes in the values of a plurality of state variables, the conversion candidate designating circuit 13 selects one of the plurality of state variables and designates the selected state variable as a conversion candidate. Further, the update circuit 14 updates the state by changing the value of the designated conversion candidate (Step S35). The state update here is a temporary update.

[0171] After the processing in Step S35, the cumulative value calculation circuit 15 calculates the cumulative value of ΔH i when the value of the conversion candidate is changed (Step S36).

[0172] After the processing in Step S36, the control circuit 17 determines whether i is n - 1 (Step S37). That is, it is determined whether n conversion candidates are designated. When the control circuit 17 determines that i is n - 1, the processing in Step S38 is executed. When the control circuit 17 determines that i is not n - 1, the processing in Step S45 is executed.

[0173] In the processing in Step S38, the determination circuit 16 determines whether to accept a change in the values of the n conversion candidates based on the cumulative value of ΔH i according to the MCMC method.

[0174] The control circuit 17 determines whether the determination circuit 16 accepts a change in the values of the n conversion candidates (Step S39). When the control circuit 17 determines that the determination circuit 16 accepts a change in the values of the n conversion candidates, the control circuit 17 executes the processing in Step S40. When the control circuit 17 determines that the determination circuit 16 does not accept a change in the values of the n conversion candidates, the control circuit 17 executes the processing in Step S43.

[0175] In the process in step S40, the control circuit 17 assigns the value of Mflip_flag to 1. Thereafter, the update circuit 14 updates h in association with the change in the value of the nth conversion candidate. i The value of h (step S41) and update h k (Step S42).

[0176] In the process in step S43, the control circuit 17 assigns the value of Mflip_flag to 0. Thereafter, the control circuit 17 sets the state and h i and h k The value of is restored to the state and value at the stored starting point (step S44).

[0177] After the processing in steps S42 and S44, i is incremented by 1 to i=n, ​​and therefore, the processing of the data processing device 10 exits from the n-bit conversion test loop and returns to Figure 6 The processing in step S18 is shown.

[0178] The updating circuit 14 updates h in association with the change in the value of the conversion candidate specified at this time. i The value of h (step S45) and update h k Then, the updating circuit 14 uses h k and h k (old) Further update i value (step S47).

[0179] Afterwards, i is incremented by 1, and the n-bit conversion test cycle is repeated.

[0180] Fig. 9 : is a flowchart showing the flow of another example of the multi-bit conversion process of the data processing method according to the first embodiment.

[0181] The processing in steps S50 to S66 is the same as Figure 8 The processes in steps S30 to S46 shown are the same.

[0182] After the processing in step S66, the control circuit 17 determines whether i has n-2 (step S67). That is, it is determined whether n-1 conversion candidates are specified. In the case where the control circuit 17 determines that i has n-2, the processing in step S68 is performed. In the case where the control circuit 17 determines that i does not have n-2, i is increased by 1, and the n-bit conversion test loop (steps S51 to S69) is repeated.

[0183] In the process of step S68, the updating circuit 14 uses h k and h as the starting point k h k(old) To update h i Thereafter, i is increased by 1, and the n-bit conversion test loop (steps S51 to S69) is repeated.

[0184] Note that Figure 8 and Fig. 9 In the example of FIG. 1 , the ΔH for all n conversion candidates has been described. i The example of performing acceptance determination based on the accumulated value of , but this example is not restrictive. For example, it is possible to perform acceptance determination based on the accumulated value of ΔH calculated each time a conversion candidate is specified. i The acceptance determination is performed based on the accumulated value of

[0185] also, Figures 6 to 9 The order of processing shown is an example, and the order of processing may be changed as appropriate.

[0186] (Example of pipeline processing)

[0187] The above processing can be performed in parallel for multiple copies using pipeline processing. The memory 12 stores the values ​​of the N state variables, the values ​​of the N first local fields, and the values ​​of the M second local fields in an amount equal to the number of multiple copies. In addition, the memory 12 can also store the values ​​of the N state variables, the values ​​of the N first local fields, and the values ​​of the M second local fields at the starting point in an amount equal to the number of multiple copies, or can store values ​​common to all copies. The W stored in the weighting factor memory 11 ij , W ki and W ik Common to all copies.

[0188] The control circuit 17 causes the conversion candidate specifying circuit 13, the updating circuit 14, the cumulative value calculating circuit 15, and the determining circuit 16 to perform pipeline processing on a plurality of replicas. Note that the control circuit 17 may control so that single-bit conversion processing is performed on some replicas.

[0189] Fig.10 and Fig.11 1 is a diagram showing a first example of pipeline processing of the data processing method according to the first embodiment. Note that Fig.10 and Fig.11 shows the execution through pipeline processing Figure 8 An example of a multi-bit conversion process is shown.

[0190] exist Fig.10 In the expression 0 to R-1, the replica numbers of the R replicas are indicated. Fig.10In the example in , a test by multi-bit conversion with a conversion bit depth n of three bits is started at the same timing in all copies. Note that since the control circuit 17 can control each copy as an independent process, the start timing of the test and the value of n may be different in a plurality of copies. In addition, in the pipeline process, a first-in-first-out (FIFO) is used to adjust the operation timing.

[0191] The processing performed by each replica is divided into an update phase and a trial phase. The update phase consists of reading W ij and W kj , calculate W ij Δx j (=Δh i )、W kj Δ xj (=Δh k ) and δh i , and h i and h k The test phase includes reading h from the memory 12 i , read h from memory 12 k or k (old) , the state at the starting point and h i and h k Stored in memory 12, calculate ΔH i , calculate ΔH i 's cumulative value, and acceptance determination is made based on the cumulative value.

[0192] The trial phase for specifying the first conversion candidate starts at timing t1. Sequentially for each copy, h is read from the memory 12. i and keep it at h i Holding circuit 14f.

[0193] Starting from time t2, for each replica, the state at the starting point and h i and h k is stored in the memory 12. In addition, starting from the timing t2, ΔH is calculated for each replica sequentially. i .

[0194] Starting from timing t3, ΔH is calculated for each replica sequentially. i The cumulative value of Fig.10 In the example in FIG. 1 , the conversion based on ΔH is not performed until the third conversion candidate is specified. i Note that although not shown, starting from timing t3, the acceptance determination based on ΔH is performed sequentially for each replica. i The acceptance determination and the designation of the conversion candidate. Fig.10, the processing in the period (timing t3 to t9) in which the first conversion candidate is specified for the R copies is represented as the first bit conversion processing.

[0195] When the first conversion candidate is specified for each copy sequentially starting from timing t3, the identification number of the conversion candidate state variable is supplied to the control circuit 17 via the FIFO. Thereafter, the update phase of the first conversion candidate is started (timing t4).

[0196] Starting from timing t4, the control circuit 17 reads the W corresponding to the identification number of the conversion candidate from the weighting factor memory 11 for each copy sequentially. ij and W kj Then, starting from timing t5, W is calculated for each replica sequentially. ij Δx j (=Δh i ) and W kj Δx j (=Δh k ). In addition, starting from timing t6, h is executed sequentially for each replica. i and h k Update processing.

[0197] Starting from timing t7, the trial phase for specifying the second conversion candidate begins. For each copy, h is read from the memory 12 sequentially. i and keep it at h i Holding circuit 14f.

[0198] Starting from timing t8, ΔH is calculated for each replica sequentially. i In addition, starting from timing t9, ΔH is calculated sequentially for each replica. i The cumulative value of Fig.10 , the processing in the period (timing t9 to t13) in which the second conversion candidates are specified for the R copies is represented as the second bit conversion processing.

[0199] Starting from the timing t10 ​​, the update phase associated with the designation of the second conversion candidate is started, and processing similar to that at the timings t4 to t6 is performed.

[0200] Starting from timing t11, the update process of the first partial field using the second partial field is performed. Starting from timing t11, h is read from the memory 12 for each copy sequentially. k and h k (old) and keep it in h k Starting from timing t12, h is read from memory 12 for each copy in sequence. k and hk (old) Another one in h k In the holding circuit 14g. Fig.10 In the example in , for the replica with replica number=1, since the values ​​of the two second local fields change, the read is performed in two cycles (a1 and a2). Fig.10 , the processing in the period (timing t13 to t18) of reading the value of the second partial field for the R copies is represented as the second partial field processing.

[0201] Starting from timing t14, the update phase of the first partial field using the second partial field is performed. Starting from timing t14, the weight factor memory 11 reads the h value changed from the value at the starting point sequentially for each copy. k The identification number of k = W corresponding to k ki Then, starting from timing t15, δh is calculated for each replica sequentially. i In addition, starting from timing t16, for each replica, use δh i To execute h i Update processing.

[0202] From timing t17, a trial phase for specifying a third conversion candidate is started, and processing similar to that at timings t8 and t9 is performed. Fig.11 , the processing in the period (timing t18 to t23) in which the third conversion candidate is specified for the R copies is represented as the third bit conversion processing.

[0203] Starting from timing t19, the execution is based on ΔH i The acceptance of the cumulative value is determined by Fig.11 In the figure, a white circle indicates a definite acceptance, and a black square indicates a rejection.

[0204] exist Fig.11 In the example in FIG. 1 , the replica with replica number = 0 and R-1 is determined to be acceptable, and acceptance is rejected for the other replicas. Therefore, the update phase is performed for the replica with replica number = 0 and R-1 (timing t20 to t26). The update phase is not performed for the other replicas, and the state at the starting point and h i and h k is read and written into the memory 12 as the current state and h i and h k .

[0205] Starting from timing t21, the update processing of the first partial field using the second partial field is performed. For the replicas with replica numbers = 0 and R-1, at the processing timing of each replica, h is read from the memory 12.k and h k (old) and keep it in h k Starting from timing t22, for the replicas with replica numbers = 0 and R-1, at the processing timing of each replica, h is read from the memory 12. k and h k (old) Another one in h k Holding circuit 14g.

[0206] Starting from timing t24, the update phase of the first partial field using the second partial field is executed. Starting from timing t24, for the copies with copy numbers = 0 and R-1, at the processing timing of each copy, the weighting factor memory 11 reads the h value changed from the value at the starting point. k The identification number of k = W corresponding to k ki Then, starting from timing t25, for these replicas, δh is calculated i In addition, starting from timing t26, using δh i Run h on these copies i Note that for other copies, use the h at the starting point i and h k To update h i and h k .

[0207] Thereafter, starting from timing t27 , the trial phase for specifying the first conversion candidate is started again, and processing similar to that starting from timing t1 is performed.

[0208] For example, in the case of executing the pipeline processing as described above, a state indicating the minimum value among the values ​​of the evaluation function obtained when the processing for each replica is repeated a predetermined number of times is output as a solution. Note that the above pipeline processing can also be applied to a solution search using the simulated annealing method, and can also be applied to a solution search using the replica exchange method.

[0209] The control circuit 17 controls the plurality of different replicas so as to execute different processing in the same period by pipeline processing, thereby enabling the plurality of replicas to be processed in parallel at the same time.

[0210] like Fig.10 and Fig.11 As shown, one step of each replica processing (each processing of the test phase + update phase) is in the same period of all processing (first bit conversion processing, second bit conversion processing, and third bit conversion processing) that changes the value of one conversion candidate for each processing. This can make it possible to hide the delay in the pipeline of each replica processing.

[0211] Fig.12 and Fig.13 is a diagram showing a second example of pipeline processing according to the data processing method of the first embodiment. Note that Fig.12 and Fig.13 shows the execution through pipeline processing Fig. 9 An example of a multi-bit conversion process is shown.

[0212] The processing from timing t30 to timing t36 is the same as Fig.10 The processes from timing t1 to timing t7 shown are the same.

[0213] Starting from timing t36, the update process of the first partial field using the second partial field is executed. The process of one cycle from timing t36 to timing t43 is the same as Fig.10 and Fig.11 The processes from the timing t11 to the timing t18 shown are the same.

[0214] The processing from one cycle before timing t43 to timing t47 is the same as Fig.11 The processes from the timing t19 to the timing t23 shown are the same.

[0215] The processing from timing t47 to timing t51 is the same as Fig.11 The processes from timing t23 to timing t27 shown are the same.

[0216] Fig.12 and Fig.13 The processing in is to reflect the difference from the value of the second partial field at the starting point in the first partial field every time a conversion candidate is specified.

[0217] Note that after determining whether to accept conversion of the n conversion candidates, since the above-mentioned difference of the second partial field does not have to be reflected in the first partial field except for the accepted copy, the pipeline processing period can be shortened.

[0218] According to the data processing device 10 and the data processing method of the first embodiment as described above, the state at the first time point (the starting point in the above example) and the values ​​of the first local field and the second local field are stored. Then, the values ​​of the conversion candidates specified one by one from this time point are changed to update the first local field and the second local field, and based on ΔH iThe cumulative value of determines whether to accept the change of the value of these conversion candidates. Even if the state and the values ​​of the first local field and the second local field are updated based on the change of the value of the conversion candidate, when the above acceptance is rejected, the state and the values ​​of the first local field and the second local field are restored to the state and the values ​​of the first local field and the second local field at the above-mentioned first time point stored in advance. In this way, there is no need to involve a complex propagation mechanism of local fields for realizing multi-bit conversion, etc. This can make it possible to promote the independence of the arithmetic unit for each bit, thereby simplifying the circuit configuration, and making it easy to realize multi-bit conversion processing. This can also achieve large-scale parallelization. In addition, even when the number of conversion candidates (n) is changed, the processing can be performed using the same circuit, and therefore the search freedom can be high.

[0219] Furthermore, since the single-bit conversion process and the multi-bit conversion process can be realized by the same circuit, the operation mode can be easily switched.

[0220] In addition, it is also possible to realize the following without complicating the circuit configuration: Figures 10 to 13 Pipeline processing using multiple copies is shown, and high performance can be expected.

[0221] In addition, according to the data processing device 10 and the data processing method of the first embodiment, a second local field for specifying the constraint violation amount of the value added to the evaluation function when the constraint condition is not satisfied is used. For the second local field, the value at the first time point is stored in the memory 12 as described above. In addition, the second local field is updated each time a conversion candidate is specified. Then, at the second time point, the value of the first local field is further updated using the value of the second local field at the first time point and the value of the second local field at the second time point. In addition, in the case of determining that the change in the value of the n conversion candidates is not accepted, the value of the second local field is restored to the value at the first time point. This can allow the multi-bit conversion processing as described above to be applied to a combinatorial optimization problem with constraints.

[0222] In addition, for example, Figures 9 to 11 As shown, the data processing device 10 can allocate the timing of updating the first partial field using the value of the second partial field at the first time point and the second time point to the time points of specifying multiple conversion candidates (in the above example, the time points of specifying n-1 conversion candidates). Compared with the case where the change of the second partial field is reflected in the first partial field each time, this can allow the change of the second partial field to be reflected centrally, and thus the number of arithmetic operations can be reduced.

[0223] Such a data processing apparatus 10 can be expected to be used as a technique for obtaining an accurate solution at high speed when solving various problems in modern society that can be converted into combinatorial optimization problems with constraints.

[0224] (Second Embodiment)

[0225] The data processing device according to the second embodiment to be described below divides N state variables into a plurality of state variable groups to perform the designation and update processing of n conversion candidates, the calculation of cumulative values, etc. in parallel for each state variable group using a plurality of modules. Note that an example in which N state variables are divided into three state variable groups and the processing is performed by three modules will be described below, but these numbers are not restrictive.

[0226] Fig.14 and Fig.15 FIG. 1 is a diagram showing an example of a data processing device according to the second embodiment. Fig.14 and Fig.15 In, with Figure 3 and Figure 5 Elements which are identical to the elements shown will be given the same reference numerals.

[0227] In the data processing device 30 of the second embodiment, the conversion candidate specifying circuit 31 includes modules 31a1, 31a2, and 31a3. The modules 31a1 to 31a3 are connected in the range of x1 to x2. N n transition candidates are specified one by one within the range of different state variable groups.

[0228] For example, module 31a1 processes x1 to x k-1 The state variable group, module 31a2 processes x k to x l-1 The state variable group, and module 31a3 processes x l to x N The state variable group.

[0229] Each of the modules 31a1 to 31a3 is provided with Figure 5 The ΔH calculation circuit 13a, ΔH holding circuit 13b, acceptance determination circuit 13d and selection circuit 13e are shown. Fig.14 , the ΔH calculation circuit 13a and the ΔH holding circuit 13b are collectively expressed as "ΔH calculation", the acceptance determination circuit 13d is expressed as "acceptance", and the selection circuit 13e is expressed as "selection".

[0230] The conversion candidate designation circuit 31 further includes a selection circuit 31b and an FF unit 31c. Under the control of the control circuit 17, the selection circuit 31b converts ΔH caused by the change in the value of the conversion candidate output from the modules 31a1 to 31a3 to iThe conversion candidate identification number is similarly selected and supplied to any one of the holding circuits 33b1, 33b2, and 33b3 for the modules 31a1 to 31a3. The FF unit 31c includes as many FFs as the number of modules 31a1 to 31a3, that is, three FFs. Figure 5 FF 13c shown. This allows the parallel output of h k (old) Three examples of .

[0231] The identification number and ΔH of the first conversion candidate outputted from each of the modules 31a1 to 31a3 may be i Supplied to one of the calculation circuits 33a1 to 33a3 and one of the holding circuits 33b1 to 33b3 for any module. The identification numbers and ΔH of the second conversion candidate and subsequent conversion candidates output from each of the modules 31a1 to 31a3 are i The voltages are supplied to the calculation circuits 33a1 to 33a3 and the holding circuits 33b1 to 33b3 for the corresponding modules, respectively.

[0232] As the selection circuit 31b that performs such selection, for example, a 3-to-1 selector having three channels can be used.

[0233] In the updating circuit 32, the state updating holding circuit 32a holds three state variable groups. The three state variable groups are obtained by dividing the values ​​of the N state variables into three. The state updating holding circuit 32a can update the values ​​of the state variables selected by the selecting circuit 31b from each state variable group in parallel under the control of the control circuit 17. In addition, the state updating holding circuit 32a can output Δx in parallel from each of the three holding areas holding the values ​​of the three state variable groups. j .

[0234] In addition, in the updating circuit 32, h i h k The update circuit 32b updates the first local field (h ) in association with changes in the values ​​of the three state variables selected by the selection circuit 31b under the control of the control circuit 17. i ) and the second local field (h k ). For example, in x j If h is a candidate for conversion, i Updated to h i =h i +W ij Δx j In addition, at x j When h is designated as a conversion candidate, kUpdated to h k =h k +W kj Δx j The value of .

[0235] h k The update detection circuit 32d detects the update of x in each of the three state variable groups. j The change in the value of h is associated with three groups k Updates. kj = 0, no h is detected for the constraint with identification number = k k Updates.

[0236] h k The contribution calculation circuit 32c reads a non-zero W from the weighting factor memory 11. ki , used to calculate the three groups h k The update of which is detected in h k The change in the value of h i The change in (δh i ). In addition, h k The contribution amount calculation circuit 32c uses h k The holding circuit 32f obtains three groups of h k , and get h from FF 31c k (old) Then, h k The contribution calculation circuit 32c calculates the three groups h k Each change in δh is associated with i , and by changing δh i Added to the h included in the first partial field group corresponding to each group i To update h i .

[0237] h i The holding circuit 32e is operated by setting h i The N instances of h are divided into three groups corresponding to the three state variables to maintain h i N instances of . Using x selected from the corresponding state variable group j The change (Δx j ) to update the h included in each of the three first partial field groups i N / 3 instances of .

[0238] h k The holding circuit 32f holds h corresponding to the three modules 31a1 to 31a3. k Three groups of M instances of .

[0239] Fig.15The cumulative value calculation circuit 33 in the embodiment includes a circuit for calculating ΔH for each of the modules 31a1 to 31a3. i Furthermore, the cumulative value calculation circuit 33 includes holding circuits 33b1 to 33b3 for holding the identification numbers of the n conversion candidates of each of the modules 31a1 to 31a3 and a selection circuit 33c.

[0240] The selection circuit 33c selects ΔH i For example, the selection circuit 33c selects the ΔH that minimizes the value of the evaluation function. i The selection circuit 33c outputs the selected cumulative value together with the indexes of the n conversion candidates corresponding to the selected cumulative value.

[0241] Based on the selected cumulative value, the determination circuit 16 determines whether to accept a change in the values ​​of the n conversion candidates corresponding to the selected cumulative value.

[0242] Next, the flow of a data processing method (solution search) performed by the data processing device 30 of the second embodiment will be described with reference to a flowchart.

[0243] Since the entire process and single-bit conversion process are similar Figure 6 and Figure 7 The process flow is shown, so the description will be omitted.

[0244] Fig.16 : is a flowchart showing the flow of an example of a multi-bit conversion process of the data processing method according to the second embodiment.

[0245] Fig.16 The processing in steps S70 to S88 in Figure 8 The processing in steps S30 to S48 shown is basically similar.

[0246] However, the processing in steps S72 to S76 and steps S85 to S87 is performed for each module. In addition, in the processing in step S78, the determination circuit 16 uses the ΔH i Whether to accept the change of the values ​​of the n conversion candidates corresponding to the one accumulated value is determined by selecting one accumulated value from among the three accumulated values ​​of .

[0247] Furthermore, in the processing in step S81, first, a process of restoring the state and the value of the first local field associated with each module to the state and the value of the first local field at the stored starting point is performed. This is because the state and the first local field held are different for each module. Thereafter, the control circuit 17 causes the update circuit 32 to update the state and the value of the first local field associated with each module based on the identification numbers of the n conversion candidates held in any one of the holding circuits 33b1 to 33b3.

[0248] In the process in step S82, the value of the second local field held corresponding to the other modules is also updated so as to match the value of the second dependent variable (h2) held corresponding to the module outputting the selected accumulated value. k ) value.

[0249] In addition, in the processing in step S84, the control circuit 17 restores the values ​​of N / 3 state variables, the values ​​of N / 3 first local fields, and the values ​​of M second local fields maintained corresponding to each of the three modules 31a1 to 31a3 to the values ​​stored at the starting point.

[0250] Fig.17 : is a flowchart showing the flow of another example of the multi-bit conversion process of the data processing method according to the second embodiment.

[0251] Fig.17 The processing in steps S90 to S109 in Fig. 9 The processing in steps S50 to S69 shown is basically similar.

[0252] However, the processing in steps S92 to S96 and steps S105 to S108 is performed for each module. In addition, in the processing in step S98, the determination circuit 16 uses the ΔH i Whether to accept the change of the values ​​of the n conversion candidates corresponding to the one accumulated value is determined by selecting one accumulated value from among the three accumulated values ​​of .

[0253] Furthermore, in the processing in step S101, first, a process of restoring the state and the value of the first local field associated with each module to the state and the value of the first local field at the stored starting point is performed. Thereafter, the control circuit 17 causes the update circuit 32 to update the state and the value of the first local field associated with each module based on the identification numbers of the n conversion candidates held in any one of the holding circuits 33b1 to 33b3.

[0254] In the process of step S102, the value of the second local field held corresponding to the other modules is also updated so as to match the value of the second local field (h k ) value.

[0255] In addition, in the processing in step S104, the control circuit 17 restores the values ​​of N / 3 state variables, the values ​​of N / 3 first local fields, and the values ​​of M second local fields maintained corresponding to each of the three modules 31a1 to 31a3 to the values ​​stored at the starting point.

[0256] Notice, Figure 16 to Figure 17 The order of processing shown is an example, and the order of processing may be changed as appropriate.

[0257] (Example of pipeline processing)

[0258] Similar to the data processing of the data processing device 10 of the first embodiment, the above processing can also be performed in parallel for multiple copies of the Ising model using pipeline processing. The memory 12 stores the values ​​of N state variables, N first local fields, and M second local fields related to each module in an amount equal to the number of multiple copies. In addition, the memory 12 can also store the values ​​of N state variables, N first local fields, and M second local fields at the starting point in an amount equal to the number of multiple copies, or can store values ​​common to all copies. However, in this case, in order to avoid multiple copies using the memory 12 at the same time, control is performed so that the multi-bit conversion processing is not activated except for one copy in the pipeline processing. W stored in the weighting factor memory 11 ij , W ki and W ik Common to all copies.

[0259] The control circuit 17 causes the conversion candidate specifying circuit 31, the updating circuit 32, the cumulative value calculating circuit 33, and the determining circuit 16 to perform pipeline processing on a plurality of replicas. Note that the control circuit 17 may control so that single-bit conversion processing is performed on some replicas.

[0260] Fig.18 and Fig.19 : is a diagram showing an example of pipeline processing of the data processing method according to the second embodiment. Note that Fig.18 and Fig.19 shows the execution through pipeline processing Fig.16 An example of multi-bit conversion processing is shown. It can also be performed by pipeline processing. Fig.17 The following will mainly describe the multi-bit conversion process. Fig.12 The differences are in the timing diagrams shown.

[0261] Each process of the update phase is performed for each module. In the test phase, acceptance determination other than the acceptance determination performed by the determination circuit 16 based on the accumulated value is performed for each module.

[0262] The processing from timing t60 to timing t74 is similar to Fig.12 The processing from timing t30 to timing t44 shown in the figure is different in that the above processing is performed for each module. Fig.16 In the processing in step S81 shown in the figure, the processing of restoring the state of the copy with copy number = 0 and the value of the first local field associated with each module to the state and the value of the first local field at the stored starting point is performed. At timing t76 and t77, the execution Fig.16 The process in step S81 shown is an update process of the state related to each module and the value of the first local field, and a process corresponding to the process in step S82.

[0263] By such processing, at the timing t77 and for example, reading h k or k (old) A standby time occurs between the start timing (timing t78) of the control circuit 17 for updating the first partial field using the second partial field. Note that, for example, the control circuit 17 can reduce the standby time by changing the processing cycle.

[0264] The second bit conversion process ends at timing t79. Thereafter, at timing t80 and t81, Fig.16 In the processing in step S81 shown in the figure, the processing of restoring the state of the copy with copy number = R-1 and the value of the first local field associated with each module to the state and the value of the first local field at the stored starting point is performed. At timing t81 and t82, the execution Fig.16 The process in step S81 shown is an update process of the state related to each module and the value of the first local field, and a process corresponding to the process in step S82.

[0265] According to the data processing device 30 and the data processing method of the second embodiment as described above, effects similar to those of the data processing device 10 and the data processing method of the first embodiment can be obtained. In addition, since the data processing device 30 of the second embodiment can perform parallel processing through multiple modules, the solution search can be performed more efficiently. As described above, in the data processing device 10 of the first embodiment, the circuit configuration for realizing multi-bit conversion processing can be simplified. Therefore, even if a configuration for performing parallel search using multiple modules as in the data processing device 30 of the second embodiment is adopted, the circuit configuration can be suppressed from becoming complicated.

[0266] (Hardware Configuration Example)

[0267] Fig. 20 is a diagram showing a hardware example of an example of a data processing device.

[0268] The data processing device 40 is, for example, a computer, and includes a processor 41, a random access memory (RAM) 42, an HDD 43, a GPU 44, an input interface 45, a media reader 46, a communication interface 47, and an accelerator card 48. The above-mentioned units are coupled to a bus.

[0269] The processor 41 loads at least a part of the program and data stored in the HDD 43 into the RAM 42, and executes the program. Note that, for example, the processor 41 may include a plurality of processor cores. In addition, the data processing device 40 may include a plurality of processors. Note that a collection of a plurality of processors (a multiprocessor) may be referred to as a "processor". A CPU, a GPU, a DSP, etc. may be used as the processor 41.

[0270] RAM 42 is a volatile semiconductor memory that temporarily stores programs to be executed by processor 41 and data to be used for arithmetic operations by processor 41. Note that data processing apparatus 40 may include a type of memory other than RAM 42, or may include a plurality of memories.

[0271] The HDD 43 is a nonvolatile storage device that stores software programs such as an operating system (OS), middleware, and application software, and data. The program includes, for example, a program for causing the data processing device 40 to perform a process of searching for a solution of combinatorial optimization. Note that the data processing device 40 may include another type of storage device, such as a flash memory or a solid state drive (SSD), or may include a plurality of nonvolatile storage devices.

[0272] The GPU 44 outputs an image to a display 44a coupled to the data processing device 40 according to a command from the processor 41. As the display 44a, a cathode ray tube (CRT) display, a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescence (OEL) display, etc. can be used.

[0273] The input interface 45 acquires an input signal from an input device 45a coupled to the data processing device 40, and outputs the acquired input signal to the processor 41. A pointing device (such as a mouse, a touch panel, a touch pad, or a trackball), a keyboard, a remote controller, a button switch, etc. can be used as the input device 45a. In addition, various types of input devices can be coupled to the data processing device 40.

[0274] The medium reader 46 is a reading device that reads the program and data recorded on the recording medium 46a. For example, a magnetic disk, an optical disk, a magneto-optical disk (MO), a semiconductor memory, etc. can be used as the recording medium 46a. The magnetic disk includes a floppy disk (FD) and an HDD. The optical disk includes a compact disk (CD) and a digital versatile disk (DVD).

[0275] The medium reader 46 copies the program and data read from the recording medium 46a to another recording medium, such as the RAM 42 or the HDD 43, for example. The read program is executed by the processor 41, for example. Note that the recording medium 46a may be a portable recording medium and is sometimes used for distribution of programs and data. In addition, the recording medium 46a or the HDD 43 will sometimes be referred to as a computer-readable recording medium.

[0276] The communication interface 47 is an interface coupled to the network 47a and communicates with other information processing devices via the network 47a. The communication interface 47 may be a wired communication interface coupled to a communication device such as a switch through a cable, or a wireless communication interface coupled to a base station through a wireless link.

[0277] The accelerator card 48 is a hardware accelerator that searches for solutions to combinatorial optimization problems. The accelerator card 48 includes an FPGA 48a and a DRAM 48b.

[0278] Can be formed by FPGA48a and DRAM 48b Figure 3 , Fig.14 and Fig.15 Each element shown. For example, the weighting factor memory 11 is formed by the DRAM 48b, and other circuits and the memory 12 may be formed by the FPGA 48a.

[0279] Note that there may be multiple accelerator cards 48 .

[0280] Furthermore, the above-described processing details performed by the data processing devices 10 and 30 (for example, such as Figures 6 to 9 , Fig.16 and Fig.17 ).

[0281] The program may be recorded in a computer-readable recording medium. For example, a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. may be used as a recording medium. The magnetic disk includes a floppy disk and an HDD. The optical disk includes a CD, a recordable (R) / rewritable (RW) CD, a DVD, and a DVD-R / RW. Sometimes, the program may be recorded in a portable recording medium and distributed. In this case, the program may be copied from the portable recording medium to another recording medium before execution.

[0282] Fig.21is a diagram showing an example of computer hardware. Fig. 20 Elements which are identical to the elements shown are given the same reference numerals.

[0283] The computer 50 is not provided with Fig. 20 An accelerator card 48 is shown.

[0284] In the computer 50, the processor 41 executes the above-mentioned processing details (for example, such as Figures 6 to 9 , Fig.16 and Fig.17 ). The processor 41 may include multiple processor cores to perform processing in parallel for multiple copies. In addition, the HDD 43 may be used as Figure 3 The weighting factor memory 11 shown in the above and the RAM 42 can be used as the memory 12.

[0285] Although one form of the data processing apparatus, the data processing program, and the data processing method according to the embodiment has been described based on the embodiment, this is only an example and is not limited to the above description.

Claims

1. A data processing device, comprising: A memory configured to store a plurality of values ​​at a first point in time, the plurality of values ​​comprising: values ​​of a plurality of state variables at the first point in time, the plurality of state variables being included in an evaluation function of a combinatorial optimization problem having constraints; a value of a first local field at the first point in time, the first local field being used to specify an amount of change in a value of the evaluation function associated with a change in the values ​​of each of the plurality of state variables; and a value of a second local field at the first point in time, the second local field being used to specify an amount of constraint violation to be added to a value of the evaluation function when the constraints are not satisfied; a conversion candidate specifying circuit configured to: calculate the change amount by using the value of the first local field at the first time point, and specify candidates whose values ​​are to be changed among the plurality of state variables one by one based on the change amount; an updating circuit configured to: update a value of the candidate and values ​​of the first local field and the second local field each time the candidate is specified, and at a second time point, further update the value of the first local field by using a value of the second local field at the first time point and a value at the second time point; a cumulative value calculation circuit configured to calculate a cumulative value of the change amount when the value of the candidate is changed; a determination circuit configured to determine whether to accept changes in values ​​of a first number of the candidates that are equal to or greater than two based on the accumulated value; and A control circuit is configured to restore each of the values ​​of the multiple state variables, the value of the first local field, and the value of the second local field to multiple values ​​at the first time point when the determination circuit determines that the change of the first number of candidate values ​​is not accepted.

2. The data processing device according to claim 1, wherein: the control circuit switches whether to cause the conversion candidate specifying circuit to execute a first process in which it is determined based on the change amount whether to allow a change in each of the values ​​of the plurality of state variables or a second process in which the candidates are specified one by one, and The first time point is a time point when the second process is started.

3. The data processing device according to claim 1, wherein: The second time point is a time point when the candidate is specified multiple times.

4. The data processing device according to claim 1, wherein: The memory stores the values ​​of the plurality of state variables and the values ​​of the first local field and the second local field in an amount equal to the number of the plurality of copies, and The control circuit causes the conversion candidate specifying circuit, the updating circuit, the cumulative value calculating circuit, and the determining circuit to perform pipeline processing on the plurality of replicas.

5. The data processing device according to claim 1, wherein: The conversion candidate specifying circuit includes a plurality of modules, and the plurality of modules specify the first number of candidates one by one within the range of mutually different state variable groups among the plurality of state variables, the updating circuit updating the value of the state variable group corresponding to each of the plurality of modules, the value of the first local field, and the value of the second local field according to the candidate specified by each of the plurality of modules, The cumulative value calculation circuit calculates a cumulative value for each of the plurality of modules and selects one of the cumulative values ​​calculated for each of the plurality of modules, and The determination circuit determines, based on the selected one of the accumulated values, whether to accept a change in the values ​​of the first number of the candidates corresponding to the selected one of the accumulated values.

6. A non-transitory computer-readable recording medium storing a data processing program, the data processing program being used to cause a processor circuit system of a data processing device to perform a process, the process comprising: storing a plurality of values ​​at a first point in time in a memory of a computer, the plurality of values ​​comprising: values ​​of a plurality of state variables at the first point in time, the plurality of state variables being included in an evaluation function of a combinatorial optimization problem having constraints; a value of a first local field at the first point in time, the first local field being used to specify an amount of change in a value of the evaluation function associated with a change in the values ​​of each of the plurality of state variables; and a value of a second local field at the first point in time, the second local field being used to specify an amount of constraint violation to be added to a value of the evaluation function when the constraints are not satisfied; calculating the change amount by using the value of the first local field at the first time point, and specifying candidates whose values ​​are to be changed among the plurality of state variables one by one based on the change amount; updating the value of the candidate and the values ​​of the first local field and the second local field each time the candidate is specified, and further updating the value of the first local field at a second time point by using the value of the second local field at the first time point and the value at the second time point; calculating a cumulative value of the change amount when the value of the candidate is changed; determining whether to accept changes to a first number of the candidates' values ​​that are equal to or greater than two based on the accumulated value; and When the determining process determines that the change of the values ​​of the first number of the candidates is not accepted, each of the values ​​of the plurality of state variables, the value of the first local field, and the value of the second local field is restored to a plurality of values ​​at the first time point.

7. A data processing method implemented by a processor circuit system of a data processing device, the data processing method comprising: storing a plurality of values ​​at a first point in time in a memory of a computer, the plurality of values ​​comprising: values ​​of a plurality of state variables at the first point in time, the plurality of state variables being included in an evaluation function of a combinatorial optimization problem having constraints; a value of a first local field at the first point in time, the first local field being used to specify an amount of change in a value of the evaluation function associated with a change in the values ​​of each of the plurality of state variables; and a value of a second local field at the first point in time, the second local field being used to specify an amount of constraint violation to be added to a value of the evaluation function when the constraints are not satisfied; calculating the change amount by using the value of the first local field at the first time point, and specifying candidates whose values ​​are to be changed among the plurality of state variables one by one based on the change amount; updating the value of the candidate and the values ​​of the first local field and the second local field each time the candidate is specified, and further updating the value of the first local field at a second time point by using the value of the second local field at the first time point and the value at the second time point; calculating a cumulative value of the change amount when the value of the candidate is changed; determining whether to accept changes to a first number of the candidates' values ​​that are equal to or greater than two based on the accumulated value; and When the determining process determines that the change of the values ​​of the first number of the candidates is not accepted, each of the values ​​of the plurality of state variables, the value of the first local field, and the value of the second local field is restored to a plurality of values ​​at the first time point.

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