Self-timing readout driver for leak-based physically unductable function (l-PUF) device, l-PUF array using the same, and

Abstract

A self-timed readout driver for a leak-based physically unduplicable function (L-PUF) device, a leak-based physically unduplicable function array using the same, and an application thereof are provided. The self-timing readout driver includes a pre-charge transistor, an inverter, and a leakage device. The pre-charge transistor has a control end, a first end and a second end. The inverter is electrically connected to the second end of the pre-charge transistor. The leakage device has a control terminal electrically connected to ground, a first terminal electrically connected to the second terminal of the pre-charge transistor, and a second terminal electrically connected to ground. A control terminal of the pre-charge transistor is configured to receive an input signal. The inverter is configured to generate a sense enable (SE) signal. The input signal and the sensing enable signal may be used as two input signals for a leakage-based physically unduplicable function device.

Description

Technical Field

[0001] The present invention generally relates to physically unclonable function (PUF) technology, and more particularly to a self-timed readout driver for a leakage-based physically unclonable function (L-PUF), an L-PUF array using the same, and applications thereof. Background Art

[0002] The background description provided herein is intended to present the background of the present invention in general. The subject matter discussed in the Background of the Present Invention section should not be assumed to be prior art simply because it is mentioned in the Background of the Present Invention section. Similarly, problems mentioned in the Background of the Present Invention section or associated with the subject matter of the Background of the Present Invention section should not be assumed to have been previously recognized in the prior art. The subject matter in the Background of the Present Invention section merely represents different approaches, which themselves may also be inventions.

[0003] A Physical Unclonable Function (PUF) is a physical object whose operation cannot be physically reproduced (i.e., "copied") (by making another system using the same technology), and for given inputs and conditions, the PUF provides a physically defined "digital fingerprint" output (response). PUF is a class of cryptographic primitives that use physical variations in hardware devices to generate unique and unpredictable keys for secure authentication and identification purposes. Specifically, PUF provides a tamper-proof solution for key generation by exploiting the randomness inherent in manufacturing variations, thereby eliminating the need for traditional storage and management of secret keys. Specifically, leakage-based PUFs (L-PUFs) are very sensitive to process variations. However, due to the large dynamic range of leakage currents, it is also difficult to determine when the data is read out.

[0004] Therefore, there exists a heretofore unaddressed need in the art to address the aforementioned deficiencies and inadequacies. Summary of the invention

[0005] Certain aspects of the present invention relate to a self-timed readout driver for a leakage-based physical non-copyable function (L-PUF) device. In one aspect, the self-timed readout driver includes a precharge transistor, an inverter, and a leakage device. The precharge transistor has a control terminal, a first terminal, and a second terminal. The inverter is electrically connected to the second terminal of the precharge transistor. The leakage device has a control terminal electrically connected to ground, a first terminal electrically connected to the second terminal of the precharge transistor, and a second terminal electrically connected to ground. The control terminal of the precharge transistor is configured to receive an input signal. The inverter is configured to generate a sense enable (SE) signal.

[0006] In some embodiments, the input signal and the SE signal are configured as two input signals of the L-PUF device.

[0007] In some embodiments, the L-PUF device includes a precharge circuit, a first leakage device and a second leakage device, and a sense amplifier. The precharge circuit is configured to receive an input signal. The first leakage device and the second leakage device are electrically connected to the precharge circuit, respectively. Each of the first leakage device and the second leakage device includes a transistor having a control terminal electrically connected to the ground, a first terminal electrically connected to the precharge circuit, and a second terminal electrically connected to the ground. The sense amplifier is electrically connected to the first terminal of the first leakage device and the first terminal of the second leakage device. The sense amplifier is configured to receive the SE signal and generate a first output signal and a second output signal. The sense amplifier is configured to switch between a first state and a second state based on a voltage difference between the first leakage device and the second leakage device, and the voltage difference between the first leakage device and the second leakage device is determined by a leakage current of the first leakage device and a leakage current of the second leakage device.

[0008] In some embodiments, the leaking device is an N-repeated leaking device, and the N-repeated leaking device is configured to leak faster than the first leaking device and the second leaking device of the L-PUF device.

[0009] In some embodiments, the sense amplifier includes: a first transistor having a control terminal configured to receive an SE input signal, a first terminal, and a second terminal electrically connected to ground; a second transistor having a control terminal electrically connected to a first terminal of a transistor of a first leakage device, a first terminal, and a second terminal configured to generate a first output signal; a third transistor having a control terminal electrically connected to a first terminal of the transistor of the first leakage device, a first terminal electrically connected to a second terminal of the second transistor, and a second terminal electrically connected to the first terminal of the first transistor; a fourth transistor having a control terminal electrically connected to a first terminal of the transistor of the second leakage device, a first terminal, and a second terminal configured to generate a second output signal; and a fifth transistor having a control terminal electrically connected to a first terminal of the transistor of the second leakage device, a first terminal electrically connected to a second terminal of the fourth transistor, and a second terminal electrically connected to the first terminal of the first transistor. The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first terminal of the transistor of the second leakage device, and the second terminal of the fourth transistor and the first terminal of the fifth transistor are electrically connected to the first terminal of the transistor of the first leakage device.

[0010] In some embodiments, the L-PUF device further includes: a first switch electrically connected to the second terminal of the second transistor; and a second switch electrically connected to the second terminal of the fourth transistor.

[0011] In some embodiments, the first switch and the second switch are controlled by input signals respectively.

[0012] In another aspect, an L-PUF array includes a plurality of L-PUF units in an array form, a plurality of input signal lines, a plurality of output signal lines, and a plurality of control circuits. Each of the L-PUF units includes a corresponding L-PUF device. The input signal lines extend in a first direction and are electrically connected to the L-PUF units respectively. Each of the input signal lines is configured to transmit one of two input signals to a first corresponding group of L-PUF units. The output signal lines extend in a second direction and are electrically connected to the L-PUF units respectively. Each of the output signal lines is configured to receive an output signal from a second corresponding group of L-PUF units. The control circuit is electrically connected to the input signal lines to provide the two input signals to the L-PUF units through the input signal lines. Each of the control circuits includes a self-timed readout driver as described above, and the input signal and the SE signal generated by the self-timed readout driver are configured as the two input signals of the L-PUF unit.

[0013] In some embodiments, one of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction.

[0014] In some embodiments, the L-PUF device includes a precharge circuit, a first leakage device, and a second leakage device. The first leakage device and the second leakage device are electrically connected to the precharge circuit, respectively. Each of the first leakage device and the second leakage device includes a transistor having a control terminal electrically connected to ground, a first terminal electrically connected to the precharge circuit, and a second terminal electrically connected to ground. The first intermediate output signal is determined based on the dropped voltage of the first leakage device, and the second intermediate output signal is determined based on the dropped voltage of the second leakage device.

[0015] In some embodiments, the leaking device is an N-repeated leaking device, and the N-repeated leaking device is configured to leak faster than the first leaking device and the second leaking device of the L-PUF device.

[0016] In some embodiments, the L-PUF device further comprises: a first switch electrically connected to a first terminal of a transistor of the first leakage device; and a second switch electrically connected to a first terminal of a transistor of the second leakage device. The first switch is configured to transmit a first intermediate output signal when controlled to switch to an on state, and the second switch is configured to transmit a second intermediate output signal when controlled to switch to an on state.

[0017] In another aspect, an L-PUF array includes a plurality of L-PUF units in an array form, a plurality of input signal lines, a plurality of output signal lines, a plurality of sense amplifiers, and a control circuit. Each of the L-PUF units includes a corresponding L-PUF device. The input signal lines extend in a first direction and are electrically connected to the L-PUF units, respectively. The output signal lines extend in a second direction and are electrically connected to the L-PUF units, respectively. The sense amplifiers are electrically connected to one of the input signal lines and the output signal lines, respectively. The input signal lines are configured to transmit two input signals to the sense amplifier and the L-PUF unit. The control circuit is electrically connected to the one of the input signal lines to provide one of the two input signals to the sense amplifier through the one of the input signal lines. The control circuit includes a self-timed readout driver as described above, and the SE signal generated by the self-timed readout driver is configured to transmit one of the two input signals to the sense amplifier.

[0018] In certain embodiments, each of the sense amplifiers is configured to receive, through an output signal line, first and second intermediate output signals transmitted by a second corresponding group of L-PUF cells and generate an output signal based on the first and second intermediate output signals.

[0019] In some embodiments, one of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction.

[0020] In certain embodiments, each of the sense amplifiers includes a first stage preamplifier and a second stage latch.

[0021] In yet another aspect, a security authentication device is provided, the security authentication device comprising the L-PUF array as described above. In one embodiment, the security authentication device is a secure cryptographic key generating device.

[0022] These and other aspects of the invention will become apparent from the following description of the preferred embodiments read in conjunction with the following drawings, but various changes and modifications may be made thereto without departing from the spirit and scope of the novel concepts of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings illustrate one or more embodiments of the present invention and together with the written description serve to explain the principles of the present invention. In all drawings, the same reference numerals may be used to refer to the same or similar elements in the embodiments.

[0024] Figure 1 An exemplary self-timed readout driver for an L-PUF device according to one embodiment of the present invention is schematically shown.

[0025] Figure 2A An exemplary L-PUF device according to an embodiment of the present invention is schematically shown.

[0026] Figure 2B Shown as Figure 2A The exemplary L-PUF device is shown operating in a first state S0 where (Z, ZB)=(0,1).

[0027] Figure 2C Shown as Figure 2A The exemplary L-PUF device is shown operating in a second state S1 where it outputs (Z, ZB)=(1,0).

[0028] Figure 3 An exemplary L-PUF device according to another embodiment of the present invention is schematically shown.

[0029] Figure 4 Shown as Figure 3 The exemplary L-PUF device is shown operating in a state where the output is (BL, BLB) = (1, 0).

[0030] Figure 5 Schematically showing a plurality of Figure 3 An exemplary L-PUF array formed by L-PUF devices is shown.

[0031] Figure 6An exemplary L-PUF device according to yet another embodiment of the present invention is schematically shown.

[0032] Figure 7 Schematically showing a plurality of Figure 6 An exemplary L-PUF array formed by L-PUF devices is shown.

[0033] Figure 8 Shown as Figure 7 Operation of the exemplary L-PUF array is shown.

[0034] Fig. 9 Schematically shown in Figure 7 Example sense amplifiers used in the example L-PUF array shown.

[0035] Main component markings

[0036] 100: Self-timed readout driver

[0037] 110: Pre-charge transistor

[0038] 120: Inverter / High Skew Inverter

[0039] 130: Sense Amplifier / Leakage Device

[0040] 200, 300, 600: L-PUF device

[0041] 210, 310, 610: Pre-charge circuit

[0042] 220, 225, 320, 325, 620, 625, Q0: Leakage device

[0043] 230, 330, 740: Sense amplifier

[0044] 500, 700: L-PUF array

[0045] 510, 710: L-PUF unit

[0046] 520, 720: Input signal line / first input line

[0047] 522, 722: Input signal line / second input line

[0048] 530, 730: Output signal line / first output line

[0049] 532, 732: Output signal line / second output line

[0050] 550, 750: Control circuit

[0051] 910: First stage preamplifier

[0052] 920: Second level latch

[0053] B: Buffer

[0054] BL: Output / First Output Signal / Output Signal / Intermediate Output Signal / First Intermediate Output Signal

[0055] BL <0> ~BL<N'-1> : First output signal / first intermediate output signal

[0056] BLB: Output / Output signal / Second output signal / Intermediate output signal / Second intermediate output signal

[0057] BLB <0> ~BLB<N'-1> : Second output signal / second intermediate output signal

[0058] OUT, OUT <0> ~OUT<N'-1> ,OUTB,OUTB <0> ~OUTB<N'-1> , VON, VOP: output signal

[0059] PCH, SE, SE <0> ~SE <m-1>WL WL <0> ~WL <m-1>: Input signal

[0060] Q1: Leakage device / First leakage device

[0061] Q2: Leakage device / Second leakage device

[0062] Q3: First transistor

[0063] Q4: Second transistor

[0064] Q5: The third transistor

[0065] Q6: The fourth transistor

[0066] Q7: The fifth transistor

[0067] S1: Switch / First switch

[0068] S2: Switch / Second switch

[0069] SL, SR: Node

[0070] V(SL), V(SR), VL, VR: voltage

[0071] V Core : High voltage level

[0072] V diff : Critical point

[0073] Z: Output / output signal / first output signal

[0074] ZB: Output / output signal / second output signal DETAILED DESCRIPTION

[0075] The present invention will now be more fully described hereinafter with reference to the accompanying drawings in which exemplary embodiments of the invention are shown. However, the present invention may be implemented in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present invention thorough and complete and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0076] The terms used in this specification generally have their ordinary meaning in the art, in the context of the present invention, and in the specific context in which each term is used. Certain terms used to illustrate the present invention will be discussed below or elsewhere in this specification to provide practitioners with additional guidance on the description of the present invention. For convenience, certain terms may be highlighted, for example, using italics and / or quotation marks. The use of highlighting will not affect the scope and meaning of the terms; in the same context, whether the terms are highlighted or not, the scope and meaning of the terms are the same. It should be understood that the same thing can be expressed in more than one way. Therefore, alternative language and synonyms may be used for any one or more of the terms discussed herein, and there is no special meaning in whether the terms are elaborated or discussed in detail in this specification. Synonyms for certain terms are provided. The description of one or more synonyms does not exclude the use of other synonyms. The use of examples of examples including any terms discussed herein anywhere in this specification is merely illustrative and in no way limits the scope and meaning of the present invention or any of the listed terms. Similarly, the present invention is not limited to the various embodiments given in this specification.

[0077] It should be understood that the meaning of "a / an" and "the" used throughout the description and appended claims herein also includes plural references unless the context clearly indicates otherwise. Similarly, it should be understood that when an element is referred to as being "located on" another element, it can be directly on the other element, or there can be intervening elements between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "and / or" as used herein include any and all combinations of one or more of the associated listed items.

[0078] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present invention.

[0079] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element illustrated in the figures. It should be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, the elements described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" may encompass both the "lower" and "upper" orientations depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, the elements described as being "below" or "under" the other elements will be oriented "above" the other elements. Thus, the exemplary terms "below" or "under" may encompass both the above and below orientations.

[0080] It should also be understood that the terms "comprises and / or comprising", or "includes and / or including", or "has and / or having", or "carry and / or carrying", or "contain and / or containing", or "involve and / or involving", etc. are open-ended terms, i.e., meaning "including but not limited to". These open-ended terms, when used in the present invention, specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0081] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0082] As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0083] The term "leakage device" used herein is formed by a transistor for implementing a corresponding leakage function, and the "leakage device" is a subthreshold region of the transistor. Specifically, when the gate and source nodes of the transistor are electrically connected together, the transistor is biased in the subthreshold region, and the current induced by the subthreshold region is a "leakage current", which is relatively smaller than the current induced by other regions.

[0084] The various devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints on the overall system. For example, an element or any portion of an element or any combination of elements can be implemented as a "processing system" including one or more processors.

[0085] The following description is merely illustrative in nature and is in no way intended to limit the present invention, its application or use. The broad teachings of the present invention can be implemented in various forms. Therefore, although the present invention includes specific examples, the true scope of the present invention should not be so limited, because other modifications will become apparent when studying the drawings, specifications and appended claims. For clarity, the same reference numbers will be used in the drawings to identify similar elements. It should be understood that one or more steps in the method can be performed in different orders (or simultaneously) without changing the principles of the present invention.

[0086] As discussed above, L-PUF is very sensitive to process variations. However, due to the large dynamic range of leakage current, it is also difficult to determine the time to read out data. In view of this, certain aspects of the present invention relate to a self-timed readout driver for L-PUF, which can be used for timing control of L-PUF. In certain embodiments, the self-timed readout driver has a simple N-repeated leakage device, so that the leakage device leaks faster than the leakage device of the L-PUF device, thereby ensuring a faster release of the sensing enable signal. In one embodiment, the proposed self-timed readout driver for L-PUF can provide a novel solution for improving the security of hardware systems, and the self-timing and adaptability of the self-timed readout driver to process variations will ensure that the system works reliably and efficiently, making it a promising area for future research and development.

[0087] Figure 1 Schematically illustrates an exemplary self-timed readout driver for an L-PUF device according to one embodiment of the present invention. Figure 1 As shown, the self-timed readout driver 100 includes a precharge transistor 110, an inverter 120, and a leakage device 130. The precharge transistor 110 has a control terminal, a first terminal, and a second terminal. The inverter 120 may be a high-skewed inverter, which is electrically connected to the second terminal of the precharge transistor 110 and is used to generate a sense enable (SE) signal as an input signal of the L-PUF device. In some embodiments, the leakage device 130 may be a leakage device Q0 (×N) repeated N times. Alternatively, in some embodiments, the leakage device 130 may be a non-repeating leakage device Q0. Specifically, the leakage device 130 has a control terminal electrically connected to the ground, a first terminal electrically connected to the second terminal of the precharge transistor 110, and a second terminal electrically connected to the ground. In other words, the control terminal (i.e., the gate) and the second terminal (i.e., the source) of the leakage device 130 are electrically connected to each other. The control terminal of the pre-charging transistor 110 is configured to receive an input signal PCH, which may also be another input signal of the L-PUF device.

[0088] When the self-timed readout driver 100 operates, the presence of N copies in Q0 causes Q0 to leak faster than the leakage device in the L-PUF device, thereby ensuring that the SE signal is released faster. Then, the high-skew inverter 120 responds quickly to the voltage drop and pulls up the SE signal, which ensures that the SE signal can adapt to process variations and is pulled up to reach the critical point voltage earlier than the voltage difference of the leakage device of the L-PUF device.

[0089] Figure 2A An exemplary L-PUF device according to an embodiment of the present invention is schematically shown. Specifically, Figure 2A The L-PUF device 200 shown mainly includes a pre-charge circuit 210, two leakage devices 220 (Q1) and 225 (Q2), and a sense amplifier 230. For the sake of clarity, the two leakage devices 220 and 225 are referred to as a first leakage device Q1 and a second leakage device Q2. Figure 2A As shown, each of the first leakage device Q1 and the second leakage device Q2 includes a transistor. Specifically, the transistor of each leakage device Q1 and Q2 has a control terminal electrically connected to the ground, a first terminal electrically connected to the precharge circuit 210, and a second terminal electrically connected to the ground. In other words, for each of the first leakage device Q1 and the second leakage device Q2, the control terminal (i.e., the gate) and the second terminal (i.e., the source) are electrically connected to each other. Specifically, the first terminal of the transistor of the first leakage device Q1 is electrically connected to the node SL, and the node SL is electrically connected to the precharge circuit 210; and the first terminal of the transistor of the second leakage device Q2 is electrically connected to the node SR, and the node SR is electrically connected to the precharge circuit 210.

[0090] The sense amplifier 230 is electrically connected to the first end of the first leakage device Q1 and the first end of the second leakage device Q2. Specifically, the L-PUF device 200 has two input signals SE and PCH, and generates two output signals Z and ZB. Specifically, the sense amplifier 230 receives the first signal from the first leakage device Q1 and the second leakage device Q2. Figure 1 The self-timed readout driver 100 shown in FIG. 1 generates an input signal SE and generates a first output signal Z and a second output signal ZB accordingly. The precharge circuit 210 receives another input signal PCH, which is similar to the input signal PCH of FIG. Figure 1 The input signal to the pre-charge transistor 110 of the self-timed sense driver 100 is shown to be the same input signal.

[0091] like Figure 2A As shown, in the L-PUF device 200, the leakage current of the first leakage device Q1 and the leakage current of the second leakage device Q2 depend on the critical point voltage (V th ). Specifically, taking into account process variations, the exponential relationship that leads to a large dynamic range is shown in the following equation (1).

[0092]

[0093] In the L-PUF device 200 , the sense amplifier 230 can switch between the first state and the second state based on the voltage difference between the first leakage device Q1 and the second leakage device Q2 , and the voltage difference between the first leakage device Q1 and the second leakage device Q2 is determined by the leakage current of the first leakage device Q1 and the leakage current of the second leakage device Q2 .

[0094] Figure 2B Shown as Figure 2A The exemplary L-PUF device shown operates in a first state S0 with output (Z, ZB) = (0, 1), and Figure 2C Shown as Figure 2B The exemplary L-PUF device shown in FIG. 1 operates in the second state S1 where the output is (Z, ZB) = (1, 0). Specifically, Figure 2B and Figure 2C As shown, at the beginning of the operation process of the L-PUF device 200, the precharge circuit 210 receiving the input signal PCH as its input starts the precharge process with the input signal PCH at a low voltage level, and precharges the nodes SL and SR to a high voltage level. At the same time, the precharge transistor 110 of the self-timed readout driver 100 also receives the input signal PCH and is also precharged. At this time, the self-timed readout driver 100 has not yet generated the SE signal. Therefore, the input signal SE of the sense amplifier 230 remains deactivated at a low voltage level.

[0095] Subsequently, the input signal PCH is activated (ie, at a high voltage level V Core ) to disable the precharge circuit 210 of the L-PUF device 200 and allow the self-timed readout driver 100 to switch to the self-timed operation mode. Specifically, at the self-timed readout driver 100, the presence of N copies in the leakage device Q0 causes the leakage device Q0 to leak faster than the leakage devices Q1 and Q2 in the L-PUF device 200, thereby ensuring that the inverter 120 releases the SE signal faster. Then, the high-skew inverter 120 quickly responds to the voltage drop and pulls up the SE signal.

[0096] Meanwhile, at the L-PUF device 200, as the two nodes SL and SR reach a high voltage level, the two leakage devices Q1 and Q2 start to operate, and the leakage current of one of the two leakage devices is greater than the leakage current of the other leakage device. Figure 2B As shown in FIG. 1 , when the leakage current of the first leakage device Q1 is greater than the leakage current of the second leakage device Q2, the voltage at the node SL connected to the first end of the transistor of the first leakage device Q1 will drop faster than the voltage at the node SR connected to the first end of the transistor of the second leakage device Q2. This difference in voltage drop is a result of the inherent variability of the manufacturing process, which makes it impossible to accurately replicate the same design from one chip to another. Once the voltage difference between the two leakage devices Q2 and Q1 exceeds a certain critical point (i.e., V diff ), the sense amplifier 230 is enabled and switched to the first state (ie, state 0), so that the two output signals (Z, ZB) are read as (0, 1).

[0097] On the contrary, Figure 2C As shown, when the leakage current of the second leakage device Q2 is greater than the leakage current of the first leakage device Q1, the voltage at the node SR connected to the first end of the transistor of the second leakage device Q2 will drop faster than the voltage at the node SL connected to the first end of the transistor of the first leakage device Q1. Once the voltage difference between the two leakage devices Q1 and Q2 exceeds a certain critical point (i.e., V diff ), the sense amplifier 230 is enabled and switched to the second state (ie, state 1), so that the two output signals (Z, ZB) are read as (1, 0).

[0098] In certain embodiments, such as Figure 2B and Figure 2C The corresponding critical points of the voltage difference between the two leakage devices Q1 and Q2 shown may have the same absolute value (ie, V diff ).in other words, Figure 2B It shows that V(SR)–V(SL)=V diff ,and Figure 2C It shows that V(SL)–V(SR)=V diff Alternatively, in certain embodiments, Figure 2B and Figure 2C The critical point of the voltage difference between the two leakage devices Q1 and Q2 shown may have different absolute values.

[0099] Use as Figure 1 The structure of the self-timed sense driver 100 shown ensures that the SE signal can adapt to process variations and be pulled up to the threshold voltage earlier than the voltage difference between the nodes SL and SR.

[0100] It should be noted that the output signal of the L-PUF device 200 is unique to each individual L-PUF and is determined by the specific characteristics of the leakage devices Q1 and Q2 that make up the circuit. By exploiting this inherent variability, L-PUFs can be used for secure cryptographic key generation and other applications requiring secure authentication.

[0101] The output of the L-PUF device is unique to each individual L-PUF and is determined by the specific characteristics of the leakage devices Q1 and Q2 that make up the circuit. By exploiting this inherent variability, L-PUF can be used for secure key generation and other applications requiring secure authentication.

[0102] Figure 3 Schematically illustrates an exemplary L-PUF device according to another embodiment of the present invention. Specifically, Figure 3 The illustrated L-PUF device 300 is a detailed version of the L-PUF device 200, using a five-transistor implementation to illustrate the circuitry of the sense amplifier 330. Figure 3 As shown, the L-PUF device 300 includes a precharge circuit 310, two leakage devices 320 (Q1) and 325 (Q2), and a sense amplifier 330. For clarity, the two leakage devices 320 and 325 are referred to as a first leakage device Q1 and a second leakage device Q2. Figure 3 As shown, each of the first leakage device Q1 and the second leakage device Q2 includes a transistor. Specifically, the transistor of each leakage device Q1 and Q2 has a control terminal electrically connected to the ground, a first terminal electrically connected to the precharge circuit 310, and a second terminal electrically connected to the ground. In other words, for each of the first leakage device Q1 and the second leakage device Q2, the control terminal (i.e., the gate) and the second terminal (i.e., the source) are electrically connected to each other. Specifically, the first terminal of the transistor of the first leakage device Q1 is electrically connected to the node SL, and the node SL is electrically connected to the precharge circuit 310; and the first terminal of the transistor of the second leakage device Q2 is electrically connected to the node SR, and the node SR is electrically connected to the precharge circuit 310.

[0103] In addition, the sense amplifier 330 includes a first transistor Q3, a second transistor Q4, a third transistor Q5, a fourth transistor Q6, and a fifth transistor Q7. The first transistor Q3 has a control terminal configured to receive an input signal SE (generated by the inverter 120 of the self-timed readout driver 100), a first terminal electrically connected to the second terminal of the third transistor Q5 and the second terminal of the fifth transistor Q7, and a second terminal electrically connected to the ground. The second transistor Q4 and the third transistor Q5 are arranged to correspond to the first leakage device Q1, the second transistor Q4 has a control terminal electrically connected to the node SL (which is electrically connected to the first terminal of the transistor of the first leakage device Q1), a first terminal, and a second terminal configured to generate a corresponding output signal Z; and the third transistor Q5 has a control terminal electrically connected to the node SL (which is electrically connected to the first terminal of the transistor of the first leakage device Q1), a first terminal electrically connected to the second terminal of the second transistor Q4, and a second terminal electrically connected to the first terminal of the first transistor Q3. In addition, the second terminal of the second transistor Q4 and the first terminal of the third transistor Q5 are electrically connected to the node SR, and the node SR is electrically connected to the first terminal of the transistor of the second leakage device Q2. In other words, the output signal Z is the signal at the node SR. The fourth transistor Q6 and the fifth transistor Q7 are arranged to correspond to the second leakage device Q2, the fourth transistor Q6 having a control terminal electrically connected to the node SR (which is electrically connected to the first end of the transistor of the second leakage device Q2), a first end, and a second end configured to generate the corresponding output signal ZB; and the fifth transistor Q7 having a control terminal electrically connected to the node SR (which is electrically connected to the first end of the transistor of the second leakage device Q2), a first end electrically connected to the second end of the fourth transistor Q6, and a second end electrically connected to the first end of the first transistor Q3. In addition, the second end of the fourth transistor Q6 and the first end of the fifth transistor Q7 are electrically connected to the node SL, and the node SL is electrically connected to the first end of the transistor of the first leakage device Q1. In other words, the output signal ZB is the signal at the node SL.

[0104] In addition, if Figure 3 As shown, the L-PUF device 300 further includes a first switch S1 electrically connected to the second end of the second transistor Q4 to transmit the output signal Z as the first output signal BL when the first switch S1 is in an ON state, and includes a second switch S2 electrically connected to the second end of the fourth transistor Q6 to transmit the output signal ZB as the second output signal BLB when the second switch S2 is in an ON state. Both the first switch S1 and the second switch S2 can be controlled by another input signal WL, which is also an input signal of the pre-charge circuit 310.

[0105] In the L-PUF device 300 , the sense amplifier 330 can switch between the first state and the second state based on the voltage difference between the first leakage device Q1 and the second leakage device Q2 , and the voltage difference between the first leakage device Q1 and the second leakage device Q2 is determined by the leakage current of the first leakage device Q1 and the leakage current of the second leakage device Q2 .

[0106] Figure 4 Shown as Figure 3 The exemplary L-PUF device shown in FIG. 1 operates in the state where the output (BL, BLB) = (1, 0). Specifically, Figure 4 As shown, at the beginning of the operation process of the L-PUF device 300, the precharge circuit 310 receiving the input signal WL as its input starts the precharge process with the input signal WL at a low voltage level, and precharges the nodes SL and SR to a high voltage level. At the same time, the precharge transistor 110 of the self-timed readout driver 100 also receives the input signal PCH and is also precharged. At this time, the input signal SE of the sense amplifier 330 remains deactivated at a low voltage level.

[0107] Subsequently, the input signal WL is activated (i.e., at a high voltage level) to disable the precharge circuit 310. At the same time, the input signal PCH of the precharge transistor 110 allows the self-timed readout driver 100 to switch to the self-timed operation mode. Specifically, at the self-timed readout driver 100, the presence of N copies in the leakage device Q0 causes the leakage device Q0 to leak faster than the leakage devices Q1 and Q2 in the L-PUF device 300, thereby ensuring that the inverter 120 releases the SE signal faster. Then, the high-skew inverter 120 quickly responds to the voltage drop and pulls up the SE signal. At the L-PUF device 300, as the input signal WL is activated, the two switches S1 and S2 simultaneously become turned on, so that the nodes SL and SR are connected to the output terminals of the two switches S1 and S2, respectively, to generate the first output signal BL and the second output signal BLB. At the same time, as the two nodes SL and SR reach a high voltage level, the two leakage devices Q1 and Q2 start to work, and the leakage current of one of the two leakage devices Q1 and Q2 is greater than the leakage current of the other leakage device. Figure 4 As shown, the leakage current of the first leakage device Q1 is greater than the leakage current of the second leakage device Q2, and the voltage at the node SL connected to the first end of the transistor of the first leakage device Q1 will drop faster than the voltage at the node SR connected to the first end of the transistor of the second leakage device Q2. This difference in voltage drop is a result of the inherent variability of the manufacturing process, which makes it impossible to accurately replicate the same design from one chip to another. Once the voltage difference between the two leakage devices Q2 and Q1 exceeds a certain critical point (i.e., V diff ), the sense amplifier 330 is enabled and switched to the first state (ie, state 0), so that the two output signals (BL, BLB) are read as (1, 0).

[0108] Figure 5 Schematically showing a plurality of Figure 3 1 and 2. The L-PUF array 500 is formed of an exemplary L-PUF array of L-PUF devices shown in FIG. 1 . Specifically, the L-PUF array 500 has an array size of (M×N′) and includes M rows and N′ columns of L-PUF units 510. For example, the L-PUF array 500 may be a 64×32 array of 64 rows and 32 columns. Each L-PUF unit 510 includes Figure 3 In addition, each row of the L-PUF array has a control circuit 550 for controlling the input signal SE. Specifically, each control circuit 550 includes a corresponding Figure 1 The self-timed readout driver 100 shown generates a corresponding input signal SE. Each control circuit 550 also receives an input signal WL. For clarity, the M rows are labeled as rows. <0> To the line <m-1>, the corresponding input signals SE of the M rows are marked as SE <0> To SE <m-1>, and the corresponding input signals WL of the M rows are marked as WL <0> To WL <m-1>.

[0109] In addition, the L-PUF array includes (M×2) input signal lines 520 and 522 and (N′×2) output signal lines 530 and 532. The input signal lines 520 and 522 extend in the row direction, respectively, and the input signal lines 520 and 522 are electrically connected to the L-PUF units 510, respectively. Specifically, the (M×2) input signal lines include M first input lines 520 and M second input lines 522, the M first input lines 520 extend in the row direction and are electrically connected to the L-PUF units 510, respectively, and the M second input lines 522 extend in the row direction and are electrically connected to the L-PUF units 510, respectively. Each first input line 520 is used to transmit an input signal SE to a first corresponding group of the L-PUF units 510, and each second input line 522 is used to transmit an input signal WL to a first corresponding group of the L-PUF units 510. For example, in the first row <0> The corresponding first input line 520 is used to convert the input signal SE <0> The first row transmitted to the L-PUF unit 510 <0> , and the corresponding second input line 522 is used to convert the input signal WL <0> The first row transmitted to the L-PUF unit 510 <0> . Similarly, in row M <m-1>The corresponding first input line 520 is used to convert the input signal SE <m-1>Sent to the Mth row of L-PUF unit 510 <m-1>, and the corresponding second input line 522 is used to convert the input signal WL <m-1>Sent to the Mth row of L-PUF unit 510 <m-1>.like Figure 5 As shown, the first input lines 520 and the second input lines 522 are alternately arranged along the column direction.

[0110] The output signal lines 530 and 532 extend in the column direction, respectively, and the output signal lines 530 and 532 are electrically connected to the L-PUF unit 510, respectively. Specifically, the (N'×2) output signal lines include N' first output lines 530 and N' second output lines 532, the N' first output lines 530 extend in the column direction and are electrically connected to the L-PUF unit 510, respectively, and the N' second output lines 532 extend in the column direction and are electrically connected to the L-PUF unit 510, respectively. Each first output line 530 is used to transmit a first output signal BL from a second corresponding group of the L-PUF unit 510, and each second output line 532 is used to transmit a second output signal BLB from a second corresponding group of the L-PUF unit 510. For clarity, the N' columns are labeled as columns 530, 532, and 532. <0> To Column<N'-1> , the corresponding first output signals BL of the N' columns are marked as BL <0> To BL<N'-1> , and the corresponding second output signals BLB of the N' columns are marked as BLB <0> To BLB<N'-1> For example, in the first column <0> , the corresponding first output line 530 is used to transmit the first column from the L-PUF unit 510 <0> The output signal OUT <0> (ie, the first output signal BL <0> ), and the corresponding second output line 532 is used to transmit the first column from the L-PUF unit 510 <0> The output signal OUTB <0> (ie, the second output signal BLB <0> ). Similarly, in column N'<N'-1> The corresponding first output line 530 is used to transmit the N'th column from the L-PUF unit 510.<N'-1> The output signal OUT<N'-1> (ie, the first output signal BL<N'-1> ), and the corresponding second output line 532 is used to transmit the N'th column from the L-PUF unit 510<N'-1> The output signal OUTB<N'-1> (ie, the second output signal BLB<N'-1> ).like Figure 5 As shown, the first output lines 530 and the second output lines 532 are alternately arranged along the row direction. In addition, each of the first output lines 530 and the second output lines 532 is connected to a buffer B to avoid output load differences from peripheral circuits.

[0111] like Figure 5 As shown, input signal lines 520 and 522 extend in the row direction, and output signal lines 530 and 532 extend in the column direction. Alternatively, in some embodiments, the structure of the signal lines may be transverse, such that input signal lines 520 and 522 extend in the column direction, and output signal lines 530 and 532 extend in the row direction.

[0112] Figure 6 Schematically illustrates an exemplary L-PUF device according to another embodiment of the present invention. Specifically, Figure 6 The L-PUF device 600 shown is an L-PUF device with the sense amplifier removed from each device. In contrast, when the L-PUF device 600 is used in an L-PUF array, additional sense amplifiers are provided for corresponding groups of L-PUF units. Figure 6 As shown, the L-PUF device 600 includes a precharge circuit 610, two leakage devices 620 (Q1) and 625 (Q2), and two switches S1 and S2. For clarity, the two leakage devices 620 and 625 are referred to as the first leakage device Q1 and the second leakage device Q2. Figure 6 As shown, each of the first leakage device Q1 and the second leakage device Q2 includes a transistor. Specifically, the transistor of each leakage device Q1 and Q2 has a control terminal electrically connected to the ground, a first terminal electrically connected to the precharge circuit 610, and a second terminal electrically connected to the ground. In other words, for each of the first leakage device Q1 and the second leakage device Q2, the control terminal (i.e., the gate) and the second terminal (i.e., the source) are electrically connected to each other. Specifically, the first terminal of the transistor of the first leakage device Q1 is electrically connected to the node SL, which is electrically connected to the precharge circuit 610; and the first terminal of the transistor of the second leakage device Q2 is electrically connected to the node SR, which is electrically connected to the precharge circuit 610. The two switches include a first switch S1 electrically connected to the node SL (which is electrically connected to the first terminal of the transistor of the first leakage device Q1) to transmit the first intermediate output signal BL when the first switch S1 is in the on state, and include a second switch S2 electrically connected to the node SR (which is electrically connected to the first terminal of the transistor of the second leakage device Q2) to transmit the second intermediate output signal BLB when the second switch S2 is in the on state. In other words, the intermediate output signals BL and BLB of the L-PUF device 600 no longer form the data output of the sense amplifier (because the sense amplifier is removed from the L-PUF device 600). Instead, the sense amplifier can be shared by a group (e.g., a column) of L-PUF cells in the L-PUF array to reduce area and power consumption in the previous version, and the intermediate output signals BL and BLB of the L-PUF device 600 are used as inputs of the sense amplifier.

[0113] Figure 7 Schematically showing a plurality of Figure 6 1 and 2. The L-PUF array 700 is formed of an exemplary L-PUF array of L-PUF devices shown in FIG. 1 . Specifically, the L-PUF array 700 has an array size of (M×N′) and includes M rows and N′ columns of L-PUF units 710. For example, the L-PUF array 700 may be a 64×32 array of 64 rows and 32 columns. Each L-PUF unit 710 includes Figure 6 In addition, the L-PUF array 700 has N' sense amplifiers 740, each sense amplifier 740 is arranged to correspond to a column of L-PUF units 710. For clarity, Figure 5 Similar to the notation shown, the M rows are labeled as rows <0> To the line <m-1>, and the N' columns are labeled as columns <0> To Column<N'-1> .

[0114] In addition, the L-PUF array includes (M+1) input signal lines 720 and 722 and (N'×2) output signal lines 730 and 732. The input signal lines 720 and 722 extend in the row direction, respectively, and the input signal lines 720 and 722 are electrically connected to the L-PUF unit 710 accordingly. Specifically, the (M+1) input signal lines include a first input line 720 and M second input lines 722, the first input line 720 extends in the row direction and is electrically connected to the sense amplifier 740 accordingly, and the M second input lines 722 extend in the row direction and are electrically connected to the L-PUF unit 710 accordingly. The first input line 720 is used to transmit the input signal SE from the control circuit 750 to the sense amplifier 740. In other words, only one control circuit 750 and one first input line 720 may be required. The control circuit also includes the following: Figure 1 The self-timed readout driver 100 is shown to generate a corresponding input signal SE for the sense amplifier 740. On the other hand, each second input line 722 is used to transmit the input signal WL to the first corresponding group of L-PUF cells 710. For example, in the first row <0> The corresponding second input line 722 is used to convert the input signal WL <0> The first row transmitted to the L-PUF unit 710 <0> . Similarly, in row M <m-1>The corresponding second input line 722 is used to convert the input signal WL <m-1>Sent to the Mth row of L-PUF unit 710 <m-1>.

[0115] The output signal lines 730 and 732 extend in the column direction, respectively, and the output signal lines 730 and 732 are electrically connected to the L-PUF unit 710, respectively. Specifically, the (N'×2) output signal lines include N' first output lines 730 and N' second output lines 732, the N' first output lines 730 extend in the column direction and are electrically connected to the L-PUF unit 710, respectively, and the N' second output lines 732 extend in the column direction and are electrically connected to the L-PUF unit 710, respectively. Each first output line 730 is used to transmit the first intermediate output signal BL from the second corresponding group of the L-PUF unit 710 to the corresponding sense amplifier 740, and each second output line 732 is used to transmit the second intermediate output signal BLB from the second corresponding group of the L-PUF unit 710 to the corresponding sense amplifier 740. For example, in the first column <0> The corresponding first output line 730 is used to transmit the first column from the L-PUF unit 710 <0> The first intermediate output signal BL <0> Transfer to the same first column <0> The corresponding sense amplifier 740 in the L-PUF unit 710 and the corresponding second output line 732 are used to transmit the first column from the L-PUF unit 710 <0> The second intermediate output signal BLB <0> Transfer to the same first column <0> 740 in the corresponding sense amplifier. Similarly, in the N'th column<N'-1> The corresponding first output line 730 is used to transmit the N'th column from the L-PUF unit 710<N'-1> The first intermediate output signal BL<N'-1> Transfer to the same N'th column<N'-1> The corresponding sense amplifier 740 in the L-PUF unit 710 and the corresponding second output line 732 are used to transmit the N'th column from the L-PUF unit 710<N'-1> The second intermediate output signal BLB<N'-1> Transfer to the same N'th column<N'-1> The corresponding sense amplifier 740 in FIG. Figure 7 As shown, the first output lines 730 and the second output lines 732 are alternately arranged along the row direction.

[0116] The sense amplifier 740 in each column receives the corresponding first intermediate output signal BL and the corresponding second intermediate output signal BLB, and then amplifies the voltage difference generated by the two leakage devices and outputs a corresponding output signal. Figure 7 As shown, the first column <0> The sense amplifier 740 generates an output signal OUT <0> , and the N'th column<N'-1> The sense amplifier 740 generates an output signal OUT<N'-1> In addition, each sense amplifier 740 is connected to a buffer B to avoid output load differences from peripheral circuits.

[0117] Figure 8 Shown as Figure 7 The operation of the exemplary L-PUF array shown in FIG. Figure 8 In addition to the intermediate output signals BL and BLB being used as inputs to the sense amplifier, Figure 8 The operation shown is similar to Figure 4 As shown in the operation. Figure 8 As shown, at the beginning of the operation process of the L-PUF array 700, for a specific L-PUF unit 710, the precharge circuit 610 receiving the input signal WL as its input starts the precharge process with the input signal WL at a low voltage level, and precharges the nodes SL and SR to a high voltage level. At the same time, the precharge transistor 110 of the self-timed readout driver 100 also receives the input signal PCH and is also precharged. At this time, the input signal SE of the sense amplifier 740 remains deactivated at a low voltage level.

[0118] Subsequently, the input signal WL signal is activated (i.e., at a high voltage level) to disable the precharge circuit 610 of the L-PUF unit 710. At the same time, the input signal PCH of the precharge transistor 110 allows the self-timed readout driver 100 to switch to the self-timed operation mode. Specifically, at the self-timed readout driver 100, the presence of N copies in the leakage device Q0 causes the leakage device Q0 to leak faster than the leakage devices Q1 and Q2 in the L-PUF device 600 of the L-PUF unit 710, thereby ensuring that the inverter 120 releases the SE signal faster. Then, the high-skew inverter 120 quickly responds to the voltage drop and pulls up the SE signal. At the L-PUF device 600 of the L-PUF unit 710, as the input signal WL is activated, the two switches S1 and S2 of the L-PUF unit 710 simultaneously become turned on, so that the nodes SL and SR are respectively connected to the output terminals of the two switches S1 and S2 to output the first intermediate output signal BL and the second intermediate output signal BLB. At the same time, as the two nodes SL and SR reach a high voltage level, the two leakage devices Q1 and Q2 start to work, and the leakage current of one of the two leakage devices Q1 and Q2 is greater than the leakage current of the other leakage device. Figure 8 As shown, the leakage current of the first leakage device Q1 is greater than the leakage current of the second leakage device Q2, and the voltage at the node SL connected to the first end of the transistor of the first leakage device Q1 will drop faster than the voltage at the node SR connected to the first end of the transistor of the second leakage device Q2. This difference in voltage drop is a result of the inherent variability of the manufacturing process, which makes it impossible to accurately replicate the same design from one chip to another. Once the voltage difference between the two leakage devices Q2 and Q1 exceeds a certain critical point (i.e., V diff ), the intermediate output signals BL and BLB will be transmitted to the corresponding sense amplifier 740, so that the two output signals (OUT, OUTB) are read as (1, 0).

[0119] Fig. 9 Schematically shown in Figure 7 An example sense amplifier used in the example L-PUF array shown. Specifically, Fig. 9 The sense amplifier shown is a two-stage dynamic sense amplifier, which includes a first-stage preamplifier 910 and a second-stage latch 920. Each of the first-stage preamplifier 910 and the second-stage latch 920 is implemented by a plurality of transistors or diodes. The first-stage preamplifier 910 is used to provide a first-stage voltage equalization, thereby reducing the offset error from the second-stage latch 920, wherein the first intermediate output signal BL and the second intermediate output signal BLB are used as inputs of the first-stage preamplifier 910. The first-stage preamplifier 910 generates two voltages VL and VR, which are provided to the second-stage latch 920 to generate output signals VOP and VON. The output terminals of the second-stage latch 920 can be connected to buffers, respectively.

[0120] Return to reference Figure 7 , the input signal lines 720 and 722 extend in the row direction, and the output signal lines 730 and 732 extend in the column direction. Alternatively, in some embodiments, the structure of the signal lines may be transverse, such that the input signal lines 720 and 722 extend in the column direction, and the output signal lines 730 and 732 extend in the row direction.

[0121] In some embodiments, the system may be switched to a self-timed operation mode using the self-timed readout driver 100. After the input signal PCH / WL is enabled for a period of time, the self-timed readout driver 100 may be self-activated to generate the SE signal, thereby activating the sense amplifier in the L-PUF cell.

[0122] The foregoing description of example embodiments of the present invention has been presented for purposes of illustration and description only and is not intended to be exhaustive or to limit the invention to the precise form disclosed.Many modifications and variations are possible in light of the above teachings.

[0123] The embodiments are selected and described in order to illustrate the principles of the invention and its practical application, so as to enable other persons skilled in the art to utilize the invention and the various embodiments and to make various modifications suitable for the specific use contemplated. Alternative embodiments will become apparent to those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the foregoing description and the exemplary embodiments described therein.

Claims

1. A self-timed readout driver for a leak-based physically uncopyable function (L-PUF) device, the self-timed readout driver comprising: A pre-charge transistor having a control terminal, a first terminal and a second terminal; an inverter electrically connected to the second end of the pre-charge transistor; as well as a leakage device having a control terminal electrically connected to ground, a first terminal electrically connected to the second terminal of the pre-charge transistor, and a second terminal electrically connected to ground; The control terminal of the pre-charge transistor is configured to receive an input signal, and the inverter is configured to generate a sense enable (SE) signal. 2 . The self-timed readout driver of claim 1 , wherein the input signal and the sense enable signal are configured as two input signals of the leakage-based physically non-copyable functional device.

3. The self-timed readout driver of claim 1, wherein the leak-based physically non-copyable functional means comprises: a precharge circuit configured to receive the input signal; a first leakage device and a second leakage device, each electrically connected to the pre-charge circuit, wherein each of the first leakage device and the second leakage device comprises a transistor having a control terminal electrically connected to ground, a first terminal electrically connected to the pre-charge circuit, and a second terminal electrically connected to ground; as well as a sense amplifier electrically connected to the first end of the first leakage device and the first end of the second leakage device, wherein the sense amplifier is configured to receive the sense enable signal and generate a first output signal and a second output signal; wherein the sense amplifier is configured to switch between a first state and a second state based on a voltage difference between the first leakage device and the second leakage device, and the voltage difference between the first leakage device and the second leakage device is determined by a leakage current of the first leakage device and a leakage current of the second leakage device.

4. The self-timed readout driver of claim 3, wherein the leaking device is an N-times-repeated leaking device, and the N-times-repeated leaking device is configured to leak faster than the first leaking device and the second leaking device of the leak-based physically non-copyable functional device.

5. The self-timed readout driver of claim 3, wherein the sense amplifier comprises: a first transistor having a control terminal configured to receive the sense enable input signal, a first terminal, and a second terminal electrically connected to ground; a second transistor having a control terminal electrically connected to the first terminal of the transistor of the first leakage device, a first terminal, and a second terminal configured to generate the first output signal; a third transistor having a control terminal electrically connected to the first terminal of the transistor of the first leakage device, a first terminal electrically connected to the second terminal of the second transistor, and a second terminal electrically connected to the first terminal of the first transistor; a fourth transistor having a control terminal electrically connected to the first terminal of the transistor of the second leakage device, a first terminal, and a second terminal configured to generate the second output signal; as well as a fifth transistor having a control terminal electrically connected to the first terminal of the transistor of the second leakage device, a first terminal electrically connected to the second terminal of the fourth transistor, and a second terminal electrically connected to the first terminal of the first transistor; The second end of the second transistor and the first end of the third transistor are electrically connected to the first end of the transistor of the second leakage device, and the second end of the fourth transistor and the first end of the fifth transistor are electrically connected to the first end of the transistor of the first leakage device.

6. The self-timed readout driver of claim 5, wherein the leakage-based physically non-copyable function means further comprises: a first switch electrically connected to the second terminal of the second transistor; as well as A second switch is electrically connected to the second end of the fourth transistor.

7. The self-timed readout driver of claim 6, wherein the first switch and the second switch are controlled by the input signal, respectively.

8. A leak-based physically non-copyable functional array comprising: a plurality of leak-based physically non-copyable functional units in the form of an array, wherein each of said leak-based physically non-copyable functional units comprises a respective leak-based physically non-copyable functional device; a plurality of input signal lines extending along a first direction respectively and electrically connected to the leakage-based physically non-copyable functional units respectively, wherein each of the input signal lines is configured to transmit one of two input signals to a first corresponding group of the leakage-based physically non-copyable functional units; a plurality of output signal lines extending along a second direction respectively and electrically connected to the leakage-based physically non-copyable functional units respectively, wherein each of the output signal lines is configured to receive an output signal from a second corresponding group of the leakage-based physically non-copyable functional units; as well as a plurality of control circuits electrically connected to the input signal lines to provide the two input signals to the leakage-based physically non-copyable functional unit through the input signal lines; Wherein each of the control circuits comprises the self-timed readout driver as claimed in claim 3, and the input signal and the sense enable signal generated by the self-timed readout driver are configured as the two input signals of the leakage-based physically non-copyable functional unit.

9. The leakage-based physically non-copyable functional array of claim 8, wherein one of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction.

10. A security authentication device, comprising the leakage-based physically non-copyable function array as claimed in claim 8.

11. The security authentication device as described in claim 10, wherein the security authentication device is a security encryption key generating device.

12. The self-timed readout driver of claim 1, wherein the leak-based physically non-copyable functional means comprises: Pre-charging circuit; as well as a first leakage device and a second leakage device, each electrically connected to the pre-charge circuit, wherein each of the first leakage device and the second leakage device comprises a transistor having a control terminal electrically connected to ground, a first terminal electrically connected to the pre-charge circuit, and a second terminal electrically connected to ground; Wherein a first intermediate output signal is determined based on a dropped voltage of the first leakage device, and a second intermediate output signal is determined based on a dropped voltage of the second leakage device.

13. The self-timed readout driver of claim 12, wherein the leaking device is an N-times-repeated leaking device, and the N-times-repeated leaking device is configured to leak faster than the first leaking device and the second leaking device of the leak-based physically non-copyable functional device.

14. The self-timed readout driver of claim 12, wherein the leakage-based physically non-copyable function means further comprises: a first switch electrically connected to the first terminal of the transistor of the first leakage device; as well as a second switch electrically connected to the first terminal of the transistor of the second leakage device; The first switch is configured to transmit the first intermediate output signal when controlled to switch to an on state, and the second switch is configured to transmit the second intermediate output signal when controlled to switch to an on state.

15. A leak-based physically non-copyable functional array comprising: a plurality of leak-based physically non-copyable functional units in the form of an array, wherein each of said leak-based physically non-copyable functional units comprises a respective leak-based physically non-copyable functional device; A plurality of input signal lines respectively extending along a first direction and correspondingly electrically connected to the leakage-based physically non-copyable functional units; A plurality of output signal lines respectively extending along the second direction and correspondingly electrically connected to the leakage-based physically non-copyable functional units; a plurality of sense amplifiers electrically connected to one of the input signal line and the output signal line, respectively, wherein the input signal line is configured to transmit two input signals to the sense amplifier and the leakage-based physically non-copyable functional unit; as well as a control circuit electrically connected to the one of the input signal lines to provide one of the two input signals to the sense amplifier through the one of the input signal lines, wherein the control circuit includes the self-timed readout driver as described in claim 12, and the sense enable signal generated by the self-timed readout driver is configured to be transmitted to the one of the two input signals to the sense amplifier.

16. The leakage-based physically non-copyable functional array of claim 15 , wherein each of the sense amplifiers is configured to receive the first intermediate output signal and the second intermediate output signal transmitted by the second corresponding group of the leakage-based physically non-copyable functional units through the output signal line, and to generate an output signal based on the first intermediate output signal and the second intermediate output signal.

17. The leakage-based physically non-copyable functional array of claim 15, wherein one of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction.

18. The leakage-based physically non-copyable functional array of claim 15, wherein each of the sense amplifiers comprises: First stage preamplifier; as well as Second level latch.

19. A security authentication device, comprising the leakage-based physically non-copyable function array as claimed in claim 15.

20. The security authentication device as claimed in claim 19, wherein the security authentication device is a security encryption key generating device.

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