Fault isolation processing method and device for vehicle gauge chip function safety system

Abstract

The invention provides a fault isolation processing method, device and equipment for a vehicle gauge chip function safety system and a medium, and the method comprises the steps: determining a fault node needing to be isolated based on a circuit topology structure of a chip in a simulation process; based on the fault node needing to be isolated, constructing an isolation module capable of replacing the fault module corresponding to the fault node needing to be isolated; constructing a binding relation between the isolation module and a circuit structure of the chip; and in the simulation process of the chip, mapping a fault injection signal of the fault module to the isolation module based on the binding relationship to complete fault simulation of the chip. According to the method, the verilog source code of the chip does not need to be damaged, the reliability of the circuit structure is not damaged, the simulation speed is high, the reliability is high, and the fault isolation function required by the industry can be met in large-scale fault simulation.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a fault isolation processing method, device, equipment and medium for a functional safety system of an automotive chip. Background Art

[0002] When developing chips, fault injection is used at the simulation level to evaluate safety mechanisms. This requires a lot of time to simulate the behavior of the faulty module in specific hardware. At the same time, safety assessments can often only be performed after the chip is completed, which greatly increases the cost of assessment. Therefore, fault injection at the simulation level has become the most mainstream fault injection method in the industry.

[0003] Simulation-level fault injection technology can be divided into destructive (instrument) and non-destructive (non-instrument) fault injection. The main difference between the two is whether destructive changes are made to the source code of the circuit module used for fault simulation. Non-destructive fault injection technology has become a popular choice due to its faster simulation speed and more reliable fault injection model, but its feature of not destroying the source code makes it difficult to meet the fault isolation function required by the industry (fault isolation is the process of effectively isolating the faulty part from the rest of the system in a computer system or network to ensure system stability and security). This is because the built-in mechanism of the Verilog language will perform certain port folding optimizations during simulation, resulting in two different node variables actually sharing the same value when externally assigned. In circuit simulation, this is manifested as the impact of the fault being reversed, which is contrary to the circuit propagation mode required by industrial standards. The industry believes that the fault transmission behavior of an actual chip will not propagate backward to its driver side, but only backward in the forward direction. However, due to the method characteristics of non-destructive fault injection technology that does not change the source code, the simulator often folds and optimizes the ports that will propagate backward after compilation, and the assignment operation during simulation cannot isolate the impact of the fault. Destructive fault injection technology often introduces a large number of circuit structures to simulate the fault behavior of the circuit. Although fault isolation can be achieved by inserting buffs in this process, the significant reduction in simulation speed and the reliability of the circuit after changing the source code are disadvantages that cannot be ignored.

[0004] SUMMARY OF THE INVENTION

[0005] In view of the problems existing in the prior art, the present invention provides a fault isolation processing method, device, equipment and medium for a functional safety system of an automotive chip.

[0006] The present invention provides a fault isolation processing method for a functional safety system of an automotive chip, comprising: Based on the circuit topology of the chip during simulation, determine the faulty nodes that need to be isolated; Based on the faulty node to be isolated, construct an isolation module capable of replacing the faulty module corresponding to the faulty node to be isolated; Establishing a binding relationship between the isolation module and the circuit structure of the chip; During the simulation of the chip, based on the binding relationship, the fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip.

[0007] According to a fault isolation processing method for a functional safety system of an automotive chip provided by the present invention, the fault node to be isolated is determined based on the circuit topology of the chip during the simulation process, including: Use the VPI interface to automatically analyze the circuit topology and identify all potential reverse-propagation fault nodes; By iterative traversal, the connection relationship between the ports of the faulty modules corresponding to all potential reverse propagation faulty nodes is obtained from top to bottom to obtain a connection relationship set; According to the port folding mechanism of the Verilog language and the connection relationship set, the faulty nodes to be isolated are screened out from all potential reverse-propagation faulty nodes.

[0008] According to a fault isolation processing method for a functional safety system of an automotive chip provided by the present invention, based on the fault node to be isolated, an isolation module capable of replacing a fault module corresponding to the fault node to be isolated is constructed, comprising: Analyze the input and output of the fault module corresponding to the faulty node to be isolated; Obtain the instantiation parameters of the fault module corresponding to the faulty node to be isolated; The isolation module is constructed based on the instantiation parameters, inputs and outputs of the fault module.

[0009] According to a fault isolation processing method for a functional safety system of an automotive chip provided by the present invention, the binding relationship between the isolation module and the circuit structure of the chip is constructed, including: The isolation module is externally written using the bind syntax of SystemVerilog, and is bound to the circuit structure of the chip. The output of the fault module in the circuit structure of the chip is changed to the output of the isolation module through the VPI internal assignment method.

[0010] According to a fault isolation processing method for a functional safety system of an automotive chip provided by the present invention, based on the binding relationship, the fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip, including: Build packaging files for each isolation module and attach them to the simulator compilation simulation link in the form of SystemVerilog files. When injecting faults into fault modules that need to be isolated, map the fault injection signals to the isolation modules with the same functions corresponding to the fault modules to complete the fault simulation of the chip.

[0011] According to a fault isolation processing method for a functional safety system of an automotive chip provided by the present invention, the fault nodes to be isolated are screened out from all potential reverse propagation fault nodes according to the port folding mechanism of the Verilog language and the connection relationship set, including: Based on the port folding mechanism of the Verilog language, all port handles in the connection relationship set are accessed, and when it is determined that the types of the two variables connected inside and outside the port are both wire-type variables, the fault node corresponding to the fault module where the port is located is the fault node that needs to be isolated.

[0012] According to a fault isolation processing method for a functional safety system of an automotive chip provided by the present invention, the instantiation parameters of a fault module corresponding to a fault node to be isolated are obtained, including: Use VPI to access the handle of the instantiation example of the faulty module and obtain the instantiation parameters of the faulty module.

[0013] The present invention also provides a fault isolation processing device for a functional safety system of an automotive chip, comprising: A screening module is used to determine the faulty nodes that need to be isolated based on the circuit topology of the chip during simulation; A construction module, used for constructing an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated; An association module, used to establish a binding relationship between the isolation module and the circuit structure of the chip; The processing module is used to map the fault injection signal of the fault module to the isolation module based on the binding relationship during the simulation process of the chip, so as to complete the fault simulation of the chip.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a fault isolation processing method for a functional safety system of an automotive chip as described above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements a fault isolation processing method for any of the above-mentioned automotive chip functional safety systems.

[0016] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements a fault isolation processing method for any of the above-mentioned automotive chip functional safety systems.

[0017] The present invention provides a fault isolation processing method, device, equipment and medium for a functional safety system of an automotive chip. Based on the fault node to be isolated, an isolation module capable of replacing the fault module corresponding to the fault node to be isolated is constructed, and a binding relationship between the isolation module and the circuit structure of the chip is constructed. During the simulation process of the chip, based on the binding relationship, the fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip, thereby achieving the goal of not needing to destroy the Verilog source code of the chip and not destroying the reliability of the circuit structure. The simulation speed is fast and the reliability is high, and the fault isolation function required by the industry can be met in large-scale fault simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of the fault isolation processing method of the automotive chip functional safety system provided by the present invention.

[0020] Figure 2 It is a structural schematic diagram of a fault isolation processing device for a functional safety system of a vehicle-grade chip provided by the present invention; Figure 3 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Combine the following Figure 1-Figure 3 The present invention describes the fault isolation processing method, device, equipment and medium of the automotive chip functional safety system.

[0023] Figure 1A schematic diagram showing a flow chart of a fault isolation processing method for a functional safety system of a vehicle-grade chip provided by the present invention is shown in FIG. Figure 1 , the method comprises the following steps: Step 11: Based on the circuit topology of the chip during the simulation process, determine the faulty node that needs to be isolated.

[0024] Step 12: Based on the faulty node to be isolated, construct an isolation module capable of replacing the faulty module corresponding to the faulty node to be isolated.

[0025] Step 13: Establish a binding relationship between the isolation module and the circuit structure of the chip.

[0026] Step 14: During the simulation of the chip, based on the binding relationship, the fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip.

[0027] Regarding the above steps 11 to 14, it should be noted that the functional safety system of automotive chips is designed to ensure that the chips can safely and reliably perform their intended functions throughout their life cycle through a series of technical and management means, avoiding safety hazards caused by systematic failures or random hardware failures. With the improvement of automobile electronics and intelligence, the use of automotive chips has increased significantly, and their safety is directly related to the life safety of drivers, passengers and pedestrians. Therefore, it is crucial to ensure the functional safety of chips.

[0028] When developing chips, fault injection is used at the simulation level to evaluate safety mechanisms. This requires a lot of time to simulate the behavior of the faulty module in specific hardware. At the same time, safety assessments can often only be performed after the chip is completed, which greatly increases the cost of assessment. Therefore, fault injection at the simulation level has become the most mainstream fault injection method in the industry.

[0029] Simulation-level fault injection technology can be divided into destructive (instrument) and non-destructive (non-instrument) fault injection. The main difference between the two is whether destructive changes are made to the source code of the circuit module used for fault simulation. Non-destructive fault injection technology has become a popular choice due to its faster simulation speed and more reliable fault injection model, but its feature of not destroying the source code makes it difficult to meet the fault isolation function required by the industry (fault isolation is the process of effectively isolating the faulty part from the rest of the system in a computer system or network to ensure system stability and security). This is because the built-in mechanism of the Verilog language will perform certain port folding optimizations during simulation, resulting in two different node variables actually sharing the same value when externally assigned. In circuit simulation, this is manifested as the impact of the fault being reversed, which is contrary to the circuit propagation mode required by industrial standards. The industry believes that the fault transmission behavior of an actual chip will not propagate backward to its driver side, but only backward in the forward direction. However, due to the method characteristics of non-destructive fault injection technology that does not change the source code, the simulator often folds and optimizes the ports that will propagate backward after compilation, and the assignment operation during simulation cannot isolate the impact of the fault. Destructive fault injection technology often introduces a large number of circuit structures to simulate the fault behavior of the circuit. Although fault isolation can be achieved by inserting buffs in this process, the significant reduction in simulation speed and the reliability of the circuit after changing the source code are disadvantages that cannot be ignored.

[0030] To this end, the present invention aims to insert an isolation module into the target circuit by incrementally adding circuits, which not only avoids damage to the original circuit structure, but also realizes the fault isolation requirements during simulation. To this end, firstly, based on the circuit topology of the chip during the simulation process, the fault node to be isolated is determined. It should be noted that the circuit structure of the chip includes multiple functional modules, and the chip failure can occur at the port position of the module or inside the module.

[0031] Here, it should also be noted that the simulation safety detection of the chip requires modeling of the circuit structure of the chip, that is, executing it in the simulator through the code file to achieve the simulation execution of the chip circuit structure. To this end, the screening of faulty nodes can be done by screening code segments in the code file that represents the circuit module on the chip.

[0032] In the present invention, the failure of the module can be monitored on some fault nodes. Thus, there is a corresponding relationship between the module and the fault node. Therefore, after screening out the fault nodes to be isolated, the fault module corresponding to the fault node to be isolated in the circuit structure of the chip can be determined. From the design idea of ​​inserting the isolation module into the original circuit by incremental additional circuit mode, an isolation module that can replace the fault module corresponding to the fault node to be isolated can be constructed at this time. Here, the isolation module is through the bind syntax, and a module can be written externally without changing the source code to bind to the inside of the fault module in the circuit for safety simulation detection. Therefore, it is necessary to construct a binding relationship between the isolation module and the circuit structure of the chip, and based on the binding relationship, the isolation module has the same circuit structure as the original module and has an isolation function. The built-in mechanism port folding of Verilog will not occur, and fault injection in the isolation module avoids the reverse propagation behavior of the fault. It can be obtained that in the simulation process of the chip, based on the binding relationship, the fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip.

[0033] In a further method of the above method, the process of determining the faulty node to be isolated based on the circuit topology of the chip during the simulation is mainly explained as follows: The VPI interface is used to automatically analyze the circuit topology and identify all potential reverse-propagation fault nodes.

[0034] By iterative traversal, the connection relationship between the ports of the faulty modules corresponding to all potential reverse propagation faulty nodes is obtained from top to bottom to obtain a connection relationship set.

[0035] According to the port folding mechanism and connection relationship set of the Verilog language, the fault nodes to be isolated are screened out from all potential reverse propagation fault nodes.

[0036] In this regard, it should be noted that in the present invention, for fault injection simulation, in order to achieve the fault isolation function, the system must first be able to automatically analyze and screen out which fault points will cause the reverse propagation of the fault. In the present invention, it is necessary to use the VPI interface (Verilog programming language interface) to write an algorithm to automatically analyze the circuit topology structure in the simulation and screen out all fault nodes where the fault may be reverse propagated. Among them, the routine provided by VPI can be used by external algorithms to access the connection relationship between each port of the circuit module. That is, through iterative traversal, the connection relationship between the ports of the fault modules corresponding to all potential reverse propagation fault nodes is obtained from top to bottom, and a connection relationship set is obtained, which is stored in the linked list structure of the library function for easy screening and analysis later.

[0037] Then, according to the port folding mechanism and connection relationship set of the Verilog language, the faulty nodes to be isolated are screened out from all potential reverse propagation faulty nodes.

[0038] When the signal variables on both sides of the Verilog port are wire-type variables, Verilog will fold the variables on both sides of the port. During simulation, the variables that actually participate in the simulation are only the main variables during folding, and the values ​​of the folded secondary variables cannot be different from the values ​​of the main variables. Therefore, based on the port folding mechanism of the Verilog language, all port handles in the connection relationship set are accessed, and the variable types on both sides of the module ports are screened. If the variables on both sides are wire-type variables, the port will have a reverse propagation of the fault during the simulation process, and this type of port will be saved in a new linked list. That is, the fault node corresponding to the faulty module where the port is located is the faulty node that needs to be isolated.

[0039] In a further method of the above method, the processing of constructing an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated is mainly explained as follows: Analyze the input and output of the faulty module corresponding to the faulty node to be isolated.

[0040] Get the instantiation parameters of the fault module corresponding to the faulty node to be isolated.

[0041] Build isolation modules based on the instantiation parameters, inputs, and outputs of the faulty module

[0042] In this regard, it should be noted that in the present invention, all fault ports that need to be isolated have been obtained by automatically analyzing the circuit structure, but in fact, the most important part is to isolate the impact of these reverse transmissions. The reason why the fault propagates backwards at the module port is due to the port folding mechanism of Verilog itself. Therefore, for the simulation platform, the two folded variables actually share the same handle. They are essentially the same variable, which also shows that it is impossible to assign different values ​​to the values ​​of the two variables through other assignment methods after compilation. Therefore, the present invention needs to use the bind syntax combined with the VPI library function algorithm without changing the Veilog circuit source code to alternatively realize the fault isolation function.

[0043] The previously obtained port set that needs to be isolated is processed and traversed, and the faulty module in which it is located is analyzed using the VPI library function, and all inputs and outputs in the faulty module are traversed.

[0044] In addition, parameters of the isolated module must be transferred. In order to ensure that the behavior of the isolated module is completely consistent with that of the original module, the input and output of the module and the instantiation parameters should be consistent with those of the faulty module in the original circuit. Therefore, VPI is used to access the handle of the instantiation example of the faulty module to obtain the instantiation parameters of the faulty module.

[0045] Based on the instantiation parameters, inputs and outputs of the fault module, the parameters, inputs and outputs are passed through the script to package the corresponding isolation module. The isolation module has the same circuit structure as the original module and packages the isolation function. By wrapping a layer of ports defined by logic, the built-in mechanism of Verilog, port folding, does not occur. Fault injection in the module avoids the reverse propagation of faults.

[0046] In a further method of the above method, the processing of building a binding relationship between the isolation module and the circuit structure of the chip is mainly explained, as follows: The isolation module is written externally using the bind syntax of SystemVerilog, bound to the circuit structure of the chip, and the output of the fault module in the circuit structure of the chip is changed to the output of the isolation module through the VPI internal assignment method.

[0047] In this regard, it should be noted that in the present invention, after obtaining all the isolation instantiation modules, these modules need to be bound to the original circuit structure to replace the original non-isolated function modules with modules that can be isolated and automatically generated by the algorithm.

[0048] In the present invention, SystemVerilog provides a bind syntax to facilitate verification engineers to perform some additional functions on the original circuit without changing the source code, such as assertion coverage statistics, etc. This syntax can bind the externally written module to the circuit module for simulation without changing the source code. Therefore, with the help of the bind syntax, the isolation module is externally written, the isolation module is bound to the circuit structure of the chip, and the output of the fault module in the circuit structure of the chip is changed to the output of the isolation module through the VPI internal assignment method.

[0049] In a further method of the above method, the processing of mapping the fault injection signal of the fault module to the isolation module based on the binding relationship to complete the fault simulation of the chip is explained as follows: Build packaging files for each isolation module and attach them to the simulator compilation simulation link in the form of SystemVerilog files. When injecting faults into fault modules that need to be isolated, map the fault injection signals to the isolation modules with the same functions corresponding to the fault modules to complete the fault simulation of the chip.

[0050] In this regard, it should be noted that in the present invention, the algorithm automatically analyzes the circuit structure, automatically generates a packaging file for the isolation module set, attaches it to the simulator compilation simulation link in the form of a SystemVerilog file, and automatically implements the mapping of isolation points in the algorithm. When fault injection is performed on a faulty module that needs to be isolated, the fault injection point is automatically mapped to its corresponding isolation module with the same function. Fault injection on the faulty node of the isolation module will not cause reverse propagation. At the same time, the forward fault impact is consistent with the original circuit, thereby realizing the fault isolation function.

[0051] The present invention provides a fault isolation processing method for a functional safety system of an automotive chip. Based on the fault nodes to be isolated, an isolation module capable of replacing the fault module corresponding to the fault nodes to be isolated is constructed, and a binding relationship between the isolation module and the circuit structure of the chip is constructed. During the simulation process of the chip, based on the binding relationship, a fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip, thereby achieving the goal of not destroying the Verilog source code of the chip and not destroying the reliability of the circuit structure. The method has fast simulation speed and high reliability, and can meet the fault isolation function required by the industry in large-scale fault simulation.

[0052] The fault isolation processing device for the automotive chip functional safety system provided by the present invention is described below. The fault isolation processing device for the automotive chip functional safety system described below and the fault isolation processing method for the automotive chip functional safety system described above can be referenced to each other.

[0053] Figure 2 A schematic diagram of the structure of a fault isolation processing device for a functional safety system of a vehicle-grade chip provided by the present invention is shown. Figure 2 The device comprises a screening module 21, a construction module 22, an association module 23 and a processing module 23, wherein: A screening module 21 is used to determine the faulty nodes that need to be isolated based on the circuit topology of the chip during the simulation process; A construction module 22, configured to construct, based on the faulty node to be isolated, an isolation module capable of replacing a faulty module corresponding to the faulty node to be isolated; An association module 23, used to establish a binding relationship between the isolation module and the circuit structure of the chip; The processing module 24 is used to map the fault injection signal of the fault module to the isolation module based on the binding relationship during the chip simulation process to complete the fault simulation of the chip.

[0054] Since the principle of the device of the embodiment of the present invention is the same as that of the method of the above embodiment, a more detailed explanation is omitted here.

[0055] It should be noted that, in the embodiments of the present invention, relevant functional modules may be implemented by a hardware processor.

[0056] The present invention provides a fault isolation processing device for a functional safety system of an automotive chip. An isolation module capable of replacing a fault module corresponding to a fault node to be isolated is constructed based on a fault node to be isolated, and a binding relationship between the isolation module and a circuit structure of the chip is constructed. During the simulation process of the chip, a fault injection signal of the fault module is mapped to the isolation module based on the binding relationship, and the fault simulation of the chip is completed, so that the Verilog source code of the chip does not need to be destroyed, and the reliability of the circuit structure will not be destroyed. The device has fast simulation speed and high reliability, and can meet the fault isolation function required by the industry in large-scale fault simulation.

[0057] Figure 3 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 3 As shown, the electronic device may include: a processor 31, a communication interface 32, a memory 33 and a communication bus 34, wherein the processor 31, the communication interface 32 and the memory 33 communicate with each other through the communication bus 34. The processor 31 may call the logic instructions in the memory 33 to execute a fault isolation processing method for a functional safety system of a vehicle-grade chip, the method comprising: determining a fault node to be isolated based on the circuit topology of the chip during the simulation process; constructing an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated; constructing a binding relationship between the isolation module and the circuit structure of the chip; in the simulation process of the chip, based on the binding relationship, mapping the fault injection signal of the fault module to the isolation module to complete the fault simulation of the chip.

[0058] In addition, the logic instructions in the above-mentioned memory 33 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0059] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the fault isolation processing method for the functional safety system of a vehicle-grade chip provided by the above-mentioned methods. The method includes: determining the fault node to be isolated based on the circuit topology structure of the chip during the simulation process; based on the fault node to be isolated, constructing an isolation module that can replace the fault module corresponding to the fault node to be isolated; constructing a binding relationship between the isolation module and the circuit structure of the chip; during the simulation process of the chip, based on the binding relationship, mapping the fault injection signal of the fault module to the isolation module to complete the fault simulation of the chip.

[0060] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the fault isolation processing method for the functional safety system of a vehicle-grade chip provided by the above-mentioned methods. The method includes: determining the fault node to be isolated based on the circuit topology structure of the chip during the simulation process; based on the fault node to be isolated, constructing an isolation module that can replace the fault module corresponding to the fault node to be isolated; constructing a binding relationship between the isolation module and the circuit structure of the chip; during the simulation process of the chip, based on the binding relationship, mapping the fault injection signal of the fault module to the isolation module to complete the fault simulation of the chip.

[0061] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0062] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fault isolation processing method for a functional safety system of an automotive chip, characterized in that: include: Based on the circuit topology of the chip during simulation, determine the faulty nodes that need to be isolated; Based on the faulty node to be isolated, construct an isolation module capable of replacing the faulty module corresponding to the faulty node to be isolated; Establishing a binding relationship between the isolation module and the circuit structure of the chip; During the simulation of the chip, based on the binding relationship, the fault injection signal of the fault module is mapped to the isolation module to complete the fault simulation of the chip.

2. The fault isolation processing method for the functional safety system of automotive chip according to claim 1 is characterized in that: The determining of the faulty node to be isolated based on the circuit topology of the chip during the simulation process includes: Use the VPI interface to automatically analyze the circuit topology and identify all potential reverse-propagation fault nodes; By iterative traversal, the connection relationship between the ports of the faulty modules corresponding to all potential reverse propagation faulty nodes is obtained from top to bottom to obtain a connection relationship set; According to the port folding mechanism of the Verilog language and the connection relationship set, the faulty nodes to be isolated are screened out from all potential reverse-propagation faulty nodes.

3. The fault isolation processing method for the functional safety system of a vehicle-grade chip according to claim 1 or 2 is characterized in that: The method of constructing an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated includes: Analyze the input and output of the fault module corresponding to the faulty node to be isolated; Obtain the instantiation parameters of the fault module corresponding to the faulty node to be isolated; The isolation module is constructed based on the instantiation parameters, inputs and outputs of the fault module.

4. The fault isolation processing method for the functional safety system of a vehicle-grade chip according to claim 3 is characterized in that: The step of constructing a binding relationship between the isolation module and the circuit structure of the chip includes: The isolation module is externally written using the bind syntax of SystemVerilog, and is bound to the circuit structure of the chip. The output of the fault module in the circuit structure of the chip is changed to the output of the isolation module through the VPI internal assignment method.

5. The fault isolation processing method for the functional safety system of a vehicle-grade chip according to claim 4 is characterized in that: The step of mapping the fault injection signal of the fault module to the isolation module based on the binding relationship to complete the fault simulation of the chip includes: Build packaging files for each isolation module and attach them to the simulator compilation simulation link in the form of SystemVerilog files. When injecting faults into fault modules that need to be isolated, map the fault injection signals to the isolation modules with the same functions corresponding to the fault modules to complete the fault simulation of the chip.

6. The fault isolation processing method for the functional safety system of a vehicle-grade chip according to claim 2 is characterized in that: The method of screening out the faulty nodes to be isolated from all potential reverse propagation faulty nodes according to the port folding mechanism of the Verilog language and the connection relationship set includes: Based on the port folding mechanism of the Verilog language, all port handles in the connection relationship set are accessed, and when it is determined that the types of the two variables connected inside and outside the port are both wire-type variables, the fault node corresponding to the fault module where the port is located is the fault node that needs to be isolated.

7. The fault isolation processing method for the functional safety system of a vehicle-grade chip according to claim 3 is characterized in that: The obtaining of instantiation parameters of the fault module corresponding to the faulty node to be isolated includes: Use VPI to access the handle of the instantiation example of the faulty module and obtain the instantiation parameters of the faulty module.

8. A fault isolation processing device for a functional safety system of an automotive chip, characterized in that: include: A screening module is used to determine the faulty nodes that need to be isolated based on the circuit topology of the chip during simulation; A construction module, used for constructing an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated; An association module, used to establish a binding relationship between the isolation module and the circuit structure of the chip; The processing module is used to map the fault injection signal of the fault module to the isolation module based on the binding relationship during the simulation process of the chip, so as to complete the fault simulation of the chip.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, it implements the fault isolation processing method of the automotive chip functional safety system as described in any one of claims 1-7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the fault isolation processing method of the automotive chip functional safety system as described in any one of claims 1-7.

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