Low-delay high-bandwidth 2D-mesh FPGA chip array and construction method thereof
By introducing switched FPGA nodes into the 2D-mesh FPGA array and adopting fixed-length Ethernet protocol and virtual channel VC technology, the problems of large delay and limited bandwidth in the array are solved, and a low delay and high bandwidth FPGA chip array is realized. Improves the reliability and scalability of the system.
Patent Information
- Application Number
- CN202411457327.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-14
AI Technical Summary
The FPGA array composed of existing 2D-mesh structures has the disadvantages of large delays, limited point-to-point bandwidth, related delays to network scale, complex network connections, and poor reliability.
The switching FPGA node is introduced to convert indirect fiber connections into on-chip connections, adopting fixed-length Ethernet protocol and on-chip fixed-length routing and switching based on Cell, and adopting virtual channel VC technology and credit-based flow control mechanism.
It reduces latency overhead and resource usage, improves bandwidth and latency performance, reduces the probability of network congestion, ensures delay jitter in a small range, and improves system reliability and scalability.
Smart Images
Figure CN119443004A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of FPGA architecture design and optimization, and in particular relates to a low-latency and high-bandwidth 2D-mesh FPGA chip array and a construction method thereof. Background Art
[0002] With the rapid development of applications such as neural networks and machine learning, there is a huge demand for computing power. However, in the construction of computing power systems, as Dennard scaling and Moore's Law gradually become invalid, the contribution of chip manufacturing process technology to single-chip computing performance is no longer significant. In order to solve the contradiction between the serious mismatch between the computing power demand of large applications and the computing power supply of single chips, building distributed heterogeneous computing clusters has become the main way to improve the computing power of the system. The processors generally used as heterogeneous hardware accelerators are usually CPU, GPU, FPGA, NPU, etc. Among them, from the perspective of programming flexibility and performance, CPU has the best programming flexibility, while ASIC-based NPU can play the best performance, while FPGA and GPU are different trade-offs between performance and programming convenience. Since ASIC design requires a long cycle, it may not be able to meet the needs after the ASIC tape-out is completed, so a configurable accelerator needs to be designed. Due to its structural characteristics, FPGA is very suitable for computing scenarios where the hardware structure needs to change dynamically and has relatively high energy efficiency requirements. For this reason, FPGA systems or FPGA arrays are often used for heterogeneous computing acceleration.
[0003] At present, FPGA systems or arrays are under construction. Generally, FPGA arrays are composed of multiple FPGA subsystems. Each FPGA subsystem has resources such as FPGA, Mem, and high-speed IO. Each FPGA subsystem is interconnected through optical fiber. Due to the maturity of Ethernet technology, most FPGAs have Ethernet endpoints integrated inside. Therefore, each interconnected FPGA is generally interconnected through Ethernet protocol using optical fiber as a carrier. The interconnection topology is generally a switching topology or a 2D-mesh structure. This solution is mainly optimized for FPGA arrays composed of 2D-mesh structures.
[0004] For FPGA arrays composed of 2D-mesh structures, each FPGA node has at least 4 Ethernet interfaces, and the FPGA nodes are connected to form a mesh structure in two dimensions through optical fiber Ethernet interfaces. Under the requirements of computing applications, the FPGA arrays with 2D-mesh structures between chips have disadvantages such as large latency, limited point-to-point bandwidth, latency related to network scale, complex network connections, and poor reliability. Summary of the invention
[0005] In order to overcome the above-mentioned shortcomings or deficiencies of the prior art, the present invention provides a low-latency and high-bandwidth 2D-mesh FPGA chip array and a construction method thereof.
[0006] The object of the present invention is achieved through the following technical solutions: In the first aspect, a method for constructing a 2D-mesh FPGA chip array with low latency and high bandwidth comprises:
[0007] A type of switching node is added, which is composed of FPGA and is called a switching FPGA; the switching FPGA is connected to several computing FPGAs; and the switching FPGA implements 2D-mesh-based interconnection and switching.
[0008] Furthermore, the switching FPGA and the computing FPGA are interconnected via optical fiber.
[0009] Furthermore, it also includes: the switching FPGAs are interconnected.
[0010] Furthermore, a fixed-length Ethernet protocol is used between the computing FPGA and the switching FPGA; a fixed-length packet is the shortest Ethernet frame of 64B; and fixed-length encapsulation of data is completed by the computing FPGA.
[0011] Furthermore, the switching FPGA is implemented by using Cell-based on-chip bus fixed-length routing and switching.
[0012] Furthermore, the entire network adopts virtual channel VC technology and uses a credit-based flow control mechanism.
[0013] In a second aspect, the present invention also provides a low-latency and high-bandwidth 2D-mesh FPGA chip array, including a switching FPGA and several computing FPGAs; the switching FPGA is connected to several computing FPGAs; the switching FPGA is composed of several FPGAs to achieve 2D-mesh-based interconnection and switching.
[0014] Furthermore, the switching FPGA and the computing FPGA are interconnected via optical fiber.
[0015] Furthermore, it also includes a plurality of switching FPGAs, and the switching FPGAs are interconnected.
[0016] Furthermore, a fixed-length Ethernet protocol is used between the computing FPGA and the switching FPGA; a fixed-length packet is the shortest Ethernet frame of 64B; and fixed-length encapsulation of data is completed by the computing FPGA.
[0017] Furthermore, the switching FPGA is implemented by using Cell-based on-chip bus fixed-length routing and switching.
[0018] Furthermore, the entire network adopts virtual channel VC technology and uses a credit-based flow control mechanism.
[0019] Compared with the prior art, the present invention has the following beneficial effects:
[0020] 1) The logical interconnection structure remains unchanged
[0021] Logically, each computing FPGA is still interconnected by a 2D-mesh structure.
[0022] 2) Low latency
[0023] By converting indirect fiber connections into on-chip connections, repeated Ethernet protocol stack encapsulation and caching for inter-chip transmission is avoided, reducing latency overhead and resource usage.
[0024] The bandwidth and latency performance on a chip are generally an order of magnitude higher than those between chips. Therefore, when the traffic load is large, it can also provide the entire network with an interconnection bandwidth far exceeding the interface and better forwarding latency, greatly reducing the probability of congestion in the entire network and ensuring that latency jitter is within a smaller range.
[0025] 3) High bandwidth
[0026] The point-to-point bandwidth between any two computing FPGAs is equal to the access bandwidth of the computing node FPGA, and there will be no access bandwidth convergence problem.
[0027] 4) Easy to implement and expand
[0028] The use of fixed-length packet transmission and switching increases the PPS (packets per second) of the entire network, while the functional logic of the switching FPGA is simple and clear and easy to implement. In addition, the use of a fixed-length short packet mechanism reduces the demand for cache resources, making it easier to integrate larger-scale switching functions on a single chip.
[0029] Due to the good scalability of 2D-mesh, when the delay budget is met, the switching FPGA also has good scalability.
[0030] 5) Simple networking
[0031] This solution is still based on the 2D-mesh structure in terms of logic, but at the system level, the interconnection topology between chips forms a formal point-to-point star interconnection topology, with simple wiring logic and no mutual constraints between ports.
[0032] 6) High reliability
[0033] On the one hand, since the inter-chip optical interconnection is mapped to the internal interconnection of the chip, it is equivalent to exchanging the reliability of the PCB between chips for the reliability of the consistent semiconductor process, thus improving the reliability of the entire system. On the other hand, since the optical interconnection endpoints are greatly reduced, the low energy efficiency and failure probability of photoelectric conversion are avoided, which improves the system reliability and reduces the system power consumption and cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.
[0035] Figure 1 A schematic diagram of changing external optical fiber interconnection to on-chip interconnection in a current 2D-mesh FPGA array structure provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0036] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.
[0037] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "the" and "the" used in the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0038] It should be understood that although the terms first, second, third, etc. may be used in the present invention to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0039] The present invention is described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.
[0040] Glossary:
[0041] Computing FPGA refers to using FPGA to perform computing tasks.
[0042] Switching FPGA refers to the use of FPGA to implement switching and routing functions.
[0043] By analyzing the characteristics of the FPGA array of the 2D-mesh structure, the connection between FPGAs is divided into direct connection and indirect connection. The fiber-optic interconnection method between nodes has the following disadvantages: First, both direct connection and indirect connection are off-chip interconnections based on optical fiber. Each data packet must pass through the various layers of Ethernet on both sides of the transmitter and receiver, as well as the corresponding transmitter and receiver buffer buf. This method brings huge delays. Second, each FPGA node requires at least 4 ports, but the point-to-point bandwidth between two points is only the bandwidth of 1 port (assuming that the speed of each port is the same), and the bandwidth between nodes is reduced. Third, the bandwidth of direct connection and indirect connection is the same, but due to the aggregation and distribution of routes, when the traffic load is large, it will inevitably cause congestion of the intermediate indirect connection, resulting in huge delay jitter of the entire network communication. Fourth, in the scenario where there is a large amount of fine-grained data in the computing domain, the interconnection and exchange of Ethernet variable-length packets will put forward huge cache resource requirements for the intermediate connection.
[0044] A method for constructing a low-latency and high-bandwidth 2D-mesh FPGA chip array of the present invention comprises:
[0045] Add a type of switching node, which is composed of FPGA, called switching FPGA; the switching FPGA connects several computing FPGAs; the switching FPGA implements 2D-mesh-based interconnection and switching. The on-chip connection avoids repeated Ethernet protocol stack encapsulation and caching of inter-chip transmission, reducing latency overhead and resource usage; compared with inter-chip, the bandwidth and latency performance on the chip are generally one order of magnitude higher, so under the condition of large traffic load, it can also provide the entire network with interconnection bandwidth far exceeding the interface and better forwarding latency, greatly reducing the congestion probability of the entire network and ensuring that the latency jitter is within a smaller range; and the point-to-point bandwidth between any two computing FPGAs is equal to the access bandwidth of the computing node FPGA, and there will be no access bandwidth convergence problem.
[0046] In one embodiment, if Figure 1As shown, for the FPGA array composed of a 2D-mesh structure, the off-chip optical fiber connection is converted into an on-chip connection, which is equivalent to a switching FPGA; the switching FPGA is connected to several computing FPGAs to obtain a low-latency and high-bandwidth 2D-mesh FPGA chip array of the present invention.
[0047] In one embodiment, the switching FPGA and the computing FPGA are interconnected via optical fiber.
[0048] In one embodiment, the computing FPGA and the switching FPGA use a fixed-length Ethernet protocol; the fixed-length packet is the shortest Ethernet frame 64B (called a Cell); the fixed-length encapsulation of data is completed by the computing FPGA. Due to the use of fixed-length packet transmission and switching, the PPS (packets per second) of the entire network is improved, and the functional logic of the switching FPGA is simple, clear, and easy to implement. In addition, due to the use of a fixed-length short packet mechanism, the demand for cache resources is reduced, making it easier to integrate larger-scale switching functions on a single chip.
[0049] In one embodiment, due to the good scalability of 2D-mesh, when the delay budget is met, the switching FPGA also has good scalability, that is, the switching FPGAs can be interconnected.
[0050] The embodiment of the present invention also provides a low-latency and high-bandwidth 2D-mesh FPGA chip array, including a switching FPGA and a plurality of computing FPGAs; the switching FPGA is connected to the plurality of computing FPGAs; the switching FPGA is composed of a plurality of FPGAs to achieve interconnection and switching based on 2D-mesh; specifically, its structure can be seen in Figure 1 Right picture in .
[0051] It should be noted that the low-latency and high-bandwidth 2D-mesh FPGA chip array embodiment shown in this embodiment matches the content of the above-mentioned low-latency and high-bandwidth 2D-mesh FPGA chip array construction method embodiment. You can refer to the content of the above-mentioned method embodiment and will not repeat it here.
[0052] The above embodiments are only used to illustrate the design ideas and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design ideas disclosed by the present invention are within the protection scope of the present invention.
[0053] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only.
[0054] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.
Claims
1. A method for constructing a low-latency and high-bandwidth 2D-mesh FPGA chip array, characterized in that: include: A type of switching node is added, which is composed of FPGA and is called a switching FPGA; the switching FPGA is connected to several computing FPGAs; and the switching FPGA implements 2D-mesh-based interconnection and switching.
2. According to claim 1, a method for constructing a low-latency and high-bandwidth 2D-mesh FPGA chip array is characterized in that: The switching FPGA and the computing FPGA are interconnected via optical fibers.
3. The method for constructing a low-latency and high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: Also includes: The switching FPGAs are interconnected.
4. The method for constructing a low-latency, high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: The fixed-length Ethernet protocol is used between the computing FPGA and the switching FPGA; the fixed-length packet is the shortest Ethernet frame 64B; and the fixed-length encapsulation of data is completed by the computing FPGA.
5. The method for constructing a low-latency and high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: The switching FPGA is implemented by using Cell-based on-chip bus fixed-length routing and switching.
6. The method for constructing a low-latency, high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: The entire network adopts virtual channel VC technology and uses a credit-based flow control mechanism.
7. A low-latency, high-bandwidth 2D-mesh FPGA chip array, characterized in that: It includes a switching FPGA and several computing FPGAs; the switching FPGA is connected to several computing FPGAs; the switching FPGA is composed of several FPGAs to realize interconnection and switching based on 2D-mesh.
8. The low-latency, high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: The switching FPGA and the computing FPGA are interconnected via optical fibers.
9. The low-latency, high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: It also includes a plurality of switching FPGAs, which are interconnected.
10. The low-latency, high-bandwidth 2D-mesh FPGA chip array according to claim 1, characterized in that: The fixed-length Ethernet protocol is used between the computing FPGA and the switching FPGA; the fixed-length packet is the shortest Ethernet frame of 64B; the fixed-length encapsulation of data is completed by the computing FPGA; the switching FPGA is implemented using Cell-based on-chip bus fixed-length routing and switching; the entire network adopts virtual channel VC technology and uses a credit-based flow control mechanism.