Method for designing semiconductor structure

Abstract

A method of designing a semiconductor structure is provided. The method includes determining a first hot spot region of the contact structure chart. The method includes enlarging the first hot spot region according to a first predefined enlargement profile to determine a first enlarged region of the contact structure chart. The method includes determining that a first portion of the first enlarged region overlaps a functional region of a functional component. The method includes determining a cut-out region of the first portion of the contact structure chart that does not include the first enlarged region. The method includes updating the first patterned oxide layer pattern based on the cut region to generate an updated patterned oxide layer pattern. The above method achieves a reduced amount of residue, such as metal residue, remaining on the set of contact structures in the semiconductor device. The reduced amount of residue achieves at least one of improved operation, reduced loss, increased throughput, improved production efficiency, and the like of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for designing a semiconductor structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, such as mobile phones, laptops, desktop computers, tablet computers, watches, gaming systems, and a variety of other industrial, commercial, and consumer electronic products. Semiconductor wafers typically undergo one or more processes to produce semiconductor devices thereon and / or therefrom. Summary of the invention

[0003] In some embodiments, a method for designing a semiconductor structure is provided. The method includes determining a first hot spot region of a contact structure diagram. The method includes enlarging the first hot spot region according to a first predefined enlarged profile to determine a first enlarged region of the contact structure diagram. The method includes determining that a first portion of the first enlarged region overlaps a functional region of a functional component. The method includes determining a cutout region of the contact structure diagram that does not include the first portion of the first enlarged region. The method includes updating a first patterned oxide layer map based on the cutout region to generate an updated patterned oxide layer map.

[0004] In some embodiments, a method for designing a semiconductor structure is provided. The method includes determining a first region of a contact structure map. The method includes determining a second region of the contact structure map. The method includes updating a first patterned oxide layer map in response to determining that a resistive region does not overlap with the first region and overlaps with the second region to generate an updated patterned oxide layer map defining a first patterned oxide layer that resides in the first region and does not reside in the second region.

[0005] In some embodiments, a method for designing a semiconductor structure is provided. The method includes determining a first area of ​​a contact structure diagram. The method includes determining that a first portion of the first area overlaps with a functional area of ​​a functional component. The method includes determining a cutout area of ​​the contact structure diagram that does not include the first portion of the first area. The method includes updating a first patterned oxide layer map based on the cutout area to generate an updated patterned oxide layer map that defines a patterned oxide layer residing in the cutout area. The method includes manufacturing an oxide layer patterning unit based on the updated patterned oxide layer map. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1Aillustrates a representation of a contact structure diagram indicating a configuration of a contact structure according to some embodiments;

[0008] Figure 1B Illustrate determining one or more hotspot areas according to some embodiments;

[0009] Figure 1C Illustrate expanding a hot spot area to determine an expansion area according to some embodiments;

[0010] Figure 1D illustrating one or more first patterned layer regions of a first patterned layer map mapped to a contact structure map according to some embodiments;

[0011] Figure 1E illustrates comparing a region of a contact structure map to one or more functional regions according to some embodiments;

[0012] Figure 1F illustrates a cutout region of a contact structure diagram according to some embodiments;

[0013] Figure 1G illustrates determining a cutout region of a contact structure diagram according to some embodiments;

[0014] Figure 1H illustrates comparing a region of a contact structure map to one or more resistance regions according to some embodiments;

[0015] Fig. 1I illustrates a second patterned layer diagram according to some embodiments;

[0016] Figure 1J illustrates a second patterned layer diagram according to some embodiments;

[0017] Figure 1K illustrates a first patterned layer diagram according to some embodiments;

[0018] Figure 1L illustrates a patterned layer region of a first patterned layer map according to some embodiments;

[0019] Figure 1M illustrates a patterned layer region of a first patterned layer map according to some embodiments;

[0020] Figure 1N illustrates a patterned layer region of a first patterned layer map according to some embodiments;

[0021] Figure 2 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0022] Figure 3illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0023] Figure 4 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0024] Figure 5 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0025] Figure 6 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0026] Figure 7 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0027] Figure 8 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0028] Fig. 9A illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0029] Fig. 9B illustrates a top view of a semiconductor device at a manufacturing stage according to some embodiments;

[0030] Fig.10 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0031] Fig.11A illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0032] Fig. 11B illustrates a top view of a semiconductor device at a manufacturing stage according to some embodiments;

[0033] Fig. 12A illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0034] Fig. 12B illustrates a top view of a semiconductor device at a manufacturing stage according to some embodiments;

[0035] Fig.13A illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0036] Fig. 13B illustrates a top view of a semiconductor device at a manufacturing stage according to some embodiments;

[0037] Fig.14 illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0038] Fig.15A illustrates a cross-sectional view of a semiconductor device at a stage of fabrication according to some embodiments;

[0039] Fig. 15B illustrates a top view of a semiconductor device at a manufacturing stage according to some embodiments;

[0040] Fig.16A illustrates a cross-sectional view of a semiconductor device according to some embodiments;

[0041] Fig. 16B illustrates a cross-sectional view of a semiconductor device according to some embodiments;

[0042] Fig.17 illustrates a cross-sectional view of a semiconductor device according to some embodiments;

[0043] Fig.18 illustrates a cross-sectional view of a semiconductor device according to some embodiments;

[0044] Fig.19 illustrates a cross-sectional view of a semiconductor device according to some embodiments;

[0045] Fig. 20 illustrates a perspective view of a semiconductor device according to some embodiments;

[0046] Fig.21 illustrates a perspective view of a semiconductor device according to some embodiments;

[0047] Fig. 22 illustrates a perspective view of a semiconductor device according to some embodiments;

[0048] Fig.23 is a flow chart illustrating a method according to some embodiments;

[0049] Fig.24 is a flow chart illustrating a method according to some embodiments;

[0050] Fig.25 is a flow chart illustrating a method according to some embodiments.

[0051] Fig.26 Exemplary computer-readable media are illustrated in accordance with some embodiments, which may include processor-executable instructions to embody one or more of the provisioning described herein.

[0052]

Explanation of symbols

[0053] 100: System

[0054] 102A~102L: The first contact structure

[0055] 104A~104F: The second contact structure

[0056] 105: length of the side wall of each contact structure

[0057] 106: First Area

[0058] 107A: first length of the first sidewall of the contact structure

[0059] 107B: Length of the second side wall of the contact structure

[0060] 108: Second Area

[0061] 109: Total length of the second set of contact structures

[0062] 111: The distance between two adjacent contact structures

[0063] 113A~113I: The third contact structure

[0064] 115: Contact structure diagram

[0065] 117A~117C: The fourth contact structure

[0066] 118: The first expansion area

[0067] 119: Second expansion area

[0068] 120: The first hot spot area

[0069] 121: Total length of the third group of contact structures

[0070] 122: Second hot spot area

[0071] 123: The distance between two adjacent contact structures

[0072] 125: first patterned layer area

[0073] 127: Second patterned layer area

[0074] 132A-132D: Edges of the first hot spot area

[0075] 134A-134D: Edges of the first enlarged area

[0076] 135: Cutting area

[0077] 137: first functional area of ​​the first functional component

[0078] 139: Second functional area of ​​the second functional component

[0079] 140: first resistance region of the first resistance component

[0080] 141: The first part of the third expansion area

[0081] 142: second resistance region of the second resistance component

[0082] 143: The second part of the third expansion area

[0083] 145: The third part of the third expansion area

[0084] 147: The fourth part of the third expansion area

[0085] 149: The fifth part of the third expansion area

[0086] 151: The First Gap

[0087] 153: The Second Gap

[0088] 155: length of the side wall of each contact structure

[0089] 156A~156E: a set of contact structures

[0090] 157: Second patterned layer diagram

[0091] 158A~158E: a set of contact structures

[0092] 160: Area

[0093] 162A~162E: A set of contact structures

[0094] 164A~164E: A set of contact structures

[0095] 165: Patterned layer area

[0096] 166: Patterned layer area

[0097] 168: Area

[0098] 170A~170E: a set of contact structures

[0099] 171: length of the sidewall of each contact structure

[0100] 172: The distance between two adjacent contact structures

[0101] 173: The distance between two adjacent contact structures

[0102] 174: The distance between two adjacent contact structures

[0103] 175: length of the sidewall of each contact structure

[0104] 176: Area

[0105] 177: Representation of the first patterned layer diagram

[0106] 178: Area

[0107] 179: Space

[0108] 180: Area

[0109] 181: The third expansion area

[0110] 182: Patterned layer area

[0111] 183: The fourth expansion area

[0112] 184A~184E: A set of contact structures

[0113] 185A~185D: The edge of the third expansion area

[0114] 187: first supplementary patterned layer region

[0115] 196:Offset

[0116] 198: Region

[0117] 200:Semiconductor devices

[0118] 202:Semiconductor body

[0119] 204: first work function layer

[0120] 206: first dielectric layer

[0121] 208A~208F:Structure

[0122] 302: First oxide layer

[0123] 402: first photoresist

[0124] 502: first patterned photoresist

[0125] 602: first patterned oxide layer

[0126] 604A~604D: first groove

[0127] 702: First metal layer

[0128] 802A~802D: Contact structure

[0129] 902: Second oxide layer

[0130] 1002: second photoresist

[0131] 1102: second exposure photoresist

[0132] 1102A: Insoluble part

[0133] 1102B: Soluble fraction

[0134] 1104: Light

[0135] 1108: First micro-shadow mask

[0136] 1110: Second lens

[0137] 1112: Second light source

[0138] 1202: second patterned photoresist

[0139] 1204A~1204B:Part

[0140] 1206A-1206B: Semiconductor device part

[0141] 1302: Second patterned oxide layer

[0142] 1304A~1304B: Part

[0143] 1306A-1306B: Semiconductor device part

[0144] 1308: Semiconductor device part

[0145] 1402: Second metal layer

[0146] 1502: Portion of the second patterned oxide layer

[0147] 1504A~1504L: The fifth contact structure

[0148] 1508A~1508I: The seventh contact structure

[0149] 1510A~1510C: The eighth contact structure

[0150] 1512: First functional component

[0151] 1514: Second functional component

[0152] 1516: first resistor component

[0153] 1518: Second resistance component

[0154] 1520: Semiconductor device part

[0155] 1524A~1524B: Part

[0156] 1526A-1526B: Semiconductor device part

[0157] 1600:Semiconductor devices

[0158] 1602A~1602E: a group of doped regions

[0159] 1604:Semiconductor body

[0160] 1606: First trench isolation structure

[0161] 1607: Second trench isolation structure

[0162] 1608A~1608F: A set of contact structures

[0163] 1610: Work function layer

[0164] 1612: Dielectric layer

[0165] 1614: Second Structure

[0166] 1616: The Third Structure

[0167] 1618: First Structure

[0168] 1620: Oxide layer residue

[0169] 1700: Semiconductor devices

[0170] 1702A~1702E: a group of doped regions

[0171] 1704:Semiconductor body

[0172] 1706: First trench isolation structure

[0173] 1707: Second trench isolation structure

[0174] 1708A~1708F: A set of contact structures

[0175] 1710: Work function layer

[0176] 1712: Dielectric layer

[0177] 1714: Second Structure

[0178] 1716: The Third Structure

[0179] 1718: First Structure

[0180] 1800: Semiconductor devices

[0181] 1802: First Section

[0182] 1804: Part 2

[0183] 1806: First trench isolation structure

[0184] 1808: Second trench isolation structure

[0185] 1810: Third trench isolation structure

[0186] 1900: Semiconductor devices

[0187] 1902A~1902E: a group of doped regions

[0188] 1904: Semiconductor body

[0189] 1906: First trench isolation structure

[0190] 1907: Second trench isolation structure

[0191] 1908A~1908F: A set of contact structures

[0192] 1910: Work function layer

[0193] 1912: Dielectric layer

[0194] 1914: Second Structure

[0195] 1916: The Third Structure

[0196] 1918: First Structure

[0197] 1920: The Fifth Structure

[0198] 1922: The Fourth Structure

[0199] 1924: The Seventh Structure

[0200] 1926: The Sixth Structure

[0201] 2000: Semiconductor Devices

[0202] 2008A~2008F: A set of contact structures

[0203] 2010: Work Function Layer

[0204] 2012: Dielectric layer

[0205] 2014: Second Structure

[0206] 2016: The Third Structure

[0207] 2018: First Structure

[0208] 2050: FinFET structure

[0209] 2052: Trench Isolation Structure

[0210] 2054:Substrate

[0211] 2100:Semiconductor Devices

[0212] 2108A~2108C: A set of contact structures

[0213] 2110: Work function layer

[0214] 2112: Dielectric layer

[0215] 2114: Second Structure

[0216] 2116: The Third Structure

[0217] 2118: First Structure

[0218] 2120: The fourth structure

[0219] 2152: Trench isolation structure

[0220] 2154:Substrate

[0221] 2200:Semiconductor devices

[0222] 2208A~2208C: A set of contact structures

[0223] 2210: Work function layer

[0224] 2212: Dielectric layer

[0225] 2214: Second Structure

[0226] 2216: The Third Structure

[0227] 2218: First Structure

[0228] 2220: The fourth structure

[0229] 2250: FinFET structure

[0230] 2252: Trench isolation structure

[0231] 2254:Substrate

[0232] 2300: Method

[0233] 2302,2304,2306,2308,2310: Methods and Steps

[0234] 2400: Method

[0235] 2402,2404,2406: Methods and Steps

[0236] 2500: Method

[0237] 2502,2504,2506,2508,2510: Methods and Steps

[0238] 2600: Embodiment

[0239] 2602: Method

[0240] 2604: A set of processors that can execute computer instructions

[0241] 2606: Computer readable data

[0242] 2608: Computer readable media DETAILED DESCRIPTION

[0243] The following disclosure provides several different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the subsequent description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself determine the relationship between the various embodiments or configurations discussed.

[0244] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (or other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0245] The term "overlying" and / or the like may be used to describe an element or feature that is vertically overlapped with and at a higher elevation than another element or feature. For example, a first element overlies a second element if it is at a higher elevation than a second element and at least a portion of the first element vertically overlaps with at least a portion of the second element.

[0246] The term "below" and / or the like may be used to describe that one element or feature is vertically overlapped with another element or feature and is at a lower height than the other element or feature. For example, a first element is below a second element if it is at a lower height than a second element and at least a portion of the first element vertically overlaps with at least a portion of the second element.

[0247] The term “over” may be used to describe that one element or feature is at a higher elevation than another element or feature. For example, if a first element is at a higher elevation than a second element, the first element is over the second element.

[0248] The term "below" may be used to describe that one element or feature is at a lower elevation than another element or feature. For example, if a first element is at a lower elevation than a second element, the first element is below the second element.

[0249] The term “overlapping” and / or the like may be used to describe that one element or feature and another element or feature cover the same area and / or at least partially overlap each other in the same area and / or the same dimension.

[0250] A system and method for determining a patterned layer map is provided. In some embodiments, a first patterned layer map defining a first patterned layer is updated to generate an updated patterned layer map defining a second patterned layer. The system identifies a hot spot region of a contact structure map. In some embodiments, the hot spot region includes a set of contact structures. In some embodiments, at least one of the hot spot region or a second region derived from the hot spot region is compared with at least one of a functional region of a functional component or a resistance region of a resistance component. In some embodiments, in response to determining that the functional region overlaps with at least one of the hot spot region or the second region, the system cuts off a portion of at least one of the hot spot region or the second region to determine a cut region. In some embodiments, in response to determining that the resistance region overlaps with at least one of the hot spot region or the second region, the system abandons at least one of the hot spot region or the second region. In some embodiments, the updated patterned layer map is determined based on the cut region. For example, the second patterned layer defined by the updated patterned layer map includes a portion residing in the cut region, while according to some embodiments, the first patterned layer defined by the first patterned layer map does not include a portion residing in the cut region. In some embodiments, the updated patterned layer map is used to manufacture a layer patterning unit, such as a lithography mask. According to some embodiments, the present disclosure achieves at least one of automatically designing and / or generating patterned layer maps or patterned layer manufacturing units for semiconductor devices with different configurations and / or configurations in a dynamic and / or flexible manner. In some embodiments, patterning the layer of the semiconductor device according to the updated patterned layer map achieves a reduced amount of residues, such as metal residues, remaining on the set of contact structures in the semiconductor device compared to patterning the layer according to the first patterned layer map. In some embodiments, the reduced amount of residues achieves at least one of improved operation of the semiconductor device, reduced losses, increased yield, improved production efficiency, etc.

[0251] Figures 1A to 1M A system 100 for determining a patterned layer map for fabricating a semiconductor device is illustrated. Figure 1AA representation of a contact structure diagram 115 indicating the configuration of contact structures according to some embodiments is illustrated. In some embodiments, the contact structures indicated by the contact structure diagram 115 are configured in one or more layers of a wafer. In some embodiments, the contact structures include at least one of a first set of contact structures 102A-102L, a second set of contact structures 104A-104F, a third set of contact structures 113A-113I, a fourth set of contact structures 117A-117C, or one or more other contact structures. In some embodiments, the contact structure diagram 115 indicates one or more types of semiconductor device components other than contact structures within the scope of the present disclosure. In some embodiments, the contact structure diagram 115 indicates a semiconductor device component including at least one of a resistive component, a polycrystalline structure such as a doped polycrystalline structure, a doped region, or other suitable types of semiconductor components.

[0252] In some embodiments, the first group of contact structures 102A-102L is within the first region 106. Figure 1ATwelve contact structures in the first set of contact structures 102A-102L are illustrated, but any number of contact structures in the first set of contact structures 102A-102L is contemplated. In some embodiments, the first contact structure density of the first region 106 is greater than a first threshold contact structure density. The first threshold contact structure density is between about 50% and about 90%. Other values ​​of the first threshold contact structure density are within the scope of the present disclosure. In some embodiments, the first contact structure density corresponds to the proportion of the area of ​​the first region 106 occupied by the first set of contact structures 102A-102L. In some embodiments, each contact structure in one, some, or all of the contact structures in the first set of contact structures 102A-102L comprises at least one of polysilicon, one or more metals, or one or more other suitable materials. In some embodiments, each contact structure in one, some, or all of the contact structures in the first set of contact structures 102A-102L has at least one sidewall, the length 105 of the at least one sidewall being between about 1 micron and about 20 microns, such as between about 1 micron and about 10 microns. In some embodiments, each contact structure of one, some, or all of the contact structures in the first set of contact structures 102A-102L comprises a gate electrode, such as an n-type gate electrode or a p-type gate electrode. In some embodiments, the gate electrode comprises a metal gate, such as an n-type metal gate or a p-type metal gate. In some embodiments, each contact structure of one, some, or all of the contact structures in the first set of contact structures 102A-102L is in a transistor or connected to at least one of the transistors. In some embodiments, each contact structure of one, some, or all of the contact structures in the first set of contact structures 102A-102L provides a connection between a transistor and a semiconductor component, such as at least one of a metal layer, a doped region, a connecting element, an interconnect structure, a contact structure, a via, a metal line, a logic component, a circuit system, etc. In some embodiments, each contact structure of one, some, or all of the contact structures in the first set of contact structures 102A-102L is in at least one of the following situations: in a metal-oxide-semiconductor (MOS) structure, a metal-oxide-semiconductor field-effect transistor (MOSFET) structure, a fin field-effect transistor (FinFET) structure, or another suitable structure or connected to at least one of them. In some embodiments, some or all of the contact structures in the first set of contact structures 102A-102L share at least one of the same material composition, the same shape, the same size, or another same feature with each other.In some embodiments, there are differences in at least one of material composition, shape, size, or another characteristic between the contact structures in the first set of contact structures 102A- 102L.

[0253] In some embodiments, the fourth group of contact structures 117A- 117C is within the second region 108. Figure 1A Three contact structures in the fourth set of contact structures 117A-117C are illustrated, but any number of contact structures in the fourth set of contact structures 117A-117C is contemplated. In some embodiments, the second contact structure density of the second region 108 is less than the second threshold contact structure density. The second threshold contact structure density is between about 10% and about 50%. Other values ​​of the second threshold contact structure density are within the scope of the present disclosure. In some embodiments, the second contact structure density corresponds to the proportion of the area of ​​the second region 108 occupied by the fourth set of contact structures 117A-117C. In some embodiments, each contact structure in one, some, or all of the contact structures in the fourth set of contact structures 117A-117C includes at least one of polysilicon, one or more metals, or one or more other suitable materials. In some embodiments, each contact structure in one, some, or all of the contact structures in the fourth set of contact structures 117A-117C includes a gate electrode, such as an n-type gate electrode or a p-type gate electrode. In some embodiments, the gate electrode includes a metal gate, such as an n-type metal gate or a p-type metal gate. In some embodiments, each contact structure in one, some or all of the fourth group of contact structures 117A-117C exists in at least one of the following situations: in a transistor or connected to a transistor. In some embodiments, each contact structure in one, some or all of the fourth group of contact structures 117A-117C provides a connection between a transistor and a semiconductor component, such as at least one of a metal layer, a doped region, a connecting element, an interconnect structure, a contact structure, a via, a metal line, a logic component, a circuit system, etc. In some embodiments, each contact structure in one, some or all of the fourth group of contact structures 117A-117C exists in at least one of the following situations: in a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure or connected to at least one of them. In some embodiments, some or all of the fourth group of contact structures 117A-117C share at least one of the same material composition, the same shape, the same size, or another same feature with each other. In some embodiments, there is a difference in at least one of the material composition, shape, size, or another feature between the contact structures in the fourth group of contact structures 117A-117C.

[0254] In some embodiments, the second set of contact structures 104A-104F are located between the first region 106 and the second region 108. Figure 1A Six contact structures in the second set of contact structures 104A-104F are illustrated, but any number of contact structures in the second set of contact structures 104A-104F is contemplated. In some embodiments, the first number of contact structures in the second set of contact structures 104A-104F ranges from at least about one contact structure to at most about 150 contact structures, such as at least about three contact structures to at most about 12 contact structures. In some embodiments, each contact structure in one, some, or all of the contact structures in the second set of contact structures 104A-104F has a first area of ​​at most a first threshold area. In some embodiments, the first threshold area is between about 0.5 μm 2 to about 2 μm 2. In some embodiments, the first area corresponds to the product of a first length 107A of a first sidewall of the contact structure and a length 107B of a second sidewall of the contact structure. In some embodiments, the second group of contact structures 104A-104F corresponds to a column of contact structures. In some embodiments, a distance 111 between two adjacent contact structures in the second group of contact structures 104A-104F is at most about 10 microns, such as at most about 5 microns. In some embodiments, the contact structures in the second group of contact structures 104A-104F are evenly spaced apart, such that each pair of adjacent contact structures in the second group of contact structures 104A-104F is spaced apart by a distance approximately equal to the distance 111. In some embodiments, the second group of contact structures 104A-104F has a total length 109 that is greater than the first threshold total length. In some embodiments, the first threshold total length is between about 500 microns and about 1,000 microns. In some embodiments, the total length 109 corresponds to the distance between the outer sidewalls of the two outermost contact structures 104A and 104F in the second group of contact structures 104A-104F. In some embodiments, each contact structure of one, some, or all of the second set of contact structures 104A-104F comprises at least one of polysilicon, one or more metals, or one or more other suitable materials. In some embodiments, each contact structure of one, some, or all of the second set of contact structures 104A-104F comprises a gate electrode, such as an n-type gate electrode or a p-type gate electrode. In some embodiments, the gate electrode comprises a metal gate, such as an n-type metal gate or a p-type metal gate. In some embodiments, each contact structure of one, some, or all of the second set of contact structures 104A-104F exists in at least one of the following situations: in a transistor or connected to a transistor. In some embodiments, each contact structure of one, some, or all of the second set of contact structures 104A-104F provides a connection between a transistor and a semiconductor component, such as at least one of a metal layer, a doped region, a connecting element, an interconnect structure, a contact structure, a via, a metal line, a logic component, a circuit system, etc. In some embodiments, each contact structure in one, some, or all of the contact structures in the second set of contact structures 104A-104F is in at least one of the following situations: in a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure or connected to at least one of them. In some embodiments, some or all of the contact structures in the second set of contact structures 104A-104F share at least one of the same material composition, the same shape, the same size, or another common feature with each other. In some embodiments, there are differences in at least one of the material composition, shape, size, or another feature between the contact structures in the second set of contact structures 104A-104F.In some embodiments, one, some, or all of the contact structures in the second group of contact structures 104A-104F share at least one of the same material composition, the same shape, the same size, or another same feature with each other. In some embodiments, one, some, or all of the contact structures in the second group of contact structures 104A-104F share at least one of the same material composition, the same shape, the same size, or another same feature with at least one of a contact structure in the first group of contact structures 102A-102L, a contact structure in the third group of contact structures 113A-113I, or a contact structure in the fourth group of contact structures 117A-117C.

[0255] In some embodiments, the third group of contact structures 113A-113I is located between the first region 106 and the second region 108. Figure 1ANine contact structures in the third group of contact structures 113A-113I are illustrated, but any number of contact structures in the third group of contact structures 113A-113I is contemplated. In some embodiments, the second number of contact structures in the third group of contact structures 113A-113I ranges from at least about one contact structure to at most about 150 contact structures, such as at least about three contact structures to at most about 12 contact structures. In some embodiments, each contact structure in one, some, or all of the contact structures in the third group of contact structures 113A-113I has an area of ​​at most the first threshold area. In some embodiments, the third group of contact structures 113A-113I corresponds to a column of contact structures. In some embodiments, the distance 123 between two adjacent contact structures in the third group of contact structures 113A-113I is at most about 10 microns, such as at most about 5 microns. In some embodiments, the contact structures in the third group of contact structures 113A-113I are uniformly spaced apart such that each pair of adjacent contact structures in the third group of contact structures 113A-113I are spaced apart by a distance approximately equal to distance 123. In some embodiments, the third group of contact structures 113A-113I has a total length 121 greater than the first threshold total length. In some embodiments, the total length 121 corresponds to the distance between the outer sidewalls of the two outermost contact structures 113A and 113I in the third group of contact structures 113A-113I. In some embodiments, each contact structure in one, some, or all of the contact structures in the third group of contact structures 113A-113I comprises at least one of polysilicon, one or more metals, or one or more other suitable materials. In some embodiments, each contact structure in one, some, or all of the contact structures in the third group of contact structures 113A-113I comprises a gate electrode, such as an n-type gate electrode or a p-type gate electrode. In some embodiments, the gate electrode comprises a metal gate, such as an n-type metal gate or a p-type metal gate. In some embodiments, each contact structure of one, some, or all of the contact structures in the third group of contact structures 113A-113I exists in at least one of the following situations: in a transistor or connected to a transistor. In some embodiments, each contact structure of one, some, or all of the contact structures in the third group of contact structures 113A-113I provides a connection between a transistor and a semiconductor component, such as at least one of a metal layer, a connection element, an interconnect structure, a contact structure, a via, a doped region, a metal line, a logic component, a circuit system, etc. In some embodiments, each contact structure of one, some, or all of the contact structures in the third group of contact structures 113A-113I exists in at least one of the following situations: in a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure or connected to at least one of them.In some embodiments, some or all of the contact structures in the third group of contact structures 113A-113I share at least one of the same material composition, the same shape, the same size, or another same feature with each other. In some embodiments, there are differences in at least one of the material composition, shape, size, or another feature between the contact structures in the third group of contact structures 113A-113I. In some embodiments, one, some or all of the contact structures in the third group of contact structures 113A-113I share at least one of the same material composition, the same shape, the same size, or another same feature with at least one of a contact structure in the first group of contact structures 102A-102L, a contact structure in the second group of contact structures 104A-104F, or a contact structure in the fourth group of contact structures 117A-117C.

[0256] Reference Figure 1B , the system 100 determines at least one of the first hot spot region 120 of the contact structure map 115 or the second hot spot region 122 of the contact structure map 115. In some embodiments, the first hot spot region 120 includes the second group of contact structures 104A-104F. In some embodiments, the second hot spot region 122 includes the third group of contact structures 113A-113I.

[0257] In some embodiments, the system 100 determines a first hot spot region 120 of the contact structure map 115 based on a first position of a first defect in the first wafer. In some embodiments, the first wafer includes contact structures, such as at least one of the first group of contact structures 102A-102L, the second group of contact structures 104A-104F, the third group of contact structures 113A-113I, or the fourth group of contact structures 117A-117C. In some embodiments, the contact structures in the first wafer are configured according to the contact structure map 115. In some embodiments, the first defect includes a first residue disposed on one, some, or all of the contact structures of the second group of contact structures 104A-104F in the first wafer. In some embodiments, the first defect, such as the first residue, has a negative impact on the operation of the first wafer. In some embodiments, the first wafer having a first defect, such as the first residue, causes an increase in leakage current in the first wafer. In some embodiments, the first position of the first defect is determined by analyzing the first wafer via at least one of scanning electron microscopy (SEM), transmission electron microscopy (TEM), or other suitable techniques. In some embodiments, the first location of the first defect is determined by detecting a leakage current in the first wafer. In some embodiments, the leakage current is detected by measuring a current in the first wafer when a voltage, such as a voltage applied to a semiconductor component of the first wafer, is at least one of a first defined voltage or within a first defined voltage range. In some embodiments, the first defined voltage or at least one of the first defined voltage range corresponds to at least one of VDD or VDDL. In some embodiments, the system 100 maps the first location of the first defect in the first wafer to the first hot spot region 120.

[0258] In some embodiments, the system 100 determines the first hot spot region 120 of the contact structure diagram 115 based on determining at least one of the following: (i) each contact structure in one, some, or all of the contact structures in the second group of contact structures 104A-104F has an area no greater than the first threshold area, (ii) the first number of contact structures in the second group of contact structures 104A-104F is no greater than a first threshold number of contact structures, such as about 150 contact structures or about 12 contact structures, (iii) the first number of contact structures in the second group of contact structures 104A-104F is greater than a second threshold number of contact structures, such as about 1 contact structure or about 3 contact structures, (iv) the total length 109 (in Figure 1A) is greater than the first threshold total length, (v) the total length 109 of the second group of contact structures 104A~104F is not greater than the second threshold total length, or (vi) the first hot spot area 120 is located between the first area 106 having a first contact structure density greater than the first threshold contact structure density and the second area 108 having a second contact structure density less than the second threshold contact structure density.

[0259] In some embodiments, the system 100 determines a second hot spot region 122 of the contact structure map 115 using one or more of the techniques provided herein for determining the first hot spot region 120. In some embodiments, the system 100 determines the second hot spot region 122 based on a second position of a second defect in the second wafer. In some embodiments, the second wafer includes contact structures, such as at least one of the first group of contact structures 102A-102L, the second group of contact structures 104A-104F, the third group of contact structures 113A-113I, or the fourth group of contact structures 117A-117C. In some embodiments, the contact structures in the second wafer are configured according to the contact structure map 115. The second wafer is the same as the first wafer or different from the first wafer. In some embodiments, the second defect includes a second residue disposed on one, some, or all of the contact structures of the third group of contact structures 113A-113I in the second wafer. In some embodiments, the second defect, such as the second residue, negatively affects the operation of the second wafer. In some embodiments, the system 100 maps the second position of the second defect in the second wafer to the second hot spot region 122.

[0260] In some embodiments, the system 100 determines the second hot spot region 122 of the contact structure diagram 115 based on determining at least one of the following: (i) each contact structure in one, some, or all of the contact structures in the third group of contact structures 113A-113I has an area no greater than the first threshold area, (ii) the first number of contact structures in the third group of contact structures 113A-113I is no greater than the first threshold number of contact structures, (iii) the first number of contact structures in the third group of contact structures 113A-113I is greater than the second threshold number of contact structures, (iv) the total length 121 (in Figure 1A ) is greater than the first threshold total length, (v) the total length 121 of the third group of contact structures 113A~113I is not greater than the second threshold total length, or (vi) the second hot spot area 122 is located between the first area 106 having a first contact structure density greater than the first threshold contact structure density and the second area 108 having a second contact structure density less than the second threshold contact structure density.

[0261] In some embodiments, the system 100 scans the contact structure map 115 to identify a first group of contact structures 102A- 102L. In some embodiments, the system 100 determines that the first group of contact structures 102A-102L is not in the hot spot region based on determining at least one of the following: (i) each contact structure in one, some or all of the contact structures in the first group of contact structures 102A-102L has an area greater than the first threshold area, (ii) the number of contact structures in the first group of contact structures 102A-102L is greater than the first threshold number of contact structures, (iii) the number of contact structures in the first group of contact structures 102A-102L is not greater than the second threshold number of contact structures, (iv) the total length of the first group of contact structures 102A-102L is not greater than the first threshold total length, (v) the total length of the first group of contact structures 102A-102L is greater than the second threshold total length, or (vi) the first group of contact structures 102A-102L is not located between a region having a first contact structure density greater than the first threshold contact structure density and a region having a second contact structure density less than the second threshold contact structure density. In some embodiments, in response to determining that the first set of contact structures 102A- 102L is not in the hot spot region, the system 100 does not generate a hot spot region including the first set of contact structures 102A- 102L.

[0262] In some embodiments, the system 100 scans the contact structure map 115 to identify the second group of contact structures 104A-104F. In some embodiments, the system 100 determines that the second group of contact structures 104A-104F is in the hot spot region based on determining at least one of the following: (i) each contact structure in one, some, or all of the second group of contact structures 104A-104F has an area no greater than the first threshold area, (ii) the first number of contact structures in the second group of contact structures 104A-104F is no greater than the first threshold number of contact structures, (iii) the first number of contact structures in the second group of contact structures 104A-104F is greater than the second threshold number of contact structures, (iv) the total length 109 (in Figure 1A ) is greater than the first threshold total length, (v) the total length 109 of the second group of contact structures 104A-104F is not greater than the second threshold total length, or (vi) the second group of contact structures 104A-104F is located between a first region 106 having a first contact structure density greater than the first threshold contact structure density and a second region 108 having a second contact structure density less than the second threshold contact structure density. In some embodiments, in response to determining that the second group of contact structures 104A-104F is in the hot spot region, the system 100 generates a first hot spot region 120 of the contact structure map 115.

[0263] Reference Figure 1C , the system 100 performs at least one of the following operations: expanding the first hot spot region 120 to determine the first expanded region 118 of the contact structure diagram 115 or expanding the second hot spot region 122 to determine the second expanded region 119 of the contact structure diagram 115. In some embodiments, the first expanded region 118 includes the second group of contact structures 104A-104F. In some embodiments, the second expanded region 119 includes the third group of contact structures 113A-113I.

[0264] In some embodiments, the system 100 enlarges the first hot spot region 120 according to the first predefined enlarged profile to determine the first enlarged region 118. In some embodiments, the system 100 enlarges the first hot spot region 120 according to the first predefined enlarged profile by increasing one, some, or all of the edges 132A-132D (in Figure 1B In some embodiments, at least one of the following operations is performed: (i) the first side 132A (in Figure 1B The length of the first enlarged area 118 is increased by the first enlarged value to determine the first side 134A (in Figure 1C (ii) the second side 132B of the first hot spot region 120 (in Figure 1B The length of the first enlarged area 118 is increased by a second enlarged value to determine the second side 134B (in Figure 1C (iii) the third side 132C (in Figure 1B The length of the first enlarged area 118 is increased by the second enlarged value to determine the third side 134C (in Figure 1C ), or (iv) extending the fourth side 132D (at Figure 1B The length of the first enlarged area 118 is increased by the first enlarged value to determine the fourth side 134D (in Figure 1C). In some embodiments, the first expansion value is equal to the second expansion value. It is contemplated that different embodiments of the first expansion value and the second expansion value are provided. In some embodiments, the first predefined expansion profile indicates at least one of the first expansion value or the second expansion value. In some embodiments, the first expansion value corresponds to a constant value. In some embodiments, the first expansion value is between about 0.1 microns and about 2 microns, such as between about 0.1 microns and about 0.5 microns. In some embodiments, the first expansion value is determined based on a first ratio indicated by the first predefined expansion profile. In some embodiments, the first ratio is between about 0.01% and about 10%. In some embodiments, the system 100 determines the first expansion value based on the first ratio and the first side 132A of the first hot spot area 120 (at Figure 1B In some embodiments, when the first ratio is about 0.1% and the length of the first side 132A of the first hot spot region 120 is about 500 microns, the system 100 determines the first expansion value to be about 0.5 microns, and therefore, the system 100 increases the length of the first side 132A of the first hot spot region 120 by about 0.5 microns to determine the first side 134A of the first expanded region 118 (shown in FIG. 1 ). Figure 1C Length shown in ).

[0265] In some embodiments, the first side 134A (at Figure 1C ) and the distance between the contact structure 104A in the second group of contact structures 104A-104F is greater than the first side 132A of the first hot spot region 120 (in Figure 1B ) and the distance between the contact structure 104A in the second group of contact structures 104A-104F. In some embodiments, the second side 134B of the first enlarged region 118 (at Figure 1C ) and a contact structure in the second group of contact structures 104A-104F is greater than the second side 132B of the first hot spot region 120 (in Figure 1B In some embodiments, the third side 134C of the first enlarged region 118 (shown in FIG. Figure 1C ) and a contact structure in the second group of contact structures 104A-104F is greater than the third side 132C of the first hot spot region 120 (in Figure 1B In some embodiments, the fourth side 134D (in Figure 1C The distance between the contact structure 104F in the second group of contact structures 104A-104F is greater than the fourth side 132D of the first hot spot region 120 (shown in Figure 1B) and the distance between the contact structure 104F in the second group of contact structures 104A-104F.

[0266] In some embodiments, the system 100 uses one or more of the techniques provided herein for expanding the first hot spot area 120 to determine the first expanded area 118 to expand the second hot spot area 122 to determine the second expanded area 119. In some embodiments, the system 100 expands the second hot spot area 122 according to a second predefined expanded profile to determine the second expanded area 119. In some embodiments, the second predefined expanded profile is the same as the first predefined expanded profile. Embodiments are contemplated in which the second predefined expanded profile is different from the first predefined expanded profile.

[0267] In some embodiments, the system 100 compares at least one of the first enlarged area 118 or the second enlarged area 119 to one or more first patterned layer regions of a first patterned layer map defining a first patterned layer. In some embodiments, the first patterned layer map is (previously) used to form a patterned layer in at least one of a first wafer associated with a first defect or a second wafer associated with a second defect. In some embodiments, a first patterning process is performed according to the first patterned layer map to pattern the first layer to form a first patterned layer. In some embodiments, the first patterned layer map indicates one or more portions of the first layer that are removed in the first patterning process to form the first patterned layer. In some embodiments, the first patterned layer map indicates one or more portions of the first layer that are not removed in the first patterning process to form the first patterned layer. In some embodiments, a patterned layer region of the one or more first patterned layer regions corresponds to an area where the first patterned layer resides. In some embodiments, the patterned layer region includes a portion of the first layer that is not removed in the first patterning process to form the first patterned layer.

[0268] In some embodiments, in a first scenario (not shown) where the first enlarged region 118 overlaps with a patterned layer region of the one or more first patterned layer regions, the system 100 classifies the first enlarged region 118 as an unqualified region in response to determining that the first enlarged region 118 overlaps with the patterned layer region of the one or more first patterned layer regions. In some embodiments, the system 100 abandons the first enlarged region 118 in response to classifying the first enlarged region 118 as an unqualified region. In some embodiments, the system 100 stops considering the first enlarged region 118 as a candidate supplemental patterned layer region to be added to the first patterned layer map to generate the second patterned layer map 157 (at Figures 1I to 1J ).

[0269] Figure 1DOne or more first patterned layer regions of the first patterned layer map mapped to the contact structure map 115 are illustrated according to some embodiments. Figure 1D According to some embodiments, the system 100 compares at least one of the first enlarged region 118 or the second enlarged region 119 with one or more first patterned layer regions of the first patterned layer map. In some embodiments, the one or more first patterned layer regions include the first patterned layer region 125 (in Figure 1D The second patterned layer region 127 (shown as a filled pattern rectangle in FIG. Figure 1D ). In some embodiments, the first patterned layer overlies some or all of the contact structures in the contact structure diagram 115. In some embodiments, the first patterned layer region 125 corresponds to a first portion of the first patterned layer overlying the first set of contact structures 102A-102L. In some embodiments, the second patterned layer region 127 corresponds to a second portion of the first patterned layer overlying the fourth set of contact structures 117A-117C. In some embodiments, the first patterning process includes (i) removing portions of the first layer outside of one or more first patterned layer regions, and (ii) not removing portions of the first layer in one or more first patterned layer regions, such as not removing a portion of the first layer within the first patterned layer region 125 and not removing a portion of the first layer within the second patterned layer region 127. In some embodiments, the fact that the first enlarged region 118 does not overlap with one or more first patterned layer regions indicates that the first enlarged region 118 does not overlap with the first patterned layer according to the first patterned layer diagram. In some embodiments, the second enlarged region 119 does not overlap with one or more first patterned layer regions, indicating that the second enlarged region 119 does not overlap with the first patterned layer according to the first patterned layer map.

[0270] Reference Figure 1E , the system 100 compares at least one of the third enlarged region 181 or the fourth enlarged region 183 with one or more functional regions of one or more first functional components. In some embodiments, the third enlarged region 181 corresponds to the first hot spot region 120. In some embodiments, the fourth enlarged region 183 corresponds to the second hot spot region 122. In some embodiments, the third enlarged region 181 includes the second set of contact structures 104A-104F. In some embodiments, the fourth enlarged region 183 includes the third set of contact structures 113A-113I.

[0271] In some embodiments, the system 100 enlarges the first hot spot region 120 according to the third predefined enlarged profile to determine the third enlarged region 181. In some embodiments, the system 100 increases one, some, or all of the edges 132A-132D (in Figure 1BIn some embodiments, at least one of the following operations is performed: (i) the first side 132A (in Figure 1B The length of the third enlarged area 181 is increased by a third enlarged value to determine the first side 185A of the third enlarged area 181 (in Figure 1E (ii) the second side 132B of the first hot spot region 120 (in Figure 1B The length of the third enlarged area 181 is increased by a fourth enlarged value to determine the second side 185B (in Figure 1E (iii) the third side 132C (in Figure 1B The length of the third side 185C (shown in FIG. 185A ) is increased by a fourth expansion value to determine the third side 185C of the third expansion area 181 (shown in FIG. 185B ). Figure 1E ), or (iv) extending the fourth side 132D (at Figure 1B The length of the third enlarged area 181 is increased by the third enlarged value to determine the fourth side 185D (in Figure 1E ). In some embodiments, the third expansion value is equal to the fourth expansion value. Embodiments are contemplated in which the third expansion value is different from the fourth expansion value. In some embodiments, the third predefined expansion profile indicates at least one of the third expansion value or the fourth expansion value. In some embodiments, the third expansion value corresponds to a constant value. In some embodiments, the third expansion value is between about 0.1 microns and about 2 microns, such as between about 0.1 microns and about 1 micron. In some embodiments, the third expansion value is determined based on a first ratio indicated by the third predefined expansion profile. In some embodiments, the first ratio is between about 0.01% and about 10%. In some embodiments, the system 100 determines the third expansion value based on the first ratio and the first side 132A of the first hot spot area 120 (at Figure 1B In some embodiments, when the first ratio is about 0.1% and the length of the first side 132A of the first hot spot region 120 is about 500 microns, the system 100 determines the third expansion value to be about 0.5 microns, and therefore, the system 100 increases the length of the first side 132A of the first hot spot region 120 by about 0.5 microns to determine the first side 185A of the third expanded region 181 (shown in FIG. 1 ). Figure 1E Length shown in ).

[0272] In some embodiments, the first side 185A of the third expanded area 181 (at Figure 1E ) and the distance between the contact structure 104A in the second group of contact structures 104A-104F is greater than the first side 132A of the first hot spot region 120 (in Figure 1BIn some embodiments, the second side 185B of the third enlarged region 181 (shown in FIG. 1 ) is the distance between the second side 185B of the third enlarged region 181 and the contact structure 104A in the second group of contact structures 104A-104F. Figure 1E ) and a contact structure in the second group of contact structures 104A-104F is greater than the second side 132B of the first hot spot region 120 (in Figure 1B In some embodiments, the third side 185C of the third enlarged region 181 (shown in FIG. Figure 1E ) and a contact structure in the second group of contact structures 104A-104F is greater than the third side 132C of the first hot spot region 120 (in Figure 1B In some embodiments, the fourth side 185D (in Figure 1E The distance between the contact structure 104F in the second group of contact structures 104A-104F is greater than the fourth side 132D of the first hot spot region 120 (shown in Figure 1B ) and the distance between the contact structure 104F in the second group of contact structures 104A-104F.

[0273] In some embodiments, the system 100 uses one or more of the techniques provided herein for expanding the first hot spot area 120 to determine the third expanded area 181 to expand the second hot spot area 122 to determine the fourth expanded area 183. In some embodiments, the system 100 expands the second hot spot area 122 according to a fourth predefined expanded profile to determine the fourth expanded area 183. In some embodiments, the fourth predefined expanded profile is the same as the third predefined expanded profile. Embodiments are contemplated in which the fourth predefined expanded profile is different from the third predefined expanded profile.

[0274] In some embodiments, the third expanded region 181 is different from the first expanded region 118 and the fourth expanded region 183 is different from the second expanded region 119. Embodiments where at least one of the third expanded region 181 is the same as the first expanded region 118 or the fourth expanded region 183 is the same as the second expanded region 119 are contemplated.

[0275] In some embodiments, the one or more functional regions of the one or more first functional components include at least one of the first functional region 137 of the first functional component or the second functional region 139 of the second functional component. In some embodiments, the one or more first functional components correspond to one or more semiconductor components in a wafer such as a first wafer, which is manufactured based on at least one of the first patterned layer map, the contact structure map 115, or a functional component map (not shown) indicating the one or more functional regions.

[0276] In some embodiments, the first functional component includes a first polycrystalline structure, such as a first doped polycrystalline structure. In some embodiments, the first polycrystalline structure includes an n-type doped polycrystalline structure or a p-type doped polycrystalline structure. In some embodiments, the first functional component, such as the first polycrystalline structure, includes at least one of polysilicon, a polymer, or one or more other suitable materials. In some embodiments, the second functional component includes a second polycrystalline structure, such as a second doped polycrystalline structure. In some embodiments, the second polycrystalline structure includes an n-type doped polycrystalline structure or a p-type doped polycrystalline structure. In some embodiments, the second functional component, such as the second polycrystalline structure, includes at least one of polysilicon, a polymer, or one or more other suitable materials. In some embodiments, the contact structure map 115 indicates at least one of the first functional region 137 of the first functional component or the second functional region 139 of the second functional component. In some embodiments, the system 100 determines at least one of the position or size of the first functional region 137 and / or the second functional region 139 based on the functional component map. In some embodiments, the system 100 maps one or more functional regions indicated by the functional component diagram to the first functional region 137 and / or the second functional region 139 in the contact structure diagram 115 .

[0277] In some embodiments, the system 100 determines at least one of the following: (i) the first portion 141 of the third enlarged region 181 (in Figure 1G ) overlaps with the first functional area 137, or (ii) the second portion 143 of the third enlarged area 181 (in Figure 1G ) overlaps with the second functional area 139. In some embodiments, the first portion 141 of the third expanded area 181 overlaps with at least a portion of the first functional area 137. In some embodiments, the second portion 143 of the third expanded area 181 overlaps with at least a portion of the second functional area 139. In some embodiments, in response to determining that at least one of the first portion 141 of the third expanded area 181 overlaps with the first functional area 137 or the second portion 143 of the third expanded area 181 overlaps with the second functional area 139, the system 100 removes at least one of the first portion 141 of the third expanded area 181 or the second portion 143 of the third expanded area 181 to determine the cutout area 135 of the contact structure diagram 115 (in Figure 1F In some embodiments, the system 100 determines that the fourth expanded area 183 does not overlap with a functional area of ​​the one or more functional areas.

[0278] Reference Figure 1FAccording to some embodiments, the system 100 determines a cutout region 135 of the contact structure diagram 115, and the cutout region 135 does not include at least one of: (i) the first portion 141 of the third enlarged region 181, or (ii) the second portion 143 of the third enlarged region 181. In some embodiments, based on determining that the fourth enlarged region 183 does not overlap with a functional region of the one or more functional regions, the system 100 does not modify the fourth enlarged region 183.

[0279] Figure 1G One or more operations performed by the system 100 to determine the cropping area 135 according to some embodiments are illustrated. In some embodiments, the third expanded area 181 includes at least one of: (i) the first portion 141, (ii) the second portion 143, (iii) the third portion 145 adjacent to the first portion 141, (iv) the fourth portion 147 between the first portion 141 and the second portion 143, or (v) the fifth portion 149 adjacent to the second portion 143. In some embodiments, the system 100 removes the first portion 141 and the second portion 143 from the third expanded area 181 to determine the area 131 of the contact structure figure 115. In some embodiments, removing the first portion 141 and the second portion 143 forms a first gap 151 between the third portion 145 and the fourth portion 147 and a second gap 153 between the fourth portion 147 and the fifth portion 149. In some embodiments, the system 100 removes at least one of the third portion 145, the fourth portion 147, or the fifth portion 149 from the region 131 to determine the cut region 135 of the contact structure diagram 115. In some embodiments, by removing the third portion 145, the fourth portion 147, and the fifth portion 149 from the region 131, a cut region 135 without the first gap 151 and the second gap 153 is generated.

[0280] Reference Figure 1H , the system 100 compares at least one of the cut area 135 or the fourth enlarged area 183 with one or more resistance regions of the one or more first resistance components. In some embodiments, the one or more resistance regions of the one or more first resistance components include at least one of the first resistance region 140 of the first resistance component or the second resistance region 142 of the second resistance component. In some embodiments, the one or more first resistance components correspond to one or more semiconductor components in a wafer such as a first wafer, which is manufactured based on at least one of the first patterned layer map, the contact structure map 115, or a resistance component map (not shown) indicating the one or more resistance regions.

[0281] In some embodiments, the first resistor component includes a first high resistance device. In some embodiments, the first resistor component has a first resistance higher than a threshold resistance. In some embodiments, the first resistor component includes a p-type resistor component or an n-type resistor component. In some embodiments, the first resistor component includes at least one of polysilicon, a polymer, an oxide material, or one or more other suitable materials. In some embodiments, the first resistor component includes a resist protective oxide (RPO). In some embodiments, the first resistor component includes a first high resistance device. In some embodiments, the second resistor component has a second resistance higher than a threshold resistance. In some embodiments, the second resistor component includes a p-type resistor component or an n-type resistor component. In some embodiments, the second resistor component includes at least one of polysilicon, a polymer, an oxide material, or one or more other suitable materials. In some embodiments, the second resistor component includes RPO. In some embodiments, the contact structure map 115 indicates at least one of the first resistor region 140 of the first resistor component or the second resistor region 142 of the second resistor component. In some embodiments, the system 100 determines at least one of the position or size of the first resistor region 140 and / or the second resistor region 142 based on the resistor component map. In some embodiments, the system 100 maps one or more resistance regions indicated by the resistance component map to the first resistance region 140 and / or the second resistance region 142 in the contact structure map 115 .

[0282] In some embodiments, the system 100 determines that the cutout region 135 does not overlap with a resistance region of the one or more resistance regions. In some embodiments, the system 100 determines that the fourth expanded region 183 overlaps with at least one of the first resistance region 140 or the second resistance region 142. In some embodiments, the fourth expanded region 183 overlaps with at least a portion of the first resistance region 140. In some embodiments, the fourth expanded region 183 overlaps with at least a portion of the second resistance region 142.

[0283] In some embodiments, in response to determining that the cut region 135 does not overlap with a resistive region of the one or more resistive regions, the system 100 classifies the cut region 135 as a qualified region.

[0284] In some embodiments, in response to determining that the fourth expanded area 183 overlaps with at least one of the first resistance area 140 or the second resistance area 142 of the one or more resistance areas, the system 100 classifies the fourth expanded area 183 as an unqualified area. In some embodiments, in response to classifying the fourth expanded area 183 as an unqualified area, the system 100 abandons the fourth expanded area 183. In some embodiments, the system 100 stops considering the fourth expanded area 183 as a candidate supplemental patterned layer area to be added to the first patterned layer map to generate the second patterned layer map 157 (at Figures 1I to 1J In a second scenario (not shown) where the fourth expanded area 183 is determined to not overlap with a resistance area of ​​the one or more resistance areas, in some embodiments, the system 100 classifies the fourth expanded area 183 as a qualified area.

[0285] Reference Fig. 1I According to some embodiments, the system 100 determines a second patterned layer map 157. In some embodiments, the second patterned layer map 157 indicates one or more second patterned layer regions. In some embodiments, the second patterned layer map 157 is determined based on the first patterned layer map or at least one of the one or more qualified regions determined by the system 100. In some embodiments, the one or more qualified regions include the cutout region 135. In some embodiments, the system 100 supplements the first patterned layer map with one or more supplementary patterned layer regions to generate the second patterned layer map 157. In some embodiments, the one or more supplementary patterned layer regions are generated based on the one or more qualified regions.

[0286] In some embodiments, the one or more second patterned layer regions indicated by the second patterned layer map 157 include at least one of the first patterned layer region 125, the second patterned layer region 127, or the first supplemental patterned layer region 187. In some embodiments, the first supplemental patterned layer region 187 is generated based on the cut region 135. In some embodiments, the first supplemental patterned layer region 187 matches the cut region 135, such as having the same size and position as the cut region 135. In some embodiments, the cut region 135 is modified to generate the first supplemental patterned layer region 187, such as where the first supplemental patterned layer region 187 is a modified version of the cut region 135. In some embodiments, based on the fourth enlarged region 183 (in Figure 1HIn some embodiments, in a first scenario (not shown) where the first enlarged area 118 overlaps with a patterned layer area in one or more first patterned layer areas, in response to classifying the first enlarged area 118 as an unqualified area, the second patterned layer map 157 does not include the first supplementary patterned layer area 187. In a second scenario (not shown) where the fourth enlarged area 183 is determined to not overlap with a resistance area in one or more resistance areas, in some embodiments, in response to classifying the fourth enlarged area 183 as a qualified area, the second patterned layer map 157 includes a supplementary patterned layer area (not shown).

[0287] In some embodiments, the second patterned layer image 157 is generated without a space 179 (at Fig. 1I ). Figure 1J The second patterned layer map 157 is illustrated without the space 179 according to some embodiments. In some embodiments, the second patterned layer map 157 corresponds to an updated version of the first patterned layer map.

[0288] Figure 1K A representation 177 of a first patterned layer map according to some embodiments is illustrated. In some embodiments, since the first patterned layer map does not include the first supplemental patterned layer region 187, the first patterned layer defined by the first patterned layer map does not reside in the first supplemental patterned layer region 187. In some embodiments, the first patterning process includes removing a portion of the first layer that resides in the first supplemental patterned layer region 187 to form the first layer.

[0289] In some embodiments, the second patterned layer map 157 defines a second patterned layer. In some embodiments, a second patterning process is performed according to the second patterned layer map to pattern the second layer to form a second patterned layer. In some embodiments, the second patterned layer map indicates one or more portions of the second layer that are removed in the second patterning process to form the second patterned layer. In some embodiments, the second patterned layer map indicates one or more portions of the second layer that are not removed in the second patterning process to form the second patterned layer. In some embodiments, a patterned layer region of the one or more second patterned layer regions corresponds to an area where the second patterned layer resides. In some embodiments, the patterned layer region includes a portion of the second layer that is not removed in the second patterning process to form the second patterned layer.

[0290] In some embodiments, the first layer patterning unit is manufactured based on the second patterning layer image 157. In some embodiments, the first layer patterning unit includes a first lithography mask, such as a photomask. In some embodiments, the first layer patterning unit is used to pattern the second layer to form a second patterned layer.

[0291] Figure 1L to Figure 1M Embodiments of the second patterned layer image 157 incorporating various contact structure configurations are illustrated. Figure 1L An illustration of a patterned layer region 166 representing a second patterned layer map 157 determined using the system 100 is illustrated. In some embodiments, the patterned layer region 166 includes at least one of a set of contact structures 156A-156E or a set of contact structures 162A-162E. In some embodiments, the set of contact structures 156A-156E includes at least some of the features, characteristics, functions, interrelationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the first set of contact structures 102A-102L. In some embodiments, the set of contact structures 162A-162E includes at least some of the features, characteristics, functions, interrelationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the second set of contact structures 104A-104F. In some embodiments, at least some of the set of contact structures 156A-156E are located in a region 176 where the contact structure density is greater than a first threshold contact structure density. In some embodiments, the group of contact structures 162A-162E is located between region 176 and region 168 where the contact structure density is less than the second threshold contact structure density. In some embodiments, each contact structure in one, some, or all of the contact structures in the group of contact structures 162A-162E has an area of ​​at most the first threshold area. In some embodiments, the group of contact structures 162A-162E corresponds to a column of contact structures. In some embodiments, the distance 172 between two adjacent contact structures in the group of contact structures 162A-162E is at most about 10 microns, such as at most about 5 microns. In some embodiments, the contact structures in the group of contact structures 162A-162E are evenly spaced apart, so that each pair of adjacent contact structures in the third group of contact structures 162A-162E is spaced apart by a distance approximately equal to the distance 172. In some embodiments, the total length of the group of contact structures 162A-162E is greater than about 500 microns. In some embodiments, each contact structure in one, some, or all of the set of contact structures 156A-156E has at least one sidewall having a length 155 between about 1 micron and about 20 microns, such as between about 1 micron and about 10 microns.

[0292] Figure 1MA diagram of a patterned layer region 165 representing a second patterned layer map 157 determined using the system 100 is illustrated. In some embodiments, the patterned layer region 165 includes at least one of a group of contact structures 158A-158E or a group of contact structures 170A-170E. In some embodiments, the group of contact structures 158A-158E includes at least some of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the first group of contact structures 102A-102L. In some embodiments, the group of contact structures 170A-170E includes at least some of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the second group of contact structures 104A-104F. In some embodiments, at least some of the group of contact structures 158A-158E are located in a region 160 where the contact structure density is greater than a first threshold contact structure density. In some embodiments, the group of contact structures 170A-170E is located between the region 160 and the region 178 where the contact structure density is less than the second threshold contact structure density. In some embodiments, each contact structure in one, some or all of the contact structures in the group of contact structures 170A-170E has an area of ​​at most the first threshold area. In some embodiments, the group of contact structures 170A-170E corresponds to a column of contact structures. In some embodiments, the distance 174 between two adjacent contact structures in the group of contact structures 170A-170E is at most about 10 microns, such as at most about 5 microns. In some embodiments, the contact structures in the group of contact structures 170A-170E are evenly spaced apart, so that each pair of adjacent contact structures in the third group of contact structures 170A-170E is spaced apart by a distance approximately equal to the distance 174. In some embodiments, the total length of the group of contact structures 170A-170E is greater than about 80 microns. In some embodiments, each contact structure in one, some or all of the contact structures in the set of contact structures 158A-158E has at least one sidewall having a length 171 between about 1 micron and about 20 microns, such as between about 1 micron and about 10 microns.

[0293] Figure 1NAn illustration of a patterned layer region 182 representing a second patterned layer map 157 determined using the system 100 is illustrated. In some embodiments, the patterned layer region 182 includes at least one of a group of contact structures 164A-164E or a group of contact structures 184A-184E. In some embodiments, the group of contact structures 164A-164E includes at least some of the features, characteristics, functions, interrelationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the first group of contact structures 102A-102L. In some embodiments, the group of contact structures 184A-184E includes at least some of the features, characteristics, functions, interrelationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the second group of contact structures 104A-104F. In some embodiments, at least some of the group of contact structures 164A-164E are located in a region 180 where the contact structure density is greater than a first threshold contact structure density. In some embodiments, the group of contact structures 184A-184E is located between region 180 and region 198 where the contact structure density is less than the second threshold contact structure density. In some embodiments, each contact structure in one, some or all of the contact structures in the group of contact structures 184A-184E has an area of ​​at most the first threshold area. In some embodiments, the group of contact structures 184A-184E corresponds to a column of contact structures. In some embodiments, the distance 173 between two adjacent contact structures in the group of contact structures 184A-184E is at most about 10 microns, such as at most about 5 microns. In some embodiments, the contact structures in the group of contact structures 184A-184E are evenly spaced apart so that each pair of adjacent contact structures in the third group of contact structures 184A-184E is spaced apart by a distance approximately equal to the distance 173. In some embodiments, the total length of the group of contact structures 184A-184E is greater than about 500 microns. In some embodiments, each contact structure in one, some, or all of the contact structures in the set of contact structures 164A-164E has at least one sidewall having a length 175 between about 1 micron and about 20 microns, such as between about 1 micron and about 10 microns. In some embodiments, region 198 includes one or more functional regions of one or more functional components, such as one or more first functional components. In some embodiments, the one or more functional regions include at least one of the first functional region 137 or the second functional region 139. In some embodiments, system 100 determines patterned layer region 182 such that there is an offset 196 of at least a threshold distance between a functional region in the one or more functional regions and patterned layer region 182.

[0294] Figures 2 to 15B A cross-sectional view of a semiconductor device 200 at various stages of fabrication is illustrated in accordance with some embodiments. Figures 2 to 8 , Fig.10 and Fig.14 A cross-sectional view of a semiconductor device 200 is illustrated.

[0295] Fig. 9B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 15B A top view of a semiconductor device 200 is shown, and Fig. 9A , Fig.11A , Fig. 12A , Fig.13A and Fig.15A Examples are given along Fig. 9B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 15B 2 is a cross-sectional view of the semiconductor device 200 taken along line AA.

[0296] Figure 2A semiconductor device 200 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 includes at least one of a semiconductor body 202, a first dielectric layer 206 overlying the semiconductor body 202, or a first work function layer 204. In some embodiments, the semiconductor body 202 includes at least one of a semiconductor layer, a substrate, a silicon-on-insulator (SOI) structure, an epitaxial layer, or other suitable layers. In some embodiments, the semiconductor body 202 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. In some embodiments, the first dielectric layer 206 includes at least one of phosphosilicate glass (PSG) or other suitable materials. In some embodiments, the first dielectric layer 206 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, growth, or other suitable techniques. In some embodiments, the first work function layer 204 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the first work function layer 204 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0297] In some embodiments, the semiconductor device 200 includes structures 208A-208F. In some embodiments, the first dielectric layer 206 electrically isolates the structures 208A-208F from each other. In some embodiments, the structures 208A-208F have one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the first set of contact structures 102A-102L. In some embodiments, each contact structure in one, some, or all of the contact structures 208A-208F includes at least one of polysilicon or one or more other suitable materials.

[0298] Figure 3 The first oxide layer 302 is shown formed on the first dielectric layer 206. The first oxide layer 302 includes at least one of an oxide material such as silicon oxide or one or more other suitable materials. In some embodiments, the first oxide layer 302 includes a first stop oxide layer or another type of oxide layer. The first oxide layer 302 is at least one of the following: overlying the first dielectric layer 206, directly contacting the top surface of the first dielectric layer 206, or indirectly contacting the top surface of the first dielectric layer 206. In some embodiments, the first oxide layer 302 is at least one of the following: overlying the structures 208A-208F, directly contacting the top surface of one of the structures 208A-208F, or indirectly contacting the top surface of the structure 208A-208F.

[0299] Figure 4 A first photoresist 402 is illustrated as being formed over the first oxide layer 302 according to some embodiments. The first photoresist 402 is formed over the first oxide layer 302 by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The first photoresist 402 includes a photosensitive material, wherein a property of the first photoresist 402, such as solubility, is affected by light. In some embodiments, light is directed from a first light source through a second lithographic mask, such as a template, to the first photoresist 402 to produce a first exposed photoresist.

[0300] Figure 5The example shows that a first patterned photoresist 502 is formed on the first oxide layer 302 according to some embodiments. In some embodiments, a first developer such as a solvent is applied to the first exposed photoresist to form the first patterned photoresist 502. The first exposed photoresist is a negative photoresist or a positive photoresist. With respect to embodiments in which the first exposed photoresist includes a negative photoresist, regions of the first exposed photoresist become insoluble when illuminated by a first light source, so that the application of the first developer to the first exposed photoresist removes the un-illuminated regions of the first exposed photoresist. Therefore, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque regions of the second lithographic mask between the first light source and the negative photoresist. In embodiments in which the first exposed photoresist includes a positive photoresist, the illuminated regions of the first exposed photoresist become soluble and are removed by applying the first developer during development. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque regions of the second lithographic mask between the first light source and the positive photoresist.

[0301] Figure 6 Patterning the first oxide layer 302 using the first patterned photoresist 502 to form the first patterned oxide layer 602 is illustrated in accordance with some embodiments. In some embodiments, a first etching process is performed to remove one or more portions of the first oxide layer 302 to form the first patterned oxide layer 602. In some embodiments, the one or more first etchants of the first etching process are selective such that the one or more first etchants remove or etch away first oxide layer 302 that is not exposed or covered by the first patterned photoresist 502 at a greater rate than the one or more first etchants remove or etch away the first patterned photoresist 502. Thus, the openings in the first patterned photoresist 502 allow the one or more first etchants to form corresponding openings in the first oxide layer 302 below the photoresist and thereby transfer the pattern in the photoresist to the first oxide layer 302 below the photoresist. In some embodiments, the first etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The one or more first etchants include fluorine, hydrogen fluoride (HF), diluted HF, such as hydrogen chloride (HCl 2 ) of chlorine compounds, hydrogen sulfide (H 2 S), or at least one of another suitable material. Other processes and / or techniques for forming the first patterned oxide layer 602 are within the scope of the present disclosure. In some embodiments, after forming the first patterned oxide layer 602, the first patterned photoresist 502 is removed, such as by stripping or washing.

[0302] In some embodiments, the first etching process removes one or more first structures in structures 208A-208F that are not covered by the first patterned photoresist 502 during the first etching process. In some embodiments, the one or more first structures include at least one of structure 208B, structure 208C, structure 208D, or structure 208E. In some embodiments, removing the one or more first structures forms one or more first trenches, which include at least one of trench 604A, trench 604B, trench 604C, or trench 604D. In some embodiments, the first etching process does not remove one or more second structures in structures 208A-208F that are covered by the first patterned photoresist 502 during the first etching process. In some embodiments, the one or more second structures include at least one of structure 208A or structure 208F.

[0303] Figure 7 The first metal layer 702 is shown formed on at least one of the first dielectric layer 206 or the first patterned oxide layer 602 according to some embodiments. In some embodiments, the first metal layer 702 includes at least one of one or more metals or one or more other suitable materials. The first metal layer 702 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the first metal layer 702 fills one or more first trenches, such as trench 604A (in Figure 6 ), at least one of groove 604B, groove 604C or groove 604D.

[0304] Figure 8 Removal of a first upper portion of semiconductor device 200 is illustrated according to some embodiments. In some embodiments, the first upper portion of semiconductor device 200 includes at least one of a top portion of first metal layer 702, a top portion of first dielectric layer 206, a top portion of first work function layer 204, a top portion of structure 208A, or a top portion of structure 208F. In some embodiments, the first upper portion of semiconductor device 200 is removed by a first layer removal process including at least one of chemical-mechanical polishing (CMP), etching, or other suitable techniques.

[0305] In some embodiments, the first metal layer 702 is deposited to form one or more third contact structures of the semiconductor device 200. In some embodiments, the one or more third contact structures include at least one of the contact structure 802A, the contact structure 802B, the contact structure 802C, the contact structure 802D, or one or more other contact structures formed by the first metal layer 702. In some embodiments, the first metal layer 702 or at least one of the one or more third contact structures is associated with a first conductivity type. In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type. In some embodiments, a contact structure in the one or more third contact structures includes a gate electrode, such as a gate electrode having a first conductivity type. In some embodiments, the gate electrode includes a metal gate, such as a metal gate having a first conductivity type. In some embodiments, a contact structure in the one or more third contact structures exists in at least one of the following situations: in a transistor or connected to a transistor. In some embodiments, a contact structure in the one or more third contact structures provides a connection between a transistor and a semiconductor component, such as at least one of a metal layer, a connecting element, an interconnect structure, a contact structure, a via, a doped region, a metal line, a logic component, a circuit system, etc. In some embodiments, a contact structure in the one or more third contact structures exists in at least one of the following situations: in a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure or connected to at least one of them. In some embodiments, a contact structure in the one or more third contact structures is connected to a doped region having a first conductivity type.

[0306] FIG. 9A to FIG. 9B The second oxide layer 902 is shown formed on the first dielectric layer 206. The second oxide layer 902 includes at least one of an oxide material such as silicon oxide or one or more other suitable materials. In some embodiments, the second oxide layer 902 includes a second stop oxide layer or another type of oxide layer. The second oxide layer 902 is at least one of overlying the first dielectric layer 206, directly contacting the top surface of the first dielectric layer 206, or indirectly contacting the top surface of the first dielectric layer 206. In some embodiments, the second oxide layer 902 is at least one of: overlying the structures 208A and 208F, directly contacting the top surface of one of the structures 208A and 208F, or indirectly contacting the top surface of the structure 208A and 208F. In some embodiments, the second oxide layer 902 is at least one of: overlying the contact structures 802A-802D, directly contacting a top surface of one of the contact structures 802A-802D, or indirectly contacting a top surface of the one of the contact structures 802A-802D.

[0307] In some embodiments, a second patterned layer image 157 (in Figures 1I to 1J The second oxide layer 902 is patterned by a first patterning unit such as a first lithographic mask to form a second patterned oxide layer 1302 (shown in FIG. FIG. 13A to FIG. 13B ).

[0308] Fig.10 The second photoresist 1002 is shown to be formed on the second oxide layer 902 according to some embodiments. The second photoresist 1002 is present in at least one of the following situations: overlying the second oxide layer 902, directly contacting the top surface of the second oxide layer 902, or indirectly contacting the top surface of the second oxide layer 902. The second photoresist 1002 is formed on the second oxide layer 902 by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The second photoresist 1002 includes a photosensitive material, wherein properties such as solubility of the second photoresist 1002 are affected by light. The second photoresist 1002 is a positive photoresist or a negative photoresist.

[0309] FIG. 11A to FIG. 11B The use of a first lithography mask (shown with reference numeral 1108) to produce a second exposed photoresist 1102 is illustrated in accordance with some embodiments. Fig.11A According to some embodiments, light 1104 from a second light source 1112 is directed to the second photoresist 1002 through at least one of a first lens 1106, a first lithographic mask 1108, or a second lens 1110 to produce a second exposed photoresist 1102. In some embodiments, at least one of the following conditions exists: the first lens 1106 comprises a condenser lens or the second lens 1110 comprises a projection lens. With respect to embodiments in which the second exposed photoresist 1102 comprises a negative photoresist, the region of the second exposed photoresist 1102 illuminated by the second light source 1112 is insoluble. Therefore, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque region of the first lithographic mask 1108. In some embodiments, when the second exposed photoresist 1102 is a negative photoresist, the first lithographic mask corresponds to a negative image of the second patterned layer image 157. In embodiments in which the second exposed photoresist 1102 comprises a positive photoresist, the illuminated region of the second exposed photoresist 1102 is soluble. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque areas of the first lithographic mask 1108 between the second light source 1112 and the positive photoresist. In some embodiments, when the second exposed photoresist 1102 is a positive photoresist, the first lithographic mask corresponds to a positive image of the second patterned layer image 157.

[0310] In some embodiments, the second exposed photoresist 1102 includes one or more insoluble portions 1102A and one or more soluble portions 1102B (in Fig. 11B ).

[0311] FIG. 12A to FIG. 12B The second patterned photoresist 1202 is shown formed over the second oxide layer 902 according to some embodiments. In some embodiments, a second developer such as a solvent is applied to the first exposed photoresist to form the second patterned photoresist 1202. In some embodiments, applying the second developer removes one or more soluble portions 1102B (at the bottom of the second exposed photoresist 1102) of the second exposed photoresist 1102. Fig. 11B ). In some embodiments, applying the second developer does not remove one or more insoluble portions 1102A of the second exposed photoresist 1102.

[0312] In some embodiments, the second oxide layer 902 is patterned using the second patterned photoresist 1202 to form a second patterned oxide layer 1302 (in FIG. 13A to FIG. 13B ). In some embodiments, a second etching process is performed to remove one or more portions of the second oxide layer 902 to form a second patterned oxide layer 1302. In some embodiments, the one or more second etchants of the second etching process are selective, so that the one or more second etchants remove or etch away the second oxide layer 902 that is not exposed or covered by the second patterned photoresist 1202 at a greater rate than the one or more second etchants remove or etch away the second patterned photoresist 1202. Therefore, the openings in the second patterned photoresist 1202 allow the one or more second etchants to form corresponding openings in the second oxide layer 902 below the photoresist, and thereby transfer the pattern in the photoresist to the second oxide layer 902 below the photoresist. In some embodiments, the second etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The one or more second etchants include fluorine, HF, diluted HF, such as HCl 2 Chlorine compounds, H 2 S, or at least one of another suitable material. Other processes and / or techniques for forming the second patterned oxide layer 1302 are within the scope of the present disclosure. In some embodiments, after forming the second patterned oxide layer 1302, the second patterned photoresist 1202 is removed, such as by stripping or washing.

[0313] In some embodiments, the second patterned photoresist 1202 does not extend beyond the portion 1206A of the semiconductor device 200 (at Fig. 12A ) or portion 1206B of semiconductor device 200 (shown in dashed outline in FIG. Fig. 12A In some embodiments, the second patterned photoresist 1202 does not include at least one of the following: (i) a portion 1204A overlying a portion 1206A of the semiconductor device 200 (shown in dashed outline in FIG. 1 ); Fig. 12A ) or (ii) a portion 1204B overlying a portion 1206A of the semiconductor device 200 (shown by a dashed outline in FIG. Fig. 12A In some embodiments, at least one of portion 1206A of semiconductor device 200 or portion 1206B of semiconductor device 200 is exposed.

[0314] FIG. 13A to FIG. 13B The semiconductor device 200 is illustrated after removing the second patterned photoresist 1202 over the second patterned oxide layer 1302 according to some embodiments. In some embodiments, after forming the second patterned oxide layer 1302 and before removing the second patterned photoresist 1202, the second patterned photoresist 1202 is at least one of: overlying the second patterned oxide layer 1302, directly contacting the top surface of the second patterned oxide layer 1302, or indirectly contacting the top surface of the second patterned oxide layer 1302. In some embodiments, the second patterned oxide layer 1302 does not cover the portion 1308 of the semiconductor device 200 (at Fig. 13B ).

[0315] In some embodiments, the second patterned oxide layer 1302 does not extend beyond the portion 1306A of the semiconductor device 200 (at Fig.13A ) or portion 1306B of semiconductor device 200 (shown in dashed outline in FIG. Fig.13A In some embodiments, the second patterned oxide layer 1302 does not include at least one of the following: (i) a portion 1304A overlying a portion 1306A of the semiconductor device 200 (shown in dashed outline in FIG. 1 ). Fig.13A ) or (ii) a portion 1304B overlying a portion 1306A of the semiconductor device 200 (shown by a dashed outline in FIG. Fig.13A In some embodiments, if the second patterned photoresist 1202 does not include the portion 1204A (shown as a dashed outline in FIG. Fig. 12A 1304A and 1304B are not shown in FIG. 1304B, the second patterned oxide layer 1302 does not include the portion 1304A and the portion 1304B. In some embodiments, at least one of the portion 1306A of the semiconductor device 200 or the portion 1306B of the semiconductor device 200 is exposed.

[0316] Fig.14The second metal layer 1402 is illustrated as being formed on at least one of the first dielectric layer 206 or the second patterned oxide layer 1302 according to some embodiments. In some embodiments, the second metal layer 1402 includes at least one of one or more metals or one or more other suitable materials. The second metal layer 1402 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0317] FIG. 15A to FIG. 15B Removal of a second upper portion of semiconductor device 200 is illustrated in accordance with some embodiments. In some embodiments, the second upper portion of semiconductor device 200 includes at least a portion of second metal layer 1402 and at least a portion of second patterned oxide layer 1302. In some embodiments, the second upper portion of semiconductor device 200 is removed by a second layer removal process including at least one of CMP, etching, or other suitable techniques. In some embodiments, after removal of the second upper portion of semiconductor device 200, portion 1502 of second patterned oxide layer 1302 remains on semiconductor device 200, such as due at least in part to at least one of one or more parameters of the second layer removal process, one or more physical properties of second metal layer 1402, or a top surface of semiconductor device 200 having a varying height. In some embodiments, portion 1502 of second patterned oxide layer 1302 does not cover portion 1520 of semiconductor device 200 (at least in part to at least one of one or more parameters of the second layer removal process, one or more physical properties of second metal layer 1402, or a top surface of semiconductor device 200 having a varying height. Fig. 15B In some embodiments, portion 1520 of semiconductor device 200 corresponds to portion 1308 of semiconductor device 200 (shown in Fig. 13B In some embodiments, the varying height of the top surface of the semiconductor device 200 prevents a layer removal tool, such as a CMP tool, used in the second layer removal process from being able to remove the portion 1502 of the second patterned oxide layer 1302 .

[0318] In some embodiments, portion 1502 of second patterned oxide layer 1302 does not extend beyond portion 1526A of semiconductor device 200 (at Fig.15A ) or portion 1526B of semiconductor device 200 (shown in dashed outline in FIG. Fig.15A In some embodiments, portion 1502 of second patterned oxide layer 1302 does not include at least one of the following: (i) portion 1524A overlying portion 1526A of semiconductor device 200 (shown in dashed outline in FIG. 1 ) Fig.15A ) or (ii) a portion 1524B overlying a portion 1526A of the semiconductor device 200 (shown by a dashed outline in FIG. Fig.15A In some embodiments, if the second patterned photoresist 1202 does not include the portion 1204A (shown as a dashed outline in FIG. Fig. 12A 1524A and 1524B are not shown in FIG. 15. In some embodiments, at least one of portion 1526A of semiconductor device 200 or portion 1526B of semiconductor device 200 is exposed.

[0319] In some embodiments, the second metal layer 1402 is deposited (on Fig.14 ) to form one or more fourth contact structures of the semiconductor device 200. In some embodiments, the second metal layer 1402 or at least one of the one or more fourth contact structures is associated with a second conductivity type. In some embodiments, the second conductivity type is n-type or p-type. In other embodiments, the first conductivity type is p-type and the second conductivity type is n-type. Embodiments in which the first conductivity type is n-type and the second conductivity type is p-type are envisioned. In some embodiments, a contact structure in the one or more fourth contact structures includes a gate electrode, such as a gate electrode having the second conductivity type. In some embodiments, the gate electrode includes a metal gate, such as a metal gate having the second conductivity type. In some embodiments, a contact structure in the one or more fourth contact structures exists in at least one of the following situations: in a transistor or connected to a transistor. In some embodiments, a contact structure in the one or more fourth contact structures provides a connection between a transistor and a semiconductor component, such as at least one of a metal layer, a connecting element, an interconnect structure, a contact structure, a via, a doped region, a metal line, a logic component, a circuit system, etc. In some embodiments, a contact structure of the one or more fourth contact structures exists in at least one of the following situations: in a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure or connected to at least one of them. In some embodiments, a contact structure of the one or more fourth contact structures is connected to a doped region having a second conductivity type.

[0320] In some embodiments, one or more first functional components are associated with the second conductivity type. In some embodiments, the first functional component includes at least a portion of a component having the second conductivity type, such as a transistor, a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure.

[0321] According to some embodiments, semiconductor device 200 includes a plurality of semiconductor components including at least one of a plurality of contact structures, one or more second functional components, one or more second resistance components, or one or more other components. Although at least some of the plurality of semiconductor components are located below at least one of portion 1502 of second patterned oxide layer 1302 or portion 1520 of semiconductor device and thus are Fig. 15B It is not visible in the top view of Fig. 15B A dashed shape is provided to indicate the location of the corresponding semiconductor component. In some embodiments, Fig. 15B One or more of the semiconductor components shown in the dashed shape are not covered by another layer and are therefore not covered by another layer. Fig. 15B can be seen in the top view.

[0322] In some embodiments, at least some of the plurality of contact structures of the semiconductor device 200 are present in at least one of the following situations: in the first dielectric layer 206 or overlying the semiconductor body 202. In some embodiments, the first dielectric layer 206 electrically isolates the contact structures in the plurality of contact structures from each other. In some embodiments, the plurality of contact structures are formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: a fifth group of contact structures 1504A-1504L corresponding to the first group of contact structures 102A-102L, a sixth group of contact structures corresponding to the second group of contact structures 104A-104F, a seventh group of contact structures 1508A-1508I corresponding to the third group of contact structures 113A-113I, or an eighth group of contact structures 1510A-1510C corresponding to the fourth group of contact structures 117A-117C. In some embodiments, the sixth group of contact structures includes at least one of the structures 208A, the structures 208F, or the contact structures 802A-802D.

[0323] In some embodiments, the fifth group of contact structures 1504A-1504L has one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the first group of contact structures 102A-102L. In some embodiments, the sixth group of contact structures has one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the second group of contact structures 104A-104F. In some embodiments, the seventh group of contact structures 1508A-1508I has one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the third group of contact structures 113A-113I. In some embodiments, the eighth group of contact structures 1510A-1510C has one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the fourth group of contact structures 117A-117C.

[0324] In some embodiments, the one or more third contact structures include at least one of the following: (i) one or more contact structures in the fifth group of contact structures 1504A-1504L, (ii) one or more contact structures in the sixth group of contact structures, (iii) one or more contact structures in the seventh group of contact structures 1508A-1508I, (iv) one or more contact structures in the eighth group of contact structures 1510A-1510C, or (v) one or more other contact structures in the plurality of contact structures.

[0325] In some embodiments, the one or more fourth contact structures include at least one of the following: (i) one or more contact structures in the fifth group of contact structures 1504A-1504L, (ii) one or more contact structures in the sixth group of contact structures, (iii) one or more contact structures in the seventh group of contact structures 1508A-1508I, (iv) one or more contact structures in the eighth group of contact structures 1510A-1510C, or (v) one or more other contact structures in the plurality of contact structures.

[0326] In some embodiments, the one or more second functional components have one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the one or more first functional components. In some embodiments, the one or more second functional components are formed according to the functional component diagram. In some embodiments, the one or more second functional components include at least one of the first functional component (shown with reference numeral 1512) or the second functional component (shown with reference numeral 1514). In some embodiments, the one or more second functional components are provided in accordance with the functional component diagram. Figure 1ECompared to the third enlarged region 181, the size of the first functional region 137 is larger than the space occupied by the first functional component 1512. In some embodiments, the one or more second functional components exist in at least one of the following situations: in the first dielectric layer 206 or in one or more other layers of the semiconductor device 200.

[0327] In some embodiments, the one or more second resistor components have one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to the one or more first resistor components. In some embodiments, the one or more second resistor components are formed according to the resistor component diagram. In some embodiments, the one or more second resistor components include at least one of the first resistor component (shown with reference numeral 1516) or the second resistor component (shown with reference numeral 1518). In some embodiments, the one or more second resistor components are provided with reference numerals 1514, 1515, 1516, 1517, 1518, 1519, 1520, 1521, 1522, 1523, 1524, 1525, 1526, 1527, 1528, 1529, 1530, 1531, 1532, 1533, 1534, 1535, 1536, 1537, 1538, 1539, 1540, 1541, 1542, 1543, 1544, 1545, 1546, 1547, 1548, 1549, 1550, 1551, 1561, 1562, 1564, 1565, 1566, 1570, 1571, 1572, 1573, 1574, 1575, 1576, 1577, 1580, 1581, 1582, 1583, 1584, 1585, 1586, 1587, 1588, 1590, 1 Figure 1H Compared to the fourth enlarged region 183, the size of the first resistive region 140 is larger than the space occupied by the first resistive element 1516. In some embodiments, the one or more second resistive elements are present in at least one of the following situations: in the first dielectric layer 206 or in one or more other layers of the semiconductor device 200.

[0328] In some embodiments, fabricating the second patterned oxide layer 1302 according to the second patterned layer map 157 achieves at least one of improved operation or reduced defects of the semiconductor device 200 as compared to a semiconductor device implemented using the first wafer fabricated according to the first patterned layer map.

[0329] In some embodiments, manufacturing the first wafer includes (i) forming a third oxide layer, (ii) performing (hereinafter referred to as Figures 1A to 1MIn some embodiments, the third patterned oxide layer does not overlie the ninth group of contact structures. In some embodiments, the ninth group of contact structures corresponds to at least one of the sixth group of contact structures or the second group of contact structures 104A-104F. In some embodiments, the ninth group of contact structures has one or more of the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided herein with respect to at least one of the sixth group of contact structures or the second group of contact structures 104A-104F. In some embodiments, the third patterned oxide layer does not overlie the ninth group of contact structures because the first portion of the third oxide layer covering the ninth group of contact structures is removed in the first patterning process according to the first patterning layer map. In some embodiments, the first portion of the third oxide layer is within the first supplemental patterned layer region 187. In some embodiments, the third metal layer corresponds to the second metal layer 1402. In some embodiments, the ninth group of contact structures is not separated from the third metal layer by the third patterned oxide layer due to the removal of the first portion of the third oxide layer in the first patterning process to form the third patterned oxide layer. In some embodiments, removing the third upper portion of the first wafer without separating the ninth group of contact structures from the third metal layer by the third oxide layer results in first metal residues from the third metal layer remaining on the ninth group of contact structures. In some embodiments, the first residue associated with the first defect comprises first metal residues from the third metal layer. In some embodiments, the first metal residues remain on the ninth group of contact structures at least in part due to at least one of one or more parameters of the third layer removal process performed to remove the third upper portion, one or more physical properties of the third metal layer, or a top surface of the first wafer having a varying height. In some embodiments, the first metal residues from the third metal layer negatively affect the operation of the first wafer. In some embodiments, the first wafer having the first metal residues from the third metal layer causes an increase in leakage current in the first wafer. In some embodiments, the first metal residues have at least one of the following conditions: deteriorating or degrading the connection between the contact structures of the first wafer and the components. However, according to some embodiments herein, the second patterned oxide layer 1302 separates the sixth set of contact structures from the second metal layer 1402 by manufacturing the second patterned oxide layer 1302 according to the second patterned layer pattern 157 instead of the first patterned layer pattern.In some embodiments, removing the second upper portion of the semiconductor device 200 with the sixth set of contact structures separated from the second metal layer 1402 by the second patterned oxide layer 1302 results in a reduced amount of metal residue from the second metal layer 1402, such as little or no metal residue, remaining on the sixth set of contact structures. In some embodiments, the reduced amount of metal residue achieves improved operation of the semiconductor device 200. In some embodiments, a first wafer having a first defect such as a first metal residue requires at least one of repair or scrapping of the first wafer or at least one of a batch of wafers including the first wafer. Therefore, reducing the amount of metal residue by at least one of generating the second patterned layer map 157 or using the second patterned layer map 157 to form the second patterned oxide layer achieves at least one of reduced losses, increased yield, improved production efficiency, etc.

[0330] In some embodiments, the second patterned oxide layer 1302 overlies the sixth set of contact structures (in Fig.15A and Fig. 15B In some embodiments, the portion 1502 of the second patterned oxide layer 1302 (shown in FIG. 1 ) has no effect on the operation of the semiconductor device 200. In some embodiments, the portion 1502 of the second patterned oxide layer 1302 has less negative impact on the operation of the semiconductor device 200 than the first metal residue associated with the first defect. In some embodiments, after removing the second upper portion of the semiconductor device 200, an etching process is performed to remove at least some of the portion 1502 of the second patterned oxide layer 1302.

[0331] Fig.16A A semiconductor device 1600 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 (in Figures 2 to 15B ) to form the semiconductor device 1600. In some embodiments, a component of the semiconductor device 1600 includes the semiconductor device 200 (shown in Figures 2 to 15B In some embodiments, the semiconductor device 1600 is formed using the second patterned layer image 157 .

[0332] In some embodiments, the semiconductor device 1600 includes at least one of the following: a semiconductor body 1604, a first trench isolation structure 1606 such as a first shallow trench isolation (STI) structure, a second trench isolation structure 1607 such as a second STI structure, a dielectric layer 1612, a work function layer 1610, a first structure 1618, a second structure 1614, or a third structure 1616. In some embodiments, the work function layer 1610 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the dielectric layer 1612 includes at least one of PSG or other suitable materials. In some embodiments, the semiconductor body 1604 includes at least one of a substrate or an epitaxial layer. In some embodiments, the semiconductor body 1604 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0333] In some embodiments, the semiconductor device 1600 includes a plurality of contact structures formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: (i) a group of contact structures corresponding to at least one of the first group of contact structures 102A-102L or the fifth group of contact structures 1504A-1504L (not shown), (ii) a group of contact structures 1608A-1608F corresponding to at least one of the second group of contact structures 104A-104F or the sixth group of contact structures, (iii) a group of contact structures corresponding to at least one of the third group of contact structures 113A-113I or the seventh group of contact structures 1508A-1508I (not shown), or (iv) a group of contact structures corresponding to at least one of the fourth group of contact structures 117A-117C or the eighth group of contact structures 1510A-1510C (not shown).

[0334] In some embodiments, at least one of the following exists: (i) contact structure 1608A in the set of contact structures 1608A-1608F comprises polysilicon, such as at least one of intrinsic polysilicon, undoped polysilicon, or doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, (ii) contact structures 1608B-1608E in the set of contact structures 1608A-1608F comprise metal, or (ii) contact structure 1608F in the set of contact structures 1608A-1608F comprises polysilicon, such as at least one of intrinsic polysilicon, undoped polysilicon, or doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon. In some embodiments, the contact structure comprising doped polysilicon is formed by at least one of doping, epitaxial doping, ion implantation, molecular diffusion, or other suitable techniques.

[0335] In some embodiments, the semiconductor body 1604 includes a set of doped regions 1602A-1602E. In some embodiments, a doped region in the set of doped regions 1602A-1602E is located between two adjacent contact structures in the set of contact structures 1608A-1608F. In some embodiments, a doped region in the set of doped regions 1602A-1602E has a first conductivity type or a second conductivity type. In some embodiments, the set of doped regions 1602A-1602E is in an active region of the semiconductor device 1600. In some embodiments, a doped region in the set of doped regions 1602A-1602E corresponds to at least one of a drain or a source of at least one of a transistor, a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure.

[0336] In some embodiments, at least one of the first structure 1618 or the second structure 1614 resides in a dielectric layer (not shown) of the semiconductor device 1600. In some embodiments, the third structure 1616 resides in a layer (not shown) (such as a metal layer) of the semiconductor device 1600. In some embodiments, at least one of the first structure 1618 or the second structure 1614 corresponds to a connection element, an interconnect structure, a contact, a via, a metal line, etc. used to establish an electrical connection between the third structure 1616 and one or more contact structures of the set of contact structures 1608A-1608F. In some embodiments, the third structure 1616 includes a metal structure.

[0337] In some embodiments, forming the semiconductor device 1600 using the second patterned layer pattern 157, such as using one or more of the techniques provided herein with respect to forming the semiconductor device 200 using the second patterned layer pattern 157, achieves a reduced amount of metal residue on the set of contact structures 1608A-1608F as compared to using the first patterned layer pattern. In some embodiments, the reduced amount of metal residue improves electrical connection between the third structure 1616 and one or more of the contact structures in the set of contact structures 1608A-1608F.

[0338] In some embodiments, the semiconductor device 1600 includes an oxide layer residue 1620 (in the Fig. 16B In some embodiments, the oxide layer residue 1620 includes a portion 1502 of the second patterned oxide layer 1302 (shown in FIG. 15A to FIG. 15B At least some of the ). Fig. 16B The semiconductor device 1600 is illustrated in accordance with some embodiments, wherein the semiconductor device 1600 includes an oxide layer residue 1620. In some embodiments, the oxide layer residue 1620 resides between the set of contact structures 1608A-1608F and at least one of the first structure 1618 or the second structure 1614.

[0339] Fig.17 A semiconductor device 1700 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 (in Figures 2 to 15B ) to form the semiconductor device 1700. In some embodiments, a component of the semiconductor device 1700 includes the semiconductor device 200 (shown in Figures 2 to 15B In some embodiments, the semiconductor device 1700 is formed using the second patterned layer image 157 .

[0340] In some embodiments, the semiconductor device 1700 includes at least one of the following: a semiconductor body 1704, a first trench isolation structure 1706 such as a first STI structure, a second trench isolation structure 1707 such as a second STI structure, a dielectric layer 1712, a work function layer 1710, a first structure 1718, a second structure 1714, or a third structure 1716. In some embodiments, the work function layer 1710 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the dielectric layer 1712 includes at least one of PSG or other suitable materials. In some embodiments, the semiconductor body 1704 includes at least one of a substrate or an epitaxial layer. In some embodiments, the semiconductor body 1704 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0341] In some embodiments, the semiconductor device 1700 includes a plurality of contact structures formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: (i) a group of contact structures corresponding to at least one of the first group of contact structures 102A-102L or the fifth group of contact structures 1504A-1504L (not shown), (ii) a group of contact structures 1708A-1708F corresponding to at least one of the second group of contact structures 104A-104F or the sixth group of contact structures, (iii) a group of contact structures corresponding to at least one of the third group of contact structures 113A-113I or the seventh group of contact structures 1508A-1508I (not shown), or (iv) a group of contact structures corresponding to at least one of the fourth group of contact structures 117A-117C or the eighth group of contact structures 1510A-1510C (not shown).

[0342] In some embodiments, at least one of the following exists: (i) contact structure 1708A in the set of contact structures 1708A-1708F includes polysilicon, such as at least one of intrinsic polysilicon, undoped polysilicon, or doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, (ii) contact structures 1708B-1708E in the set of contact structures 1708A-1708F include metal, or (ii) contact structure 1708F in the set of contact structures 1708A-1708F includes polysilicon, such as at least one of intrinsic polysilicon, undoped polysilicon, or doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon. In some embodiments, the contact structure including doped polysilicon is formed by at least one of doping, epitaxial doping, ion implantation, molecular diffusion, or other suitable techniques.

[0343] In some embodiments, the semiconductor body 1704 includes a set of doped regions 1702A-1702E. In some embodiments, a doped region in the set of doped regions 1702A-1702E is located between two adjacent contact structures in the set of contact structures 1708A-1708F. In some embodiments, a doped region in the set of doped regions 1702A-1702E has a first conductivity type or a second conductivity type. In some embodiments, the set of doped regions 1702A-1702E is in an active region of the semiconductor device 1700. In some embodiments, a doped region in the set of doped regions 1702A-1702E corresponds to at least one of a drain or a source of at least one of a transistor, a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure.

[0344] In some embodiments, at least one of the first structure 1718 or the second structure 1714 resides in a dielectric layer (not shown) of the semiconductor device 1700. In some embodiments, the third structure 1716 resides in a layer (not shown) (such as a metal layer) of the semiconductor device 1700. In some embodiments, at least one of the first structure 1718 or the second structure 1714 corresponds to a connection element, an interconnect structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the third structure 1716 and one or more contact structures of the set of contact structures 1708A-1708F. In some embodiments, the third structure 1716 includes a metal structure.

[0345] In some embodiments, forming the semiconductor device 1700 using the second patterned layer pattern 157, such as using one or more of the techniques provided herein for forming the semiconductor device 200 using the second patterned layer pattern 157, achieves a reduced amount of metal residue on the set of contact structures 1708A-1708F as compared to using the first patterned layer pattern. In some embodiments, the reduced amount of metal residue improves electrical connection between the third structure 1716 and one or more of the contact structures in the set of contact structures 1708A-1708F.

[0346] Fig.18 A semiconductor device 1800 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 (in Figures 2 to 15B ) to form semiconductor device 1800. In some embodiments, a component of semiconductor device 1800 includes the semiconductor device 200 (shown in Figures 2 to 15B ), semiconductor device 1600 (in FIG. 16A to FIG. 16B ), or semiconductor device 1700 (shown in Fig.17 In some embodiments, the semiconductor device 1800 is formed using the second patterned layer image 157. In some embodiments, the semiconductor device 1800 includes at least one of the first section 1802 or the second section 1804. In some embodiments, each section of at least one of the first section 1802 or the second section 1804 includes the features, characteristics, functions, relationships, relationships with other elements, sizes, locations, materials, etc. provided by at least one of the semiconductor device 200 (shown in Figures 2 to 15B ), semiconductor device 1600 (in FIG. 16A to FIG. 16B ), or semiconductor device 1700 (shown in Fig.17 In some embodiments, the semiconductor device 1700 includes a first trench isolation structure 1806 such as a first STI structure, a second trench isolation structure 1808 such as a second STI structure, or a third trench isolation structure 1810 such as a third STI structure. In some embodiments, the third trench isolation structure 1810 is located between the first section 1802 and the second section 1804.

[0347] Fig.19 A semiconductor device 1900 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 (in Figures 2 to 15B) to form semiconductor device 1900. In some embodiments, a component of semiconductor device 1900 includes the semiconductor device 200 (shown in Figures 2 to 15B In some embodiments, the semiconductor device 1900 is formed using the second patterned layer image 157 .

[0348] In some embodiments, the semiconductor device 1900 includes at least one of the following: a semiconductor body 1904, a first trench isolation structure 1906 such as a first shallow trench isolation (STI) structure, a second trench isolation structure 1907 such as a second STI structure, a dielectric layer 1912, a work function layer 1910, a first structure 1918, a second structure 1914, a third structure 1916, a fourth structure 1922, a fifth structure 1920, a sixth structure 1926, or a seventh structure 1924. In some embodiments, the work function layer 1910 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the dielectric layer 1912 includes at least one of PSG or other suitable materials. In some embodiments, the semiconductor body 1904 includes at least one of a substrate or an epitaxial layer. In some embodiments, the semiconductor body 1904 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0349] In some embodiments, the semiconductor device 1900 includes a plurality of contact structures formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: (i) a group of contact structures corresponding to at least one of the first group of contact structures 102A-102L or the fifth group of contact structures 1504A-1504L (not shown), (ii) a group of contact structures 1908A-1908F corresponding to at least one of the second group of contact structures 104A-104F or the sixth group of contact structures, (iii) a group of contact structures corresponding to at least one of the third group of contact structures 113A-113I or the seventh group of contact structures 1508A-1508I (not shown), or (iv) a group of contact structures corresponding to at least one of the fourth group of contact structures 117A-117C or the eighth group of contact structures 1510A-1510C (not shown).

[0350] In some embodiments, at least one of the following exists: (i) contact structure 1908A in the set of contact structures 1908A-1908F includes a first resistor, such as an n-type resistor or a p-type resistor, (ii) contact structures 1908B-1908E in the set of contact structures 1908A-1908F include metal, or (ii) contact structure 1908F in the set of contact structures 1908A-1908F includes a second resistor, such as an n-type resistor or a p-type resistor. In some embodiments, the contact structure including the doped resistor is formed by at least one of doping, epitaxial doping, ion implantation, molecular diffusion, or other suitable techniques.

[0351] In some embodiments, the semiconductor body 1904 includes a set of doped regions 1902A-1902E. In some embodiments, a doped region in the set of doped regions 1902A-1902E is located between two adjacent contact structures in the set of contact structures 1908A-1908F. In some embodiments, a doped region in the set of doped regions 1902A-1902E has a first conductivity type or a second conductivity type. In some embodiments, the set of doped regions 1902A-1902E is in an active region of the semiconductor device 1900. In some embodiments, a doped region in the set of doped regions 1902A-1902E corresponds to at least one of a drain or a source of at least one of a transistor, a MOS structure, a MOSFET structure, a FinFET structure, or another suitable structure.

[0352] In some embodiments, at least one of the first structure 1918, the second structure 1914, the fourth structure 1922, or the sixth structure 1926 resides in a dielectric layer (not shown) of the semiconductor device 1900. In some embodiments, at least one of the third structure 1916, the fifth structure 1920, or the seventh structure 1924 resides in a layer (not shown) of the semiconductor device 1900, such as a metal layer. In some embodiments, at least one of the first structure 1918 or the second structure 1914 corresponds to a connection element, an interconnection structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the third structure 1916 and one or more contact structures of the set of contact structures 1908A-1908F. In some embodiments, the third structure 1916 includes a metal structure. In some embodiments, the fourth structure 1922 corresponds to a connection element, an interconnection structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the fifth structure 1920 and the contact structure 1908A. In some embodiments, the fifth structure 1920 includes a metal structure. In some embodiments, the sixth structure 1926 corresponds to a connection element, an interconnection structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the seventh structure 1924 and the contact structure 1908F. In some embodiments, the seventh structure 1924 includes a metal structure.

[0353] In some embodiments, forming the semiconductor device 1900 using the second patterned layer pattern 157, such as using one or more of the techniques provided herein for forming the semiconductor device 200 using the second patterned layer pattern 157, achieves a reduced amount of metal residue on the set of contact structures 1908A-1908F as compared to using the first patterned layer pattern. In some embodiments, the reduced amount of metal residue improves at least one of: (i) electrical connection between the third structure 1916 and one or more of the contact structures in the set of contact structures 1908A-1908F, (ii) electrical connection between the fifth structure 1920 and the contact structure 1908A, or (iii) electrical connection between the seventh structure 1924 and the contact structure 1908F.

[0354] Fig. 20 A semiconductor device 2000 according to some embodiments is illustrated. In some embodiments, the semiconductor device 2000 is formed using the present invention. Figures 2 to 15B ) to form the semiconductor device 2000. In some embodiments, a component of the semiconductor device 2000 includes the semiconductor device 200 (shown in Figures 2 to 15B In some embodiments, the semiconductor device 2000 is formed using the second patterned layer image 157 .

[0355] In some embodiments, the semiconductor device 2000 includes at least one of the following: a substrate 2054, a trench isolation structure 2052 such as an STI structure, a dielectric layer 2012, a work function layer 2010, a first structure 2018, a second structure 2014, or a third structure 2016. In some embodiments, the work function layer 2010 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the dielectric layer 2012 includes at least one of PSG or other suitable materials. In some embodiments, the substrate 2054 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0356] In some embodiments, the semiconductor device 2000 includes a plurality of contact structures formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: (i) a group of contact structures corresponding to at least one of the first group of contact structures 102A-102L or the fifth group of contact structures 1504A-1504L (not shown), (ii) a group of contact structures 2008A-2008F corresponding to at least one of the second group of contact structures 104A-104F or the sixth group of contact structures, (iii) a group of contact structures corresponding to at least one of the third group of contact structures 113A-113I or the seventh group of contact structures 1508A-1508I (not shown), or (iv) a group of contact structures corresponding to at least one of the fourth group of contact structures 117A-117C or the eighth group of contact structures 1510A-1510C (not shown).

[0357] In some embodiments, at least one of the following exists: (i) the contact structure 2008A in the set of contact structures 2008A-2008F comprises polysilicon, such as at least one of intrinsic polysilicon, undoped polysilicon, or doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, (ii) the contact structures 2008B-2008E in the set of contact structures 2008A-2008F comprise metal, or (ii) the contact structure 2008F in the set of contact structures 2008A-2008F comprises polysilicon, such as at least one of intrinsic polysilicon, undoped polysilicon, or doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon. In some embodiments, the contact structure comprising doped polysilicon is formed by at least one of doping, epitaxial doping, ion implantation, molecular diffusion, or other suitable techniques.

[0358] In some embodiments, at least one of the first structure 2018 or the second structure 2014 resides in a dielectric layer (not shown) of the semiconductor device 2000. In some embodiments, the third structure 2016 resides in a layer (not shown) (such as a metal layer) of the semiconductor device 2000. In some embodiments, at least one of the first structure 2018 or the second structure 2014 corresponds to a connection element, an interconnection structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the third structure 2016 and one or more contact structures of the set of contact structures 2008A-2008F. In some embodiments, the third structure 2016 includes a metal structure.

[0359] In some embodiments, forming the semiconductor device 2000 using the second patterned layer pattern 157, such as using one or more of the techniques provided herein for forming the semiconductor device 200 using the second patterned layer pattern 157, achieves a reduced amount of metal residue on the set of contact structures 2008A-2008F as compared to using the first patterned layer pattern. In some embodiments, the reduced amount of metal residue improves electrical connection between the third structure 2016 and one or more of the contact structures in the set of contact structures 2008A-2008F.

[0360] In some embodiments, the semiconductor device 2000 includes a field-effect transistor (FET), such as an epitaxial FET. In some embodiments, the semiconductor device 2000 includes a FinFET, such as an epitaxial FinFET. In some embodiments, the semiconductor device 2000 includes a FinFET structure 2050 .

[0361] Fig.21 A semiconductor device 2100 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 (in Figures 2 to 15B ) to form the semiconductor device 2100. In some embodiments, a component of the semiconductor device 2100 includes the semiconductor device 200 (shown in Figures 2 to 15B In some embodiments, the semiconductor device 2100 is formed using the second patterned layer image 157 .

[0362] In some embodiments, the semiconductor device 2100 includes at least one of the following: a substrate 2154, a trench isolation structure 2152 such as an STI structure, a dielectric layer 2112, a work function layer 2110, a first structure 2118, a second structure 2114, a third structure 2116, or a fourth structure 2120. In some embodiments, the work function layer 2110 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the dielectric layer 2112 includes at least one of PSG or other suitable materials. In some embodiments, the substrate 2154 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0363] In some embodiments, the semiconductor device 2100 includes a plurality of contact structures formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: (i) a group of contact structures corresponding to at least one of the first group of contact structures 102A-102L or the fifth group of contact structures 1504A-1504L (not shown), (ii) a group of contact structures 2108A-2108C corresponding to at least one of the second group of contact structures 104A-104F or the sixth group of contact structures, (iii) a group of contact structures corresponding to at least one of the third group of contact structures 113A-113I or the seventh group of contact structures 1508A-1508I (not shown), or (iv) a group of contact structures corresponding to at least one of the fourth group of contact structures 117A-117C or the eighth group of contact structures 1510A-1510C (not shown).

[0364] In some embodiments, at least one of the following situations exists: (i) the contact structure 2108A in the group of contact structures 2108A~2108C includes polysilicon, such as intrinsic polysilicon, undoped polysilicon, or at least one of doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, (ii) the contact structure 2108B in the group of contact structures 2108A~2108C includes polysilicon, such as intrinsic polysilicon, undoped polysilicon, or at least one of doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, or (ii) the contact structure 2108C in the group of contact structures 2108A~2108C includes polysilicon, such as intrinsic polysilicon, undoped polysilicon, or at least one of doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon. In some embodiments, the contact structure including doped polysilicon is formed by at least one of doping, epitaxial doping, ion implantation, molecular diffusion, or other suitable techniques.

[0365] In some embodiments, at least one of the first structure 2118 or the second structure 2114 resides in a dielectric layer (not shown) of the semiconductor device 2100. In some embodiments, at least one of the third structure 2116 or the fourth structure 2120 resides in a layer (not shown) of the semiconductor device 2100, such as a metal layer. In some embodiments, at least one of the first structure 2118 or the second structure 2114 corresponds to a connection element, an interconnect structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the contact structure 2108B and at least one of the third structure 2116 or the fourth structure 2120, respectively. In some embodiments, at least one of the third structure 2116 or the fourth structure 2120 includes a metal structure. In some embodiments, the semiconductor device 2000 includes a resistive component, such as a high resistance device. In some embodiments, the semiconductor device 2000 implements resistance in a circuit including a connection through at least one of the third structure 2116, the fourth structure 2120, or the contact structure 2108B. In some embodiments, the resistance depends on one or more characteristics of the contact structure 2108B.

[0366] In some embodiments, forming the semiconductor device 2000 using the second patterned layer pattern 157, such as using one or more of the techniques provided herein for forming the semiconductor device 200 using the second patterned layer pattern 157, achieves a reduced amount of metal residue on the set of contact structures 2108A-2108C as compared to using the first patterned layer pattern. In some embodiments, the reduced amount of metal residue improves electrical connection between the contact structure 2108B and at least one of the third structure 2116 or the fourth structure 2120.

[0367] Fig. 22A semiconductor device 2200 according to some embodiments is illustrated. In some embodiments, the semiconductor device 200 (in Figures 2 to 15B ) to form the semiconductor device 2200. In some embodiments, a component of the semiconductor device 2200 includes the semiconductor device 200 (shown in Figures 2 to 15B In some embodiments, the semiconductor device 2200 is formed using the second patterned layer image 157 .

[0368] In some embodiments, the semiconductor device 2200 includes at least one of the following: a substrate 2254, a trench isolation structure 2252 such as an STI structure, a dielectric layer 2212, a work function layer 2210, a first structure 2218, a second structure 2214, a third structure 2216, or a fourth structure 2220. In some embodiments, the work function layer 2210 includes at least one of a nitride material such as silicon nitride, one or more metals, a metal nitride such as titanium nitride, or one or more other suitable materials. In some embodiments, the dielectric layer 2212 includes at least one of PSG or other suitable materials. In some embodiments, the substrate 2254 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0369] In some embodiments, the semiconductor device 2200 includes a plurality of contact structures formed according to the contact structure diagram 115. In some embodiments, the plurality of contact structures include at least one of the following: (i) a group of contact structures corresponding to at least one of the first group of contact structures 102A-102L or the fifth group of contact structures 1504A-1504L (not shown), (ii) a group of contact structures 2208A-2208C corresponding to at least one of the second group of contact structures 104A-104F or the sixth group of contact structures, (iii) a group of contact structures corresponding to at least one of the third group of contact structures 113A-113I or the seventh group of contact structures 1508A-1508I (not shown), or (iv) a group of contact structures corresponding to at least one of the fourth group of contact structures 117A-117C or the eighth group of contact structures 1510A-1510C (not shown).

[0370] In some embodiments, at least one of the following situations exists: (i) the contact structure 2208A in the group of contact structures 2208A~2208C includes polysilicon, such as intrinsic polysilicon, undoped polysilicon, or at least one of doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, (ii) the contact structure 2208B in the group of contact structures 2208A~2208C includes polysilicon, such as intrinsic polysilicon, undoped polysilicon, or at least one of doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon, or (ii) the contact structure 2208C in the group of contact structures 2208A~2208C includes polysilicon, such as intrinsic polysilicon, undoped polysilicon, or at least one of doped polysilicon such as n-type doped polysilicon or p-type doped polysilicon. In some embodiments, the contact structure including doped polysilicon is formed by at least one of doping, epitaxial doping, ion implantation, molecular diffusion, or other suitable techniques.

[0371] In some embodiments, at least one of the first structure 2218 or the second structure 2214 resides in a dielectric layer (not shown) of the semiconductor device 2200. In some embodiments, at least one of the third structure 2216 or the fourth structure 2220 resides in a layer (not shown) of the semiconductor device 2200, such as a metal layer. In some embodiments, at least one of the first structure 2218 or the second structure 2214 corresponds to a connection element, an interconnect structure, a contact, a via, a metal line, etc., used to establish an electrical connection between the contact structure 2208B and at least one of the third structure 2216 or the fourth structure 2220, respectively. In some embodiments, at least one of the third structure 2216 or the fourth structure 2220 includes a metal structure. In some embodiments, the semiconductor device 2000 includes a resistive component, such as a high resistance device. In some embodiments, the semiconductor device 2000 implements resistance in a circuit including a connection through at least one of the third structure 2216, the fourth structure 2220, or the contact structure 2208B. In some embodiments, the resistance depends on one or more characteristics of the contact structure 2208B.

[0372] In some embodiments, forming the semiconductor device 2000 using the second patterned layer pattern 157, such as using one or more of the techniques provided herein for forming the semiconductor device 200 using the second patterned layer pattern 157, achieves a reduced amount of metal residue on the set of contact structures 2208A-2208C as compared to using the first patterned layer pattern. In some embodiments, the reduced amount of metal residue improves electrical connection between the contact structure 2208B and at least one of the third structure 2216 or the fourth structure 2220.

[0373] In some embodiments, the semiconductor device 2200 includes a FET, such as an epitaxial FET. In some embodiments, the semiconductor device 2200 includes a FinFET, such as an epitaxial FinFET. In some embodiments, the semiconductor device 2200 includes a FinFET structure 2250 .

[0374] In some embodiments, a method for forming a Figures 1A to 22 Display and / or reference Figures 1A to 22 One, some or all of the features, components, structures, etc. provided herein are described.

[0375] Embodiments are contemplated in which a first layer patterning unit, such as the first lithographic mask 1108, is used to pattern a layer different from the second oxide layer 902, such as at least one of a semiconductor layer, a metal layer, an epitaxial layer, a dielectric layer, or another type of layer. In some embodiments, one, some, or all examples of the term "oxide layer" may be supplemented or replaced with at least one of a "semiconductor layer," a "metal layer," an "epitaxial layer," a "dielectric layer," or another type of layer.

[0376] According to some embodiments, Fig.23 The method 2300 is illustrated in FIG. 2302. At 2302, a first hot spot region of the contact structure graph is determined. In some embodiments, the first hot spot region corresponds to the first hot spot region 120 (in Figure 1B ). At 2304, the first hot spot area is enlarged according to the first predefined enlarged profile to determine the first enlarged area of ​​the contact structure diagram. In some embodiments, the first enlarged area corresponds to the first enlarged area 118. At 2306, it is determined that the functional area of ​​the functional component overlaps with the first portion of the first enlarged area. In some embodiments, the functional area corresponds to at least one of the functional area 137 or the functional area 139. At 2308, a cutout area of ​​the contact structure diagram that does not include the first portion of the first enlarged area is determined. In some embodiments, the cutout area corresponds to the cutout area 135. At 2310, the first patterned oxide layer map is updated based on the cutout area to generate an updated patterned oxide layer map. In some embodiments, the first patterned oxide layer map corresponds to the first patterned layer map. In some embodiments, the updated patterned oxide layer map corresponds to the second patterned layer map 157.

[0377] According to some embodiments, Fig.242400. At 2402, a first region of the contact structure map is determined. In some embodiments, the first region corresponds to the cutout region 135. At 2404, a second region of the contact structure map is determined. In some embodiments, the second region corresponds to at least one of the second enlarged region 119 or the fourth enlarged region 183. At 2406, in response to determining that the resistance region does not overlap with the first region and overlaps with the second region, the first patterned oxide layer map is updated to generate an updated patterned oxide layer map defining a first patterned oxide layer residing in the first region and not residing in the second region. In some embodiments, the first patterned oxide layer map corresponds to the first patterned layer map. In some embodiments, the updated patterned oxide layer map corresponds to the second patterned layer map 157. In some embodiments, the first patterned oxide layer corresponds to the second patterned oxide layer 1302.

[0378] In some embodiments, the first patterned oxide layer map defines a second patterned oxide layer that does not reside in the first region. In some embodiments, the second patterned oxide layer corresponds to a third patterned oxide layer associated with the first wafer.

[0379] According to some embodiments, Fig.25 25. The method 2500 is illustrated in FIG. 25. At 2502, a first region of a contact structure diagram is determined. In some embodiments, the first region corresponds to the first hot spot region 120. At 2504, a functional region of a functional component is determined to overlap with a first portion of the first region. In some embodiments, the functional region corresponds to at least one of the functional region 137 or the functional region 139. At 2506, a cutout region of the contact structure diagram that does not include a first portion of the first enlarged region is determined. In some embodiments, the cutout region corresponds to the cutout region 135. At 2508, a first patterned oxide layer map is updated based on the cutout region to generate an updated patterned oxide layer map that defines a patterned oxide layer residing in the cutout region. In some embodiments, the first patterned oxide layer map corresponds to the first patterned layer map. In some embodiments, the updated patterned oxide layer map corresponds to the second patterned layer map 157. In some embodiments, the patterned oxide layer corresponds to the second patterned oxide layer 1302. At 2510, an oxide layer patterning unit is manufactured based on the updated patterned oxide layer map. In some embodiments, the oxide layer patterning unit includes a first lithographic mask 1108.

[0380] One or more embodiments are directed to a computer-readable medium comprising processor-executable instructions to implement one or more of the techniques presented herein. Fig.262600, wherein an exemplary computer-readable medium is illustrated, wherein an embodiment 2600 includes a computer-readable medium 2608 (e.g., a CD-R, DVD-R, flash drive, hard drive disk, etc.) having computer-readable data 2606 encoded thereon. This computer-readable data 2606 in turn includes a set of processor-executable computer instructions 2604, which, when executed by a processor, implement one or more of the principles set forth herein. In some embodiments 2600, the processor-executable computer instructions 2604 are used to implement a method 2602 when executed by a processor, such as at least some of the aforementioned methods. In some embodiments, the processor-executable computer instructions 2604 are used to implement a system when executed by a processor, such as at least some of one or more of the aforementioned systems. In some embodiments, the processor-executable computer instructions 2604 are used to implement a device when executed by a processor, such as at least some of one or more of the aforementioned devices. Those skilled in the art may devise many such computer-readable media for operating in accordance with the techniques presented herein.

[0381] In some embodiments, a method is provided. The method includes determining a first hot spot region of a contact structure diagram. The method includes enlarging the first hot spot region according to a first predefined enlarged profile to determine a first enlarged region of the contact structure diagram. The method includes determining that a first portion of the first enlarged region overlaps a functional region of a functional component. The method includes determining a cutout region of the contact structure diagram that does not include the first portion of the first enlarged region. The method includes updating a first patterned oxide layer map based on the cutout region to generate an updated patterned oxide layer map.

[0382] In some embodiments, the first hot spot region is determined based on the location of defects in a wafer manufactured based on the first patterned oxide layer map. In some embodiments, the first patterned oxide layer map defines a first patterned oxide layer that does not reside in the cut region, and the updated patterned oxide layer map defines a second patterned oxide layer that resides in the cut region. In some embodiments, an oxide layer patterning unit is manufactured based on the updated patterned oxide layer map. In some embodiments, an oxide layer is formed on a semiconductor body and the oxide layer is patterned using an oxide layer patterning unit to form a patterned oxide layer. In some embodiments, the oxide layer patterning unit includes a lithography mask, and the patterned oxide layer includes patterning the oxide layer using a lithography mask to form a patterned oxide layer. In some embodiments, a photoresist is formed on the oxide layer, light from a light source is directed to the photoresist through the lithography mask to produce an exposed photoresist, a developer is applied to the exposed photoresist to form a patterned photoresist, and the oxide layer is patterned using the patterned photoresist to form a patterned oxide layer. In some embodiments, the first hot spot region includes at least a first contact structure including a metal or a second contact structure including polysilicon. In some embodiments, the functional component comprises a doped polycrystalline structure. In some embodiments, the cut-out region does not include a second portion of the first enlarged region that does not overlap with the functional region.

[0383] In some embodiments, a method is provided. The method includes determining a first region of a contact structure map. The method includes determining a second region of the contact structure map. The method includes updating a first patterned oxide layer map in response to determining that the resistive region does not overlap with the first region and overlaps with the second region to generate an updated patterned oxide layer map defining a first patterned oxide layer that resides in the first region and does not reside in the second region.

[0384] In some embodiments, the first patterned oxide layer map defines a second patterned oxide layer that does not reside in the first region. In some embodiments, an oxide layer patterning unit is manufactured based on the updated patterned oxide layer map. In some embodiments, an oxide layer is formed on a semiconductor body and the oxide layer is patterned using an oxide layer patterning unit to form a patterned oxide layer. In some embodiments, the oxide layer patterning unit includes a lithographic mask and the patterned oxide layer includes forming a photoresist on the oxide layer, directing light from a light source through the lithographic mask to the photoresist to produce an exposed photoresist, applying a developer to the exposed photoresist to form a patterned photoresist, and patterning the oxide layer using the patterned photoresist to form a patterned oxide layer. In some embodiments, the first region includes at least a first contact structure including a metal or a second contact structure including polysilicon and the second region includes at least a third contact structure including a metal or a fourth contact structure including polysilicon. In some embodiments, defects are detected in a wafer manufactured based on a first patterned oxide layer image, a first hot spot area of ​​a contact structure image is determined based on the location of the defect, the first hot spot area is enlarged according to a first predefined enlarged profile to determine the first enlarged area of ​​the contact structure image, and a first portion of the first enlarged area is determined to overlap with a functional area of ​​a functional component, wherein the first area is a cut area that does not include the first portion of the first enlarged area.

[0385] In some embodiments, a method is provided. The method includes determining a first area of ​​a contact structure diagram. The method includes determining that a first portion of the first area overlaps with a functional area of ​​a functional component. The method includes determining a cutout area of ​​the contact structure diagram that does not include the first portion of the first area. The method includes updating a first patterned oxide layer map based on the cutout area to generate an updated patterned oxide layer map that defines a patterned oxide layer residing in the cutout area. The method includes manufacturing an oxide layer patterning unit based on the updated patterned oxide layer map.

[0386] In some embodiments, the cutout region does not include a second portion of the first region that does not overlap the functional region. In some embodiments, the oxide layer patterning unit includes a lithographic mask, and the method includes forming an oxide layer on the semiconductor body, forming a photoresist on the oxide layer, directing light from a light source through the lithographic mask to the photoresist to produce exposed photoresist, applying a developer to the exposed photoresist to form a patterned photoresist, and patterning the oxide layer using the patterned photoresist to form a patterned oxide layer.

[0387] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose or achieving the advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0388] Although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0389] Various operations of the embodiments are provided herein. The order of describing some or all of the operations should not be interpreted as meaning that these operations must rely on the order. With the benefit of this description, alternative sequencing will be understood. In addition, it will be understood that not all operations must be present in the various embodiments provided herein. In addition, it will be understood that not all operations are necessary in some embodiments.

[0390] It will be understood that, for example, for the purpose of simplicity and ease of understanding, the layers, features, elements, etc. depicted herein are illustrated with specific dimensions relative to each other, such as structural dimensions or orientations, and their actual dimensions are substantially different from the dimensions illustrated herein in some embodiments. In addition, there are a variety of techniques to form the layers, regions, features, elements, etc. mentioned herein, such as at least one of the following: etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques such as, for example, chemical vapor deposition (CVD).

[0391] In addition, "exemplary" is used herein to mean used as an example, example, illustration, etc., and is not necessarily advantageous. As used in the present application, "or" is intended to mean inclusive "or" rather than exclusive "or". In addition, unless otherwise specified or it is obvious from the context that it is for a singular form, otherwise "one" and "a kind of" used in the present application and the attached patent scope should generally be interpreted as meaning "one or more". In addition, at least one of A and B and / or the like generally means A or B or both A and B. In addition, with respect to the "including", "having", "having", "with" or their variants used, such terms are intended to be included in a manner similar to the term "comprising". In addition, unless otherwise specified, "first", "second" or the like are not intended to imply time aspect, space aspect, sorting, etc. Instead, such terms are merely used as identifiers, names, etc. of features, elements, items, etc. For example, the first element and the second element generally correspond to element A and element B or two different or two identical elements or the same element.

[0392] In addition, although the present disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art based on the reading and understanding of this specification and the accompanying drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component (e.g., functionally equivalent) that performs the specified function of the described component, even if the structure is not equivalent to the disclosed structure. In addition, although a particular feature of the present disclosure may have been disclosed only with respect to one of several embodiments, such a feature may be combined with one or more other features of other embodiments as may be desired and advantageous for any given or particular application.

Claims

1. A method for designing a semiconductor structure, characterized in that: The following steps are involved: Determining a first hot spot area of ​​a contact structure diagram; Enlarging the first hot spot region according to a first predefined enlargement profile to determine a first enlarged region of the contact structure diagram; Determining that a first portion of the first enlarged area overlaps with a functional area of ​​a functional component; determining a cutout region of the first portion of the contact structure diagram that does not include the first expanded region; and A first patterned oxide layer map is updated based on the cut region to generate an updated patterned oxide layer map.

2. The method for designing a semiconductor structure according to claim 1, wherein: in: The first patterned oxide layer image defines a first patterned oxide layer that does not reside in the cutout region; and The updated patterned oxide layer map defines a second patterned oxide layer residing in the cutout region.

3. The method for designing a semiconductor structure according to claim 1, wherein: The following steps are involved: An oxide layer patterning unit is manufactured based on the updated patterned oxide layer map.

4. The method for designing a semiconductor structure according to claim 3, characterized in that: The following steps are involved: forming an oxide layer over a semiconductor body; and The oxide layer patterning unit is used to pattern the oxide layer to form a patterned oxide layer.

5. A method for designing a semiconductor structure, characterized in that: The following steps are involved: determining a first region of a contact structure map; determining a second region of the contact structure map; In response to determining that a resistive region does not overlap the first region and overlaps the second region, a first patterned oxide layer map is updated to generate an updated patterned oxide layer map defining a first patterned oxide layer residing in the first region and not residing in the second region.

6. The method for designing a semiconductor structure according to claim 5, wherein: The following steps are involved: An oxide layer patterning unit is manufactured based on the updated patterned oxide layer map.

7. The method for designing a semiconductor structure according to claim 6, wherein: The following steps are involved: forming an oxide layer over a semiconductor body; and The oxide layer patterning unit is used to pattern the oxide layer to form a patterned oxide layer.

8. The method for designing a semiconductor structure according to claim 5, wherein: The following steps are involved: detecting a defect in a wafer manufactured based on the first patterned oxide layer pattern; Determining a first hot spot area of ​​the contact structure diagram based on a position of the defect; Enlarging the first hot spot region according to a first predefined enlargement profile to determine a first enlarged region of the contact structure diagram; and It is determined that a first portion of the first enlarged area overlaps with a functional area of ​​a functional component, wherein the first area is a cutout area that does not include the first portion of the first enlarged area.

9. A method for designing a semiconductor structure, characterized in that: The following steps are involved: determining a first region of a contact structure map; Determining that a first portion of the first area overlaps with a functional area of ​​a functional component; determining a cutout region of the first portion of the contact structure diagram that does not include the first region; updating a first patterned oxide layer map based on the cut region to generate an updated patterned oxide layer map defining a patterned oxide layer residing in the cut region; and An oxide layer patterning unit is manufactured based on the updated patterned oxide layer map.

10. The method for designing a semiconductor structure according to claim 9, wherein: in: The oxide layer patterning unit includes a lithography mask; and The method comprises the following steps: forming an oxide layer on a semiconductor body; forming a photoresist on the oxide layer; directing light from a light source through the lithographic mask to the photoresist to produce an exposed photoresist; applying a developer to the exposed photoresist to form a patterned photoresist; and The oxide layer is patterned using the patterned photoresist to form the patterned oxide layer.

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