Simulation optimization method compatible with different layers of via hole fan-out performance

Abstract

The invention relates to a simulation optimization method compatible with fan-out performance of different layers of via holes. The method comprises the following steps: establishing a plurality of via holes of different layers of fan-out wires in the same model; grouping a plurality of ground plane reference layers of the via hole with the maximum layer span; each group of ground plane reference layer is configured with an independent anti-pad size variable; determining an anti-pad size variable combination of each via hole; setting an optimization target; and simulating all the via holes according to the anti-pad size variable combination of the model and the optimization target. According to the model, all ground plane reference layers of the long via hole with the maximum layer change span are divided into a plurality of groups, and each group is configured with an independent anti-pad size variable, so that the problem that a simulation result does not conform to expectation under a high-frequency condition is solved, and a set of anti-pad variable combination is established; a plurality of via holes of different layers of fan-out wires share the set of anti-pad variable combination for scanning optimization, and an anti-pad size combination compatible with the via holes of the upper layer of fan-out wires and the via holes of the lower layer of fan-out wires can be obtained through simulation at the same time.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a simulation optimization method compatible with fan-out performance of vias at different layers. Background Art

[0002] Printed Circuit Board (PCB), also known as printed circuit board, is an important component of the physical support and signal transmission of electronic products. The optimization of high-speed vias is generally completed through 3D simulation software. The usual practice is to set a unified default value for the via anti-pads of all layers, and then define the anti-pad parameters as variable parameters, set the optimization target, and start the software to automatically scan the variable parameters to simulate the best optimization solution.

[0003] For example, using 3D simulation software (HFSS), the anti-pad size of all layers is set as variable R, and the return loss of the via at a frequency of 20GHz is used as the optimization target, and efforts are made to find the ideal parameter value that makes the return loss less than -25dB, and then the optimization result is obtained through automatic scanning simulation by the software. Due to the high optimization frequency (up to 20GHz), after a comprehensive scan, selecting the best one from multiple simulation results may not necessarily achieve the set goal. Finally, it is necessary to manually fine-tune the size based on the optimal result to obtain a more ideal simulation result, which is very time-consuming.

[0004] In addition, there are multiple vias in the circuit design project, and different vias have different layer changes, that is, each via has different fan-out routing from the surface board to a certain inner board. For example, via A changes layers from the surface board to the 6th layer board and via B changes layers from the surface board to the 12th layer board. The above method is time-consuming, and it is found that the anti-pad parameters applicable to via A cannot be directly applied to via B. Therefore, for vias with different layer changes, the above simulation debugging method can only be repeated, which is very inconvenient.

[0005] Therefore, there is an urgent need for a more effective via simulation optimization method that can not only efficiently obtain results that meet the optimization goals, but also solve the optimization needs of two or more via models of fan-out routing on different layers. Summary of the invention

[0006] In order to overcome the low efficiency of existing simulation optimization methods, especially the optimization problem of vias for fan-out routings on multiple different layers, the present invention provides a simulation optimization method that is compatible with the fan-out performance of vias on different layers.

[0007] The technical solution of the present invention is as follows:

[0008] A simulation optimization method compatible with fan-out performance of vias in different layers includes the following steps:

[0009] Step 1: Create several vias of fan-out routing on different layers in the same model;

[0010] Step 2, grouping multiple ground plane reference layers of vias with the largest layer span;

[0011] Define the via with the largest layer-changing span as a long via, and divide the multiple ground plane reference layers that the long via passes through into several groups;

[0012] Step 3: Each set of ground plane reference layers is configured with an independent anti-pad size variable;

[0013] Step 4, determine the anti-pad size variable combination of each via;

[0014] According to the ground plane reference layer group that each via passes through, determine the anti-pad size variable corresponding to the ground plane reference layer group, and obtain the anti-pad size variable combination of each via;

[0015] Step 5: Set an optimization goal that constrains all via simulations;

[0016] Step 6: Simulate all vias based on the model's anti-pad size variable combination and optimization goals.

[0017] As a preferred technical solution of the present invention, the size of the anti-pad is defined as: from the center of the long via to the edge of the anti-pad.

[0018] As a preferred technical solution of the present invention, the step 1 specifically includes the following steps:

[0019] Step 101, establishing a multi-layer circuit board model;

[0020] Step 102: in the multi-layer circuit board model, first establish a via hole with the largest layer change span and its anti-pad structure;

[0021] Step 103: Create other vias to be simulated in the same multi-layer circuit board model, and copy the anti-pad structure of the previous step to each via.

[0022] As a preferred technical solution of the present invention, the step 2 specifically includes the following steps:

[0023] Step 201, defining a via with the largest layer-changing span as a long via, and dividing the long via into a number of unit vias;

[0024] Step 202: The ground plane reference layers passed by the same unit via are grouped together, so as to group multiple ground plane reference layers into a plurality of groups.

[0025] Furthermore, the lengths of the plurality of unit vias are equal.

[0026] Preferably, the length of the unit via is 1 mm.

[0027] As a preferred technical solution of the present invention, the specific steps of step 3 are: each group of ground plane reference layers is configured with an anti-pad size value, and several anti-pad size values ​​are set as variables, so that the model has several independent anti-pad size variables.

[0028] As a preferred technical solution of the present invention, the step 5 specifically includes the following steps:

[0029] Step 501, selecting signal return loss as an optimization criterion;

[0030] Step 502: Select a frequency value in the high frequency band as a target frequency;

[0031] Step 503: setting a target value of return loss at the target frequency according to signal quality requirements;

[0032] Step 504: All vias are set using the optimization target of the previous step.

[0033] Preferably, the target frequency in step 502 is 20 GHz, and the target value in step 503 is -25 dB.

[0034] As a preferred technical solution of the present invention, the step 6 specifically includes the following steps:

[0035] Step 601, setting a starting scan value, a scan range and a scan step value of a plurality of anti-pad size variables;

[0036] Step 602, traversing a plurality of anti-pad size combinations according to the scanning parameters, and simulating to obtain return loss curves of each via under different anti-pad size combinations;

[0037] Step 603: the system automatically selects several anti-pad size combinations and simulation results that make all via simulation results meet the optimization target;

[0038] Step 604: Select a set of combination parameters that can make the return loss results of each via hole relatively ideal from among the screened anti-pad size combinations.

[0039] Further, in step 604, the criterion for judging whether the return loss result of each via hole is ideal is one of the following conditions:

[0040] At the target frequency, the difference between the target values ​​of all return losses is less than 1dB;

[0041] All return loss curves in the entire operating frequency band are smoother without sharp fluctuations or peaks.

[0042] Preferably, in step 601, the scanning range is 12 mil to 22 mil, and the scanning step value is 1×10 - 5 mil, 1×10 -8 mil or 1×10 -10 mil.

[0043] The present invention according to the above scheme has the following beneficial effects:

[0044] The anti-pad size parameter of the via of the present invention is no longer set to a uniform value, but takes into account the difference in capacitance or inductance at different positions of the via, and applies different anti-pad parameters to several ground plane reference layers. Specifically, all ground plane reference layers of the long via with the largest layer change span are divided into several groups, and each group is configured with an independent anti-pad size variable. Not only can high-performance vias with the best anti-pad parameter combination that meet the set goals be scanned and simulated, and the problem that the simulation results do not meet expectations under high frequency conditions can be solved; a set of anti-pad variable combination parameters are established for the model, so that multiple vias of fan-out routings on different layers share a set of anti-pad variable combination parameters for scanning and optimization, so as to realize synchronous simulation operation of all vias, and obtain an anti-pad size combination that is compatible with the upper fan-out routing vias and the lower fan-out routing vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of the method of the present invention;

[0046] Figure 2 It is a structural schematic diagram of a via model of the present invention;

[0047] Figure 3 is a plan view of a via model of the present invention;

[0048] Figure 4 It is a wave loss curve diagram of two vias under a set of optimal anti-pad size combinations in a specific embodiment.

[0049] In the figure,

[0050] 1. Circuit board; 2. Via; 3. Anti-pad; 4. Surface routing; 5. Inner fan-out routing. DETAILED DESCRIPTION

[0051] In order to better understand the purpose, technical scheme and technical effect of the present invention, the present invention is further explained in conjunction with the accompanying drawings and embodiments. It should be noted that similar numbers and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, it is stated that the embodiments described below are only used to explain the present invention and are not used to limit the present invention.

[0052] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element, and when an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time. The term "several" means two or more, unless otherwise clearly and specifically defined.

[0053] like Figures 1 to 3 As shown, a simulation optimization method compatible with fan-out performance of vias in different layers includes the following steps:

[0054] Step 1: Create several vias of fan-out routing on different layers in the same model. Step 1 specifically includes the following steps:

[0055] Step 101, establishing a multi-layer circuit board model;

[0056] Step 102: in the multi-layer circuit board model, first establish a via hole with the largest layer change span and its anti-pad structure;

[0057] Step 103: Create other vias to be simulated in the same multi-layer circuit board model, and copy the anti-pad structure of the previous step to each via.

[0058] In this embodiment, the circuit board 1 of the model is a multilayer board, such as a 12-layer board, a 14-layer board, a 16-layer board or other layer board, and the multilayer board has two pairs of differential vias, the top of the differential via A is connected to the surface trace 4, penetrates from the surface board, and fans out the trace on the 12th layer board, that is, the differential via A has an inner fan-out trace 5 on the 12th layer board, and the layer-changing structure of the differential via A is from the surface to the 12th layer board. The top of the differential via B is connected to the surface trace 4, penetrates from the surface board, and fans out the trace on the 6th layer board, that is, the differential via B has an inner fan-out trace 5 on the 6th layer board, and the layer-changing structure of the differential via B is from the surface to the 6th layer board.

[0059] First, establish the differential via A with the largest layer-changing span and the anti-pad structure of the differential via A, then establish the differential via B in this multi-layer circuit board model, and copy the anti-pad structure of the differential via A to the differential via B. The size of the anti-pad 3 is defined as: from the center of the long via 2 to the edge of the anti-pad 3, that is, R. In other optional embodiments, the distance from the edge of the via to the edge of the anti-pad can be used as the size of the anti-pad.

[0060] Step 2, grouping multiple ground plane reference layers of vias with the largest layer span;

[0061] Define the via with the largest layer change span as a long via, and divide the multiple ground plane reference layers passed by the long via into several groups, specifically including the following steps:

[0062] Step 201, defining a via with the largest layer-changing span as a long via, and dividing the long via into a number of unit vias;

[0063] Step 202: The ground plane reference layers passed by the same unit via are grouped together, so as to group multiple ground plane reference layers into a plurality of groups.

[0064] In this embodiment, the differential via A is defined as a long via, and the differential via A with a length of 4 mm can be subdivided into four unit vias along its axial direction according to the division length of each 1 mm, and the several ground plane reference layers passed by each unit via are grouped together. It can be seen that the lengths of the several unit vias in this embodiment are equal. In other optional embodiments, the differential via A can be divided into several unit vias of different lengths.

[0065] Step 3: Each set of ground plane reference layers is configured with an independent anti-pad size variable;

[0066] The specific steps are as follows: each group of ground plane reference layers is configured with an anti-pad size value, and several anti-pad size values ​​are set as variables, so that the model has several independent anti-pad size variables.

[0067] In this embodiment, the four unit vias of the differential via A are configured with four anti-pad size variables R1, R2, R3, and R4.

[0068] It can be seen from steps 2 and 3 that the several ground plane reference layers of the differential via A no longer use the same anti-pad parameter structure, but take into account the capacitance or inductance differences at different positions of the via, and apply different anti-pad parameters to the several ground plane reference layers. The anti-pad size value of each group of ground plane reference layers is set as a variable variable, so that the model has several anti-pad size variables, and several anti-pad size variables are allowed to be adjusted independently, so that a set of anti-pad variable combinations containing several anti-pad size variables can be obtained to adapt to the differences in electrical characteristics at various positions and improve the authenticity and accuracy of the simulation.

[0069] After the previous three steps, the anti-pad parameters of the two via structures can be set to the same set. Specifically, execute

[0070] Step 4, determining the anti-pad size variable combination of each via; specifically, determining the anti-pad size variable corresponding to the ground plane reference layer group according to the ground plane reference layer group passed by each via, and obtaining the anti-pad size variable combination of each via;

[0071] In this embodiment, according to the ground plane reference layer (from the surface layer to the 6th layer of the board) through which the differential via B passes, there are corresponding anti-pad size variables R1 and R2, so the anti-pad size variable combination of the differential via B is R1+R2. It can be seen that the differential via A and the differential via B use the same set of anti-pad parameters, which are based on the four anti-pad size variables R1, R2, R3, and R4. Therefore, during the simulation process, the differential via A and the differential via B change synchronously.

[0072] Step 5: Set an optimization target, and the optimization target constrains the simulation of all vias; the optimization target can be return loss, insertion loss or crosstalk suppression; this embodiment uses return loss as the optimization target. Return loss is an important parameter to measure the degree of signal reflection, which is particularly critical for high-frequency applications because it directly affects the integrity and transmission efficiency of the signal. Specifically, the following steps are included:

[0073] Step 501, selecting signal return loss as an optimization criterion;

[0074] Step 502: Select a frequency value in the high frequency band as a target frequency;

[0075] Step 503: setting a target value of return loss at the target frequency according to signal quality requirements;

[0076] Step 504: All vias are set using the optimization target of the previous step.

[0077] In this embodiment, the target frequency is 20 GHz, and the target value is -25 dB, that is, at a frequency of 20 GHz, the expected return loss should not exceed -25 dB to minimize signal reflection, thereby improving the quality and efficiency of signal transmission. Therefore, the return loss objectives of differential via A and differential via B are set together, and both are set to meet the 20 GHz, -25 dB index.

[0078] In other optional embodiments, different high frequency bands (such as 18 GHz, 22 GHz, etc.) can be selected as target frequencies according to different application fields or working environments; according to specific signal quality and system requirements, the target value of return loss (such as -20dB, -30dB, etc.) can be adjusted to adapt to different design standards and performance indicators.

[0079] Step 6: Simulate all vias according to the anti-pad size variable combination of the model and the optimization target, including the following steps:

[0080] Step 601, setting a starting scan value, a scan range and a scan step value of a plurality of anti-pad size variables;

[0081] Determine the starting scan value of each anti-pad size variable, define the scan range of each anti-pad size variable, and set the step increment for each scan. In this embodiment, the scan range and scan step increment of the four anti-pad size variables are the same. Among them, the scan range is 12mil to 22mil; this range covers common anti-pad sizes, ensuring that the optimization process can cover a wide enough range of possibilities. The scan step value is 1×10 -5 mil, 1×10 -8 mil or 1×10 -10 mil; The appropriate step value depends on the specific optimization requirements and the availability of computing resources. Smaller step values ​​can provide higher accuracy but increase simulation time and computational complexity.

[0082] Step 602, traversing a plurality of anti-pad size combinations according to the scanning parameters, and simulating to obtain return loss curves of each via under different anti-pad size combinations;

[0083] In this embodiment, the scanning range is 12mil to 22mil, and the scanning step value is 1×10 -8 mil, traverse different combinations of anti-pad size variables R1, R2, R3, and R4, and obtain multiple return loss curves about differential via A and multiple return loss curves about differential via B under each combination.

[0084] Step 603: the system automatically selects several anti-pad size combinations that make all via simulation results meet the optimization target, and corresponding via return loss curves under the combinations;

[0085] In this embodiment, the system automatically screens out anti-pad size combinations 1, 2, and 3 that can make the return loss curves of differential via A and differential via B meet the indicators according to the set optimization target: (20GHz, -25dB), as well as three return loss curves of differential via A and three return loss curves of differential via B under combinations 1 to 3; the return loss curve of differential via A and the return loss curve of differential via B are displayed in two curve graphs, respectively.

[0086] Step 604: Select a set of combination parameters that can make the return loss results of each via hole relatively ideal from among the screened anti-pad size combinations.

[0087] In this embodiment, by observing the three return loss curves A1, A2, and A3 of the differential via A in the curve graph A, and the three return loss curves B1, B2, and B3 of the differential via B in the curve graph B, an anti-pad size combination is selected, and the return loss curves of the differential via A and the differential via B are relatively ideal.

[0088] Among them, whether the return loss result of the via is ideal can be judged based on one of the following conditions:

[0089] a. At the target frequency, the difference between the target values ​​of all return losses is less than 1dB;

[0090] b. All return loss curves in the entire operating frequency band are smoother, without sharp fluctuations or peaks.

[0091] In this embodiment, by condition a, it can be selected that under the anti-pad size combination of R1 = 15.69mil, R2 = 20.98mil, R3 = 21.34mil, and R4 = 20.98mil, the return loss curve A3 and the return loss curve B3 are both relatively ideal. Figure 4 .

[0092] In summary, the present invention establishes a variable parameter combination with the anti-pad of a long via, as the same set of variable parameters for all vias on the model, so that multiple vias of fan-out routings of different layers share a set of anti-pad parameters for scanning optimization, and all vias can be simulated and calculated synchronously, and a combination of anti-pad parameters compatible with the upper fan-out routing vias and the lower fan-out routing vias is obtained. There is no need to optimize a set of parameters for each layer, and then the design engineer designs the anti-pad for the via fan-out structure layer by layer, which saves a lot of time in simulation, and is also very friendly to the design engineer, without spending a lot of energy to design the anti-pad layer by layer, and this method is worth promoting.

[0093] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A simulation optimization method compatible with fan-out performance of vias at different layers, comprising the following steps: Step 1: Create several vias of fan-out routing on different layers in the same model; Step 2, grouping multiple ground plane reference layers of vias with the largest layer span; Step 3: Each set of ground plane reference layers is configured with an independent anti-pad size variable; Step 4, determine the anti-pad size variable combination of each via; According to the ground plane reference layer group that each via passes through, determine the anti-pad size variable corresponding to the ground plane reference layer group, and obtain the anti-pad size variable combination of each via; Step 5: Set an optimization goal that constrains all via simulations; Step 6: Simulate all vias based on the model's anti-pad size variable combination and optimization goals.

2. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 1 is characterized in that: The step 1 specifically comprises the following steps: Step 101, establishing a multi-layer circuit board model; Step 102: in the multi-layer circuit board model, first establish a via hole with the largest layer change span and its anti-pad structure; Step 103: Create other vias to be simulated in the same multi-layer circuit board model, and copy the anti-pad structure of the previous step to each via.

3. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 1 is characterized in that: The step 2 specifically includes the following steps: Step 201, defining a via with the largest layer-changing span as a long via, and dividing the long via into a number of unit vias; Step 202: The ground plane reference layers passed by the same unit via are grouped together, so as to group multiple ground plane reference layers into a plurality of groups.

4. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 1 is characterized in that: The specific steps of step 3 are: each group of ground plane reference layers is configured with an anti-pad size value, and a number of anti-pad size values ​​are set as variables, so that the model has a number of independent anti-pad size variables.

5. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 1 is characterized in that The step 5 specifically comprises the following steps: Step 501, selecting signal return loss as an optimization criterion; Step 502: Select a frequency value in the high frequency band as a target frequency; Step 503: setting a target value of return loss at the target frequency according to signal quality requirements; Step 504: All vias are set using the optimization target of the previous step.

6. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 5 is characterized in that: In step 502, the target frequency is 20 GHz, and in step 503, the target value is -25 dB.

7. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 1 is characterized in that: The size of the anti-pad is defined as: from the center of the long via to the edge of the anti-pad.

8. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 1, characterized in that: The step 6 specifically comprises the following steps: Step 601, setting a starting scan value, a scan range and a scan step value of a plurality of anti-pad size variables; Step 602, traversing a plurality of anti-pad size combinations according to the scanning parameters, and simulating to obtain return loss curves of each via under different anti-pad size combinations; Step 603: the system automatically selects several anti-pad size combinations and simulation results that make all via simulation results meet the optimization target; Step 604: Select a set of combination parameters that can make the return loss results of each via hole relatively ideal from among the screened anti-pad size combinations.

9. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 8, characterized in that: In step 601, the scanning range is 12 mil to 22 mil, and the scanning step value is 1×10 -5 mil, 1×10 -8 mil or 1×10 -10 mil.

10. The simulation optimization method for compatible fan-out performance of vias in different layers according to claim 8, characterized in that: In step 604, the criterion for judging whether the return loss result of each via hole is ideal is one of the following conditions: a. At the target frequency, the difference between the target values ​​of all return losses is less than 1dB; b. All return loss curves in the entire operating frequency band are smoother, without sharp fluctuations or peaks.

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