A memristive pulse neural network system and method

Abstract

The present invention discloses a memristor pulse neural network system and method, which belongs to the field of artificial intelligence technology. The memristor pulse neural network system provided by the present invention uses a bionic design concept to accurately simulate the synaptic structure of a biological neural network by connecting pairs of memristors of the same level in series; based on the positive and negative Hebbian plasticity rules, an adaptive learning mechanism is implemented to strengthen the computing function of the memristor's storage and computing performance; a cascaded scalable control architecture combining master control and slave control is adopted to give the system a high degree of scalability. According to the needs of specific tasks, users can flexibly adjust the scale of the neural network to achieve unlimited cascade expansion, thereby easily coping with various complex scenarios. In addition, the built-in ADC acquisition module provides a real-time feedback mechanism, which can improve the accuracy of system monitoring, speed up the response speed, and provide valuable data support for system optimization and adjustment.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a memristive pulse neural network system and method. Background Art

[0002] With the rapid advancement of AI technology, particularly in the training and inference of large-scale neural networks and deep learning models, computer system computing power requirements and energy efficiency are facing severe challenges. The traditional von Neumann architecture, with its separation of compute and storage, creates a "memory wall" problem, hindering computing power growth and increasing energy consumption, becoming a key bottleneck for the efficient operation of AI models. Faced with the urgent need for high-performance computing in AI applications, the limitations of the von Neumann architecture are becoming increasingly prominent. To address this challenge, the concept of memory-computing convergence has rapidly emerged. Memristors, as a core component of this integrated memory-computing architecture, have attracted significant attention, capable of simultaneously carrying both storage and compute functions, thus avoiding performance bottlenecks.

[0003] Memristors, with their exceptional parallel computing capabilities and ultra-high storage density, demonstrate tremendous potential for building novel computing architectures. Unlike traditional computing systems, memristors can directly perform matrix operations within neural networks, a significant boon for large-scale parallel computing tasks. Furthermore, memristors can significantly reduce data transmission frequency and energy consumption while also significantly improving computing efficiency at the hardware level, perfectly meeting the dual requirements of high-performance computing and low power consumption for future AI applications.

[0004] Against this backdrop, HP Labs proposed an innovative memristor-based Crossbar architecture. This architecture cleverly employs a cross-connected grid design, strategically placing memristors at the grid's intersections, enabling parallel execution of computing and storage at the same physical location. Compared to the von Neumann architecture, the Crossbar architecture achieves a deep fusion of computing and storage through the clever use of memristors, significantly reducing the frequent transfer of data between computing and storage units and effectively weakening the "memory wall" effect inherent in the von Neumann architecture. This groundbreaking architecture offers unique advantages for building spiking neural networks, capable of handling massive parallel computing tasks with extremely low power consumption and superior performance, and presents broad application prospects in the field of neuromorphic computing.

[0005] However, it's worth noting that existing Crossbar architectures, in practical applications, focus more on the storage function of memristors. Current implementations often employ traditional control methods to manage these novel neural network architectures, leaving the network's weight assignments still dependent on the decisions of traditional computers. While this approach improves computational efficiency to a certain extent, it fails to fully exploit the unique advantages of memristors' integrated storage and computing capabilities, particularly in terms of energy efficiency, leaving significant room for improvement. Summary of the Invention

[0006] The purpose of the present invention is to provide a memristor pulse neural network system and method to overcome the problem that the neural network architecture using memristors in the prior art focuses on storage functions while ignoring its computing potential, resulting in limited room for improvement in energy consumption optimization.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] A memristive pulse neural network system includes a driving source module, including a positive driving source, a directional driving source, and a negative driving source, for switching the state of the memristive pulse neural network system;

[0009] A memristive pulse neural network includes at least one input memristor group and at least one bias memristor group, wherein the input memristor group is formed by connecting a plurality of first basic structures in parallel, wherein the first basic structure is a pair of same-level positive-connected input memristors connected in series, and each of the same-level positive-connected input memristors is provided with an independent switch; the bias memristor group is formed by connecting a plurality of second basic structures in parallel, wherein the second basic structure is a pair of same-level reverse-connected bias memristors connected in series, and each of the same-level reverse-connected bias memristors is provided with an independent switch; a positive drive source is connected to the positive end of the first basic structure and the negative end of the second basic structure, a directional drive source is connected to the series node of the first and second basic structures, and a negative drive source is connected to the positive end of the first basic structure and the negative end of the second basic structure, and switches are provided on both the first and second basic structures;

[0010] Each input memristor group or bias memristor group is connected to a control module to form a cascaded memristor pulse neural network control module;

[0011] The control module includes a single-chip microcomputer, an SPI communication interface module and a visualization module connected to the single-chip microcomputer, a GPIO control port of the single-chip microcomputer connected to the memristor of the memristive pulse neural network, a slave SPI communication interface of this level is used to connect to the master SPI communication interface of the upper-level control module, and the master SPI communication interface of this level is used to connect to the slave SPI communication interface of the next-level control module, and the visualization module is used to display the system control process and results;

[0012] One of the control modules is the main control module, which is also connected to the ADC acquisition module, SD card storage module and analog switch, and the slave SPI communication interface of the main control module is connected to the master SPI communication interface of the host computer. The ADC acquisition module is used to collect the output voltage of the series node. ,The SD card storage module is used to store the network training process data and classification result data, and the analog switch is used to control the driving source module;

[0013] The host computer is used to interact with the main control module and provide guidance for the training of the memristive pulse neural network;

[0014] An external power supply is used to drive the memristor and control module of the memristive pulse neural network.

[0015] Furthermore, when the state of the memristor pulse neural network system is a state of increasing the weight of the positive-end memristor, the positive driving source is a positive voltage, the directional driving source is a negative voltage, and the negative driving source is a negative voltage;

[0016] When the state of the memristive pulse neural network system is the network result state under the output weighting, the positive driving source is a positive voltage, the directional driving source is in a floating state, and the negative driving source is a negative voltage;

[0017] When the state of the memristor pulse neural network system is to increase the weight of the negative-end memristor, the positive driving source is a positive voltage, the directional driving source is a positive voltage, and the negative driving source is a negative voltage;

[0018] When the state of the memristive pulse neural network system is the off initial state, the positive driving source is a positive voltage, the directional driving source is a positive voltage, and the negative driving source is a positive voltage.

[0019] Furthermore, the memristor is a physical memristor or an analog memristor, and the memristive pulse neural network system also includes a multi-level power management module for gradually stepping down the +24V power supply provided by an external power supply, and the output covers voltage levels of ±15V, ±2.5V, 5V and 3.3V, which is adapted to the power drive of the memristor and the control module.

[0020] Furthermore, an optocoupler isolation module and a level conversion module are sequentially arranged between the GPIO control port of the microcontroller and the memristor, wherein the optocoupler isolation module is used to achieve isolation protection, and the level conversion module is used to convert the level of the output signal of the optocoupler isolation module to adapt to the control requirements of the memristor pulse neural network.

[0021] A control method for a memristive pulse neural network system is provided. Based on the above-mentioned memristive pulse neural network system, the control method of the main control module specifically includes the following steps:

[0022] S1, initialize the main control module, ADC acquisition module, SD card storage module and analog switch;

[0023] S2, receiving a command from the host computer, determining whether to start the memristor pulse neural network system, if the judgment is yes, executing step S3; if the judgment is no, repeating step S2;

[0024] S3, numbering the main control module and transmitting it to the next level control module, the number is 0;

[0025] S4, determine whether the control module is the last level control module, if the judgment is no, execute step S5; if the judgment is yes, execute step S6;

[0026] S5, continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S6;

[0027] S6. Apply for MCU memory space to increase network training speed;

[0028] S7, control the positive drive source to positive voltage, the directional drive source to floating state, the negative drive source to negative voltage, and collect the output voltage , as the initialization classification reference voltage, create a result storage file for storing network training process data and classification result data;

[0029] S8, communicate with the host computer to obtain the pulse data set to be output, and determine whether the control module is the last level control module. If the judgment is no, execute step S9; if the judgment is yes, execute step S10;

[0030] S9, sending the pulse data required to be output in the current round Q to the next level control module; continuously waiting for the ready signal from the next level control module until the signal is received, and then executing step S10;

[0031] S10, numbering the memristors according to the pulse data of the current round Q, and combining the control module's own number to determine the memristors that need to be controlled to be turned on in the current round Q, and determining whether the label of the pulse data is 0. If not, executing the supervised learning process, and then entering step S11; if yes, executing the unsupervised learning process, and then entering step S11;

[0032] S11, obtaining the classification results of the memristor pulse neural network, performing visualization processing, and feeding back the current classification results to the host computer; determining whether the pulse data of the current round is the last set of data in the pulse data set, if the judgment is yes, executing step S13; if the judgment is no, executing step S9;

[0033] S12. Storing the network training process data and the classification result data in a pre-created result storage file.

[0034] Furthermore, the labels of the pulse data include -1, 0 and 1, wherein -1 indicates that the group of pulse data is classified as a negative class; 1 indicates that the group of pulse data is classified as a positive class; and 0 indicates that the group of pulse data is not classified.

[0035] Furthermore, the control method of the non-master control module specifically includes the following steps:

[0036] Step B1: Initializing the non-master control module and initializing the external interrupt of the non-master control module to receive the synchronization signal of the master control module;

[0037] Step B2: Determine whether the number of the upper-level control module is received. If yes, execute step B3; if no, repeat step B2;

[0038] Step B3: Add 1 to the received number as the number of this module, and determine whether this module is the last-level control module. If the judgment is no, execute step B4; if the judgment is yes, execute step B5;

[0039] Step B4: try to pass the number to the next level control module, and continue to wait for the ready signal from the next level control module until the signal is received, and then execute step B5;

[0040] Step B5: Transmitting a ready signal to the upper-level control module; clearing the suspend register, setting and enabling the external interrupt to receive the synchronization signal from the main control module; initializing and turning on all memristors controlled by this module, and cooperating with the main control module to collect the initialization classification reference voltage;

[0041] Step B6: Turn off all memristors, enable communication reception, and disable external interrupts to prevent interruptions from interrupting the communication process and causing system errors.

[0042] Step B7: Determine whether the pulse data of the current round is received. If so, execute step B8; if not, repeat step B7;

[0043] Step B8: Determine whether this module is the last level control module. If not, proceed to step B9; if yes, proceed to step B10.

[0044] Step B9: Send pulse data to the next level control module, and continue to wait for the ready signal from the next level control module until the signal is received, and then execute step B10;

[0045] Step B10: Based on the pulse data of the current round and the number of the current module, determine the memristor that needs to be controlled to be turned on in the current round, turn off communication reception, set and enable external interrupts to receive synchronization signals from the main control module, and send a ready signal to the upper-level control module;

[0046] Step B11: Determine whether the module triggers the first external interrupt. If so, execute step B12; if not, repeat step B11.

[0047] Step B12: Turn on the corresponding memristor and write the current round pulse information;

[0048] Step B13: Determine whether the module triggers the second external interrupt. If so, execute step B14; if not, repeat step B13.

[0049] Step B14: Turning on the corresponding memristor and waiting for the main control module to collect the memristor pulse neural network classification results of this round;

[0050] Step B15: After the main control module collects the data, it determines whether the module triggers the third external interrupt. If it is, it executes step B16; if it is not, it repeats step B15.

[0051] Step B16: Turn off the corresponding memristor and disable the external interrupt to prevent the interruption from interrupting the communication process and causing system errors. Then, start communication reception and execute step B7.

[0052] Furthermore, when the supervised learning process is performed in step S10, obtaining the classification result of the memristor pulse neural network in step S11 specifically includes the following steps:

[0053] Step C1: Determine whether the label of the pulse data is 1. If yes, execute step C2; if no, execute step C3;

[0054] Step C2: If the spiking neural network classification result is positive, the positive driving source is controlled to have a positive voltage, the directional driving source is controlled to have a negative voltage, and the negative driving source is controlled to have a negative voltage, and the upper half memristor between the positive driving source and the directional driving source is controlled to be turned on, and step C4 is executed;

[0055] Step C3: If the spiking neural network classification result is negative, the positive driving source is controlled to have a positive voltage, the directional driving source is controlled to have a positive voltage, the negative driving source is controlled to have a negative voltage, the lower half memristor between the directional driving source and the negative driving source is controlled to be turned on, and step C4 is executed;

[0056] Step C4: The main control module generates a synchronization signal to trigger the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0057] Furthermore, when the unsupervised learning process is executed in step S10, obtaining the classification result of the memristor pulse neural network in step S11 specifically includes the following steps:

[0058] Step D1: Obtain the classification results of the previous round of memristor pulse neural network and collect the output voltage of the previous round;

[0059] Step D2: Determine whether the output voltage of the previous round is greater than the initialization classification reference voltage. If so, execute step D3; if not, execute step D6;

[0060] Step D3: If the spiking neural network classification result is positive, the positive driving source is controlled to have a positive voltage, the directional driving source is controlled to have a negative voltage, and the negative driving source is controlled to have a negative voltage, and the upper half memristor between the positive driving source and the directional driving source is controlled to be turned on, and step D5 is executed;

[0061] Step D4: If the spiking neural network classification result is negative, the positive driving source is controlled to have a positive voltage, the directional driving source is controlled to have a positive voltage, and the negative driving source is controlled to have a negative voltage, and the negative end memristor of the lower half memristor between the directional driving source and the negative driving source is controlled to be turned on, and step D5 is executed;

[0062] Step D5: The main control module generates a synchronization signal to trigger the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0063] Furthermore, the method further comprises the following steps:

[0064] Step E1: The main control module generates a synchronization signal to trigger the second external interrupt of the non-control module, turning on the corresponding memristor, controlling the positive driving source to be positive voltage, the directional driving source to be zero voltage, and the negative driving source to be negative voltage;

[0065] Step E2: Collect the output voltage of the series node through the ADC acquisition module , the corresponding memristor is disconnected, the main control module generates a synchronization signal, triggers the third external interrupt of the non-control module, and executes step S11.

[0066] Compared with the prior art, the positive progress of the present invention is:

[0067] The memristor pulse neural network system provided by the present invention uses a bionic design concept to accurately simulate the synaptic structure of a biological neural network by connecting pairs of memristors of the same level in series. Based on the positive and negative Hebbian plasticity rules, the system implements an adaptive learning mechanism, strengthens the computing function in the storage and computing performance of the memristor, improves the learning efficiency of the neural network, and enables it to maintain excellent stability and outstanding generalization ability under different working conditions. It is particularly good at handling binary classification tasks. The cascaded scalable control architecture combining master control and slave control gives the system high scalability. According to the needs of specific tasks, users can flexibly adjust the scale of the neural network to achieve unlimited cascade expansion, thereby easily coping with various complex scenarios. In addition, the built-in ADC acquisition module provides a real-time feedback mechanism, which can improve the accuracy of experimental monitoring, speed up the response speed, and provide valuable data support for the optimization and adjustment of the experiment. The modular design concept makes the system have good compatibility and flexibility, and can easily adapt to various types of memristors. Regardless of the manufacturing process or packaging form, suitable application scenarios can be found in the system, which is suitable for various scenarios in teaching and scientific research experiments.

[0068] Furthermore, the multi-level power management module can stably step down the +24V power supply provided by the analog switch to multiple voltage levels, allowing the system to flexibly adapt to different types of memristors to meet power drive requirements, avoiding system failures or performance degradation caused by voltage fluctuations or instability, and helping to improve system stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0070] Figure 1 This is a schematic diagram of the structure of the memristor pulse neural network system;

[0071] Figure 2 Detailed diagram of an independent switch in a memristive pulse neural network system;

[0072] Figure 3 This is a schematic diagram of the module structure of the memristor pulse neural network system;

[0073] Figure 4 It is a schematic diagram of the structure of a multi-level power management module;

[0074] Figure 5 It is a structural diagram of the optocoupler isolation module and the level conversion module;

[0075] Figure 6 This is a flow chart of the main control module;

[0076] Figure 7 This is a flow chart of a non-main control module;

[0077] Figure 8 Flowchart of supervised learning for the main control module;

[0078] Figure 9 Flowchart of unsupervised learning for the main control module.

[0079] Among them, 1 is the positive driving source; 2 is the directional driving source; 3 is the negative driving source; 4 is the input memristor group; 5 is the bias memristor group; 6 is the cascaded memristor pulse neural network control module; 7 is the host computer; 41 is the independent switch of the same-level positive input memristor; 42 is the same-level positive input memristor; 51 is the same-level reverse bias memristor; 52 is the independent switch of the same-level reverse bias memristor; 61 is the MCU; 62 is the GPIO control port; 63 is the SPI communication interface module; 64 is the ADC acquisition module. DETAILED DESCRIPTION

[0080] The present invention will be further described in detail below with reference to specific embodiments, which are intended to explain the present invention rather than to limit it.

[0081] A memristive pulse neural network system includes a driving source module, including a positive driving source 1, a directional driving source 2 and a negative driving source 3, for switching the state of the memristive pulse neural network system;

[0082] A memristor pulse neural network includes at least one input memristor group 4 and at least one bias memristor group 5. The input memristor group 4 is formed by connecting a plurality of first basic structures in parallel, wherein the first basic structure is a pair of same-level positive-connected input memristors 42 connected in series, and each same-level positive-connected input memristor 42 is provided with an independent switch 41; the bias memristor group 5 is formed by connecting a plurality of second basic structures in parallel, wherein the second basic structure is a pair of same-level reverse-connected bias memristors 51 connected in series, and each same-level reverse-connected bias memristor 51 is provided with an independent switch 52; a positive drive source 1 is connected to the positive end of the first basic structure and the negative end of the second basic structure, a directional drive source 2 is connected to the series node of the first and second basic structures, a negative drive source 3 is connected to the positive end of the first basic structure and the negative end of the second basic structure, and switches are provided on both the first and second basic structures;

[0083] Each input memristor group 4 or bias memristor group 5 is connected to a control module to form a cascaded memristor pulse neural network control module 6;

[0084] The control module includes a single-chip microcomputer, which is connected to an SPI communication interface module 63 and a visualization module. The GPIO control port 62 of the single-chip microcomputer is connected to the memristor of the memristive pulse neural network. The slave SPI communication interface of this level is used to connect to the master SPI communication interface of the upper-level control module. The master SPI communication interface of this level is used to connect to the slave SPI communication interface of the next-level control module. The visualization module is used to display the system control process and results;

[0085] One of the control modules is a main control module, which is also connected to an ADC acquisition module 64, an SD card storage module and an analog switch, and a slave SPI communication interface of the main control module is connected to a master SPI communication interface of the host computer 7, wherein the ADC acquisition module 64 is used to collect the output voltage of the series node. ,The SD card storage module is used to store the network training process data and classification result data, and the analog switch is used to control the driving source module;

[0086] The host computer 7 is used to interact with the main control module and provide guidance for the training of the memristive pulse neural network;

[0087] An external power supply is used to drive the memristor and control module of the memristive pulse neural network.

[0088] Hereinafter, for the convenience of description, other control modules except the main control module are referred to as non-main control modules.

[0089] See also Figures 1 and 2 The basic structure of the memristor pulse neural network system is a synaptic structure composed of a pair of serially connected memristors of the same level. The two memristors represent the competing energy dissipation paths in the positive and negative Hebbian plasticity rules. The conductance of each memristor represents the rate of dissipation, and the difference in conductance reflects the connection weight of the synapse. When the positive driving source 1 and the negative driving source 3 apply symmetrical voltages respectively When the output voltage on the network center line driven by directional drive source 2 is That reflects the state of the synapse. When , it indicates that the dissipation path represented by the positive-end memristor has an absolute advantage, and vice versa, it indicates that the dissipation path represented by the negative-end memristor has an advantage. When the positive-end memristor has an advantage, according to the voltage divider principle, it can be seen that the voltage applied to the positive end is less than the voltage at the negative end, making the conductivity growth rate of the former lower than that of the latter, which is basically similar to the anti-Hebbian process. By connecting the basic synaptic structure in parallel, the most basic pulse neural network architecture can be obtained. Each synapse in the network will have its own weight. According to Kirchhoff's law, when the positive driving source 1 and the negative driving source 3 apply symmetrical voltages respectively When the output voltage of the network neutral line driven by directional driving source 2 is satisfy

[0090] (1)

[0091] in and Respectively represent The conductance of the positive and negative memristors connected to the network via switches is measured. It can be seen that the network's classification results are directly related to the synaptic weights of all connected networks. In addition to the normal input memristors, the network introduces bias memristors with the same structure but opposite polarity to simulate the bias in linear neuron operations, while also introducing a factor that counteracts the main learning process to prevent overfitting.

[0092] Specifically, when the state of the memristor pulse neural network system is to increase the weight of the positive-end memristor, the positive driving source 1 is a positive voltage, the directional driving source 2 is a negative voltage, and the negative driving source 3 is a negative voltage;

[0093] When the state of the memristive pulse neural network system is the network result state under the output weighting, the positive driving source 1 is a positive voltage, the directional driving source 2 is in a floating state, and the negative driving source 3 is a negative voltage;

[0094] When the state of the memristor pulse neural network system is to increase the weight of the negative-end memristor, the positive driving source 1 is a positive voltage, the directional driving source 2 is a positive voltage, and the negative driving source 3 is a negative voltage;

[0095] When the state of the memristive pulse neural network system is the off initial state, the positive driving source 1 is a positive voltage, the directional driving source 2 is a positive voltage, and the negative driving source 3 is a positive voltage.

[0096] Specifically, the memristor is a physical memristor or an analog memristor, and the memristive pulse neural network system also includes a multi-level power management module, see Figure 4 , used to step down the +24V power supply provided by the external power supply, with output voltage levels including ±15V, ±2.5V, 5V and 3.3V, suitable for power drive of memristor and control module. Figure 5 Because the voltage drive levels of different submodules in the memristor pulse neural network module are inconsistent, and if a memristor simulator based on active devices is used as the basic unit of the neural network in the system, the power supply circuit needs to provide power drives at multiple different voltage levels. The multi-level power management module controls each power supply level through a multi-level power management controller. It controls the external power input with a +24V operating voltage level using a step-by-step voltage reduction principle. The output voltage ranges include ±15V, ±2.5V, 5V, and 3.3V to ensure the normal operation of each module and the stable operation of the system. The characteristics of the memristor pulse neural network dictate that this module cannot share a common ground with the control module. Therefore, an optocoupler isolation module is used to isolate and protect the GPIO and memristor module. A level conversion module converts the output signal of the optocoupler isolation module to match the control requirements of the memristor module. The selected high-speed optocoupler chip 6N137 has a transmission rate of up to 10Mbit / s, meeting the high-speed requirements of the system.

[0097] Specifically, an optocoupler isolation module and a level conversion module are sequentially arranged between the GPIO control port 62 of the single-chip microcomputer and the memristor, wherein the optocoupler isolation module is used to achieve isolation protection, and the level conversion module is used to convert the output signal of the optocoupler isolation module into a level level to adapt to the control requirements of the memristor pulse neural network.

[0098] See also Figure 3 As a specific embodiment of the present invention, a memristor pulse neural network module includes eight pairs of memristors, mounted on a voltage bus driven by three drive sources. Power is supplied by an external power supply and a multi-stage power management module, supporting the module's on / off control function. An optocoupler isolation module and a level conversion module isolate the memristor pulse neural network module from the control module, ensuring system safety.

[0099] The control module consists of a master control module and a non-master control module, which independently control the switching of each memristor via a GPIO interface and an optocoupler isolation module. Each master and non-master control module is equipped with an SPI communication module for high-speed data transmission and reception, and an independent identity determination module is used to identify the master and slave modules. The system also integrates an independent visualization module to achieve visual display of the system control process. Compared to the non-master control module, the master control module adds an analog switch control module, an SD card storage module, and an ADC acquisition module 64. The analog switch control module is connected to an external symmetrical power supply and a zero potential point, and through logical control of the analog switch gating, it achieves dynamic switching of the three drive source functions. Specific drive source function states are shown in the drive source state function correspondence table. The ADC acquisition module 64 is directly connected to the network center line driven by the directional drive source 2 and is used to collect data in real time during the network training process. After training, all process data and final results will be stored via the SD card storage module. The master control module communicates directly with the host computer 7, receiving experimental instructions and enabling real-time control of the system by the host computer 7. In actual implementation, the MCU61 of the control module has a relatively high main frequency, ensuring that the reading time of the pulse neural network is within 1~100us and the communication time between modules is within 1ms.

[0100] Table 1 Drive source status function correspondence table

[0101]

[0102] See also Figure 6 Based on the same inventive concept, the present application provides a control method for a memristor pulse neural network system. Based on the above-mentioned memristor pulse neural network system, the control method of the main control module specifically includes the following steps:

[0103] S1, initialize the main control module, ADC acquisition module 64, SD card storage module and analog switch;

[0104] S2, receiving the instruction from the host computer 7, determining whether to start the memristor pulse neural network system, if the judgment is yes, executing step S3; if the judgment is no, repeating step S2;

[0105] S3, numbering the main control module and transmitting it to the next level control module, the number is 0;

[0106] S4, determine whether the control module is the last level control module, if the judgment is no, execute step S5; if the judgment is yes, execute step S6;

[0107] S5, continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S6;

[0108] S6. Apply for MCU memory space to increase network training speed;

[0109] S7, control the positive drive source to positive voltage, the directional drive source to floating state, the negative drive source to negative voltage, and collect the output voltage , as the initialization classification reference voltage, create a result storage file for storing network training process data and classification result data;

[0110] S8, communicate with the host computer to obtain the pulse data set to be output, and determine whether the control module is the last level control module. If the judgment is no, execute step S9; if the judgment is yes, execute step S10;

[0111] S9, sending the pulse data required to be output in the current round Q to the next level control module; continuously waiting for the ready signal from the next level control module until the signal is received, and then executing step S10;

[0112] S10, numbering the memristors according to the pulse data of the current round Q, and combining the control module's own number to determine the memristors that need to be controlled to be turned on in the current round Q, and determining whether the label of the pulse data is 0. If not, executing the supervised learning process, and then entering step S11; if yes, executing the unsupervised learning process, and then entering step S11;

[0113] S11, obtaining the classification results of the memristor pulse neural network, performing visualization processing, and feeding back the current classification results to the host computer; determining whether the pulse data of the current round is the last set of data in the pulse data set, if the judgment is yes, executing step S13; if the judgment is no, executing step S9;

[0114] S12. Storing the network training process data and the classification result data in a pre-created result storage file.

[0115] Specifically, the labels of the pulse data include three types: -1, 0 and 1, wherein -1 indicates that the group of pulse data is classified as a negative class; 1 indicates that the group of pulse data is classified as a positive class; and 0 indicates that the group of pulse data is not classified.

[0116] For details, see Figure 7 The control method of the non-master control module specifically includes the following steps:

[0117] Step B1: Initializing the non-master control module and initializing the external interrupt of the non-master control module to receive the synchronization signal of the master control module;

[0118] Step B2: Determine whether the number of the upper-level control module is received. If yes, execute step B3; if no, repeat step B2;

[0119] Step B3: Add 1 to the received number as the number of this module, and determine whether this module is the last-level control module. If the judgment is no, execute step B4; if the judgment is yes, execute step B5;

[0120] Step B4: try to pass the number to the next level control module, and continue to wait for the ready signal from the next level control module until the signal is received, and then execute step B5;

[0121] Step B5: Transmitting a ready signal to the upper-level control module; clearing the suspend register, setting and enabling the external interrupt to receive the synchronization signal from the main control module; initializing and turning on all memristors controlled by this module, and cooperating with the main control module to collect the initialization classification reference voltage;

[0122] Step B6: Turn off all memristors, enable communication reception, and disable external interrupts to prevent interruptions from interrupting the communication process and causing system errors.

[0123] Step B7: Determine whether the pulse data of the current round is received. If so, execute step B8; if not, repeat step B7;

[0124] Step B8: Determine whether this module is the last level control module. If not, proceed to step B9; if yes, proceed to step B10.

[0125] Step B9: Send pulse data to the next level control module, and continue to wait for the ready signal from the next level control module until the signal is received, and then execute step B10;

[0126] Step B10: Based on the pulse data of the current round and the number of the current module, determine the memristor that needs to be controlled to be turned on in the current round, turn off communication reception, set and enable external interrupts to receive synchronization signals from the main control module, and send a ready signal to the upper-level control module;

[0127] Step B11: Determine whether the module triggers the first external interrupt. If so, execute step B12; if not, repeat step B11.

[0128] Step B12: Turn on the corresponding memristor and write the current round pulse information;

[0129] Step B13: Determine whether the module triggers the second external interrupt. If so, execute step B14; if not, repeat step B13.

[0130] Step B14: Turning on the corresponding memristor and waiting for the main control module to collect the memristor pulse neural network classification results of this round;

[0131] Step B15: After the main control module collects the data, it determines whether the module triggers the third external interrupt. If it is, it executes step B16; if it is not, it repeats step B15.

[0132] Step B16: Turn off the corresponding memristor and disable the external interrupt to prevent the interruption from interrupting the communication process and causing system errors. Then, start communication reception and execute step B7.

[0133] For details, see Figure 8 When the supervised learning process is executed in step S10, the step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps:

[0134] Step C1: Determine whether the label of the pulse data is 1. If yes, execute step C2; if no, execute step C3;

[0135] Step C2: If the spiking neural network classification result is positive, the positive driving source 1 is controlled to have a positive voltage, the directional driving source 2 is controlled to have a negative voltage, and the negative driving source 3 is controlled to have a negative voltage. The upper half memristor between the positive driving source 1 and the directional driving source 2 is controlled to be turned on, and step C4 is executed.

[0136] Step C3: If the spiking neural network classification result is negative, the positive driving source 1 is controlled to have a positive voltage, the directional driving source 2 is controlled to have a positive voltage, and the negative driving source 3 is controlled to have a negative voltage. The memristor in the lower half of the region between the directional driving source 2 and the negative driving source 3 is controlled to be turned on, and step C4 is executed.

[0137] Step C4: The main control module generates a synchronization signal to trigger the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0138] For details, see Figure 9 When the unsupervised learning process is executed in step S10, the step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps:

[0139] Step D1: Obtain the classification results of the previous round of memristor pulse neural network and collect the output voltage of the previous round;

[0140] Step D2: Determine whether the output voltage of the previous round is greater than the initialization classification reference voltage. If so, execute step D3; if not, execute step D6;

[0141] Step D3: If the spiking neural network classification result is positive, the positive driving source 1 is controlled to have a positive voltage, the directional driving source 2 is controlled to have a negative voltage, and the negative driving source 3 is controlled to have a negative voltage. The upper half memristor between the positive driving source 1 and the directional driving source 2 is controlled to be turned on, and step D5 is executed.

[0142] Step D4: If the spiking neural network classification result is negative, the positive driving source 1 is controlled to have a positive voltage, the directional driving source 2 is controlled to have a positive voltage, and the negative driving source 3 is controlled to have a negative voltage, and the negative end memristor of the lower half memristor between the directional driving source 2 and the negative driving source 3 is controlled to be turned on, and step D5 is executed;

[0143] Step D5: The main control module generates a synchronization signal to trigger the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0144] Specifically, see 8-9, which also includes the following steps:

[0145] Step E1: The main control module generates a synchronization signal, triggers the second external interrupt of the non-control module, turns on the corresponding memristor, controls the positive driving source 1 to be positive voltage, the directional driving source 2 to be zero voltage, and the negative driving source 3 to be negative voltage;

[0146] Step E2: Collect the output voltage of the series node through the ADC acquisition module 64 , turn off the corresponding memristor, the main control module generates a synchronization signal, triggers the third external interrupt of the non-control module, and executes step S11.

[0147] The memristor pulse neural network system provided by this application adopts a cascaded scalable control architecture that combines master control and slave control. Each non-master control module independently manages the on-off operation of multiple pairs of input memristor pairs or bias memristor pairs. The main control board directly controls the real-time status of the drive source group through analog switches, manages the three drive buses in the pulse neural network, and uses the ADC acquisition module to monitor the median voltage in the network in real time, and transmits the feedback signal to the host computer to assist it in making accurate decisions. The minimum configuration of the system only requires a host computer responsible for decision-making and a main control board, and the non-master control modules can be flexibly cascaded according to the actual needs of the neural network to achieve unlimited expansion.

[0148] By simulating the synaptic structure of biological neural networks through biomimetic design and implementing adaptive learning based on the positive and negative Hebbian plasticity rules, this invention further enhances the computational capabilities of the memristor's integrated storage and computation capabilities, significantly improving learning efficiency while maintaining excellent stability and generalization capabilities under different operating conditions. The highly scalable master-slave cascade control architecture allows for flexible adjustments to network size based on actual needs. The real-time feedback mechanism of the ADC module significantly improves experimental accuracy and response speed, while the modular design ensures system compatibility and flexibility.

[0149] In practical applications, this system is compatible with a variety of memristor or memristor simulator types and manufacturing processes, such as active device memristor simulator modules, 16P packaged memristor modules, and 32P packaged memristor modules. These modules serve as the system's core units, participating in the construction and operation of neural networks. By integrating different types of memristors or simulators, the system can achieve diversified expansion of spiking neural network functions and performance optimization, demonstrating strong applicability and generalization.

[0150] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A memristive pulse neural network system, characterized in that: include A driving source module, comprising a positive driving source (1), a directional driving source (2) and a negative driving source (3), for switching the state of the memristive pulse neural network system; A memristor pulse neural network comprises at least one input memristor group (4) and at least one bias memristor group (5), wherein the input memristor group (4) is formed by connecting a plurality of first basic structures in parallel, wherein the first basic structure is a pair of same-level positive-connected input memristors (42) connected in series, and each of the same-level positive-connected input memristors (42) is provided with an independent switch (41); the bias memristor group (5) is formed by connecting a plurality of second basic structures in parallel, wherein the second basic structure is a pair of same-level reverse-connected bias memristors (51) connected in series, and each of the same-level reverse-connected bias memristors (51) is provided with an independent switch (52); a positive driving source (1) is connected to the positive end of the first basic structure and the negative end of the second basic structure, a directional driving source (2) is connected to the series node of the first basic structure and the second basic structure, and a negative driving source (3) is connected to the positive end of the first basic structure and the negative end of the second basic structure, and switches are provided on both the first basic structure and the second basic structure; Each input memristor group (4) or bias memristor group (5) is connected to a control module to form a cascaded memristor pulse neural network control module (6); The control module includes a single-chip microcomputer, an SPI communication interface module (63) and a visualization module are connected to the single-chip microcomputer, a GPIO control port (62) of the single-chip microcomputer is connected to the memristor of the memristive pulse neural network, a slave SPI communication interface of this level is used to connect to the master SPI communication interface of the previous level control module, and the master SPI communication interface of this level is used to connect to the slave SPI communication interface of the next level control module, and the visualization module is used to display the system control process and results; One of the control modules is a main control module, which is also connected to an ADC acquisition module (64), an SD card storage module and an analog switch, and a slave SPI communication interface of the main control module is connected to a master SPI communication interface of a host computer (7), wherein the ADC acquisition module (64) is used to acquire the output voltage of the series node ,The SD card storage module is used to store the network training process data and classification result data, and the analog switch is used to control the driving source module; A host computer (7) is used to interact with the main control module and provide guidance for the training of the memristor pulse neural network; An external power supply is used to drive the memristor and control module of the memristive pulse neural network.

2. A memristive pulse neural network system according to claim 1, characterized in that: When the state of the memristor pulse neural network system is the state of increasing the weight of the positive-end memristor, the positive driving source (1) is a positive voltage, the directional driving source (2) is a negative voltage, and the negative driving source (3) is a negative voltage; When the state of the memristive pulse neural network system is the network result state under the output weighting, the positive driving source (1) is a positive voltage, the directional driving source (2) is in a floating state, and the negative driving source (3) is a negative voltage; When the state of the memristor pulse neural network system is a state of increasing the weight of the negative-end memristor, the positive driving source (1) is a positive voltage, the directional driving source (2) is a positive voltage, and the negative driving source (3) is a negative voltage; When the state of the memristive pulse neural network system is the off initial state, the positive driving source (1) is a positive voltage, the directional driving source (2) is a positive voltage, and the negative driving source (3) is a positive voltage.

3. The memristive pulse neural network system according to claim 1, characterized in that: The memristor is a physical memristor or an analog memristor. The memristive pulse neural network system also includes a multi-level power management module, which is used to gradually reduce the voltage of the +24V power provided by the external power supply. The output covers voltage levels of ±15V, ±2.5V, 5V and 3.3V, which is suitable for the power drive of the memristor and the control module.

4. The memristive pulse neural network system according to claim 1, characterized in that: An optocoupler isolation module and a level conversion module are sequentially arranged between the GPIO control port (62) of the single-chip microcomputer and the memristor, wherein the optocoupler isolation module is used to realize isolation protection, and the level conversion module is used to convert the level of the output signal of the optocoupler isolation module to adapt to the control requirements of the memristor pulse neural network.

5. A control method for a memristive pulse neural network system, characterized in that: Based on the memristive pulse neural network system according to claim 1, the control method of the main control module specifically includes the following steps: S1, initializing the main control module, ADC acquisition module (64), SD card storage module and analog switch; S2, receiving the instruction from the host computer (7), judging whether to start the memristor pulse neural network system, if the judgment is yes, executing step S3; if the judgment is no, repeating step S2; S3, numbering the main control module and transmitting it to the next level control module, the number is 0; S4, determine whether the control module is the last level control module, if the judgment is no, execute step S5; if the judgment is yes, execute step S6; S5, continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S6; S6. Apply for MCU memory space to increase network training speed; S7, control the positive drive source (1) to a positive voltage, the directional drive source (2) to a floating state, the negative drive source (3) to a negative voltage, and collect the output voltage , as the initialization classification reference voltage, create a result storage file for storing network training process data and classification result data; S8, communicate with the host computer (7), obtain the pulse data set to be output, and determine whether the control module is the last level control module. If the determination is no, execute step S9; if the determination is yes, execute step S10; S9, sending the pulse data required to be output in the current round Q to the next level control module; continuously waiting for the ready signal from the next level control module until the signal is received, and then executing step S10; S10, numbering the memristors according to the pulse data of the current round Q, and combining the control module's own number to determine the memristors that need to be controlled to be turned on in the current round Q, and determining whether the label of the pulse data is 0. If not, executing the supervised learning process, and then entering step S11; if yes, executing the unsupervised learning process, and then entering step S11; S11, obtain the classification result of the memristor pulse neural network, perform visualization processing, and feed back the current classification result to the host computer (7); determine whether the pulse data of the current round is the last set of data in the pulse data set. If the judgment is yes, execute step S13; if the judgment is no, execute step S9; S12. Storing the network training process data and the classification result data in a pre-created result storage file.

6. The control method of a memristive pulse neural network system according to claim 5, characterized in that: The labels of the pulse data include -1, 0 and 1, wherein -1 indicates that the group of pulse data is classified as a negative class; 1 indicates that the group of pulse data is classified as a positive class; and 0 indicates that the group of pulse data is not classified.

7. The control method of a memristive pulse neural network system according to claim 5, characterized in that: The control method of the non-master control module specifically includes the following steps: Step B1: Initializing the non-master control module and initializing the external interrupt of the non-master control module to receive the synchronization signal of the master control module; Step B2: Determine whether the number of the upper-level control module is received. If yes, execute step B3; if no, repeat step B2; Step B3: Add 1 to the received number as the number of this module, and determine whether this module is the last-level control module. If the judgment is no, execute step B4; if the judgment is yes, execute step B5; Step B4: try to pass the number to the next level control module, and continue to wait for the ready signal from the next level control module until the signal is received, and then execute step B5; Step B5: Transmitting a ready signal to the upper-level control module; clearing the suspend register, setting and enabling the external interrupt to receive the synchronization signal from the main control module; initializing and turning on all memristors controlled by this module, and cooperating with the main control module to collect the initialization classification reference voltage; Step B6: Turn off all memristors, enable communication reception, and disable external interrupts to prevent interruptions from interrupting the communication process and causing system errors. Step B7: Determine whether the pulse data of the current round is received. If so, execute step B8; if not, repeat step B7; Step B8: Determine whether this module is the last level control module. If not, proceed to step B9; if yes, proceed to step B10. Step B9: Send pulse data to the next level control module, and continue to wait for the ready signal from the next level control module until the signal is received, and then execute step B10; Step B10: Based on the pulse data of the current round and the number of the current module, determine the memristor that needs to be controlled to be turned on in the current round, turn off communication reception, set and enable external interrupts to receive synchronization signals from the main control module, and send a ready signal to the upper-level control module; Step B11: Determine whether the module triggers the first external interrupt. If so, execute step B12; if not, repeat step B11. Step B12: Turn on the corresponding memristor and write the current round pulse information; Step B13: Determine whether the module triggers the second external interrupt. If so, execute step B14; if not, repeat step B13. Step B14: Turning on the corresponding memristor and waiting for the main control module to collect the memristor pulse neural network classification results of this round; Step B15: After the main control module collects the data, it determines whether the module triggers the third external interrupt. If it is, it executes step B16; if it is not, it repeats step B15. Step B16: Turn off the corresponding memristor and disable the external interrupt to prevent the interruption from interrupting the communication process and causing system errors. Then, start communication reception and execute step B7.

8. The control method of a memristive pulse neural network system according to claim 5, characterized in that: When the supervised learning process is performed in step S10, obtaining the classification result of the memristor pulse neural network in step S11 specifically includes the following steps: Step C1: Determine whether the label of the pulse data is 1. If yes, execute step C2; if no, execute step C3; Step C2: The pulse neural network classification result is positive, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a negative voltage, the negative driving source (3) is controlled to be a negative voltage, the upper half-area memristor between the positive driving source (1) and the directional driving source (2) is controlled to be turned on, and step C4 is executed; Step C3: The pulse neural network classification result is negative, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a positive voltage, the negative driving source (3) is controlled to be a negative voltage, the lower half memristor between the directional driving source (2) and the negative driving source (3) is controlled to be turned on, and step C4 is executed; Step C4: The main control module generates a synchronization signal to trigger the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

9. The control method of a memristive pulse neural network system according to claim 5, characterized in that: When the unsupervised learning process is performed in step S10, obtaining the classification result of the memristor pulse neural network in step S11 specifically includes the following steps: Step D1: Obtain the classification results of the previous round of memristor pulse neural network and collect the output voltage of the previous round; Step D2: Determine whether the output voltage of the previous round is greater than the initialization classification reference voltage. If so, execute step D3; if not, execute step D6; Step D3: The pulse neural network classification result is positive, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a negative voltage, the negative driving source (3) is controlled to be a negative voltage, the upper half-area memristor between the positive driving source (1) and the directional driving source (2) is controlled to be turned on, and step D5 is executed; Step D4: The pulse neural network classification result is negative, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a positive voltage, the negative driving source (3) is controlled to be a negative voltage, the negative end memristor of the lower half memristor between the directional driving source (2) and the negative driving source (3) is controlled to be turned on, and step D5 is executed; Step D5: The main control module generates a synchronization signal to trigger the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

10. The control method of a memristive pulse neural network system according to claim 8 or 9, characterized in that: The following steps are also included: Step E1: The main control module generates a synchronization signal, triggers the second external interrupt of the non-control module, turns on the corresponding memristor, controls the positive driving source (1) to be a positive voltage, the directional driving source (2) to be a floating state, and the negative driving source (3) to be a negative voltage; Step E2: Collect the output voltage of the series node through the ADC acquisition module (64) , turn off the corresponding memristor, the main control module generates a synchronization signal, triggers the third external interrupt of the non-control module, and executes step S11.

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