Pixel driving circuit and its driving method, array substrate and display panel

Abstract

This disclosure provides a pixel driving circuit and its driving method, an array substrate, and a display panel, relating to the field of display technology, and aims to improve the problem of insufficient threshold compensation time in pixel driving circuits. The pixel driving circuit includes a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node. The light-emitting control sub-circuit includes a first branch, which is coupled to a first power signal line, a first enable signal line, and a second node. The compensation sub-circuit is coupled to a first scan signal line, a second scan signal line, a first node, a third node, a fourth node, and a second power signal line. The writing sub-circuit is coupled to a third scan signal line, a data writing signal line, and a fourth node. The storage sub-circuit is coupled to the first node and the fourth node. The display panel described above is used to display images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit and its driving method, an array substrate, and a display panel. Background Technology

[0002] Currently, OLED (Organic Light-Emitting Diode) display devices are widely used due to their characteristics such as self-emission, fast response, wide viewing angle, and ability to be fabricated on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The light-emitting device is driven by the pixel driving circuit to emit light, thereby realizing the display. Summary of the Invention

[0003] The purpose of the embodiments of this disclosure is to provide a pixel driving circuit and its driving method, an array substrate and a display panel, to improve the problem of insufficient threshold compensation time in driving pixel driving circuits.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a pixel driving circuit is provided. The pixel driving circuit includes a driving sub-circuit, a light emission control sub-circuit, a writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node, and is configured to transmit a voltage from the second node to the third node under the control of the voltage of the first node. The light emission control sub-circuit includes a first branch coupled to a first power signal line, a first enable signal line, and a second node. The first branch is configured to, during the compensation phase, under the control of a first enable signal from the first enable signal line, cooperate with the driving sub-circuit to transmit a first power signal received at the first power signal line to the third node. The compensation sub-circuit is coupled to a first scan signal line, a second scan signal line, the first node, the third node, a fourth node, and a second power signal line. The compensation sub-circuit is configured to, during the compensation phase, transmit the voltage of the third node to the first node under the control of a first scan signal received from the first scan signal line, and to transmit a second power signal received from the second power signal line to the fourth node under the control of a second scan signal received from the second scan signal line. The write sub-circuit is coupled to the third scan signal line, the data write signal line, and the fourth node. The write sub-circuit is configured to, during the write phase, transmit a data write signal received from the data write signal line to the fourth node under the control of a third scan signal received from the third scan signal line. The storage sub-circuit is coupled to the first node and the fourth node. During the write phase, the storage sub-circuit is configured to couple the voltage of the fourth node to the first node.

[0006] The aforementioned pixel driving circuit utilizes a combination of driving sub-circuit, light emission control sub-circuit, writing sub-circuit, compensation sub-circuit, and storage sub-circuit to implement the write data voltage and compensation threshold voltage through two separate paths. This separates the threshold compensation stage from the writing stage, preventing the duration of the writing stage from limiting the duration of the threshold compensation stage. In other words, the duration of the threshold compensation stage is unaffected by the data writing time (line time), ensuring sufficient duration for the threshold compensation stage to fully write the required voltage, compensating for threshold voltage fluctuations over a wide range, and achieving complete threshold voltage compensation.

[0007] Based on this, the pixel driving circuit provided in this embodiment can fully compensate the threshold voltage of the driving sub-circuit (driving transistor) in the pixel driving circuit even at high refresh rates, or in low grayscale images and black states, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0008] In some embodiments, the driving sub-circuit includes a driving transistor, the control electrode of which is coupled to the first node, the first electrode of which is coupled to the second node, and the second electrode of which is coupled to the third node.

[0009] In some embodiments, the compensation sub-circuit includes a second transistor and a ninth transistor. The control electrode of the second transistor is coupled to the first scan signal line, the first electrode of the second transistor is coupled to the third node, and the second electrode of the second transistor is coupled to the first node. The control electrode of the ninth transistor is coupled to the third scan signal line, the first electrode of the ninth transistor is coupled to the second power supply signal line, and the second electrode of the ninth transistor is coupled to the fourth node.

[0010] In some embodiments, the write sub-circuit includes a fourth transistor, the control electrode of which is coupled to the third scan signal line. The first electrode of the fourth transistor is coupled to the data write signal line, and the second electrode of the fourth transistor is coupled to the fourth node.

[0011] In some embodiments, the storage sub-circuit includes a storage capacitor, the first plate of which is coupled to the fourth node, and the second plate of which is coupled to the first node.

[0012] In some embodiments, the light-emitting control subcircuit further includes a second branch coupled to the third node, the second enable signal line, and the light-emitting device. During the light-emitting phase, the light-emitting control subcircuit is configured to, under the control of a first enable signal from the first enable signal line and a second enable signal from the second enable signal line, cooperate with the driving subcircuit to transmit a first power signal received at the first power signal line to the light-emitting device.

[0013] In some embodiments, the first branch includes a fifth transistor, the control electrode of which is coupled to the first enable signal line, the first electrode of which is coupled to the first power supply signal line, and the second electrode of which is coupled to the second node. The second branch includes a sixth transistor, the control electrode of which is coupled to the second enable signal line, the first electrode of which is coupled to the third node, and the second electrode of which is coupled to the light-emitting device.

[0014] In some embodiments, the pixel driving circuit further includes a first reset sub-circuit. The first reset sub-circuit is coupled to the first node, a first reset signal line, and a first initialization signal line. The first reset sub-circuit is configured to, under the control of a first reset signal received from the first reset signal line, transmit a first initialization signal received from the first initialization signal line to the first node, thereby resetting the first node.

[0015] In some embodiments, the first reset sub-circuit includes a first transistor, the control electrode of the first transistor being coupled to the first reset signal line. The first electrode of the first transistor is coupled to the first initialization signal line, and the second electrode of the first transistor is coupled to the first node.

[0016] In some embodiments, the pixel driving circuit further includes a second reset sub-circuit. The second reset sub-circuit is coupled to the light-emitting device, a second reset signal line, and a second initialization signal line. The second reset sub-circuit is configured to, under the control of a second reset signal received from the second reset signal line, transmit a second initialization signal received from the second initialization signal line to the light-emitting device to reset the light-emitting device.

[0017] In some embodiments, the second reset sub-circuit includes a seventh transistor, the control electrode of which is coupled to the second reset signal line. The first electrode of the seventh transistor is coupled to the second initialization signal line, and the second electrode of the seventh transistor is coupled to the light-emitting device.

[0018] In some embodiments, the pixel driving circuit further includes a third reset sub-circuit. The third reset sub-circuit is coupled to the second node, a third reset signal line, and a first reference voltage signal line. The third reset sub-circuit is configured to, under the control of a third reset signal received from the third reset signal line, transmit a first reference voltage signal received from the first reference voltage signal line to the second node, thereby resetting the second node.

[0019] In some embodiments, the third reset sub-circuit includes an eighth transistor, the control electrode of which is coupled to the third reset signal line. The first electrode of the eighth transistor is coupled to the first reference voltage signal line, and the second electrode of the eighth transistor is coupled to the second node.

[0020] In some embodiments, the voltage value of the first power signal is equal to the voltage value of the second power signal.

[0021] In some embodiments, the first power signal line is multiplexed as the second power signal line.

[0022] In some embodiments, where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor, and a ninth transistor: at least one of the first transistor, the second transistor, the fourth transistor, and the ninth transistor is a dual-gate transistor.

[0023] In some embodiments, where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor, and a ninth transistor: at least one of the first transistor, the second transistor, the fourth transistor, and the ninth transistor is an N-type transistor.

[0024] On the other hand, a driving method for a pixel driving circuit is provided. The pixel driving circuit includes: a driving sub-circuit, a light emission control sub-circuit, a writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node. The light emission control sub-circuit includes a first branch, which is coupled to a first power signal line, a first enable signal line, and a second node. The compensation sub-circuit is coupled to a first scan signal line, a second scan signal line, the first node, the third node, the fourth node, a first power signal line, and a second power signal line. The writing sub-circuit is coupled to a third scan signal line, a data writing signal line, and the fourth node. The storage sub-circuit is coupled to the first node and the fourth node.

[0025] The driving method includes a compensation phase and a write phase. In the compensation phase, the first branch, under the control of a first enable signal from the first enable signal line, cooperates with the driving sub-circuit to transmit a first power signal received at the first power signal line to the third node. The compensation sub-circuit, under the control of a first scan signal received from the first scan signal line, transmits the voltage of the third node to the first node; and under the control of a second scan signal received from the second scan signal line, transmits a second power signal received at the second power signal line to the fourth node. The storage sub-circuit receives the voltage of the first node and the voltage of the fourth node. In the write phase, the write sub-circuit, under the control of a third scan signal received from the third scan signal line, transmits a data write signal received at the data write signal line to the fourth node. The storage sub-circuit couples the voltage of the fourth node to the first node.

[0026] In some embodiments, the pixel driving circuit further includes a third reset sub-circuit, which is coupled to the second node, the third reset signal line, and the first reference voltage signal line. The driving method further includes a first reset phase. In the first reset phase, under the control of a third reset signal received from the third reset signal line, the third reset sub-circuit transmits a first reference voltage signal received from the first reference voltage signal line to the second node, thereby resetting the second node.

[0027] In some embodiments, the pixel driving circuit further includes a first reset sub-circuit, which is coupled to the first node, the first reset signal line, and the first initialization signal line. The driving method further includes a first initialization phase. In the first initialization phase, under the control of a first reset signal received from the first reset signal line, the first reset sub-circuit transmits the first initialization signal received from the first initialization signal line to the first node to initialize the first node.

[0028] In some embodiments, the driving method further includes a second initialization phase. In the second initialization phase, the first reset sub-circuit, under the control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node. The compensation sub-circuit, under the control of a first scan signal received from the first scan signal line, transmits the voltage of the first node to the third node. And the driving sub-circuit, under the control of the voltage of the first node, transmits the voltage from the second node to the third node to initialize the first node, the second node, and the third node.

[0029] The driving method of the pixel driving circuit described above has the same structure and beneficial technical effects as the pixel driving circuit provided in some of the above embodiments, and will not be described again here.

[0030] In another aspect, an array substrate is provided. The array substrate includes a substrate and a plurality of pixel driving circuits as described in any of the above embodiments located on the substrate.

[0031] In some embodiments, the plurality of pixel driving circuits are arranged in multiple rows and columns. The array substrate further includes: a plurality of first scan signal lines, a plurality of second scan signal lines, and a plurality of first reset signal lines. The plurality of first scan signal lines are located on one side of the substrate and extend along a first direction and are arranged along a second direction. The second direction intersects the first direction. The plurality of second scan signal lines are located on one side of the substrate and extend along the first direction and are arranged along the second direction. The plurality of first reset signal lines are located on one side of the substrate and extend along the first direction and are arranged along the second direction. The second scan signal line coupled to the nth row pixel driving circuit, the first scan signal line coupled to the (n+3)th row pixel driving circuit, and the first reset signal line coupled to the (n+6)th row pixel driving circuit are all responsive to the control of the same control signal, where n is a positive integer.

[0032] The array substrate described above has the same structure and beneficial technical effects as the pixel driving circuits provided in some of the above embodiments, and will not be described again here.

[0033] In another aspect, a display panel is provided. The display panel includes a light-emitting device layer and an array substrate as described in any of the above embodiments. The light-emitting device layer includes a plurality of light-emitting devices, and the pixel driving circuit is coupled to the light-emitting devices.

[0034] The above-described display panel has the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0036] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0037] Figure 2 This is a structural diagram of a display panel according to some embodiments;

[0038] Figure 3 This is a cross-sectional view of a display panel according to some embodiments;

[0039] Figure 4 This is a structural diagram of an array substrate according to some embodiments;

[0040] Figure 5 This is an equivalent circuit diagram of a pixel driving circuit based on some feasible implementations;

[0041] Figure 6 This is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0042] Figure 7 An equivalent circuit diagram of a pixel driving circuit according to some other embodiments;

[0043] Figure 8 An equivalent circuit diagram of a pixel driving circuit according to some other embodiments;

[0044] Figure 9 An equivalent circuit diagram of a pixel driving circuit according to some other embodiments;

[0045] Figure 10 An equivalent circuit diagram of a pixel driving circuit according to some other embodiments;

[0046] Figure 11 A timing diagram of a pixel driving circuit according to some embodiments;

[0047] Figure 12 A timing diagram of a pixel driving circuit according to some other embodiments;

[0048] Figure 13 This is a structural diagram of an array substrate according to some other embodiments;

[0049] Figure 14 A timing diagram of a pixel driving circuit according to some other embodiments;

[0050] Figure 15 This is a timing diagram of a pixel driving circuit according to some other embodiments. Detailed Implementation

[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0054] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0055] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0056] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0057] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0058] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0059] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0060] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0061] As used herein, “vertical” includes the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “vertical” includes absolute verticality and approximate verticality, where an acceptable range of deviation for approximate verticality could, for example, be within 5°.

[0062] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0063] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] In the circuit structure provided by the embodiments of this disclosure, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0065] In the circuit structure provided in the embodiments of this disclosure, the first terminal of each transistor is one of the source and the drain, and the second terminal of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be symmetrical in structure, they can be indistinguishable in structure. That is to say, the first and second terminals of the transistors in the embodiments of this disclosure can be indistinguishable in structure.

[0066] Figure 1 This is a structural diagram of a display device according to some embodiments. Please refer to... Figure 1 As shown, some embodiments of this disclosure provide a display device 300, which includes a display panel 200.

[0067] For example, the display device 300 also includes a frame, as well as other electronic accessories.

[0068] For example, the display device 300 can be an electroluminescent display device or a photoluminescent display device. When the display device is an electroluminescent display device, it can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). When the display device is a photoluminescent display device, it can be a quantum dot photoluminescent display device.

[0069] For example, the display device 300 described above can be any display device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the display device of the described embodiments is contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0070] Figure 2 This is a structural diagram of a display panel according to some embodiments. Figure 3 This is a cross-sectional view of a display panel according to some embodiments.

[0071] Some embodiments of this disclosure provide a display panel 200. Please refer to... Figure 2 and Figure 3 As shown, the display panel 200 includes a display area (full name: Active Area, abbreviated as AA area; also known as effective display area) AA. The display area AA includes multiple sub-pixel areas P, which can be arranged in an array. The sub-pixel area P is the smallest unit for displaying images on the display panel 200.

[0072] In some examples, a subpixel region P includes a pixel driving circuit Q and a light-emitting device O electrically connected to the pixel driving circuit Q. The pixel driving circuit Q can be adjusted based on various types of signal lines to generate a driving signal, and each light-emitting device O can emit light under the driving signal generated by its corresponding pixel driving circuit Q. Based on this, the pixel driving circuits Q in multiple subpixel regions can drive their corresponding light-emitting devices O to emit light, so that the display panel 200 can display a predetermined image in the display area AA. Specifically, the multiple subpixel regions P may include multiple subpixel regions P with different emission colors.

[0073] For example, multiple sub-pixel regions P may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first, second, and third sub-pixel regions each emit three primary colors of light; for example, the first sub-pixel region may emit red light, the second sub-pixel region may emit green light, and the third sub-pixel region may emit blue light. Based on this, by adjusting the brightness (grayscale) of different color sub-pixel regions P, and through color combination and superposition, multiple colors can be displayed, thereby achieving full-color display of the display panel 200.

[0074] Please continue to combine Figure 2 and Figure 3 As shown, the display panel 200 also includes an array substrate 100 and a light-emitting device layer 210. The array substrate 100 may include a plurality of pixel driving circuits Q. The light-emitting device layer 210 is located on one side of the array substrate 100 and includes a plurality of light-emitting devices O, which are electrically connected to the pixel driving circuits Q in the array substrate 100.

[0075] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer stacked sequentially. In some examples, an electron transport layer is further disposed between the cathode layer and the light-emitting layer, and a hole transport layer is further disposed between the anode layer and the light-emitting layer. Exemplarily, the light-emitting device O described above can be an OLED light-emitting device, but is not limited thereto. The embodiments of this disclosure do not limit the type of light-emitting device; that is, the light-emitting device O can be any other light-emitting device (e.g., a light-emitting device that emits light through discharge), as long as they can emit light so that the display panel 200 can display an image.

[0076] In some examples, the multiple pixel driving circuits Q and multiple light-emitting devices O can be coupled one-to-one. In other examples, one pixel driving circuit Q can be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q can be coupled to one light-emitting device O.

[0077] The present disclosure will now illustrate the structure of the display panel 200 by taking the example of a pixel driving circuit Q coupled to a light-emitting device O.

[0078] Figure 4 This is a structural diagram of an array substrate according to some embodiments.

[0079] Please see Figure 4 As shown, some embodiments of this disclosure provide an array substrate 100. The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 located on one side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q.

[0080] In some examples, substrate 01 can be a flexible substrate. Exemplarily, the material of substrate 01 can be an organic material. For example, the material of substrate 01 can be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0081] In other examples, substrate 01 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.

[0082] In some examples, the pixel circuit layer 02 includes multiple metal layers stacked on the substrate 01. Pixel driving circuits Q and various types of signal lines are disposed within these multiple metal layers. These different types of signal lines include multiple first scan signal lines G1, but are not limited to this; other types of signal lines may also be included, as will be described in detail below.

[0083] In this embodiment, multiple pixel driving circuits Q are located on one side of substrate 01, and the multiple pixel driving circuits Q are arranged in multiple rows and columns. For ease of explanation, the above-mentioned multiple pixel driving circuits Q are illustrated in a matrix form in this disclosure.

[0084] At this point, return Figure 2 As shown, pixel driving circuits Q arranged in a row along the first direction X are called a row pixel driving circuit Q, and pixel driving circuits Q arranged in a row along the second direction Y are called a column pixel driving circuit Q.

[0085] Figure 5 This is an equivalent circuit diagram of a pixel driving circuit based on some feasible implementations.

[0086] Please see Figure 5 As shown, the pixel driving circuit Q can be a first type of pixel driving circuit. The first type of pixel driving circuit includes: a first reset transistor M1, a compensation transistor M2, a driving transistor M3, a data writing transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second reset transistor M7, and a capacitor Cst.

[0087] Because the first type of pixel driving circuit needs to be electrically connected to various types of signal lines, therefore Figure 5The diagram also illustrates various types of signal lines. These various types of signal lines may include: a first scan signal line G1, a second scan signal line G2, a data write signal line Data, an enable signal line EM, a first power supply signal line Vdd, a first reset signal line R1, a second reset signal line R2, a first initialization signal line Vinit1, and a second initialization signal line Vinit2, etc.

[0088] The control electrode of the first reset transistor M1 is coupled to the first reset signal line R1, the first electrode of the first reset transistor M1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first reset transistor M1 is coupled to the first node N1.

[0089] The control electrode of the compensation transistor M2 is coupled to the first scan signal line Gate1, the first electrode of the compensation transistor M2 is coupled to the first node N1, and the second electrode of the compensation transistor M2 is coupled to the third node N3.

[0090] The control electrode of the driving transistor M3 is coupled to the first node N1, the first electrode of the driving transistor M3 is coupled to the second node N2, and the second electrode of the driving transistor M3 is coupled to the third node N3.

[0091] The control electrode of the data writing transistor M4 is coupled to the second scan signal line Gate2, the first electrode of the data writing transistor M4 is coupled to the data writing signal line Data, and the second electrode of the data writing transistor M4 is coupled to the second node N2.

[0092] The control electrode of the first light-emitting control transistor M5 is coupled to the enable signal line EM, the first electrode of the first light-emitting control transistor M5 is coupled to the first power supply signal line VDD, and the second electrode of the first light-emitting control transistor M5 is coupled to the second node N2.

[0093] The control electrode of the second light-emitting control transistor M6 is coupled to the enable signal line EM. The first electrode of the second light-emitting control transistor M6 is coupled to the third node N3. The second electrode of the second light-emitting control transistor M6 is coupled to one end of the light-emitting device O. The other end of the light-emitting device O is coupled to the third power signal line VSS. The voltage value of the third power signal provided by the third power signal line VSS is less than the voltage value of the first power signal provided by the first power signal line VDD.

[0094] For example, one end of the light-emitting device O coupled to the first pixel driving circuit is the anode of the light-emitting device O, and the other end of the light-emitting device O coupled to the third power signal point VSS is the cathode of the light-emitting device O.

[0095] The control electrode of the second reset transistor M7 is coupled to the second reset signal line R2, the first electrode of the second reset transistor M7 is coupled to the second initialization signal line Vinit2, and the second electrode of the second reset transistor M7 is coupled to the light-emitting device O.

[0096] It should be noted that each sub-pixel in the display panel 200 is driven to emit light by multiple thin-film transistors (TFTs). TFT driving technology can improve display speed, contrast, brightness, and resolution. However, TFTs exhibit a hysteresis effect. The hysteresis effect of a TFT is an uncertainty in the electrical characteristics of the TFT under a certain bias voltage; that is, the current flowing through the TFT is not only related to the current bias voltage but also to the state of the TFT at the previous moment. The hysteresis effect of a TFT is related to the TFT's gate dielectric, semiconductor material, and the interface state traps between them. During the light-emitting phase, the hysteresis effect of the TFT can cause a trend of current decrease within a frame, which is perceived by the human eye as flickering, thus affecting the display quality of the display panel 200.

[0097] To improve the hysteresis effect of the driving transistor M3, the threshold voltage of the pixel circuit is typically compensated to enhance the brightness uniformity of the entire display screen. Specifically, the threshold voltage of the pixel circuit can be compensated during data writing.

[0098] In some embodiments, for Figure 5 The driving process of the first pixel driving circuit shown is as follows: one frame cycle includes an initialization stage, a writing stage, and a light emission stage.

[0099] Initialization phase: The first reset signal transmitted by the first reset signal line R1 is a valid signal. At this time, the first reset transistor M1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the third node N3 to reset the third node N3, which helps to improve the stability of the driving transistor M3 included in the first pixel driving circuit.

[0100] During the writing phase: The first scan signal transmitted through the first scan signal line G1 is valid, and the compensation transistor M2 is turned on. Also, the second scan signal transmitted through the second scan signal line G2 is valid, at which point the data writing transistor M4 is turned on. The data writing signal transmitted through the data writing signal line Data can sequentially pass through the data writing transistor M4, the driving transistor M3, and the compensation transistor M2 to the first node N1, compensating for the first node N1. The potential of the first node N1 gradually rises to Vdata + Vth.

[0101] Where Vdata is the voltage value of the data write signal provided by the data write signal line Data, and Vth is the threshold voltage of the driving transistor M3 in the first pixel driving circuit. The charging process is completed when the potential of the first node N1 is Vdata + Vth. Subsequently, the storage capacitor Cst is discharged to keep the driving transistor M3 included in the first pixel driving circuit continuously conducting, ensuring that the light-emitting device O emits light.

[0102] During the light-emitting stage: The enable signal transmitted through the enable signal line EM is valid, at which point both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on. Meanwhile, the discharge of the storage capacitor Cst keeps the driving transistor M3, included in the first pixel driving circuit, continuously conducting.

[0103] Based on this, the constant voltage power signal provided by the first power signal line Vdd can flow sequentially through the first light-emitting control transistor M5, the driving transistor M3, and the second light-emitting control transistor M6 to the anode of the light-emitting device O. The cathode of the light-emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light-emitting device O to emit light. The first power signal line Vdd can be a high power signal line, and the third power signal line Vss can be a low power signal line.

[0104] It should be noted that a "valid signal" refers to a signal that enables the transistors it is electrically connected to to conduct. For example, if the first scan signal line G1 is electrically connected to a P-type transistor, the valid signal is a low-voltage signal; or, if the first scan signal line G1 is electrically connected to an N-type transistor, the valid signal is a high-voltage signal, and so on for other signal lines.

[0105] The inventors discovered that in the above-mentioned operation process, the threshold compensation and data voltage writing of the first pixel driving circuit are in the same stage (writing stage), which makes it impossible to separate the threshold compensation time from the row period.

[0106] When the display panel 200 has a high resolution or is driven by a high refresh rate, the line period of the display panel 200 becomes shorter, that is, the line period of each first pixel driving circuit becomes shorter, which shortens the writing stage duration of the first pixel driving circuit, resulting in a shorter threshold compensation duration of the first pixel driving circuit. The threshold compensation effect of the pixel driving circuit is poor, which in turn leads to poor display uniformity of the display panel 200.

[0107] Furthermore, when the display panel 200 is in a low grayscale image or in a black state, the voltage value Vdata of the data write signal provided by the data write signal line Data required by the driving transistor M3 is larger, which will result in a longer time required for data writing, and thus a shorter threshold compensation time for the first pixel driving circuit. The threshold compensation effect of the pixel driving circuit is poor, which will result in poor display uniformity of the display panel 200.

[0108] Figure 6 This is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.

[0109] Based on the above issues, please refer to Figure 6 As shown, some embodiments of this disclosure provide a pixel driving circuit Q. The pixel driving circuit Q can be a second type of pixel driving circuit. In the following text, the pixel driving circuit Q refers to the second type of pixel driving circuit.

[0110] The pixel driving circuit Q (the second type of pixel driving circuit) includes a driving sub-circuit 10, an emissive control sub-circuit 20, a writing sub-circuit 30, a compensation sub-circuit 40, and a storage sub-circuit 50.

[0111] A driving sub-circuit 10 is coupled to a first node N1, a second node N2, and a third node N3. The driving sub-circuit 10 is configured to transmit voltage from the second node N2 to the third node N3 under the control of the voltage at the first node N1. The driving sub-circuit 10 includes a driving transistor.

[0112] The light emission control sub-circuit 20 includes a first branch 21, which is coupled to a first power signal line VDD, a first enable signal line EM1, and a second node N2. The first branch 21 is configured to, during the compensation phase, cooperate with the drive sub-circuit 10 under the control of a first enable signal from the first enable signal line EM1 to transmit the first power signal received at the first power signal line VDD to the third node N3.

[0113] The compensation sub-circuit 40 is coupled to the first scan signal line Gate1, the second scan signal line Gate2, the first node N1, the third node N3, the fourth node N4, and the second power signal line VGH. The compensation sub-circuit 40 is configured to, during the compensation phase, transmit the voltage of the third node N3 to the first node N1 under the control of the first scan signal received from the first scan signal line Gate1, and to transmit the second power signal received from the second power signal line VGH to the fourth node N4 under the control of the second scan signal received from the second scan signal line Gate2.

[0114] The write sub-circuit 30 is coupled to the third scan signal line Gate3, the data write signal line Date, and the fourth node N4. The write sub-circuit 30 is configured to, during the write phase, transmit the data write signal received at the data write signal line Date to the fourth node N4 under the control of the third scan signal received from the third scan signal line Gate3.

[0115] The storage sub-circuit 50 is coupled to the first node N1 and the fourth node N4. During the write phase, the storage sub-circuit 50 is configured to couple the voltage of the fourth node N4 to the first node N1.

[0116] Using the above configuration, during the compensation phase, the first enable signal of the first enable signal line EM1 is a valid signal, controlling the first branch 21 in the light emission control sub-circuit 20 to be turned on. The first scan signal received at the first scan signal line Gate1 is a valid signal, and the second scan signal received at the second scan signal line Gate2 is also a valid signal, controlling the compensation sub-circuit 40 to be turned on.

[0117] Based on this, the control compensation sub-circuit 40 is turned on, which can transmit the second power signal received at the second power signal line VGH to the fourth node N4. At this time, the voltage of the fourth node N4 is the voltage V2 of the second power signal.

[0118] Furthermore, based on the conduction of the control compensation sub-circuit 40 and the conduction of the first branch 21, and in cooperation with the drive sub-circuit 10 (at this time, the drive sub-circuit 10 is in the conducting state), the first power signal received at the first power signal line VDD can be transmitted to the first node N1 via the second node N2 and the third node N3 to compensate the first node N1, and the potential of the first node N1 gradually rises to V1+Vth.

[0119] Where V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the second pixel driving circuit. When the potential of the first node N1 is V1+Vth, the driving sub-circuit 10 (driving transistor T3) is turned off, completing the threshold compensation.

[0120] Meanwhile, since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, one end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4, and the other end of the storage sub-circuit 50 receives the voltage V1+Vth from the first node N1. The storage sub-circuit 50 determines the voltage difference between its two ends.

[0121] Subsequently, the storage capacitor Cst is discharged to keep the driving sub-circuit 10 (driving transistor T3) included in the second pixel driving circuit continuously conducting, ensuring that the light-emitting device O emits light.

[0122] After the compensation phase, upon entering the writing phase, the third scan signal received at the third scan signal line Gate3 is valid, controlling the writing sub-circuit 30 to conduct. This transmits the data writing signal received at the data writing signal line Date to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the voltage change of the fourth node N4 is Δ = Vdata - V2. Here, Vdata is the voltage value of the data writing signal provided by the data writing signal line Data.

[0123] Due to the coupling effect of the storage sub-circuit 50, the voltage of the first node N1 follows the voltage change of the fourth node N4, and the voltage change of the first node N1 is approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0124] During the light-emitting phase, the first enable signal on the first enable signal line EM1 is active, controlling the first branch 21 in the light-emitting control sub-circuit 20 to conduct, allowing the first power signal received at the first power signal line VDD to be transmitted to the second node N2. At this time, the voltage of the second node N2 is V1. In conjunction with the driver sub-circuit 10, the voltage of the second node N2 can be transmitted to the third node N3, and finally to the light-emitting device O. Furthermore, the voltage of the first node N1 remains at Vdata + Vth.

[0125] The light-emitting current of the light-emitting device O, which is electrically connected to the pixel driving circuit Q, is equal to the current flowing through the driving sub-circuit 10, and its expression is as follows:

[0126] (1);

[0127] Where μ is the electron mobility of the driving sub-circuit 10 (driving transistor), and Cox is the insulation capacitance per unit area. Vth is the width-to-length ratio of the driving sub-circuit 10 (driving transistor), Vgs is the threshold voltage of the driving sub-circuit 10 (driving transistor), and Vgs is the gate-source voltage of the driving sub-circuit 10 (driving transistor). Vgs is the difference between the voltage at the first node N1 and the voltage at the second node N2, and its expression is as follows:

[0128] (2);

[0129] Based on this, substituting expression (2) into expression (1), we obtain the following expression:

[0130] (3);

[0131] Therefore, it can be known that the current flowing through the driver sub-circuit 10 (driver transistor) is... The current flowing through the driver sub-circuit 10 (driver transistor) is only related to the voltage Vdata of the data write signal provided by the data write signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH. It is independent of the threshold voltage Vth. Based on this, it can help to improve the influence of the threshold voltage Vth on the luminous brightness of the light-emitting device O, and improve the uniformity of the brightness of the light-emitting device O.

[0132] In summary, the pixel driving circuit Q provided in this embodiment can utilize the cooperation of the driving sub-circuit 10, the light emission control sub-circuit 20, the writing sub-circuit 30, the compensation sub-circuit 40, and the storage sub-circuit 50 to implement the written data voltage Vdata and the compensation threshold voltage through two separate paths, separating the threshold compensation stage from the writing stage to prevent the duration of the writing stage from limiting the duration of the threshold compensation stage. That is, the duration of the threshold compensation stage is not affected by the data writing time (line time), ensuring that the threshold compensation stage has sufficient duration to fully write the required voltage to compensate for threshold voltage fluctuations over a large range, thus achieving complete threshold voltage compensation.

[0133] Based on this, the problem of poor display uniformity in high-resolution display panels 200 or display panels 200 driven by high refresh rates, caused by insufficient Q-threshold compensation stage duration in the pixel driving circuit, can be effectively improved. Furthermore, the problem of poor display uniformity in low grayscale images and black states, caused by insufficient threshold compensation stage duration in the pixel driving circuit, can also be effectively improved.

[0134] That is, even at high refresh rates, or in low grayscale images and black states, the pixel driving circuit Q provided in this embodiment can fully compensate the threshold voltage of the driving sub-circuit 10 (driving transistor T3) within the pixel driving circuit Q, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0135] In some embodiments, please refer to Figure 6 As shown, the voltage value V1 of the first power supply signal is equal to the voltage value V2 of the second power supply signal, and its expression is as follows:

[0136] V2=V1; (4);

[0137] Based on this, after the compensation phase and during the light emission phase, the voltage of the first node N1 can be V1 + Vth + Vdata - V2 = Vth + Vdata.

[0138] Furthermore, the gate-source voltage Vgs of the driving sub-circuit 10 (driving transistor) (5);

[0139] Substituting expression (5) into expression (1) above, we get the following expression:

[0140] (6);

[0141] Therefore, it can be known that the current flowing through the driver sub-circuit 10 (driver transistor) is... The current of the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data write signal provided by the data write signal line Data and the voltage V1 of the first power signal provided by the first power signal line VDD. It is independent of the threshold voltage Vth. Based on this, it can help to improve the influence of the threshold voltage Vth on the luminous brightness of the light-emitting device O, and improve the uniformity of the brightness of the light-emitting device O.

[0142] In some embodiments, please refer to Figure 6 As shown, the first power signal line VDD is multiplexed into the second power signal line VGH.

[0143] This configuration allows the first power signal line VDD to be reused as the second power signal line VGH, eliminating the need for a separate second power signal line VGH. This simplifies the structure of the pixel driving circuit Q and reduces the layout difficulty within the display panel 200.

[0144] On the other hand, multiplexing the first power signal line VDD as the second power signal line VGH can make the voltage value V1 of the first power signal equal to the voltage value V2 of the second power signal, thereby increasing the current flowing through the driver sub-circuit 10 (driving transistor). The current of the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data write signal provided by the data write signal line Data and the voltage V1 of the first power signal provided by the first power signal line VDD. It is independent of the threshold voltage Vth. Based on this, it can help to improve the influence of the threshold voltage Vth on the luminous brightness of the light-emitting device O, and improve the uniformity of the brightness of the light-emitting device O.

[0145] Figure 7 This is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments.

[0146] In some embodiments, please refer to Figure 7As shown, the driving sub-circuit 10 includes a driving transistor T3. The control electrode of the driving transistor T3 is coupled to the first node N1, the first electrode of the driving transistor T3 is coupled to the second node N2, and the second electrode of the driving transistor T3 is coupled to the third node N3.

[0147] When the voltage of the first node N1 is an effective signal, the driving transistor T3 can be turned on under the control of the voltage of the first node N1 to transmit the electrical signal (e.g., data signal) from the second node N2 to the third node N3.

[0148] It should be noted that, in this disclosure, "effective signal" refers to a signal that enables the transistor to conduct. When the transistor is an N-type transistor, the "effective signal" is a high-voltage signal; when the transistor is a P-type transistor, the "effective signal" is a low-voltage signal. The following embodiments are the same and will not be described again.

[0149] For example, when the driving transistor T3 is a P-type transistor, the driving transistor T3 is turned on when the voltage of the first node N1 is a low voltage signal, so that the electrical signal (e.g., data signal) from the second node N2 can be transmitted to the third node N3.

[0150] For example, when the driving transistor T3 is an N-type transistor, the driving transistor T3 is turned on when the voltage of the first node N1 is a high voltage signal, so that the electrical signal (e.g., data signal) from the second node N2 can be transmitted to the third node N3.

[0151] It should be noted that the terms "high voltage signal" and "low voltage signal" mentioned above are colloquial terms. Generally speaking, the condition for an N-type transistor to turn on is that the gate-source voltage difference is greater than its threshold voltage. That is, the gate voltage of an N-type transistor is greater than the sum of its source voltage and its threshold voltage. If the threshold voltage of an N-type transistor is positive, then the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The condition for a P-type transistor to turn on is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. If the threshold voltage of a P-type transistor is negative, that is, the gate voltage of a P-type transistor is less than the sum of its source voltage and its threshold voltage, then the gate voltage signal that turns on the P-type transistor is called a low voltage signal. In this case, the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0152] In some embodiments, please refer to Figure 7As shown, the compensation sub-circuit 40 includes a second transistor T2 and a ninth transistor T9. The control electrode of the second transistor T2 is coupled to the first scan signal line Gate1, the first electrode of the second transistor T2 is coupled to the third node N3, and the second electrode of the second transistor T2 is coupled to the first node N1. The control electrode of the ninth transistor T9 is coupled to the third scan signal line Gate3, the first electrode of the ninth transistor T9 is coupled to the second power supply signal line VGH, and the second electrode of the ninth transistor T9 is coupled to the fourth node N4.

[0153] Based on this, during the compensation phase, the second scan signal received at the second scan signal line Gate2 is also a valid signal, which controls the ninth transistor T9 to turn on, so that the second power signal received at the second power signal line VGH can be transmitted to the fourth node N4.

[0154] Furthermore, during the compensation phase, the first scan signal received at the first scan signal line Gate1 is a valid signal, which controls the second transistor T2 to turn on, so that the voltage of the third node N3 can be transmitted to the first node N1 to compensate the first node N1. The potential of the first node N1 gradually rises to V1+Vth, the driving sub-circuit 10 (driving transistor T3) turns off, and the threshold compensation is completed, as well as the charging process of the storage sub-circuit 50 is completed.

[0155] In some embodiments, please refer to Figure 7 As shown, the write sub-circuit 30 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is coupled to the third scan signal line Gate3, the first electrode of the fourth transistor T4 is coupled to the data write signal line Date, and the second electrode of the fourth transistor T4 is coupled to the fourth node N4.

[0156] Based on this, during the write phase, the third scan signal received at the third scan signal line Gate3 is a valid signal, controlling the fourth transistor T4 to turn on and transmit the data write signal received at the data write signal line Date to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the voltage change of the fourth node N4 is Δ = Vdata - V2. Here, Vdata is the voltage value of the data write signal provided by the data write signal line Data.

[0157] Due to the coupling effect of the storage sub-circuit 50, the voltage of the first node N1 follows the voltage change of the fourth node N4, and the voltage change of the first node N1 is approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0158] The subsequent calculation involves the current flowing through the driver sub-circuit 10 (driver transistor). When the threshold voltage Vth is eliminated, the effect of the threshold voltage Vth on the luminous brightness of the light-emitting device O can be reduced, thus improving the uniformity of the brightness of the light-emitting device O.

[0159] In some embodiments, please refer to Figure 7 As shown, the storage sub-circuit 50 includes a storage capacitor Cst, the first plate of the storage capacitor Cst is coupled to the fourth node N4, and the second plate of the storage capacitor Cst is coupled to the first node N1.

[0160] During the compensation phase, since the first plate of the storage capacitor Cst is coupled to the fourth node N4, the voltage of the first plate of the storage capacitor Cst is the voltage V2 of the second power signal received at the second power signal line VGH; and since the second plate of the storage capacitor Cst is coupled to the first node N1, the voltage of the second plate of the storage capacitor Cst is the voltage V1 + Vth of the first node N.

[0161] During the write phase, the third scan signal received at the third scan signal line Gate3 is valid, controlling the fourth transistor T4 to turn on and transmit the data write signal received at the data write signal line Date to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata, and the voltage change of the fourth node N4 is Δ = Vdata - V2.

[0162] Due to the coupling effect of the storage capacitor Cst, the voltage of the first node N1 can follow the change of the voltage of the fourth node N4.

[0163] Based on this, the voltage change at the first node N1 is approximately Δ = Vdata - V2. Therefore, the voltage at the first node N1 can change from V1 + Vth to V1 + Vth + Δ = V1 + Vth + Vdata - V2.

[0164] The subsequent calculation involves the current flowing through the driver sub-circuit 10 (driver transistor). When the threshold voltage Vth is eliminated, the effect of the threshold voltage Vth on the luminous brightness of the light-emitting device O can be reduced, thus improving the uniformity of the brightness of the light-emitting device O.

[0165] Figure 8 This is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments.

[0166] In some embodiments, please refer to Figure 8 As shown, the light-emitting control sub-circuit 20 in the pixel driving circuit Q also includes a second branch 22. The second branch 22 is coupled to the third node N3, the second enable signal line EM2, and the light-emitting device O.

[0167] During the light-emitting stage, under the control of the second enable signal from the second enable signal line EM2, the second branch 22 is turned on, which can transmit the voltage of the third node N3 to the light-emitting device O to drive the light-emitting device O to emit light.

[0168] Regarding the light-emitting control sub-circuit 20, during the light-emitting stage, it is configured such that the first branch 21 is turned on under the control of the first enable signal from the first enable signal line EM1, and the second branch 22 is turned on under the control of the second enable signal from the second enable signal line EM2. It can also cooperate with the driving sub-circuit 10 to transmit the first power signal received at the first power signal line VDD to the light-emitting device O. That is, during the light-emitting stage, the light-emitting control sub-circuit 20 is configured to transmit the first power signal received at the first power signal line VDD to the anode of the light-emitting device O, while the cathode of the light-emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light-emitting device O to emit light.

[0169] In some embodiments, please continue reading Figure 8 As shown, the first branch 21 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is coupled to the first enable signal line EM1, the first electrode of the fifth transistor T5 is coupled to the first power supply signal line VDD, and the second electrode of the fifth transistor T5 is coupled to the second node N2.

[0170] During the compensation phase, the first enable signal provided by the first enable signal line EM1 is a valid signal, controlling the fifth transistor T5 to turn on, and the first power signal provided by the first power signal line VDD is transmitted to the second node N2; then, in cooperation with the driving sub-circuit 10, the voltage of the second node N2 (the voltage V1 of the first power signal) is transmitted to the third node N3; finally, in cooperation with the compensation sub-circuit 40, the voltage of the third node N3 (the voltage V1 of the first power signal) is transmitted to the first node N1 until the voltage of the first node N1 is V1+Vth, controlling the driving sub-circuit 10 (driving transistor T3) to turn off, thus completing the threshold compensation.

[0171] In some embodiments, please continue reading Figure 8 As shown, the second branch 22 includes a sixth transistor T6, the control electrode of the sixth transistor T6 is coupled to the second enable signal line EM2, the first electrode of the sixth transistor T6 is coupled to the third node N3, and the second electrode of the sixth transistor T6 is coupled to the light-emitting device O.

[0172] During the light-emitting stage, the first enable signal provided by the first enable signal line EM1 is a valid signal, which controls the fifth transistor T5 to turn on. The second enable signal provided by the second enable signal line EM2 is also a valid signal, which controls the sixth transistor T6 to turn on. Then, in conjunction with the driver sub-circuit 10, the first power signal provided by the first power signal line VDD is transmitted to the light-emitting device O to drive the light-emitting device O to emit light.

[0173] In some embodiments, please continue reading Figure 8 As shown, the pixel driving circuit Q also includes a first reset sub-circuit 60. The first reset sub-circuit 60 is coupled to the first node N1, the first reset signal line R1, and the first initialization signal line Vinit1. The first reset sub-circuit 60 is configured to, under the control of a first reset signal received from the first reset signal line R1, transmit a first initialization signal received from the first initialization signal line Vinit1 to the first node N1 to initialize the first node N1.

[0174] Before the compensation phase, the first node N1 of the pixel driving circuit Q can be initialized. At this time, the first reset signal provided by the first reset signal line R1 is valid, controlling the first reset sub-circuit 60 to conduct. The first initialization signal received by the first initialization signal line Vinit1 is transmitted to the first node N1 to initialize it. That is, the control electrode of the driving transistor T3 is initialized using the first initialization signal provided by the first initialization signal line Vinit1, thereby improving the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0175] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low-voltage signal. Based on this, before the compensation phase, the low-voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0176] For example, a low voltage signal can be a signal lower than the voltage Vdata of the data write signal when the display panel 200 displays any grayscale, in order to eliminate signal residue when displaying the previous frame of the image.

[0177] In some embodiments, please continue reading Figure 8 As shown, the first reset sub-circuit 60 includes a first transistor T1, the control electrode of the first transistor T1 is coupled to the first reset signal line R1, the first electrode of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the first node N1.

[0178] Before the compensation phase, the first reset signal provided by the first reset signal line R1 can be controlled to be a valid signal, the first transistor T1 can be turned on, the first initialization signal received by the first initialization signal line Vinit1 can be transmitted to the first node N1, the first node N1 can be reset, and the control electrode of the driving transistor T3 can be reset, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0179] Furthermore, when initializing the first node N1 using the first initialization signal provided by the first initialization signal line Vinit1, the first initialization signal provided by Vinit1 is simultaneously transmitted to the storage capacitor Cst in the storage sub-circuit 50. Subsequently, during the compensation phase, the storage capacitor Cst in the storage sub-circuit 50 can be discharged to keep the driving sub-circuit 10 (driving transistor T3) continuously conducting, ensuring that the first power signal provided by the first power signal terminal VDD can be transmitted to the first node N1.

[0180] In some embodiments, please continue reading Figure 8 As shown, the pixel driving circuit Q also includes a second reset sub-circuit 70. The second reset sub-circuit 70 is coupled to the light-emitting device O, the second reset signal line R2, and the second initialization signal line Vinit2. The second reset sub-circuit 70 is configured to, under the control of a second reset signal received from the second reset signal line R2, transmit a second initialization signal received from the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the light-emitting device O.

[0181] Before the light-emitting stage, the light-emitting device O, which is electrically connected to the pixel driving circuit Q, can be reset. At this time, the second reset signal provided by the second reset signal line R2 is a valid signal, which controls the second reset sub-circuit 70 to be turned on, so as to transmit the second initialization signal received by the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the anode of the light-emitting device O and improving the stability of the light-emitting device O.

[0182] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low-voltage signal. Based on this, before the light emission stage, the low-voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O from emitting light, thereby reducing the influence of the charge remaining on the anode of the light-emitting device O on the brightness and improving the uniformity of the brightness of the light-emitting device O.

[0183] For example, the low voltage signal can be a signal less than 0V to control the light-emitting device O to not emit light, thereby reducing the effect of the charge remaining on the anode of the light-emitting device O on the brightness of the light emission.

[0184] In some embodiments, please continue reading Figure 8As shown, the second reset circuit 70 includes a seventh transistor T7, the control electrode of the seventh transistor T7 is coupled to the second reset signal line R2, the first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, and the second electrode of the seventh transistor T7 is coupled to the light-emitting device O.

[0185] Before the light-emitting stage, the second reset signal provided by the second reset signal line R2 can be controlled to be a valid signal, and the seventh transistor T7 can be turned on to transmit the second initialization signal received by the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the anode of the light-emitting device O and improving the stability of the light-emitting device O.

[0186] In some embodiments, please continue reading Figure 8 As shown, the pixel driving circuit Q also includes a third reset sub-circuit 80. The third reset sub-circuit 80 is coupled to the second node N2, the third reset signal line R3, and the first reference voltage signal line Vref. The third reset sub-circuit 80 is configured to, under the control of the third reset signal received from the third reset signal line R3, transmit the first reference voltage signal received from the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2.

[0187] Before the compensation phase, the third reset signal provided by the third reset signal line R3 can be controlled to be valid, thereby controlling the third reset sub-circuit 80 to conduct and transmit the first reference voltage signal received by the first reference voltage signal line Vref to the second node N2, resetting the second node N2. Based on this, the initial state of the driving transistor T3 can be fixed before the writing phase, making it easier to keep the driving transistor T3 in a stable state during the writing phase and greatly improving the hysteresis effect of the driving transistor T3.

[0188] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref can be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in a conduction-biased state. That is, before data is written, the driving transistor is in a conduction-biased state, ensuring that the driving transistors in each pixel driving circuit start charging and compensating from the conduction-biased state, unaffected by the data voltage of the previous frame. This eliminates the hysteresis effect of the driving transistor T3, improving image retention and response time.

[0189] In some embodiments, please continue reading Figure 8 As shown, the third reset circuit 80 includes an eighth transistor T8. The control electrode of the eighth transistor T8 is coupled to the third reset signal line R3. The first electrode of the eighth transistor T8 is coupled to the first reference voltage signal line Vref. The second electrode of the eighth transistor T8 is coupled to the second node N2.

[0190] Before the compensation phase, the third reset signal provided by the third reset signal line R3 can be controlled to be valid, thereby controlling the eighth transistor T8 to turn on and transmit the first reference voltage signal received by the first reference voltage signal line Vref to the second node N2, resetting the second node N2. Based on this, the initial state of the driving transistor T3 can be fixed before the writing phase, making it easier to keep the driving transistor T3 in a stable state during the writing phase and greatly improving the hysteresis effect of the driving transistor T3.

[0191] In some embodiments, please continue reading Figure 8 As shown, the third reset signal line R3 is multiplexed as the second reset signal line R2.

[0192] This configuration allows the third reset signal line R3 to be reused as the second reset signal line R2, eliminating the need for a separate second reset signal line R2. This simplifies the structure of the pixel driving circuit Q and reduces the layout difficulty within the display panel 200.

[0193] On the other hand, by multiplexing the third reset signal line R3 as the second reset signal line R2, the second reset sub-circuit 70 (seventh transistor T7) can be turned on multiple times using the third reset signal (once during the reset phase, once after the write phase, and once before the light emission phase). The second initialization signal received by the second initialization signal line Vinit2 is transmitted to the light-emitting device O, and the anode of the light-emitting device O is reset multiple times, which can help improve the stability of the light-emitting device O.

[0194] In some embodiments, please continue reading Figure 8 As shown, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9:

[0195] All nine transistors can be configured to be P-type transistors. That is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can all be P-type transistors.

[0196] When all nine transistors are P-type transistors, the aforementioned "effective signal" can be understood as a low-voltage signal. That is, all nine transistors can be turned on under the control of a low-level signal.

[0197] In some examples, all nine transistors can be configured as Low-Temperature Poly-silicon (LTPS) transistors. That is, transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9 can all be LTPS transistors. Because LTPS transistors have higher carrier mobility, they can achieve faster response times.

[0198] Figure 9 This is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments.

[0199] In some embodiments, please refer to Figure 9 As shown, the first transistor T1 in the first reset circuit 60 of the pixel driving circuit Q can be an N-type transistor. When the first transistor T1 is an N-type transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the first transistor T1 can be turned on under the control of a high-voltage signal.

[0200] Setting the first transistor T1 as an N-type transistor can help reduce the risk of leakage current in the first transistor T1 and help ensure the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0201] In some examples, the semiconductor material of the N-type transistor can be indium gallium zinc oxide (IGZO). Oxide transistors have a smaller turn-off leakage current, which can reduce the leakage current of the first node N1 through the first transistor T1 during the light-emitting stage.

[0202] In some embodiments, please refer to Figure 9 As shown, the second transistor T2 in the compensation sub-circuit 40 of the pixel driving circuit Q can be an N-type transistor. When the second transistor T2 is an N-type transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the second transistor T2 can be turned on under the control of a high-voltage signal.

[0203] Setting the second transistor T2 as an N-type transistor can help reduce the risk of leakage current in the second transistor T2 and help ensure the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0204] In some examples, the semiconductor material of the N-type transistor can be indium gallium zinc oxide (IGZO). Oxide transistors have a smaller turn-off leakage current, which can reduce the leakage current of the first node N1 through the second transistor T2 during the light-emitting stage.

[0205] In some embodiments, please refer to Figure 9 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, during the light-emitting stage, both the first node N1 and the fourth node N4 are in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0206] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 of the pixel driving circuit Q can be an N-type transistor. When the fourth transistor T4 is an N-type transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the fourth transistor T4 can be turned on under the control of a high-voltage signal.

[0207] Setting the fourth transistor T4 as an N-type transistor can help reduce the risk of leakage current in the fourth transistor T4 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1, thus improving the stability of the voltage of the first node N1, which in turn ensures the stability of the driving transistor T3, thereby improving the brightness retention rate of the light-emitting device O within a frame.

[0208] In some examples, the semiconductor material of the N-type transistor can be indium gallium zinc oxide (IGZO). Oxide transistors have a smaller turn-off leakage current, which can reduce the leakage current of the fourth node N4 through the fourth transistor T4 during the light-emitting stage.

[0209] In some embodiments, please refer to Figure 9 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, during the light-emitting stage, both the first node N1 and the fourth node N4 are in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0210] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 of the pixel driving circuit Q can be an N-type transistor. When the ninth transistor T9 is an N-type transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the aforementioned ninth transistor T9 can be turned on under the control of a high-voltage signal.

[0211] Setting the ninth transistor T9 as an N-type transistor can help reduce the risk of leakage current in the ninth transistor T9 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1, thus improving the stability of the voltage of the first node N1, which in turn ensures the stability of the driving transistor T3, thereby improving the brightness retention rate of the light-emitting device O within a frame.

[0212] In some examples, the semiconductor material of the N-type transistor can be indium gallium zinc oxide (IGZO). Oxide transistors have a smaller turn-off leakage current, which can reduce the leakage current of the fourth node N4 through the ninth transistor T9 during the light-emitting stage.

[0213] In some embodiments, please refer to Figure 9 As shown, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a ninth transistor T9: at least one of the four transistors T1, T2, T4, and T9 is an N-type transistor.

[0214] This configuration can improve the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, thereby improving the brightness retention rate of the light-emitting device O within a frame.

[0215] The phrase "at least one of the four transistors T1, T2, T4, and T9 is an N-type transistor" can include the following cases:

[0216] The first type: any one of the four transistors, namely the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9, can be an N-type transistor.

[0217] The second type: Any two of the four transistors, namely the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9, can be N-type transistors.

[0218] The third type: any three of the four transistors, namely the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9, can be N-type transistors.

[0219] The fourth type: All four transistors—the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9—are N-type transistors. Among them, Figure 9 The illustration is based on the example where the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all N-type transistors. However, this disclosure is not limited to this.

[0220] Regardless of how many of the four transistors—the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9—are set to N-type transistors, it can improve the stability of the driving transistor T3 and enhance the brightness retention rate of the light-emitting device O within a frame.

[0221] Figure 10 This is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments.

[0222] In some embodiments, please refer to Figure 10 As shown, the first transistor T1 in the first reset circuit 60 of the pixel driving circuit Q can be a dual-gate transistor.

[0223] When the first transistor T1 is a dual-gate transistor: the first transistor T1 can be a P-type transistor or the first transistor T1 can be an N-type transistor.

[0224] When the first transistor T1 is a P-type dual-gate transistor, the aforementioned "effective signal" can be understood as a low-voltage signal. That is, the first transistor T1 can be turned on under the control of a low-voltage signal.

[0225] When the first transistor T1 is an N-type dual-gate transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the first transistor T1 can be turned on under the control of a high-voltage signal.

[0226] Setting the first transistor T1 as a dual-gate transistor can improve its stability, thereby reducing the risk of leakage current in the first transistor T1. Based on this, it can help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0227] In some embodiments, please refer to Figure 10 As shown, the second transistor T2 in the compensator circuit 40 of the pixel driving circuit Q can be a dual-gate transistor.

[0228] When the second transistor T2 is a dual-gate transistor: the second transistor T2 can be a P-type transistor or the second transistor T2 can be an N-type transistor.

[0229] When the second transistor T2 is a P-type dual-gate transistor, the aforementioned "effective signal" can be understood as a low-voltage signal. That is, the second transistor T2 can be turned on under the control of a low-voltage signal.

[0230] When the second transistor T2 is an N-type dual-gate transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the second transistor T2 can be turned on under the control of a high-voltage signal.

[0231] Setting the second transistor T2 as a dual-gate transistor can improve its stability, thereby reducing the risk of leakage current. Based on this, it can help ensure the stability of the voltage at the first node N1, that is, ensure the stability of the driving transistor T3, thus improving the brightness retention rate of the light-emitting device O within a frame.

[0232] In some embodiments, please refer to Figure 10 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, during the light-emitting stage, both the first node N1 and the fourth node N4 are in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0233] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 of the pixel driving circuit Q can be a dual-gate transistor.

[0234] When the fourth transistor T4 is a dual-gate transistor: the fourth transistor T4 can be a P-type transistor or an N-type transistor.

[0235] When the fourth transistor T4 is a P-type dual-gate transistor, the aforementioned "effective signal" can be understood as a low-voltage signal. That is, the fourth transistor T4 can be turned on under the control of a low-voltage signal.

[0236] When the fourth transistor T4 is an N-type dual-gate transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the fourth transistor T4 can be turned on under the control of a high-voltage signal.

[0237] Setting the fourth transistor T4 as a dual-gate transistor can improve its stability, thereby reducing the risk of leakage current and ensuring the stability of the voltage at the fourth node N4. This prevents the fourth node N4 from affecting the voltage at the first node N1, improving the stability of the first node N1's voltage, and consequently ensuring the stability of the driving transistor T3, thus improving the brightness retention rate of the light-emitting device O within a frame.

[0238] In some embodiments, please refer to Figure 10 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, during the light-emitting stage, both the first node N1 and the fourth node N4 are in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0239] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 of the pixel driving circuit Q can be set as a dual-gate transistor.

[0240] When the ninth transistor T9 is a dual-gate transistor: the ninth transistor T9 can be a P-type transistor or the ninth transistor T9 can be an N-type transistor.

[0241] When the ninth transistor T9 is a P-type dual-gate transistor, the aforementioned "effective signal" can be understood as a low-voltage signal. That is, the ninth transistor T9 can be turned on under the control of a low-voltage signal.

[0242] When the ninth transistor T9 is an N-type dual-gate transistor, the aforementioned "effective signal" can be understood as a high-voltage signal. That is, the ninth transistor T9 can be turned on under the control of a high-voltage signal.

[0243] Setting the ninth transistor T9 as a dual-gate transistor can improve its stability, thereby reducing the risk of leakage current and ensuring the stability of the voltage at the fourth node N4. This prevents the fourth node N4 from affecting the voltage at the first node N1, thus improving the stability of the first node N1's voltage, which in turn ensures the stability of the driving transistor T3, thereby improving the brightness retention rate of the light-emitting device O within a frame.

[0244] In some embodiments, please refer to Figure 10 As shown, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a ninth transistor T9: at least one of the four transistors T1, T2, T4, and T9 is a dual-gate transistor.

[0245] This configuration can improve the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, thereby improving the brightness retention rate of the light-emitting device O within a frame.

[0246] The phrase "at least one of the four transistors T1, T2, T4, and T9 is a dual-gate transistor" can include the following cases:

[0247] The first type: any one of the four transistors, namely the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9, can be a dual-gate transistor.

[0248] The second type: any two of the four transistors, namely the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9, can be dual-gate transistors.

[0249] The third type: any three of the four transistors, namely the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9, can be dual-gate transistors.

[0250] The fourth type: All four transistors—the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9—are dual-gate transistors. Among them, Figure 10 The illustration is based on the example where the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all dual-gate transistors. However, this disclosure is not limited to this.

[0251] Regardless of how many of the four transistors—the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9—are configured as dual-gate transistors, it can improve the stability of the driving transistor T3 and enhance the brightness retention rate of the light-emitting device O within a single frame.

[0252] Figure 11 This is a timing diagram of a pixel driving circuit according to some embodiments.

[0253] Some embodiments of this disclosure also provide a driving method for a pixel driving circuit, which is applied to the pixel driving circuit Q in any of the above embodiments.

[0254] Please combine Figures 8-10 As shown, the pixel driving circuit Q includes: a driving sub-circuit 10, an emissive control sub-circuit 20, a writing sub-circuit 30, a compensation sub-circuit 40, and a storage sub-circuit 50. The driving sub-circuit 10 is coupled to a first node N1, a second node N2, and a third node N3. The emissive control sub-circuit 20 includes a first branch 21, which is coupled to a first power signal line VDD, a first enable signal line EM1, and a second node N2. The compensation sub-circuit 40 is coupled to a first scan signal line Gate1, a second scan signal line Gate2, a first node N1, a third node N3, a fourth node N4, a first power signal line VDD, and a second power signal line VGH; wherein the voltage value of the first power signal is equal to the voltage value of the second power signal. The writing sub-circuit 30 is coupled to a third scan signal line Gate3, a data writing signal line Date, and a fourth node N4. The storage sub-circuit 50 is coupled to the first node N1 and the fourth node N4.

[0255] First of all, with Figure 8 The pixel driving circuit Q shown is used as an example for explanation; that is, the explanation is based on the premise that all nine transistors in pixel driving circuit Q are P-type transistors. The following method also applies to pixel driving circuit Q that includes P-type dual-gate transistors; that is, the following method also applies to… Figure 10 The pixel driving circuit shown.

[0256] The driving method includes multiple emission cycles F. One emission cycle F (one frame) includes one refresh frame and at least one hold frame. One emission cycle (one frame) is one display frame, that is, one display screen.

[0257] The refresh frame includes a compensation phase t2 and a writing phase t3.

[0258] During compensation phase t2, the second scan signal provided by the second scan signal line Gate2 is a low-level signal, controlling the compensation sub-circuit 40 (ninth transistor T9) to conduct, transmitting the second power signal received at the second power signal line VGH to the fourth node N4. At this time, the voltage value of the fourth node N4 is the voltage value V2 of the second power signal.

[0259] The first enable signal provided by the first enable signal line EM1 is a low voltage signal, which controls the first branch 21 to be turned on, and can transmit the first power signal received at the first power signal line VDD to the second node N2; then, in cooperation with the driver sub-circuit, the voltage of the second node N2 is transmitted to the third node N3.

[0260] The first scan signal provided by the first scan signal line Gate1 is a low voltage signal, which controls the compensation sub-circuit 40 (second transistor T2) to turn on, and transmits the voltage of the third node N3 to the first node N1 to compensate the first node N1. The potential of the first node N1 gradually rises to V1+Vth.

[0261] Where V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the second pixel driving circuit. When the potential of the first node N1 is V1+Vth, the driving sub-circuit 10 (driving transistor T3) is turned off, completing the threshold compensation.

[0262] Since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, when one end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4 and the other end of the storage sub-circuit 50 receives the voltage V1+Vth from the first node N1, the charging process of the storage sub-circuit 50 is completed.

[0263] Based on this, the first power signal provided by the first power signal line VDD can be used to perform threshold compensation on the driving transistor T3 included in the driving sub-circuit 10.

[0264] During the write phase t3, the third scan signal provided by the third scan signal line Gate3 is a low-voltage signal, controlling the data write sub-circuit 30 (fourth transistor T4) to turn on. The data write signal received at the data write signal line Date is transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the voltage change of the fourth node N4 is Δ = Vdata - V2. Where Vdata is the voltage value of the data write signal provided by the data write signal line Data.

[0265] The storage sub-circuit 50 couples the voltage of the fourth node N4 to the first node N1. That is, the voltage of the first node N1 follows the change in the voltage of the fourth node N4, and the change in the voltage of the first node N1 is approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0266] In some examples, the refresh frame may also include a light-up phase t5 after the write phase t3.

[0267] During the light-emitting stage t5, the first enable signal of the first enable signal line EM1 is a low voltage signal, which controls the first branch 21 (the fifth transistor T5) to conduct, allowing the first power signal received at the first power signal line VDD to be transmitted to the second node N2. At this time, the voltage of the second node N2 is V1. In conjunction with the driver sub-circuit 10, the voltage of the second node N2 can be transmitted to the third node N3, and finally to the light-emitting device O.

[0268] The light-emitting current of the light-emitting device O, which is electrically connected to the pixel driving circuit Q, is equal to the current flowing through the driving sub-circuit 10, and its expression is as follows:

[0269] (1);

[0270] Where μ is the electron mobility of the driving sub-circuit 10 (driving transistor), and Cox is the insulation capacitance per unit area. Vth is the width-to-length ratio of the driving sub-circuit 10 (driving transistor), Vgs is the threshold voltage of the driving sub-circuit 10 (driving transistor), and Vgs is the gate-source voltage of the driving sub-circuit 10 (driving transistor). Vgs is the difference between the voltage at the first node N1 and the voltage at the second node N2, and its expression is as follows:

[0271] (2);

[0272] Based on this, substituting expression (2) into expression (1), we obtain the following expression:

[0273] (3);

[0274] Therefore, it can be known that the current flowing through the driver sub-circuit 10 (driver transistor T3) is... The current flowing through the driver sub-circuit 10 (driver transistor) is only related to the voltage Vdata of the data write signal provided by the data write signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH. It is independent of the threshold voltage Vth. Based on this, it can help to improve the influence of the threshold voltage Vth on the luminous brightness of the light-emitting device O, and improve the uniformity of the brightness of the light-emitting device O.

[0275] In summary, the pixel driving circuit Q-driving method provided in this disclosure includes a separate compensation stage t2 and a writing stage t3. That is, the written data voltage Vdata and the compensation threshold voltage are implemented through two separate paths, separating the threshold compensation stage from the writing stage to prevent the duration of the writing stage from limiting the duration of the threshold compensation stage. This ensures that the duration of the threshold compensation stage is not affected by the data writing time (line time), guaranteeing sufficient duration for the threshold compensation stage to fully write the required voltage, compensating for threshold voltage fluctuations over a wide range, and achieving complete threshold voltage compensation.

[0276] Based on this, the problem of poor display uniformity in high-resolution display panels 200 or display panels 200 driven by high refresh rates, caused by insufficient threshold compensation phase duration during pixel driving circuit Q, can be effectively improved. Furthermore, the problem of poor display uniformity in low grayscale images and black states, caused by insufficient threshold compensation phase duration during pixel driving circuit Q, can also be effectively improved.

[0277] That is, even at high refresh rates, or in low grayscale images and black states, the pixel driving circuit Q provided in this embodiment can fully compensate the threshold voltage of the driving sub-circuit 10 (driving transistor T3) within the pixel driving circuit Q, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0278] In some embodiments, please continue to combine Figure 8 and Figure 11 As shown, the pixel driving circuit Q also includes a third reset sub-circuit 80. The third reset sub-circuit 80 is coupled to the second node N2, the third reset signal line R3, and the first reference voltage signal line Vref.

[0279] The refresh frame also includes a reset phase t1, which may include a first reset phase t11.

[0280] In the first reset phase t11, the third reset signal provided by the third reset signal line R3 is a low voltage signal, which controls the third reset sub-circuit (eighth transistor T8) 80 to turn on, and transmits the first reference voltage signal received by the first reference voltage signal line Vref to the second node N2, thus resetting the second node N2.

[0281] Based on this, it is equivalent to resetting the second node N2 of the pixel driving circuit Q before the compensation stage t2. This allows the initial state of the driving transistor T3 to be fixed before the writing stage, facilitating a stable state for T3 during the writing stage and significantly improving the hysteresis effect of T3.

[0282] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref can be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in a conduction-biased state. That is, before data is written, the driving transistor is in a conduction-biased state, ensuring that the driving transistors in each pixel driving circuit start charging and compensating from the conduction-biased state, unaffected by the data voltage of the previous frame. This eliminates the hysteresis effect of the driving transistor T3, improving image retention and response time.

[0283] In some embodiments, please continue to combine Figure 8 and Figure 11 As shown, the pixel driving circuit Q also includes a second reset sub-circuit 70. The second reset sub-circuit 70 is coupled to the light-emitting device O, the second reset signal line R2, and the second initialization signal line Vinit2.

[0284] In the first reset phase t11, the second reset signal provided by the second reset signal line R2 can be a low voltage signal, which controls the second reset sub-circuit (seventh transistor T7) 70 to be turned on, and transmits the second initialization signal received by the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the light-emitting device O.

[0285] This is equivalent to resetting the light-emitting device O, which is electrically connected to the pixel driving circuit Q, before the light-emitting stage t5, which helps to improve the stability of the light-emitting device O.

[0286] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low-voltage signal. Based on this, before the light emission stage, the low-voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O from emitting light, thereby reducing the influence of the charge remaining on the anode of the light-emitting device O on the brightness and improving the uniformity of the brightness of the light-emitting device O.

[0287] For example, the low voltage signal can be a signal less than 0V to control the light-emitting device O to not emit light, thereby reducing the effect of the charge remaining on the anode of the light-emitting device O on the brightness of the light emission.

[0288] In some embodiments, please continue to combine Figure 8 and Figure 11 As shown, the third reset signal line R3 is multiplexed as the second reset signal line R2.

[0289] With the above structural configuration, in the first reset phase t11, the second reset sub-circuit 70 and the third reset sub-circuit 80 simultaneously turn on in response to the low voltage signal provided by the third reset signal line R3, transmitting the first reference voltage signal received on the first reference voltage signal line Vref to the second node N2, resetting the second node N2, which can help improve the hysteresis effect of the driving transistor T3. Furthermore, the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, resetting the light-emitting device O, which helps improve the stability of the light-emitting device O.

[0290] In some embodiments, please continue to combine Figure 8 and Figure 11 As shown, the pixel driving circuit Q also includes a first reset sub-circuit 60. The first reset sub-circuit 60 is coupled to the first node N1, the first reset signal line R1, and the first initialization signal line Vinit1.

[0291] The refresh frame also includes a reset phase t1, which may also include a first initialization phase t12.

[0292] In the first initialization phase t12, the first reset signal provided by the first reset signal line R1 is a low voltage signal, which controls the first reset sub-circuit (first transistor T1) 60 to be turned on, and transmits the first initialization signal received by the first initialization signal line Vinit1 to the first node N1 to initialize the first node N1.

[0293] Based on this, it is equivalent to initializing the first node N1 in the pixel driving circuit Q before the compensation stage t2, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0294] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low-voltage signal. Based on this, before the compensation phase, the low-voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0295] For example, a low voltage signal can be a signal lower than the voltage Vdata of the data write signal when the display panel 200 displays any grayscale, in order to eliminate signal residue when displaying the previous frame of the image.

[0296] In some embodiments, please continue to combine Figure 8 and Figure 11 As shown, the reset phase t1 also includes a second initialization phase t13.

[0297] During the second initialization phase t13, the first reset signal provided by the first reset signal line R1 remains at a low voltage, controlling the first reset sub-circuit (first transistor T1) 60 to turn on, transmitting the first initialization signal received by the first initialization signal line Vinit1 to the first node N1. At this time, the voltage of the first node N1 is the first initialization signal. Furthermore, the first scan signal provided by the first scan signal line Gate1 is at a low voltage, controlling the second transistor T2 in the compensation sub-circuit 40 to turn on, transmitting the voltage of the first node N1 to the third node N3.

[0298] In addition, the driving sub-circuit (driving transistor T3) 10 is turned on under the control of the voltage of the first node N1, which can transmit the voltage of the third node N3 to the second node N2.

[0299] Based on this, the first reset signal line R1, the first scan signal line Gate1, and the first initialization signal line Vinit1 can be used to synchronously initialize the first node N1, the second node N2, and the third node N3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0300] In some embodiments, please continue to combine Figure 8 and Figure 11 As shown, the refresh frame also includes a second reset phase t4. The second reset phase t4 occurs after the write phase t3 and before the light emission phase t5.

[0301] In the second reset phase t4, the low voltage signal provided by the second reset signal line R2 is used to control the second reset sub-circuit (seventh transistor T7) 70 to be turned on. The second initialization signal received by the second initialization signal line Vinit2 is transmitted to the light-emitting device O, and the light-emitting device O is reset again, which helps to improve the stability of the light-emitting device O.

[0302] Furthermore, since the three reset signal lines R3 are multiplexed as the second reset signal line R2, during the second reset stage t4, the low voltage signal provided by the third reset signal line R3 can be used to control the third reset sub-circuit (eighth transistor T8) 80 to turn on, transmitting the first reference voltage signal received by the first reference voltage signal line Vref to the second node N2, resetting the second node N2, which helps to improve the stability of the driving transistor T3.

[0303] Furthermore, after the refresh frame is completed within each frame emission period F, a hold frame phase begins. At this time, a low voltage signal can be provided using the third reset signal line R3 to control the conduction of the second reset sub-circuit 70 and the third reset sub-circuit 80. The first reference voltage signal received on the first reference voltage signal line Vref is transmitted to the second node N2, resetting the second node N2, which helps improve the stability of the driving transistor T3. Additionally, the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, resetting the light-emitting device O. This ensures that the anode voltage of each light-emitting device O is consistent at the start of the next frame refresh, improving the uniformity of the brightness of the light-emitting device O.

[0304] In addition, during the holding frame, a low voltage signal can be provided using the first enable signal line EM1 and the second enable signal line EM2 to turn on the light-emitting control sub-circuit 20 and cooperate with the driving sub-circuit 10 to drive the light-emitting device O to emit light.

[0305] Figure 12 This is a timing diagram of a pixel driving circuit according to some other embodiments.

[0306] by Figure 9 The pixel driving circuit Q shown is used as an example for explanation; that is, the explanation is based on the assumption that the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 in the pixel driving circuit Q are all N-type transistors. The following method also applies to pixel driving circuits Q that include N-type dual-gate transistors.

[0307] and Figure 11 The difference between the driving methods shown is: Figure 11 In the corresponding pixel driving circuit Q, the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all P-type transistors.

[0308] and Figure 12 In the corresponding pixel driving circuit Q, the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all N-type transistors.

[0309] Based on this Figure 12 In the pixel driving circuit Q driven by the timing diagram shown, the effective signals of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are high-voltage signals. That is, the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all turned on under high-voltage control. Regarding the driving method and... Figure 11 The driving methods shown are the same, the only difference being the "valid signal" that controls the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 to turn on. For how the pixel driving circuit is driven in other stages, please refer to... Figure 11 The aforementioned driving methods will not be elaborated upon here.

[0310] Figure 13 This is a structural diagram of an array substrate according to some other embodiments. Wherein, Figure 13 To clearly illustrate how to configure all signal lines to respond to the same signal terminal, Figure 13 The diagram only shows the second scan signal line Gate2, which is coupled to the first row pixel driving circuit; the first scan signal line Gate1, which is coupled to the fourth row pixel driving circuit; and the first reset signal line R1, which is coupled to the seventh row pixel driving circuit Q.

[0311] Please see Figure 13 As shown, some embodiments of this disclosure provide an array substrate 100. The array substrate 100 includes a display area AA and a peripheral area SA. The peripheral area SA may be located on at least one side of the display area AA (e.g., one side; or, all around, including the top and bottom sides and the left and right sides).

[0312] The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 located on one side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q, and the plurality of pixel driving circuits Q are arranged in multiple rows and columns.

[0313] For ease of explanation, the above-mentioned multiple pixel driving circuits Q are illustrated in a matrix arrangement as an example.

[0314] At this time, the pixel driving circuits Q arranged in a row along the first direction X are called a row pixel driving circuit Q, and the pixel driving circuits Q arranged in a row along the second direction Y are called a column pixel driving circuit Q.

[0315] The array substrate 100 also includes various types of signal lines to drive the pixel driving circuit Q. Among them, the various types of signal lines include multiple first scan signal lines Gate1, multiple second scan signal lines Gate2, and multiple first reset signal lines R1.

[0316] Multiple first scan signal lines Gate1 are located on one side of the substrate, extending along a first direction X and arranged along a second direction Y, with the second direction Y intersecting the first direction X. One first scan signal line Gate1 is coupled to a row of pixel driving circuits Q.

[0317] Multiple second scan signal lines Gate2 are located on one side of the substrate, and these multiple second scan signal lines Gate2 extend along a first direction X and are arranged along a second direction Y. One second scan signal line Gate2 is coupled to a row pixel driving circuit Q.

[0318] Multiple first reset signal lines R1 are located on one side of the substrate, and the multiple first reset signal lines R1 extend along the first direction X and are arranged along the second direction Y. One first reset signal line R1 is coupled to a row pixel driving circuit Q.

[0319] Multiple first scan signal lines (Gate1), multiple second scan signal lines (Gate2), and multiple first reset signal lines (R1) can be controlled using different signal terminals. However, research has shown that since the signal terminals are located in the peripheral area (SA), controlling these multiple first scan signal lines (Gate1), multiple second scan signal lines (Gate2), and multiple first reset signal lines (R1) using different signal terminals results in an excessive number of signal terminals needing to be placed within the array substrate 100. This leads to the occupation of too much space within the array substrate 100, which in turn increases the area of ​​the peripheral area (SA), thus affecting the achievement of a narrow bezel in the subsequent display panel 200.

[0320] In some examples, the first direction X and the second direction Y can be set approximately perpendicularly, in which case the angle between the first direction X and the second direction Y is approximately 90°. For example, the angle between the first direction X and the second direction Y can be 85°, 90°, or 95°.

[0321] In view of the above problems, the array substrate 100 provided in some embodiments of this disclosure is described in detail below. Figure 13 As shown, a second scan signal line Gate2 coupled to the nth row pixel driving circuit and a first scan signal line Gate1 coupled to the (n+3)th row pixel driving circuit can be set to respond to the control of the same control signal.

[0322] That is, the second scan signal line Gate2, which is coupled to the pixel driving circuit of the nth row, can be coupled to the first scan signal line Gate1, which is coupled to the pixel driving circuit of the (n+3)th row, at the same signal terminal. Here, n is a positive integer.

[0323] Since the first scan signal provided by the first scan signal line Gate1 can be used to control the second transistor T2 in the compensation sub-circuit 40 to turn on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N2 simultaneously; then the second scan signal provided by the second scan signal line Gate2 can be used to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light emission control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0324] Based on this, a second scan signal line Gate2 coupled to the nth row pixel driving circuit can be set, and a first scan signal line Gate1 coupled to the (n+3)th row pixel driving circuit can be coupled to the same signal terminal. That is, when the gate signal is sent to the second scan signal line Gate2 coupled to the nth row pixel driving circuit to control the ninth transistor T9 in the compensation sub-circuit 40 of the nth row pixel driving circuit to turn on, the gate signal can be sent synchronously to the first scan signal line Gate1 coupled to the (n+3)th row pixel driving circuit to control the second transistor T2 in the compensation sub-circuit 40 of the (n+3)th row pixel driving circuit to turn on, so that the (n+3)th row pixel driving circuit can initialize the first node N1, the second node N2, and the third node N2 before performing threshold compensation.

[0325] This configuration ensures the continuity of the sub-circuits in the pixel driving circuit Q that are electrically connected to the first scan signal line Gate1 and the second scan signal line Gate2; it also effectively reduces the number of signal terminals in the array substrate 100, which helps to reduce the area of ​​the peripheral region SA, so as to facilitate the subsequent realization of a narrow bezel in the display panel 200.

[0326] In some embodiments, please refer to Figure 13 As shown, a second scan signal line Gate2 coupled to the nth row pixel driving circuit and a first reset signal line R1 coupled to the (n+6)th row pixel driving circuit can be configured to respond to the control of the same control signal.

[0327] That is, the second scan signal line Gate2, which is coupled to the pixel driving circuit of the nth row, and the first reset signal line R1, which is coupled to the pixel driving circuit of the (n+6)th row, can be coupled to the same signal terminal. Here, n is a positive integer.

[0328] When driving the pixel driving circuit Q, the first reset signal provided by the first reset signal line R1 is used to control the first transistor T1 in the first reset sub-circuit to turn on, and the first node N1 is initialized; then the second scan signal provided by the second scan signal line Gate2 is used to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and in conjunction with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light emission control sub-circuit 20 and the storage sub-circuit 50, threshold compensation is performed.

[0329] Based on this, a second scan signal line Gate2, which is coupled to the nth row pixel driving circuit, and a first reset signal line R1, which is coupled to the (n+6)th row pixel driving circuit, can be set to be coupled to the same signal terminal.

[0330] That is, when the gate signal is sent to the second scan signal line Gate2 coupled to the nth row pixel driving circuit to control the ninth transistor T9 in the compensation sub-circuit 40 of the nth row pixel driving circuit to turn on, the gate signal can be sent synchronously to the first reset signal line R1 coupled to the n+6th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit of the n+6th row pixel driving circuit to turn on, so that the n+6th row image driving circuit can initialize the first node N1 before performing threshold compensation.

[0331] This configuration ensures the continuity of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the second scan signal line Gate2; it also effectively reduces the number of signal terminals in the array substrate 100, which helps to reduce the area of ​​the peripheral region SA, so as to facilitate the subsequent realization of a narrow bezel in the display panel 200.

[0332] In some embodiments, please refer to Figure 13 As shown, a first scan signal line Gate1 coupled to the pixel driving circuit of the nth row and a first reset signal line R1 coupled to the pixel driving circuit of the (n+3)th row can be configured to respond to the control of the same control signal. Here, n is a positive integer. That is, the first scan signal line Gate1 coupled to the pixel driving circuit of the nth row and the first reset signal line R1 coupled to the pixel driving circuit of the (n+3)th row can be configured to be coupled to the same signal terminal.

[0333] When driving the pixel driving circuit Q, the first reset signal provided by the first reset signal line R1 is used to control the first reset sub-circuit to turn on and initialize the first node N1; then the first scan signal provided by the first scan signal line Gate1 is used to control the second transistor T2 in the compensation sub-circuit 40 to turn on, and together with the first reset sub-circuit 60 and the driving sub-circuit 10, the first node N1, the second node N2 and the third node N3 are initialized at the same time.

[0334] Based on this, the first scan signal line Gate1, which is coupled to the pixel driving circuit of the nth row, and the first reset signal line R1, which is coupled to the pixel driving circuit of the (n+3)th row, can be set to be coupled to the same signal terminal.

[0335] That is, when the gate signal is sent to a scan signal line Gate1 coupled to the nth row pixel driving circuit to control the second transistor T2 in the compensation sub-circuit 40 of the nth row pixel driving circuit to turn on, the gate signal can be sent synchronously to the first reset signal line R1 coupled to the n+3rd row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit of the n+3rd row pixel driving circuit to turn on, so that the n+3rd row image driving circuit can initialize the first node N1, the second node N2 and the third node N2 before performing threshold compensation.

[0336] This configuration ensures the continuity of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the first scan signal line Gate1; it also effectively reduces the number of signal terminals in the array substrate 100, which helps to reduce the area of ​​the peripheral region SA, so as to facilitate the subsequent realization of a narrow bezel in the display panel 200.

[0337] In some embodiments, please refer to Figure 13 As shown, a second scan signal line Gate2 coupled to the pixel driving circuit of the nth row, a first scan signal line Gate1 coupled to the pixel driving circuit of the (n+3)th row, and a first reset signal line R1 coupled to the pixel driving circuit of the (n+6)th row can be configured to respond to the control of the same control signal. Here, n is a positive integer.

[0338] When driving the pixel driving circuit Q, the first reset signal provided by the first reset signal line R1 is used to control the first reset sub-circuit to conduct and initialize the first node N1; then the first scan signal provided by the first scan signal line Gate1 is used to control the second transistor T2 in the compensation sub-circuit 40 to turn on, and together with the first reset sub-circuit 60 and the driving sub-circuit 10, the first node N1, the second node N2 and the third node N2 are initialized simultaneously; finally, the second scan signal provided by the second scan signal line Gate2 is used to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and together with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light emission control sub-circuit 20 and the storage sub-circuit 50, threshold compensation is performed.

[0339] Based on this, a second scan signal line Gate2 coupled to the nth row pixel driving circuit, a first scan signal line Gate1 coupled to the (n+3)th row pixel driving circuit, and a first reset signal line R1 coupled to the (n+6)th row pixel driving circuit can be set to respond to the same control signal.

[0340] That is, when the gate signal is sent to the second scan signal line Gate2 coupled to the nth row pixel driving circuit to control the ninth transistor T9 in the compensation sub-circuit 40 of the nth row pixel driving circuit to turn on, the gate signal can be sent to a scan signal line Gate1 coupled to the (n+3)th row pixel driving circuit to control the second transistor T2 in the compensation sub-circuit 40 of the (n+3)th row pixel driving circuit to turn on, so that the (n+3)th row pixel driving circuit can initialize the first node N1 before performing threshold compensation; and the gate signal can be sent synchronously to the first reset signal line R1 coupled to the (n+6)th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit of the (n+6)th row pixel driving circuit to turn on, so that the (n+6)th row pixel driving circuit can initialize each node before performing threshold compensation.

[0341] This configuration ensures the continuity of the sub-circuits in the pixel driving circuit Q that are electrically connected to the first scan signal line Gate1, the second scan signal line Gate2, and the first reset signal line R1; it also effectively reduces the number of signal terminals in the array substrate 100, which helps to reduce the area of ​​the peripheral region SA, so as to facilitate the subsequent realization of a narrow bezel in the display panel 200.

[0342] In some examples, please refer to Figure 13 As shown, the aforementioned driving multiple first scan signal lines Gate1, multiple second scan signal lines Gate2, and multiple first reset signal lines R1 can be coupled to the same signal terminal. This signal terminal can be the gate driver on array (GOA) circuit 101.

[0343] The gate drive circuit 101 is used to provide gate signals to the first scan signal line Gate1, the second scan signal line Gate2, and the first reset signal line R1. The first scan signal line Gate1, the second scan signal line Gate2, and the first reset signal line R1 transmit the gate signal to the corresponding coupled sub-circuit to control the turn-on and turn-off of the transistors included in the sub-circuit.

[0344] In some examples, the gate drive circuit 101 may include multiple cascaded shift register units. One shift register unit may be coupled to a second scan signal line Gate2 coupled to the nth row pixel drive circuit, a first scan signal line Gate1 coupled to the (n+3)th row pixel drive circuit, and a first reset signal line R1 coupled to the (n+6)th row pixel drive circuit, so as to drive the second scan signal line Gate2 coupled to the nth row pixel drive circuit, the first scan signal line Gate1 coupled to the (n+3)th row pixel drive circuit, and the first reset signal line R1 coupled to the (n+6)th row pixel drive circuit using the same shift register unit.

[0345] For example, a shift register 102 may be coupled to a second scan signal line Gate2 coupled to the first row pixel driving circuit, a first scan signal line Gate1 coupled to the fourth row pixel driving circuit, and a first reset signal line R1 coupled to the seventh row pixel driving circuit.

[0346] Based on this, when the first row pixel driving circuit Q receives the second scan signal provided by the second scan signal line Gate2, the fourth row pixel driving circuit Q can simultaneously receive the first scan signal provided by the first scan signal line Gate1, and the seventh row pixel driving circuit Q receives the first reset signal provided by the first reset signal R1.

[0347] This allows the 7th row pixel driving circuit Q and the 4th row pixel driving circuit Q to initialize each node before performing threshold compensation.

[0348] This configuration ensures the continuity of the sub-circuits in the pixel driving circuit Q that are electrically connected to the first scan signal line Gate1, the second scan signal line Gate2, and the first reset signal line R1; it also effectively reduces the number of signal terminals in the array substrate 100, which helps to reduce the area of ​​the peripheral region SA, so as to facilitate the subsequent realization of a narrow bezel in the display panel 200.

[0349] Figure 14 The following is a timing diagram of a pixel driving circuit according to some other embodiments. Figure 15 This is a timing diagram of a pixel driving circuit according to some other embodiments.

[0350] It should be noted that when the second scan signal line Gate2 coupled to the nth row pixel driving circuit, the first scan signal line Gate1 coupled to the (n+3)th row pixel driving circuit, and the first reset signal line R1 coupled to the (n+6)th row pixel driving circuit respond to the same control signal, the timing diagram corresponding to the driving of the corresponding pixel driving circuit, in conjunction with... Figure 14 and Figure 15As shown, the pulse widths of the signals transmitted by the first scan signal line Gate1, the second scan signal line Gate2, and the first reset signal line R1 are equal.

[0351] in, Figure 14 The timing diagram shown is Figure 11 The timing diagrams shown are similar. Figure 15 The timing diagram shown is Figure 12 The timing diagrams shown are similar. That is, Figure 14 The timing diagram shown can be used to drive Figure 8 and Figure 11 The pixel driving circuit shown is Figure 15 Can be used for drivers Figure 9 The pixel driving circuit is shown. For specific driving methods, please refer to the embodiments described above; they will not be repeated here.

[0352] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel driving circuit, characterized in that, The application relates to a display driving circuit. The driving sub-circuit, the light-emitting control sub-circuit, the writing sub-circuit, the compensation sub-circuit and the storage sub-circuit are coupled with the first node, the second node and the third node. The driving sub-circuit is configured to transmit the voltage from the second node to the third node under the control of the voltage of the first node. The light-emitting control sub-circuit comprises a first branch which is coupled with a first power signal line, a first enable signal line and the second node. The first branch is configured to transmit the first power signal received at the first power signal line to the third node in cooperation with the driving sub-circuit under the control of the first enable signal from the first enable signal line in the compensation stage. The compensation sub-circuit is coupled with a first scan signal line, a second scan signal line, the first node, the third node, a fourth node and a second power signal line. The compensation sub-circuit is configured to transmit the voltage of the third node to the first node under the control of the first scan signal received at the first scan signal line and transmit the second power signal received at the second power signal line to the fourth node under the control of the second scan signal received at the second scan signal line in the compensation stage.

2. The pixel driving circuit according to claim 1, characterized in that, The writing sub-circuit is coupled with a third scan signal line, a data writing signal line and the fourth node.

3. The pixel driving circuit of claim 1, wherein, The writing sub-circuit is configured to transmit the data writing signal received at the data writing signal line to the fourth node under the control of the third scan signal received at the third scan signal line in the writing stage. The storage sub-circuit is coupled with the first node and the fourth node. The storage sub-circuit is configured to couple the voltage of the fourth node to the first node in the writing stage.

4. The pixel driving circuit of claim 1, wherein, The driving sub-circuit comprises a driving transistor whose control electrode is coupled with the first node, whose first electrode is coupled with the second node and whose second electrode is coupled with the third node.

5. The pixel driving circuit of claim 1, wherein, The compensation sub-circuit comprises a second transistor and a ninth transistor. The control electrode of the second transistor is coupled with the first scan signal line, the first electrode of the second transistor is coupled with the third node and the second electrode of the second transistor is coupled with the first node. The control electrode of the ninth transistor is coupled with the third scan signal line, the first electrode of the ninth transistor is coupled with the second power signal line and the second electrode of the ninth transistor is coupled with the fourth node. The writing sub-circuit comprises a fourth transistor whose control electrode is coupled with the third scan signal line, whose first electrode is coupled with the data writing signal line and whose second electrode is coupled with the fourth node. The storage sub-circuit comprises a storage capacitor whose first electrode plate is coupled with the fourth node and whose second electrode plate is coupled with the first node.

6. The pixel driving circuit of claim 1, wherein, The light emitting control sub-circuit further comprises a second branch coupled with the third node, a second enable signal line and a light emitting device; in the light emitting stage, the light emitting control sub-circuit is configured to, under the control of a first enable signal from the first enable signal line and a second enable signal from the second enable signal line, cooperate with the driving sub-circuit to transmit the first power signal received at the first power signal line to the light emitting device.

7. The pixel driving circuit of claim 6, wherein, the first branch comprises a fifth transistor, a control electrode of the fifth transistor is coupled with the first enable signal line, a first electrode of the fifth transistor is coupled with the first power signal line, and a second electrode of the fifth transistor is coupled with the second node; the second branch comprises a sixth transistor, a control electrode of the sixth transistor is coupled with the second enable signal line, a first electrode of the sixth transistor is coupled with the third node, and a second electrode of the sixth transistor is coupled with the light emitting device. 8.The pixel driving circuit of claim 1, wherein, further comprising a first reset sub-circuit; the first reset sub-circuit is coupled with the first node, a first reset signal line and a first initialization signal line; the first reset sub-circuit is configured to, under the control of a first reset signal received at the first reset signal line, transmit a first initialization signal received at the first initialization signal line to the first node to reset the first node.

9. The pixel driving circuit of claim 8, wherein, the first reset sub-circuit comprises a first transistor, a control electrode of the first transistor is coupled with the first reset signal line, a first electrode of the first transistor is coupled with the first initialization signal line, and a second electrode of the first transistor is coupled with the first node.

10. The pixel driving circuit of claim 1, wherein, further comprising a second reset sub-circuit; the second reset sub-circuit is coupled with the light emitting device, a second reset signal line and a second initialization signal line; the second reset sub-circuit is configured to, under the control of a second reset signal received at the second reset signal line, transmit a second initialization signal received at the second initialization signal line to the light emitting device to reset the light emitting device.

11. The pixel driving circuit of claim 10, wherein, the second reset sub-circuit comprises a seventh transistor, a control electrode of the seventh transistor is coupled with the second reset signal line, a first electrode of the seventh transistor is coupled with the second initialization signal line, and a second electrode of the seventh transistor is coupled with the light emitting device.

12. The pixel driving circuit of claim 1, wherein, further comprising a third reset sub-circuit; the third reset sub-circuit is coupled with the second node, a third reset signal line and a first reference voltage signal line; the third reset sub-circuit is configured to, under the control of a third reset signal received at the third reset signal line, transmit a first reference voltage signal received at the first reference voltage signal line to the second node to reset the second node.

13. The pixel driving circuit of claim 12, wherein, the third reset sub-circuit comprises an eighth transistor, a control electrode of the eighth transistor is coupled with the third reset signal line, a first electrode of the eighth transistor is coupled with the first reference voltage signal line, and a second electrode of the eighth transistor is coupled with the second node.

14. The pixel driving circuit of claim 1, wherein, A voltage value of the first power signal is equal to a voltage value of the second power signal.

15. The pixel driving circuit of claim 1, wherein, The first power signal line is multiplexed as the second power signal line.

16. The pixel driving circuit of claim 1, wherein, In a case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor, and a ninth transistor: At least one of the first transistor, the second transistor, the fourth transistor, and the ninth transistor is a double-gate transistor.

17. The pixel driving circuit of claim 1, wherein, In a case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor, and a ninth transistor: At least one of the first transistor, the second transistor, the fourth transistor, and the ninth transistor is an N-type transistor.

18. A driving method of a pixel driving circuit, characterized by, The pixel driving circuit includes a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit; The driving sub-circuit is coupled with a first node, a second node, and a third node; The light-emitting control sub-circuit includes a first branch, and the first branch is coupled with a first power signal line, a first enable signal line, and the second node; The compensation sub-circuit is coupled with a first scan signal line, a second scan signal line, the first node, the third node, a fourth node, the first power signal line, and a second power signal line; The writing sub-circuit is coupled with a third scan signal line, a data writing signal line, and the fourth node; The storage sub-circuit is coupled with the first node and the fourth node; The driving method includes a compensation phase and a writing phase; In the compensation phase, the first branch, under the control of a first enable signal from the first enable signal line, cooperates with the driving sub-circuit to transmit a first power signal received at the first power signal line to the third node; the compensation sub-circuit, under the control of a first scan signal received at the first scan signal line, transmits a voltage of the third node to the first node; under the control of a second scan signal received at the second scan signal line, transmits a second power signal received at the second power signal line to the fourth node; and the storage sub-circuit receives a voltage of the first node and a voltage of the fourth node; In the writing phase, the writing sub-circuit, under the control of a third scan signal received at the third scan signal line, transmits a data writing signal received at the data writing signal line to the fourth node; and the storage sub-circuit couples the voltage of the fourth node to the first node.

19. The driving method according to claim 18, wherein The pixel driving circuit further includes a third reset sub-circuit, and the third reset sub-circuit is coupled with the second node, a third reset signal line, and a first reference voltage signal line; The driving method further includes a first reset phase, and in the first reset phase, the third reset sub-circuit, under the control of a third reset signal received at the third reset signal line, transmits a first reference voltage signal received at the first reference voltage signal line to the second node to reset the second node.

20. The driving method according to claim 19, wherein The pixel driving circuit further comprises a first reset sub-circuit coupled with the first node, a first reset signal line and a first initialization signal line; The driving method further comprises a first initialization stage, in which the first reset sub-circuit, under the control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node to initialize the first node.

21. The driving method according to claim 20, wherein The driving method further comprises a second initialization stage; In the second initialization stage, the first reset sub-circuit, under the control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node; The compensation sub-circuit, under the control of a first scan signal received from the first scan signal line, transmits the voltage of the first node to the third node; And the driving sub-circuit, under the control of the voltage of the first node, transmits the voltage from the second node to the third node to initialize the first node, the second node and the third node.

22. An array substrate, characterized in that, Comprise: a substrate, and a plurality of pixel driving circuits as claimed in any one of claims 1-17 above on the substrate.

23. The array substrate of claim 22, wherein, The plurality of pixel driving circuits are arranged in multiple rows and multiple columns; the array substrate further comprises: a plurality of first scan signal lines located on one side of the substrate and extending along a first direction and arranged along a second direction intersecting the first direction; a plurality of second scan signal lines located on one side of the substrate and extending along the first direction and arranged along the second direction; a plurality of first reset signal lines located on one side of the substrate and extending along the first direction and arranged along the second direction; wherein the second scan signal line coupled with the nth row of pixel driving circuits, the first scan signal line coupled with the n+3th row of pixel driving circuits, and the first reset signal line coupled with the n+6th row of pixel driving circuits are controlled in response to the same control signal, n being a positive integer.

24. A display panel comprising: Comprise: a light emitting device layer comprising a plurality of light emitting devices; and the array substrate as claimed in claim 22 or 23; wherein the pixel driving circuit is coupled with the light emitting device.

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