Field sequential display pixel circuit

Abstract

The invention discloses a field sequential display pixel circuit. The field sequential display pixel circuit comprises a plurality of pixel units which are distributed in multiple rows and multiple columns; a plurality of scanning signal lines extending along the horizontal direction and a plurality of data signal lines extending along the vertical direction; and the plurality of cascaded GOA units are arranged in the peripheral circuit, and each stage of GOA unit is connected with the plurality of scanning signal lines so as to input scanning signals to each scanning line. The beneficial effects of the invention are that the control switch and the multi-channel data line are turned on through the multi-stage scanning line signal for writing, and the refresh rate is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a field sequential display pixel circuit. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] In order to achieve a high refresh rate, the present invention proposes a field sequential display pixel circuit. Summary of the invention

[0004] The purpose of the present invention is to provide a field sequential display pixel circuit to achieve a high refresh rate.

[0005] The object of the present invention is to realize a field sequential display pixel circuit through the following technical scheme, comprising a plurality of pixel units distributed in multiple rows and columns, two adjacent pixel units in the same column have opposite polarities, and two adjacent pixel units in the same row have opposite polarities; A plurality of scanning signal lines extending in a horizontal direction, the plurality of scanning signal lines being used to connect with the pixel units to transmit driving signals to the pixel units; and a plurality of data signal lines extending in a vertical direction, being used to connect with the pixel units to input data signals to the pixel units; the data signal lines also input reset signals to the pixel units; And multiple cascaded GOA units are arranged in the peripheral circuit, the GOA unit is an array substrate integrated gate drive unit, the nth level GOA unit is used to output the nth level scanning signal, and each level of GOA unit is respectively connected to multiple scanning signal lines to input scanning signals to each row of pixel units.

[0006] Further, when the nth-stage GOA unit is connected to m scanning signal lines, the pixel circuit is provided with m data signal lines; The xth data signal line is used to input data signals to the mn-(mx)th row of pixel units of the nth level GOA unit, where x=1, 2, ..., m; m and n are both constants.

[0007] Further, the pixel unit includes a first transistor, a second transistor, a third transistor, a pre-storage capacitor, a holding capacitor and a pixel electrode; The gate of the first transistor is coupled to the scan signal line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor and the first source and drain of the second transistor; the other end of the pre-storage capacitor is coupled to the common signal line; the gate of the second transistor is coupled to the transfer signal line, the second source and drain of the second transistor are coupled to one end of the pixel electrode and one end of the holding capacitor; the other end of the pixel electrode and the other end of the holding capacitor are coupled to the common signal line; the first source and drain of the third transistor are coupled to the second source and drain of the second transistor, and the gate of the third transistor is coupled to the reset signal line.

[0008] Further, when the n-th level GOA unit controls any two rows of pixel units, the m data signal lines include a first data signal line and a second data signal line; The first transistor of the pixel unit in the 2n-1th row controlled by the GOA unit of the nth stage receives the data signal of the first data signal line, and the second source and drain of the third transistor of the pixel unit in the 2n-1th row is coupled to the second data signal line; The first source and drain of the first transistor of the pixel unit in the 2nth row controlled by the GOA unit of the nth level are coupled to the second data signal line, and the second source and drain of the third transistor of the pixel unit in the 2nth row are coupled to the first data signal line; the second data signal line inputs a reset signal to the pixel units in the 2n-1th row and the pixel units in the 2nth row.

[0009] Further, when the n-th level GOA unit controls any three rows of pixel units, the plurality of data signal lines include a first data signal line, a second data signal line and a third data signal line; The first transistor of the pixel unit in the 3n-2th row controlled by the GOA unit of the nth stage receives the data signal of the first data signal line, and the second source and drain of the third transistor of the pixel unit in the 3n-2th row is coupled to the third data signal line; The first source and drain of the first transistor of the pixel unit in the 3n-1th row controlled by the nth-stage GOA unit are coupled to the second data signal line, and the second source and drain of the third transistor of the pixel unit in the 3n-1th row are coupled to the first data signal line.

[0010] The first transistor of the pixel unit in the 3nth row controlled by the GOA unit of the nth level is coupled to the third data signal line, the second source and drain of the third transistor of the pixel unit in the 3nth row is coupled to the third data signal line, and the third data signal inputs a reset signal to the pixel units in the 3n-2th row, the 3n-1th row and the 3nth row.

[0011] Further, the third data signal line may be replaced by a reset signal line and a transfer signal line, and the third data signal line may be replaced by a reset signal line or a transfer signal line.

[0012] Furthermore, the nth row of pixel units and the n+1th row of pixel units are arranged in mirror symmetry, and the nth row of pixel units and the n+1th row of pixel units are coupled to the same scanning signal line, the same transfer signal line and the same reset signal line.

[0013] Advantages of the present invention: The present invention is provided with a multi-level GOA unit and a plurality of data signal lines. The GOA unit can simultaneously input scanning signals to a plurality of scanning signal lines to drive a plurality of pixel units, and simultaneously control the on and off of a plurality of first transistors through the scanning signal lines; and cooperate with a plurality of data signal lines to realize that a plurality of data signal lines simultaneously transmit data signals to a plurality of pixel units to realize the display of a plurality of pixel units; The multiple data signal lines of the present invention can be multiplexed as reset signal lines or transfer signal lines or reset signal lines, and the data signal lines have a multiplexing function, thereby saving the number of signal lines and improving the aperture ratio of the display pixel circuit; The present invention also arranges the nth row of pixel units and the n+1th row of pixel units in mirror symmetry, and couples the nth row of pixel units and the n+1th row of pixel units to the same scanning signal line, the same transfer signal line and the same reset signal line, thereby saving the number of multiple signal lines and improving the aperture ratio of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A circuit diagram of Embodiment 1 of the present invention; Figure 2 Another circuit diagram of the first embodiment of the present invention; Figure 3 is a timing diagram of the first embodiment of the present invention; Figure 4 is a circuit diagram of Embodiment 2 of the present invention; Figure 5 This is a circuit diagram of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0016] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0018] The present invention provides a field sequential display pixel circuit, comprising a plurality of pixel units distributed in a plurality of rows and columns, wherein two adjacent pixel units in the same column have the same polarity, and two adjacent pixel units in the same row have opposite polarities; A plurality of scanning signal lines Scan extending in a horizontal direction, the plurality of scanning signal lines are used to connect with the pixel units to transmit driving signals to the pixel units; and a plurality of data signal lines Data extending in a vertical direction, are used to connect with the pixel units to input data signals to the pixel units, and the data signal lines Data also input reset signals to the pixel units; And multiple cascaded GOA units are arranged in the peripheral circuit (non-display area), "GOA" in the GOA unit is the abbreviation of Gate On Array, and the GOA unit refers to the gate drive unit integrated with the array substrate, each level of GOA unit is respectively connected to multiple scan signal lines Scan to input scan signals to each scan signal line Scan; when the n-th level GOA unit is connected to m scan signal lines Scan, the pixel circuit sets m data signal lines Data; the x-th data signal line is used to input data signals to the mn-(mx)-th row of pixel units driven by the n-th level GOA unit, x=1, 2, ..., m; wherein m and n are both constants. In some specific embodiments, refer to Figure 1 , when the n-th level GOA unit controls any two rows of pixel units, the m data signal lines include a first data signal line Data1 and a second data signal line Data2; The first transistor T1 of the pixel unit in the 2n-1th row controlled by the nth-stage GOA unit receives the data signal of the first data signal line Data1, and the second source and drain of the third transistor T3 of the pixel unit in the 2n-1th row is coupled to the second data signal line Data2; The first source and drain of the first transistor T1 of the 2nth pixel unit controlled by the nth-stage GOA unit are coupled to the second data signal line Data2 , and the second source and drain of the third transistor T3 of the 2nth pixel unit are coupled to the first data signal line Data1 .

[0019] In some other specific embodiments, when the n-th level GOA unit is connected to m scanning signal lines Scan, the n-th level GOA unit controls any m rows through the m scanning signal lines Scan; see Figure 2 , when m=2, the nth level GOA unit controls the pixel units of the first row and the pixel units of the third row, and the n+1th level GOA unit controls the pixel units of the second row and the pixel units of the fourth row. When this embodiment is adopted, the control rows selected by each level of GOA unit can be allocated as needed.

[0020] In some specific embodiments, the pixel unit includes a first transistor T1, a second transistor T2, a third transistor T3, a pre-storage capacitor Cs1, a holding capacitor Cs2 and a pixel electrode Clc; The gate of the first transistor T1 is coupled to the scan signal line Scan, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1 and the first source and drain of the second transistor T2; the other end of the pre-storage capacitor Cs1 is coupled to the common signal line Com; the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source and drain of the second transistor T2 are coupled to one end of the pixel electrode Clc and one end of the holding capacitor Cs2; the other end of the pixel electrode Clc and the other end of the holding capacitor Cs2 are coupled to the common signal line Com; the first source and drain of the third transistor T3 are coupled to the second source and drain of the second transistor T2, and the gate of the third transistor T3 is coupled to the reset signal line Reset.

[0021] While working, refer to Figure 3 , in the positive polarity frame, the nth level GOA circuit outputs a driving signal, and the scanning signal lines Scan of the pixel units in the 2n-1th row and the 2nth row receive the driving signal, so that the first transistor T1 of each pixel unit is turned on; at this time, the first data signal line Data1 and the second data signal line Data2 input data signals to the pixel units in the 2n-1th row and the 2nth row, respectively; In the reset phase, the level of the reset signal line Reset jumps to a high level, and the third transistor T3 is turned on. At this time, the second data signal line Data2 inputs the reset signal Vcom+Vop_max, so that the holding capacitor Cs2 and the pixel electrode Clc of the pixel unit in the 2n-1th row and the pixel unit in the 2nth row are reset; therefore, the second data signal line Data2 is multiplexed as a signal line with a reset function, completing the reset of the pixel electrode Clc; After the reset is completed, the level of the transfer signal line Tran jumps to a low level, the second transistors T2 of the pixel units in the 2n-1th row and the 2nth row are turned on, and their respective pre-storage capacitors Cs1 transfer the data signal to the holding capacitor Cs2 and the pixel electrode Clc, so that the pixel electrode point reaches the preset potential.

[0022] In the negative polarity frame, the first data signal line Data1 and the second data signal line Data2 are written with the data signal of the negative polarity frame. In the reset stage, the second data signal line Data2 is input with the second reset signal Vcom-Vop_max. The rest of the process is the same as that in the positive polarity frame.

[0023] The present invention realizes opening and closing of multiple rows of pixel units by setting a multi-level GOA unit; and at the same time, multiple data signal lines are set to simultaneously write data signals to multiple rows of turned-on pixel units, thereby improving the refresh rate; at the same time, the data signal line Data in the present invention can also be used as a signal line for resetting the pixel electrode Clc to output a reset signal in the reset stage, so that the holding capacitor Cs2 and the pixel electrode Clc are reset, thereby saving the number of signal lines, thereby improving the aperture ratio of the display area. Example

[0024] See also Figure 4 In some specific embodiments, when the n-th level GOA unit controls any three rows of pixel units, the plurality of data signal lines include a first data signal line Data1, a second data signal line Data2, and a third data signal line Data3; The first transistor T1 of the pixel unit in the 3n-2th row controlled by the GOA unit of the nth stage receives the data signal of the first data signal line Data1, and the second source and drain of the third transistor T3 of the pixel unit in the 3n-2th row is coupled to the third data signal line Data3; The first source and drain of the first transistor T1 of the pixel unit in the 3n-1th row controlled by the GOA unit of the nth stage are coupled to the second data signal line Data2, and the second source and drain of the third transistor T3 of the pixel unit in the 3n-1th row are coupled to the first data signal line Data1; The first transistor T1 of the pixel unit in the 3nth row controlled by the nth-stage GOA unit is coupled to the third data signal line Data3 , and the second source and drain of the third transistor T3 of the pixel unit in the 3nth row is coupled to the third data signal line Data3 .

[0025] When working, in the positive polarity frame, the nth level GOA circuit outputs a driving signal, and the scanning signal lines Scan of the pixel units in the 3n-2th row, the pixel units in the 3n-1th row, and the pixel units in the 3nth row receive the driving signal, so that the first transistor T1 of each pixel unit is turned on; at this time, the first data signal line Data1, the second data signal line Data2, and the third data signal line Data3 input data signals to the pixel units in the 3n-2th row, the pixel units in the 3n-1th row, and the pixel units in the 3nth row, respectively; During the reset phase, the level of the reset signal line Reset jumps to a high level, and the third transistors T3 of the three rows of pixel units are turned on. At this time, the third data signal line Data3 inputs the reset signal Vcom+Vop_max, so that the holding capacitors Cs2 and the pixel electrodes Clc of the pixel units in the 3n-2th row, the 3n-1th row, and the 3nth row are reset; therefore, the third data signal line Data3 completes the reset of the pixel electrode Clc; After the reset is completed, the level of the transfer signal line Tran jumps to a low level, and the second transistors T2 of the pixel units in the 3n-2th row, the 3n-1th row and the 3nth row are respectively turned on, and their respective pre-storage capacitors Cs1 transfer the data signal to the holding capacitor Cs2 and the pixel electrode Clc, so that the pixel electrode point reaches the preset potential.

[0026] In the negative polarity frame, the first data signal line Data1, the second data signal line Data2 and the third data signal line Data3 are written with the data signal of the negative polarity frame. At this time, in the reset stage, the third data signal line Data3 inputs the second reset signal Vcom-Vop_max; the rest of the process is the same as that in the positive polarity frame. In this embodiment, the third data signal line Data3 also outputs a reset signal, and the number of data signal lines Data is increased to improve the refresh rate of the circuit. Example

[0027] like Figure 5 As shown, in some specific embodiments, the nth row of pixel units and the n+1th row of pixel units are arranged in mirror symmetry, and the nth row of pixel units and the n+1th row of pixel units are coupled to the same scan signal line Scan, the same transfer signal line Tran and the same reset signal line Reset.

[0028] The upper and lower mirrored pixel units enable multiple pixel units to share multiple control signal lines, thereby saving multiple signal lines and improving the aperture ratio of the circuit.

[0029] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A field sequential display pixel circuit, characterized in that: It includes a plurality of pixel units distributed in a plurality of rows and columns, wherein two adjacent pixel units in the same column have the same polarity, and two adjacent pixel units in the same row have opposite polarities; A plurality of scanning signal lines (Scan) extending in a horizontal direction, used to connect with the pixel units to transmit driving signals to the pixel units; A plurality of data signal lines (Data) extending in a vertical direction, used to be connected to the pixel units to input data signals to the pixel units, and the data signal lines (Data) also input reset signals to the pixel units; And a plurality of cascaded GOA units are arranged in the peripheral circuit, wherein the GOA unit is an array substrate integrated gate drive unit, and each level of GOA unit is respectively connected to a plurality of scan signal lines (Scan) to input scan signals to each row of pixel units.

2. A field sequential display pixel circuit according to claim 1, characterized in that: When the n-th level GOA unit is connected to m scan signal lines (Scan), the pixel circuit is provided with m data signal lines (Data); The xth data signal line is used to input data signals to the mn-(mx)th row of pixel units driven by the nth level GOA unit through the scan signal line (Scan), where x=1, 2, ..., m; wherein m and n are both constants.

3. The field sequential display pixel circuit according to claim 2, characterized in that: The pixel unit comprises a first transistor (T1), a second transistor (T2), a third transistor (T3), a pre-storage capacitor (Cs1), a holding capacitor (Cs2) and a pixel electrode (Clc); The gate of the first transistor (T1) is coupled to a scan signal line (Scan), the second source and drain of the first transistor (T1) are coupled to one end of a pre-storage capacitor (Cs1) and the first source and drain of a second transistor (T2); the other end of the pre-storage capacitor (Cs1) is coupled to a common signal line (Com); the gate of the second transistor (T2) is coupled to a transfer signal line (Tran), the second source and drain of the second transistor (T2) are coupled to one end of a pixel electrode (Clc) and one end of a holding capacitor (Cs2); the other end of the pixel electrode (Clc) and the other end of the holding capacitor (Cs2) are coupled to the common signal line (Com); the first source and drain of the third transistor (T3) are coupled to the second source and drain of the second transistor (T2), and the gate of the third transistor (T3) is coupled to a reset signal line (Reset).

4. The field sequential display pixel circuit according to claim 3, characterized in that: When the n-th level GOA unit controls any two rows of pixel units, the m data signal lines include a first data signal line (Data1) and a second data signal line (Data2); The first source and drain of the first transistor (T1) of the pixel unit in the 2n-1th row controlled by the GOA unit of the nth stage are coupled to the first data signal line (Data1), and the second source and drain of the third transistor (T3) of the pixel unit in the 2n-1th row are coupled to the second data signal line (Data2); The first source and drain of the first transistor (T1) of the pixel unit in the 2nth row controlled by the GOA unit of the nth level are coupled to the second data signal line (Data2), and the second source and drain of the third transistor (T3) of the pixel unit in the 2nth row are coupled to the first data signal line (Data1); the second data signal line (Data2) inputs a reset signal to the pixel unit in the 2n-1th row and the pixel unit in the 2nth row.

5. The field sequential display pixel circuit according to claim 3, characterized in that: When the n-th level GOA unit controls any three rows of pixel units, the plurality of data signal lines include a first data signal line (Data1), a second data signal line (Data2) and a third data signal line (Data3); The first transistor (T1) of the pixel unit in the 3n-2th row controlled by the GOA unit of the nth stage receives the data signal of the first data signal line (Data1), and the second source and drain of the third transistor (T3) of the pixel unit in the 3n-2th row is coupled to the third data signal line (Data3); The first source and drain of the first transistor (T1) of the pixel unit in the 3n-1th row controlled by the GOA unit of the nth stage are coupled to the second data signal line (Data2), and the second source and drain of the third transistor (T3) of the pixel unit in the 3n-1th row are coupled to the first data signal line (Data1); The first transistor (T1) of the pixel unit in the 3nth row controlled by the GOA unit of the nth stage is coupled to the third data signal line (Data3), and the second source and drain of the third transistor (T3) of the pixel unit in the 3nth row is coupled to the third data signal line (Data3); The third data signal (Data3) inputs a reset signal to the pixel units in the 3n-2th row, the 3n-1th row, and the 3nth row.

6. The field sequential display pixel circuit according to claim 5, characterized in that: The third data signal line (Data3) may be replaced by a reset signal line (Reset) and a transfer signal line (Tran), and the third data signal line may also be replaced by a reset signal line (Reset) or a transfer signal line (Tran).

7. A field sequential display pixel circuit according to any one of claims 4 or 5, characterized in that: The nth row of pixel units and the n+1th row of pixel units are arranged in mirror symmetry, and the nth row of pixel units and the n+1th row of pixel units are coupled to the same scan signal line (Scan), the same transfer signal line (Tran) and the same reset signal line (Reset).

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