Process for co-integration of two phase change memory (PCM) arrays with different phase change materials and in-memory computing system utilizing same

Abstract

The present disclosure relates to a process for co-integration of two phase change memory (PCM) arrays having different phase change materials and in-memory computing systems utilizing the two PCM arrays. An in-memory computation (IMC) system includes in-memory computation circuitry formed from a first array of phase change memories (PCMs) configured to store computation weights for in-memory computation operations. The data storage circuitry is formed by a second PCM array configured to store backup data for computing weights for in-memory computing operations. The first PCM array includes PCM cells made of a phase change material provided by a first GST alloy, and the second PCM array includes PCM cells made of a phase change material provided by a second GST alloy different from the first GST alloy. The control circuit operates to read backup data from the second PCM array and write the first PCM array in accordance with the backup data to refresh computational weights for in-memory computational operations.

Description

Technical Field

[0001] The present disclosure generally relates to an in-memory computing (IMC) system utilizing first and second phase change memory (PCM) arrays, wherein the first PCM array performs in-memory computations using stored computation weight data and the second PCM array stores backup data for refreshing the computation weight data in the first PCM array. In addition, the present disclosure relates to a method for co-integrating the first and second PCM arrays having different phase change materials on a common integrated circuit substrate. Background Art

[0002] In-memory computing (IMC) systems store information in bit cells of a memory array and perform computations at the bit cell level. An example of a computation performed by an IMC system is a multiply and accumulate (MAC) operation, where an input array of numbers (X values, also called feature or coefficient data) is multiplied by an array of computation weights (g values) stored in memory, and the products are then added together to produce an output array of numbers (Y values, also called decision data).

[0003]

[0004] By performing these calculations at the bit cell level in memory, the IMC system does not need to move data back and forth between the memory device and the computing device. Therefore, the limitations associated with the data transfer bandwidth between devices are eliminated, and the calculations can be performed with lower power consumption.

[0005] As known in the art, the memory array of the IMC system is implemented using a phase change memory (PCM) cell. The PCM cell is configured to store weight data using a phase change material that can stably transform between an amorphous phase and a crystalline phase according to the heat transferred thereto. The amorphous phase and the crystalline phase exhibit two or more different resistances, in other words, two or more different transconductances, which are used to distinguish two (for binary data) or more (for m-ary data, m is an integer greater than or equal to three) different logical states that can be programmed into the memory cell. The amorphous phase exhibits a relatively high resistance (i.e., a lower transconductance), so the current flowing through the memory cell programmed in this state when selected is relatively small. In contrast, the crystalline phase exhibits a relatively low resistance, so the current flowing through the memory cell programmed in this state is relatively large.

[0006] Phase change materials used in PCM cells typically utilize germanium (Ge) and chemical elements from Group VI of the periodic table, such as tellurium (Te), selenium (Se), and / or antimony (Sb), which are referred to in the art as chalcogenides or chalcogenide materials. For example, a phase change material may include Ge x Sb yTe z Alloy (referred to in the art as GST alloy).

[0007] Memories utilizing phase change memory elements formed from certain widely used GST alloys are known to suffer from some reliability issues. In particular, there is evidence that certain stoichiometric GST alloys, such as GST 225 alloy (Ge2Sb2Te5) and GST447 alloy (Ge4Sb4Te7), exhibit phase retention (used to identify one or more logic states for stored data) issues at high temperatures. As a result, there may be a loss of logic states for the stored data. In order to compensate for this loss, it is necessary to refresh the data stored in the memory array. Summary of the invention

[0008] In an embodiment, a method for co-integrated manufacturing of a first phase change memory (PCM) cell and a second PCM cell on a common semiconductor substrate having a first region and a second region includes: forming a heating element in an insulating region over both the first region of the common semiconductor substrate and the second region of the common semiconductor substrate; depositing a layer of a first phase change material over the heating elements for both the first region and the second region; masking over the layer of the first phase change material at the second region and removing the layer of the first phase change material at the first region; depositing a layer of a second phase change material different from the first phase change material over the heating element for the first region and over the layer of the first phase change material at the second region; and masking over the layer of the second phase change material at the first region and removing the layer of the second phase change material at the second region.

[0009] In an embodiment, a method for co-integrated fabrication of a first phase change memory (PCM) cell and a second PCM cell on a common semiconductor substrate having a first region and a second region includes: depositing a layer of a first phase change material over a first insulating heating element associated with the first region; depositing a layer of a second phase change material different from the first phase change material over a second insulating heating element associated with the second region; photolithographically patterning the layer of the first phase change material to define a first memory region for the first PCM cell; and photolithographically patterning the layer of the second phase change material to define a second memory region for the second PCM cell.

[0010] In an embodiment, an in-memory computing (IMC) system includes: an in-memory computing circuit, including a first phase change memory (PCM) array configured to store computational weights for in-memory computing operations; wherein the first PCM array includes PCM cells made of a phase change material, the phase change material including a first GST alloy; a data storage circuit, including a second PCM array configured to store backup data of computational weights for in-memory computing operations; wherein the second PCM array includes PCM cells made of a phase change material, the phase change material including a second GST alloy different from the first GST alloy; and a control circuit configured to read the backup data from the second PCM array and write it to the first PCM array to refresh the computational weights for in-memory computing operations based on the backup data.

[0011] An in-memory computing (IMC) system comprises: an in-memory computing circuit, comprising a first phase change memory (PCM) array configured to store computational weights for in-memory computing operations; wherein the first PCM array comprises PCM cells made of a phase change material, the phase change material comprising a first GST alloy; a data storage circuit, comprising a second PCM array configured to store backup data of computational weights for in-memory computing operations; and wherein the second PCM array comprises PCM cells made of a phase change material, the phase change material comprising a second GST alloy different from the first GST alloy. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of an in-memory computing (IMC) system;

[0014] Figure 2 is used for Figure 1 A schematic diagram of an embodiment of an in-memory computing circuit of an IMC system;

[0015] Figure 3 is used for Figure 1 A schematic diagram of an embodiment of a backup data storage circuit of an IMC system;

[0016] Figure 4 shows a cross section of a phase change memory (PCM) cell;

[0017] Figure 5A-1 to Figure 5N-1 and Figure 5A-2 to Figure 5N-2 shows process steps for co-integrated fabrication of two PCM arrays having memory cells using two different phase change materials; and

[0018] Fig. 6A and Figure 6BShown by Figure 5A-1 to Figure 5N-1 and Figure 5A-2 to Figure 5N-2 A perspective view of the process of forming a PCM unit. DETAILED DESCRIPTION

[0019] Similar features in the various figures are designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be arranged in the same structure, dimensions, and material properties.

[0020] Unless otherwise indicated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0021] In the following description, when reference is made to terms such as “front”, “back”, “top”, “bottom”, “left”, “right” etc. that define absolute positions, or terms such as “up”, “down”, “upper”, “lower” etc. that define relative positions, or terms such as “horizontal”, “vertical” etc. that define directions, unless otherwise specified, the orientation of the drawing is referred to.

[0022] Reference now Figure 1 , Figure 1 1 shows a block diagram of an in-memory computing (IMC) system 100. The system 100 includes an in-memory computing circuit 10, which includes a computer configured to store computing weights (g mn The in-memory computation circuit 10 receives an input array of numbers called feature (or coefficient) data X, which are compared with the stored computation weight data g. mn The array of is subjected to matrix-vector multiplication (MVM) to produce an output array of numbers called decision data Y.

[0023] The PCM cells within the PCM1 array 12 utilize a first GST alloy for the phase change material. This first GST alloy is selected because it is suitable for supporting the implementation of a resistive memory cell. In view of this, this means that the PCM cells within the PCM1 array 12 are capable of storing m-ary (where m is an integer greater than or equal to three) logic states. In other words, the amorphous phase and the crystalline phase of the phase change material of each PCM cell in the PCM1 array 12 can be programmed to exhibit three or more different resistances and corresponding three or more different transconductances. The problem with using the first GST alloy for the phase change material to implement PCM cells within the PCM1 array 12 is that such phase change materials exhibit data retention issues at high temperatures. Exposure to high temperatures may result in the loss of logic states associated with one or more different resistances associated with the stored m-ary logic state.

[0024] In a preferred embodiment, the first GST alloy is a stoichiometric GST alloy, such as GST 225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7). In this context, a person skilled in the art will understand "stoichiometric GST alloy" as being stable in both the crystalline phase and the amorphous phase (i.e., the composition in both phases is the same). This is in contrast to non-stoichiometric GST alloys such as Ge-rich alloys, which cannot maintain the same chemical composition in both the crystalline phase and the amorphous phase. Compared to the stoichiometric composition, the excess Ge that can be incorporated into the amorphous phase must be expelled to allow the formation of a lattice. Therefore, during the phase transition, the material tends to separate into pure Ge and stoichiometric GST.

[0025] The system 100 also includes a data storage circuit 50, which includes a memory configured to store the computation weights (g mn A second phase change memory (PCM) array (PCM2) 52 for backing up the weight data).

[0026] The PCM cells within the PCM2 array 52 utilize a second GST alloy for the phase change material that is different from the first GST alloy. This second GST alloy is selected because it is suitable for providing phase retention stability over a wide temperature range (ie, it is thermally stable).

[0027] In a preferred embodiment, the second GST alloy is a germanium-rich GST alloy. In this context, a Ge-rich GST alloy is an alloy in which germanium is the dominant component in the average composition for the alloy. In other words, the stoichiometric percentage of germanium in the Ge-rich GST alloy is greater than 50%. An advantage of the Ge-rich GST alloy is the increase in crystallization temperature, thereby improving the ability to maintain the stored logic state (phase retention) without degrading cycling performance. Examples of Ge-rich GST alloys suitable for use as phase change materials for PCM cells within the PCM2 array 52 include: GST 712 alloy (Ge7Sb1Te2) and GST 523 alloy (Ge5Sb2Te3). Alternatively, a Ge-rich GST alloy including nitrogen, such as Ge may be used. x Sb y Te z N j , wherein the stoichiometric percentage of germanium is greater than or equal to 50%, for example 70% or approximately 70%, and the stoichiometric percentage of nitrogen is in the range of 5-25% (more preferably between 8-21%, still more preferably between 11-18%, even more preferably between 13-15%).

[0028] The system 100 further includes a control circuit 102 that operates to read the calculated weights (g mn The first GST alloy is used to store the weight data of the PCM1 array 12 in the memory computing circuit 10, and then writes the data to the PCM1 array 12 in the memory computing circuit 10 (see the refresh arrow). The effect of this read-write operation is to refresh the computing weights used for the memory computing operation, thereby eliminating the problem of data retention of the PCM cells in the PCM1 array 12 using the first GST alloy for phase change material.

[0029] In a preferred embodiment, by using a Ge-rich GST alloy for the PCM2 array 52, it is noted that the PCM cells will stably store the binary logic state of the data. Because the PCM1 array 12 is configured to store an m-ary logic state in each PCM cell, the PCM2 array 52 is designed to be larger in size than the PCM1 array 12 in order to support backup of all calculation weight data. Consider an example in which each PCM cell within the PCM1 array 12 can store four different logic states (i.e., the PCM cell is a 4-ary (quaternary) cell). Backup storage of the 4-ary logic state of each PCM cell of the PCM1 array 12 is supported by using two PCM cells of the PCM2 array 52. ​​The controller 102 advantageously performs conversion of multi-bit binary data stored in multiple PCM cells of the PCM2 array 52 to write one bit of m-ary data into one PCM cell of the PCM1 array 12.

[0030] refer to Figure 2 , the figure shows Figure 1 Schematic diagram of an in-memory computing circuit 10. Circuit 10 utilizes a memory array (PCM1) 12 formed of a plurality of memory cells 14 arranged in a matrix format having m columns and n rows. Each memory cell 14 is programmed to store one bit of data g ab , where a is an integer from 1 to m and b is an integer from 1 to n, these data are related to the calculation weight (also called kernel data) for the in-memory calculation operation. Each bit of the calculation weight has an m-ary logic value (where m is an integer greater than or equal to three), for example, the logic value is represented by the programmable transconductance in the memory unit 14.

[0031] In an embodiment of the memory array 12, each memory cell 14 includes a phase change memory (PCM) cell formed by a selection circuit (MOSFET transistor) 14t operating as a switch element and a variable resistive element 14r providing a programmable transconductance. The control node (gate) of the MOSFET transistor selection circuit 14t is connected to the word line WL. The source-drain conduction path of the MOSFET transistor switch element 14t is connected in series with the variable resistive element 14r between the bit line BL and a reference node (e.g., a source line or ground).

[0032] The PCM type memory cell 14 is a resistance change cell configured to store weight data using a phase change material. The phase change material is a chalcogenide in the form of a first GST alloy, such as a stoichiometric GST alloy, such as, for example, GST225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7).

[0033] Each memory cell 14 includes a word line WL and a bit line BL. The memory cells 14 in a common row of the matrix are connected by a common word line WL. The memory cells 14 in a common column of the matrix are connected to each other through a common bit line BL Connect with each other.

[0034] Each word line WL The word line is driven by word line driver circuit 16 using a pulsating word line signal generated by row controller / decoder circuit 18. Word line driver circuit 16 may be implemented as a CMOS driver circuit (eg, a series connected pair of p-channel and n-channel MOSFET transistors forming a logic inverter circuit).

[0035] The row controller / decoder circuit 18 receives address signals (ADDR) for in-memory computing operations and, in response thereto, performs selection of word lines WL to be simultaneously accessed (or actuated) in parallel during the emulated in-memory computing operations. <1> To WL <n>The row controller / decoder circuit 18 also receives the characteristic or coefficient data X for the in-memory computation operation. b , and in response thereto, for each correspondingly actuated word line WL Control the width of the generated pulsating word line signal (ie, the on time T ON ). This functionality is a form of pulse width modulation (PWM) control of the applied word line signal dependent on the digital value of the received characteristic or coefficient data X.

[0036] < / n> Figure 2 The response to the received address is illustrated by way of example only to have the corresponding coefficient data X1, . . . X n The digital value sets the pulse width of the pulsating word line signal to activate all word lines WL at the same time <1> ,…,WL <n>It will of course be appreciated that in-memory computation operations may instead utilize simultaneous activation of fewer than all rows of the memory array (selected by address signals or by given coefficient data X). b of zero).

[0037] On the bit line BL The analog signal Y formed on a Depending on the calculated weight g stored in the memory cell 14 of the column b=1 to n ab The logic states of the bits and the word lines WL applied to those memory cells 14 <1> ,…,WL <n>More specifically, it will be appreciated that each memory cell 14 contributes to the width of the pulsating word line signal X. b ×g ab is proportional to the bit line BL discharge current.< / n> Figure 1 In the example shown in FIG. , the word line signal 16 is simultaneously applied to the word line WL <1> ,…,WL <n>, bit line BL <1> The simulated signal Y1 formed on the 11 , X2×g 12 , …, and X n ×g 1n is proportional to the sum of the discharge currents caused.

[0038] The column processing circuit 20 senses and samples each bit line BL of the m columns. The analog signal Y a , and use the analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY a .Although Figure 2 An analog-to-digital converter (ADC) is shown provided for each column, but it will be appreciated that the ADC resources in the column processing circuit 20 may instead be shared by multiple columns using time division multiplexing. The column processing circuit 20 may also include a digital signal processing circuit system for processing the digital signal dY a Perform digital calculations and computations to generate decision outputs for in-memory computational operations.

[0039] The circuit 10 also includes a read-write circuit 22 that operates in conjunction with the row controller / decoder circuit 18 associated with memory access operations to write bits of data (e.g., computation weight data) to and read bits of data from the memory cells 14 of the memory array 12 in accordance with an applied address. This operation is referred to as a normal memory access mode and is distinct from the analog in-memory computation operations discussed above. The operation of writing data to the memory cells 14 of the memory array 12 in the normal memory access mode is different from the operation of using the computation weights (g stored in the PCM2 array 52 of the data storage circuit 50. mn Then, the control circuit 102 will control the read-write circuit 22 and the address selection to perform the data write operation.

[0040] Figure 2 The configuration of the in-memory computing circuit 10 shown in FIG. Figure 1 An example of an in-memory computing circuit used in the IMC system 100. Figure 2 The examples for the in-memory computing circuit 10 in the accompanying drawings should be understood to be non-limiting examples. Those skilled in the art will be well aware of other configurations of the in-memory computing circuit that may be used instead for the IMC system 100. It is important to note that regardless of which in-memory computing circuit configuration is employed, the memory cells 14 of the memory array 12 are implemented as resistive memory cells using the stoichiometric GST alloy discussed above for the phase change material.

[0041] Reference now Figure 3 , the figure shows Figure 1 Schematic diagram of a data storage circuit 50 of FIG. The circuit 50 utilizes a memory array 52 formed by a plurality of memory cells 54 arranged in a matrix format having j columns and k rows. Each memory cell 54 is programmed to store backup data h associated with a computational weight (also referred to as kernel data) of an in-memory computational operation. cd Where c is an integer from 1 to j and d is an integer from 1 to k. Each bit of the backup data has a binary logic value represented by a programmable transconductance in the memory cell 54, for example.

[0042] The data g used to calculate the weight ab Each m-bit is associated with the backup data h cd This is because the backup data h cd Multiple binary data bits to store data g ab In the specific example of m=4, the weight data g is calculated. ab A single bit and backup data h cd This relationship is in Figure 3 The dotted box 55 surrounding the two memory cells 54 is shown in FIG. 11 With binary backup data bit h 11 and h 21 Associated, and the m-ary calculation weight data g 12 With binary backup data bit h 12 and h 22 Associated.

[0043] In an embodiment of the memory array 52, each memory cell 54 includes a phase change memory (PCM) cell formed by a selection circuit (bipolar transistor) 54t operating as a switching element and a variable resistive element 54r providing a programmable transconductance. The control node (base) of the bipolar transistor selection circuit 54t is connected to the word line WL. The emitter-collector conduction path of the bipolar transistor switch element 54t is connected in series with the variable resistive element 54r between the bit line BL and a reference node (e.g., a source line or ground). For the memory cell 54, it is preferred to use a bipolar transistor for the selection circuit 54t because it occupies less space than a corresponding MOS transistor and therefore supports higher density and more compact cells. However, it will be understood that in applications where the density of the memory array 52 is less of a concern, a MOS transistor may be used instead for the selection circuit 54t.

[0044] The PCM-type memory cell 54 is configured to store backup weight data using a phase change material. The phase change material is a chalcogenide in the form of a second GST alloy different from the first GST alloy used in the array 12, such as a Ge-rich GST alloy (i.e., an alloy in which germanium is the dominant component of the average composition—e.g., where the stoichiometric percentage of germanium in the GST alloy is greater than or equal to 50%). Examples of suitable Ge-rich GST alloys are listed above. It will be noted that the PCM-type memory cell 54 is not a resistive cell.

[0045] Each memory cell 54 includes a word line WL and a bit line BL. The memory cells 54 in a common row of the matrix are connected by a common word line WL. <c>The memory cells 54 in a common column of the matrix are connected to each other through a common bit line BL <d>Connect with each other.

[0046] Each word line WL <d>The word line is driven by word line driver circuit 56 with a pulsating word line signal generated by row controller / decoder circuit 58. Word line driver circuit 56 may be implemented as a CMOS driver circuit (eg, a series connected pair of p-channel and n-channel MOSFET transistors forming a logic inverter circuit).

[0047] The row controller / decoder circuit 58 receives an address signal (address) for a memory access operation mode and, in response thereto, performs operations to select a word line WL when performing a read or write operation on the memory array. <1> To WL <j>The function of a single word line to be accessed (or actuated) in.

[0048] The read-write circuit 62 operates in conjunction with the row controller / decoder circuit 58 associated with memory access operations to write bits of data (e.g., calculation weight data) to the memory cells 54 of the memory array 52 and read bits of data from the memory cells 54. This operation is referred to as a normal memory access mode. The operation of reading data from the memory cells 54 of the memory array 52 in the normal memory access mode is performed in conjunction with the use of the backup data h read from the memory array 52. jk The data refresh of the bits is performed accordingly to generate the calculation weight (g mn As discussed above, the control circuit 102 operates to control the reading and writing of the backup data h from the memory 52 through the read-write circuit 62 and the applied address. jk The bits of the m-ary data are converted from binary to m-ary, and the m-ary calculation weight data g is converted to m-ary by the read-write circuit 22 and the applied address. mn The memory array 12 is written.

[0049] Reference now Figure 4 , which shows a cross section of a phase change memory cell 70. The memory cell 70 includes a memory region 72. A first electrode 74 contacts the lower surface of the memory region 72. A second electrode 76 contacts the upper surface of the memory region 72. The memory region is made of a phase change material, such as a chalcogenide material including a GST alloy. When the memory cell 70 is formed Figure 1 and Figure 2 When the memory cell 70 is one of the memory cells 14 of the memory array 12 in the in-memory computing circuit 10, the cell 70 is a resistance cell using a GST alloy for the memory region 72, and the GST alloy is a stoichiometric GST alloy, for example, including GST 225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7). When the memory cell 70 is formed Figure 1 and Figure 3 When one of the memory cells 54 of the memory array 52 in the data storage circuit 50 of the memory array 12 is used, the GST alloy used for the memory region 72 is a Ge-rich GST alloy (where the stoichiometric content of germanium in the alloy is equal to or greater than 50%). The first and second electrodes 74 and 76 are made of a conductive material (such as TiSiN, TiN or TaN). In the case of a resistance cell configuration for the memory cell 14 of the memory array 12, an additional conductive (resistive) layer ( Figure 4 The first electrode 74 is configured to have a very narrow width relative to the second electrode 76. This provides a smaller thermal conduction area at the lower surface of the memory area 72. The first electrode 74 is surrounded by an insulating material 80 and is electrically coupled to the second electrode 76. Figure 4 The selection circuit (transistor) is not shown in FIG. 1 , but can be referred to, for example, Figure 2 The transistor 14t or Figure 3 The selection circuit controls the current to pass through the first electrode 74 by the transistor 54t in the memory region 72. This current selectively heats the chalcogenide material in the memory region 72 by the Joule effect. Thus, the first electrode 74 acts as a heating element. Through the heat conduction area at the lower surface of the memory region 72, the heating is concentrated in the semicircular or hemispherical portion 78 of the memory region 72 to achieve a phase change.

[0050] To program the logic state in the memory cell 70, the heating element provided by the first electrode 74 is actuated to heat the phase change portion 78 of the memory region 72 to above its crystallization temperature. Control is then performed at the rate at which the phase change portion 78 is subsequently allowed to cool. The slower the cooling rate, the phase change material in the phase change portion 78 will tend to the crystalline phase. Conversely, the faster the cooling rate, the phase change material in the phase change portion 78 will tend to the amorphous phase.

[0051] In a binary data storage function, such as that associated with the memory array 52 of the data storage circuit 50 and implemented using a germanium-rich GST alloy, the resistance of the memory region 72 having the phase change portion 78 programmed in the crystalline phase provides a first logic state (referred to as a reset state or logic "0" state), and the resistance of the memory region 72 having the phase change portion 78 programmed in the amorphous phase provides a second logic state (referred to as a set state or logic "1" state). When reading from the memory cell 70, a voltage is applied between the first and second electrodes 74, 76, and the current flowing through the memory region 72 is read. The magnitude of the current will be proportional to the conductivity of the memory region 72. With the phase change portion 78 programmed in the crystalline phase, a relatively high current will flow due to the lower resistance, thereby indicating programming of the memory cell 70 in the reset state or logic "0" state, and with the phase change portion 78 programmed in the amorphous phase, a relatively low current will flow due to the higher resistance, thereby indicating programming of the memory cell 70 in the set state or logic "1" state.

[0052] In an m-ary data storage function, such as that associated with a memory array 12 of an in-memory computing circuit 10 and implemented using a variable resistance cell configuration having a stoichiometric GST alloy, the resistance of a memory region 72 having a phase change portion 78 programmed in a crystalline phase provides a first logic state, and due to the different volumes of the phase change portion 78 in the amorphous phase, the different resistances of the memory region 72 provide intermediate logic states and a final logic state. Now consider an example where m=4 (i.e., 4-ary or quaternary logic). When reading from the memory cell 70, a voltage is applied between the first and second electrodes 74, 76, and the current flowing through the memory region 72 is read. The magnitude of the current will be proportional to the conductivity of the memory region 72. The magnitude of the current as a function of resistance is sensed. As the phase change portion 78 is programmed in the crystalline phase, the highest current will flow due to the lowest resistance, thereby indicating that the memory cell 70 is programmed to the first logic "11" state. As the phase change portion 78 having the first volume is programmed in the amorphous phase, a slightly lower current will flow due to the slightly higher resistance, thereby indicating that the memory cell 70 is programmed to the second logic "10" state. As the phase change portion 78 having the second volume (larger than the first volume) is programmed in the amorphous phase, a further lower current will flow due to the higher resistance, thereby indicating that the memory cell 70 is programmed to the third logic "01" state. Finally, as the phase change portion 78 having the third volume (larger than the second volume) is programmed in the amorphous phase, the lowest current will flow due to the highest resistance, thereby indicating that the memory cell 70 is programmed to the fourth logic "00" state.

[0053] Reference again Figure 1 In order to ensure the wide application of the in-memory computing (IMC) system 100, especially to support real edge computing applications under harsh environmental conditions, a single integrated circuit chip implementation for the system 100 is preferred. Therefore, the in-memory computing circuit 10, the data storage circuit 50 and the control circuit 102 are preferably supported on a single integrated circuit substrate. This is referred to as a system-on-chip (SoC) solution in the art. The challenge then becomes how to co-integrate a memory array 12 including a PCM cell 14 using a variable resistance cell configuration with a memory array 52 including a PCM cell 54 using a germanium-rich chalcogenide material, wherein the variable resistance cell configuration uses a stoichiometric chalcogenide material provided by a first GST alloy such as GST 225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7) for the memory PCM1, wherein the germanium-rich chalcogenide material is provided by a Ge-rich GST alloy as a second GST alloy for PCM2.

[0054] Reference now Figure 5A-1 to Figure 5N-1 and Figure 5A-2 to Figure 5N-2 , these figures illustrate steps in a manufacturing method for co-integrating a PCM cell 14 using a varistor cell configuration using a chalcogenide phase change material provided by a first GST alloy (e.g., using a stoichiometric alloy such as GST 225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7)) with a PCM cell 54, wherein the varistor cell configuration uses a chalcogenide phase change material provided by a first GST alloy (e.g., using a stoichiometric alloy such as GST 225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7)), wherein the PCM cell 54 uses a chalcogenide phase change material provided by a second GST alloy different from the first GST alloy (e.g., a Ge-rich GST alloy). In these figures, a "-1" suffix is ​​used for the figure labels to indicate that the structure shown is associated with the PCM cell 14. With respect to the figures using the "-1" suffix, the structure illustrated on the right shows a cross-section taken through the dotted vertical line 200 shown on the left. Thus, the structure shown on the left side of the figure with the "-1" suffix extends in a first direction (e.g., the x-direction), and the structure shown on the right side of the figure with the "-1" suffix extends in a second direction (e.g., the y-direction) orthogonal to the first direction. Additionally, in these figures, the use of a "-2" suffix for the figure labels indicates that the structures shown are associated with the PCM cell 54. With respect to the figures using the "-2" suffix, the structures illustrated on the left side show a cross section taken through the dotted vertical line 202 shown on the right side. Thus, the structures shown on the left side of the figures with the "-2" suffix extend in a first (x) direction, and the structures shown on the right side of the figures with the "-2" suffix extend in a second (y) direction orthogonal to the first direction.

[0055] In all Figure 5A-1 to Figure 5N-1 and Figure 5A-2 to Figure 5N-2 , the structures shown preferably share a common semiconductor substrate 204 consistent with a co-integration process. In this context, the phrase "common semiconductor substrate" means a single semiconductor substrate (either a bulk substrate type or a semiconductor-on-insulator (SOI) substrate type) that supports both arrays 12 and 52 as well as other integrated circuit systems required for a given application.

[0056] Figure 5A-1 and Figure 5A-2 - using conventional integrated circuit manufacturing processes to form integrated circuit transistor devices in and on the common semiconductor substrate 204. These integrated circuit transistor devices include Figure 5A-1 The MOSFET transistor selection circuit 14t for the PCM cell 14 shown in FIG. 1 and further includes the following Figure 5A-2 14 t for the PCM cell 54 shown in FIG. 14 . Details of the implementation of the MOS transistor and the bipolar transistor are not shown in the figure; those skilled in the art are well aware of how to integrate transistor devices on a semiconductor substrate 204. A common pre-metallization dielectric (PMD) layer 206 is deposited on the semiconductor substrate 204 and the integrated circuit transistor devices for the selection circuit 14 t and the selection circuit 54 t. The upper surface of the PMD layer 206 is planarized using a suitable chemical-mechanical polishing (CMP) process. An opening is formed and then filled with a conductive material (such as, for example, tungsten) to provide a substrate contact 208 extending through the PMD layer 206 to the doped substrate region of the transistor for the selection circuit 14 t and the selection circuit 54 t. A layer of silicide may be provided to improve the contact resistance between the substrate contact 208 and the doped substrate region.

[0057] Figure 5B-1 and Figure 5B-2 - The heating elements 74 for the PCM cells 14 and 54 are then formed in the insulating region 80. The structure for the heating element includes an L-shaped first electrode 74 within the insulating region 80. The provision of the L-shaped first electrode enables the vertical portion 74v of the first electrode 74 to occupy a smaller area at the top surface of the electrode, while the horizontal portion 74h of the first electrode 74 can occupy a larger area at the bottom surface of the electrode, thereby ensuring electrical contact with the substrate contact 208 when alignment errors occur during manufacturing. The insulating region 80 includes a plurality of insulating structures, including a silicon nitride layer 210 for laterally isolating the horizontal portion 74h of the first electrode 74, silicon nitride regions 212 and 214 surrounding the vertical portion 74v of the first electrode 74, and a silicon oxide region 216 for insulation between the heating elements of adjacent memory cells. The fabrication of the structure for the heating element can, for example, utilize the process taught by U.S. Pat. Nos. 10,510,955 or 11,653,582 (both of which are incorporated herein by reference).

[0058] Figure 5C-1 and Figure 5C-2 - A layer 218 of a germanium-rich (first) GST alloy (i.e., Ge-GST alloy) is blanket deposited on top of the L-shaped first electrode 74 and the regions 212, 214, and 216 of the insulating region 80. The germanium-rich GST alloy may, for example, include a layer of GST 712 alloy (Ge7Sb1Te2), GST 523 alloy (Ge5Sb2Te3), or Ge x Sb y Te z N j The chalcogenide material provided by the alloy, wherein x is a stoichiometric percentage equal to or greater than 50% and j is a stoichiometric percentage as described above. Next, a layer 220 of titanium nitride (TiN) is blanket deposited on top of the layer 218 of germanium-rich GST alloy. The layer 220 will ultimately form the second electrode 76 for the memory cell 54.

[0059] Figure 5D-1 and Figure 5D-2 - A masking layer 222 is then blanket deposited on top of layer 220 and photolithographically patterned to form an etch mask 224 covering the PCM cells 54. The etch mask 224 comprises openings 226, exposing the areas where the PCM cells 14 are located.

[0060] Figure 5E-1 and Figure 5E-2 One or more etching operations are then performed through the openings 226 in the etching mask 224 to remove the layer 220 of titanium nitride and the layer 218 of germanium-rich GST alloy from the areas where the PCM cells 14 are located. When the silicon nitride material of the areas 212 and 214 is reached, the etching operations stop.

[0061] Figure 5F-1 and 5F-2 - The etch mask 224 is then removed and a wafer cleaning process is performed (eg, standard cleaning known to those skilled in the art).

[0062] Figure 5G-1 and Figure 5G-2 - A layer 228 of resistive material is blanket deposited on top of the L-shaped first electrode 74 within the insulating region 80 in the area where the PCM cells 14 are located and on top of the layer 220 of titanium nitride (TiN) in the area where the PCM cells 54 are located. The resistive material of the layer 228 may, for example, include titanium, titanium nitride, tungsten, a carbon alloy (doped with silicon, nitrogen or other dopants) or doped polysilicon. The choice of material for the layer 228 is preferably a material whose resistance is thermally stable. For example, refer to U.S. Patent No. 11,227,992 (incorporated herein by reference). Next, a layer 230 of a varistor (or stoichiometric) GST alloy (e.g., GST 225 alloy (Ge2Sb2Te5) or GST 447 alloy (Ge4Sb4Te7), which includes preferred alloys) is blanket deposited on top of the layer 228 of resistive material. Next, a layer 232 of titanium nitride (TiN) is blanket deposited on top of the layer 230 of stoichiometric GST alloy. Layer 232 will ultimately form the second electrode 76 for the memory cell 14 .

[0063] The layer 228 of resistive material is a component of the resistive memory cell 12, but it is noted that the inclusion of the layer 228 can also help solve the problem of surface cleaning effect of the wafer ( Figure 5F-1 ), which is performed after etching away the layer 218 of the germanium-rich GST alloy. For example, this surface cleaning may not produce a sufficiently clean surface finish in the area where the PCM cells 14 are located to ensure electrical continuity between the L-shaped first electrode 74 and the deposited layer 230 of the GST alloy.

[0064] Figure 5H-1 and Figure 5H-2 - A masking layer 234 is then blanket deposited on top of layer 232 and photolithographically patterned to form an etch mask 236 that partially covers PCM cells 14 (but does not completely cover PCM cells 54). The partial coverage of etch mask 236 includes openings 238 to form a plurality of holes in the x-direction ( Figure 5H-1 ) defines the dimension “a” of the PCM cell 14.

[0065] Figure 5I-1 and Figure 5I-2 - One or more etching operations are then performed through the openings 238 in the etch mask 236 to: i) remove the layer 232 of titanium nitride (TiN), the layer 230 of stoichiometric GST alloy, and the layer 228 of resistive material not covered by the etch mask 236 in the area where the PCM cells 54 are located; and ii) remove portions of the layer 232 of titanium nitride (TiN), the layer 230 of stoichiometric GST alloy, and the layer 228 of resistive material not covered by the etch mask 236 in the area where the PCM cells 14 are located. The etching leaves an opening 240 in the area where the PCM cells 14 are located, adjacent to the defined dimension "a" in the x-direction of the stack 242 of layers 228, 230, 232 for the PCM cells 14. The etching operation stops when the silicon nitride material in the region 214 is reached.

[0066] Figure 5J-1 and Figure 5J-2 After removing mask 236, the top surface and sidewalls of stack 242 in the area of ​​PCM cells 14 and the top surface of layer 220 in the area of ​​PCM cells 54 are then lined / covered with a layer 244 of silicon nitride, and the remainder of opening 240 is filled with a silicon oxide fill 246. A planarization operation is then performed using a CMP process to remove excess silicon nitride and silicon oxide and provide a planar top surface 248.

[0067] Figure 5K-1 and Figure 5K-2 - A masking layer 254 is then blanket deposited on top of the planar surface 248 provided by layer 244 and filler 246 and photolithographically patterned to form an etch mask 256 that partially covers PCM cells 14 and PCM cells 54. The partial coverage of the etch mask 256 includes the y-direction ( Figure 5K-1 The opening 258 of dimension "b" defining the PCM unit 14 and the opening 258 in the x direction ( Figure 5K-2 ) defines an opening 260 of dimension “c” of the PCM unit 14.

[0068] Figure 5L-1 and Figure 5L-2 -One or more etching operations are then performed through the openings 258 and 260 in the etching mask 256 to: i) remove the layer 244 of silicon oxide, the layer 232 of titanium nitride (TiN), the layer 230 of the stoichiometric GST alloy, the layer 228 of the resistive material, and the portions of the vertical 74v and horizontal 74h portions of the heater that are not covered by the mask 256 in the area where the PCM cell 14 is located; and ii) remove the layer 244 of silicon oxide, the layer 220 of titanium nitride (TiN), the layer 218 of the germanium-rich GST alloy, and the portions of the vertical 74v and horizontal 74h portions of the heater that are not covered by the mask 256 in the area where the PCM cell 54 is located. The etching leaves openings 262 in the region where PCM cells 14 are located, adjacent to the defined dimension "b" of the stack 264 of layers 244, 232, 230, 228, and 74 for PCM cells 14 in the y-direction, and leaves openings 266 in the region where PCM cells 54 are located, adjacent to the defined dimension "c" of the stack 268 of layers 244, 220, 218, and 74 for PCM cells 54 in the x-direction. The etching operation stops when the material of the pre-metallization dielectric layer 206 is reached. Wafer cleaning may then be performed.

[0069] Figure 5M-1 and Figure 5M-2 - After removal of mask 256, the sidewalls of stack 264 in the region where PCM cell 14 is located and the sidewalls of stack 268 in the region where PCM cell 54 is located are then lined with a layer of silicon nitride 270, and the remainder of openings 262 and 266 are filled with silicon oxide fill 272. A planarization operation is performed to remove excess silicon nitride and silicon oxide and provide a planar top surface. It will be noted that memory cell 14 is now bounded on all four sides (in both the x and y directions) by SiN insulating material (244, 270), so that each cell includes its own memory region 72 with an associated phase change portion 78 isolated from the memory regions of other cells (see Figure 4 and Fig. 6A ). For example, this is referred to in the art as a "fully confined cell" embodiment (see also U.S. Patent No. 11,227,992), in which materials 244, 246, 270 and 272 used for cell 14 provide galvanic isolation and thermal barriers that separate adjacent variable resistance cells 14 in memory array 12 from each other. The variable resistance cell is fully confined in the x and y directions (two dimensions) because in order to obtain a fully amorphous state (indicating weight=0), it is required that the amorphized region covers the entire cell area (region 78 width is greater than the cell critical dimension). If the cell 14 is instead confined in only one dimension, as shown for cell 54 of array 52, then it would not be possible to obtain an amorphous volume in region 78 extending to the edge of the cell. For cells 54 used in the backup storage area, full confinement (in two dimensions) is not necessary because these cells lack the lamina provided by layer 228, and the high resistive amorphous state can be obtained simply by forming a certain volume of amorphous material above the heater. Thus, the memory cell 54 is bounded on both sides (in the x-direction) by the SiN insulating material (270) such that multiple cells in the y-direction share a common memory region 72 having multiple phase change portions 78 (see Figure 4 and Figure 6B ).

[0070] Figure 5N-1 and Figure 5N-2 Conventional metallization layer formation is then performed to provide vias 280 and metal lines 282 using dielectric material 264 to make electrical contact with layer 232 for PCM cells 14 and layer 22 for PCM cells 54 .

[0071] Although the present invention has been illustrated and described in detail in the drawings and the above description, these illustrations and descriptions should be considered illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.< / j> < / d> < / d> < / c> < / n> < / n>

Claims

1. A method for co-integrating a first phase change memory PCM cell and a second PCM cell on a common semiconductor substrate having a first region and a second region, comprising: depositing a layer of a first phase change material over a first insulating heating element associated with the first region; depositing a layer of a second phase change material different from the first phase change material over a second insulating heating element associated with the second region; photolithographically patterning the layer of the first phase change material to define a first memory region for a first PCM cell; and The layer of the second phase change material is photolithographically patterned to define a second memory region for a second PCM cell.

2. The method of claim 1, wherein: Depositing the layer of the first phase change material includes depositing the layer of the first phase change material over the first insulating heating element and the second insulating heating element associated with the first region and the second region, the method further comprising: masking over the layer of the first phase change material at the first region; and The layer of the first phase change material at the second region is removed.

3. The method of claim 2, wherein: Depositing the layer of the second phase change material includes depositing the layer of the second phase change material over a remainder of the layer of the first phase change material at the first region, the method further comprising: masking over the layer of the second phase change material at the second region; and The layer of the second phase change material at the first region is removed.

4. The method of claim 1, wherein: The first phase change material is a germanium-rich GST alloy and the second phase change material is a stoichiometric GST alloy.

5. The method of claim 4, wherein: The stoichiometric GST alloy is selected from the group consisting of GST 225 alloy (Ge2Sb2Te5) and GST 447 alloy (Ge4Sb4Te7), and wherein the germanium-rich GST alloy includes a stoichiometric percentage of greater than or equal to 50% germanium.

6. The method of claim 5, wherein: The germanium-rich GST alloy also includes nitrogen in a stoichiometric percentage in the range of 5-25%.

7. The method of claim 1, wherein: Photolithographically patterning the layer of the first phase change material to define the first memory region for the first PCM cell includes defining opposing sides of the first PCM cell in only one direction.

8. The method of claim 1, wherein: Lithographically patterning the layer of the second phase change material to define the second memory region for the second PCM cell includes defining first opposing sides of the second PCM cell in a first direction and defining second opposing sides of the second PCM cell in a second direction orthogonal to the first direction.

9. The method of claim 1, wherein: Photolithographically patterning the layer of the first phase change material and photolithographically patterning the layer of the second phase change material include: masking over a portion of the layer of the second phase change material at the second region and masking over the layer of the first phase change material at the first region; and The layer of the second phase-change material at the second region that is not masked thereon is removed to define the second phase-change material at the second region in a first direction.

10. The method of claim 9, wherein: removing the layer of the second phase-change material at the second region that is not masked thereon to define the second phase-change material at the second region in the first direction to form a first opening at a first opposite side of a stack including the second phase-change material defined in the first direction, the method further comprising: lining sidewalls of the stack in the first opening with a silicon nitride material; and The first opening is then filled with a silicon oxide material.

11. The method of claim 9, further comprising: masking over another portion of the layer of the second phase change material at the second region and masking over the layer of the first phase change material at the first region; as well as The layer of the second phase-change material at the second region that is not masked thereon is removed to further define the second phase-change material at the second region in a second direction perpendicular to the first direction.

12. The method of claim 11 , wherein removing the layer of the second phase-change material at the second region that is not masked thereon to further define the second phase-change material at the second region in the second direction forms a second opening at a second opposite side of the stack including the second phase-change material defined in the second direction, the method further comprising: lining sidewalls of the stack in the second opening with a silicon nitride material; as well as The second opening is then filled with a silicon oxide material.

13. The method of claim 9, further comprising: masking over another portion of the layer of the second phase change material at the second region and over a portion of the layer of the first phase change material at the first region; removing the layer of the second phase-change material at the second region that is not masked thereon to further define the second phase-change material at the second region in a second direction orthogonal to the first direction; as well as The layer of the first phase change material at the first region that is not masked thereon is removed to define the first phase change material at the first region in the second direction.

14. The method of claim 13: in, removing the layer of the second phase-change material at the second region that is not masked thereon to further define the second phase-change material at the second region in the second direction to form a second opening on an opposite side of the first stack including the second phase-change material defined in the second direction; wherein the layer of the first phase-change material at the first region that is not masked thereon is removed to define the first phase-change material at the first region in the second direction to form a second opening on an opposite side of a second stack including the first phase-change material defined in the second direction; The method further includes: lining sidewalls of the first stack and the second stack in the first opening and the second opening, respectively, with a silicon nitride material; and The first opening and the second opening are then filled with silicon oxide material.

15. The method of claim 1 further comprising depositing a resistive layer between the insulating heating element for the second region and the layer of the second phase change material.

16. The method of claim 15, wherein: The resistive layer is made of a material selected from the group consisting of: titanium, titanium nitride, tungsten, a carbon alloy, or doped polysilicon.

17. The method of claim 1: in, photolithographically patterning the layer of the first phase change material to define the first memory region for the first PCM cell to be confined in one lateral extension dimension; and Therein, photolithographically patterning the layer of the second phase change material defines the second memory region for the second PCM cell to be completely confined in two laterally extending orthogonal dimensions.

18. The method of claim 1, wherein: Each of the first phase change material and the second phase change material is a GST material, and wherein the second phase change material differs from the first phase change material by having a greater stoichiometric percentage of germanium.

19. The method of claim 1, wherein: The second PCM cell is a resistance-varying PCM cell and the first PCM cell is not a resistance-varying PCM cell.

20. An in-memory computing (IMC) system, comprising: an in-memory computation circuit comprising a first phase change memory PCM array configured to store computation weights for an in-memory computation operation; wherein the first PCM array comprises PCM units made of a phase change material, the phase change material comprising a first GST alloy; Data storage circuitry including a second PCM array configured to store backup data of said computation weights for said in-memory computation operations; and The second PCM array includes PCM units made of a phase change material, and the phase change material includes a second GST alloy different from the first GST alloy.

21. The IMC system of claim 20, further comprising a control circuit configured to read the backup data from the second PCM array and write to the first PCM array according to the backup data to refresh the calculation weights used for the in-memory calculation operation.

22. The IMC system of claim 21, wherein: The calculated weights include m-ary data stored in each PCM cell of the first PCM array, m being an integer greater than or equal to three, and wherein the backup data includes binary data stored in each PCM cell of the second PCM array.

23. The IMC system of claim 22, wherein: The control circuit is further configured to convert binary data of the backup data into m-ary data for the calculation weight.

24. The IMC system of claim 20, wherein: The first GST alloy is a stoichiometric GST alloy and the second GST alloy is a germanium-rich GST alloy.

25. The IMC system of claim 24, wherein: The stoichiometric GST alloy is selected from the group consisting of GST 225 alloy (Ge2Sb2Te5) and GST 447 alloy (Ge4Sb4Te7), and wherein the germanium-rich GST alloy includes a stoichiometric percentage of greater than or equal to 50% germanium.

26. The IMC system of claim 25, wherein: The germanium-rich GST alloy also includes nitrogen in a stoichiometric percentage in the range of 5-25%.

27. The IMC system of claim 20, wherein: The in-memory computation operation is a matrix-vector multiplication operation.

28. The IMC system of claim 20, wherein: The in-memory computing circuit having the first PCM array and the data storage circuit including the second PCM array are both disposed on a common semiconductor substrate.

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