DIE data line and address line fault diagnosis method and test system

Abstract

The invention discloses a diagnosis method and a test system for DIE data line and address line faults, relates to the technical field of semiconductor integrated circuit test, and discloses the diagnosis method for the DIE data line and address line faults, which is used for testing a plurality of DIEs to be tested. The method comprises the following steps: pre-writing and / or pre-reading a plurality of to-be-tested DIEs to determine an actual sampling interval of read-write data of each to-be-tested DIE; obtaining a pattern vector test program, wherein the pattern vector test program is used for generating third data for testing a fault; writing the third data into each to-be-tested DIE at the corresponding actual sampling interval; and reading data in the to-be-tested DIE at the actual sampling interval to obtain fourth data, and positioning a fault of a data line or an address line according to the third data and the fourth data. The method and the device can adapt to tests of DIEs of DRAMs of different brands and different capacities, and can position faults of data lines or address lines.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit testing technology, and in particular to a method and a testing system for diagnosing faults of DIE data lines and address lines. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory. Since DRAM can only store data for a short time, in order to maintain data, DRAM must be refreshed every once in a while. Among them, the basic storage unit of DRAM is composed of a transistor (Transistor) and a capacitor (Capacitor). Its working principle is that when the word line (Word line, WL) is selected, the transistor is turned on, and the information stored on the capacitor can be read through the bit line (Bit line, BL), that is, the data line. Among them, the state of the capacitor determines the logical state of the storage unit as 1 or 0. Specifically, a charged capacitor is considered to be a logical 1 in digital electronics, while an "empty" capacitor is 0.

[0003] With the development of technology, the performance of DRAM is getting higher and higher, and the manufacturing process size is getting smaller and smaller. In order to improve the stability of DRAM operation, it is necessary to test the performance of DRAM. However, the current DRAM testing method is only a preliminary and simple read and write test that cannot accurately locate the faulty data lines and address lines.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a method and a test system for diagnosing DIE data line and address line faults, aiming to locate the faulty data lines and address lines.

[0006] To achieve the above object, the present application proposes a method for diagnosing DIE data line and address line faults, which is used to test multiple DIEs to be tested, and the method comprises:

[0007] Pre-writing and / or pre-reading the plurality of DIEs to be tested to determine an actual sampling interval of read and write data of each of the DIEs to be tested;

[0008] Acquire a pattern vector test program, wherein the pattern vector test program is used to generate third data for testing a fault;

[0009] Writing the third data to each of the DIEs to be tested at the corresponding actual sampling interval;

[0010] The data in the DIE to be tested is read at the actual sampling interval to obtain fourth data, and the fault of the data line or the address line is located according to the third data and the fourth data.

[0011] In one embodiment, the step of pre-writing and / or pre-reading the plurality of DIEs to be tested to determine the actual sampling interval of the read and write data of each DIE to be tested comprises:

[0012] Writing first data into a first storage space of the DIE to be tested at a first sampling interval in response to a write enable signal;

[0013] In response to a read enable signal, reading the data in the DIE to be tested at a first sampling interval to obtain second data;

[0014] When the second data is inconsistent with the first data, the first sampling interval is adjusted and then the step of writing the first data into the first storage space of the DIE to be tested at the first sampling interval in response to the write enable signal is performed;

[0015] When the second data is consistent with the first data, the first sampling interval is recorded as the actual sampling interval.

[0016] In one embodiment, when the second data is inconsistent with the first data, the step of adjusting the first sampling interval and executing the step of writing the first data into the first storage space of the DIE to be tested at the first sampling interval in response to the write enable signal further includes:

[0017] Adjusting the first sampling interval includes increasing the value of the first sampling interval by a preset step value.

[0018] In one embodiment, in the step of adjusting the first sampling interval including increasing the value of the first sampling interval by a preset step value,

[0019] The value of the first sampling interval is less than a quarter of a clock period.

[0020] In one embodiment, when the value of the first sampling interval is greater than a quarter of a clock cycle, and the second data is inconsistent with the first data, the step of pre-writing and / or pre-reading the plurality of DIEs to be tested to determine the actual sampling interval of the read and write data of each of the DIEs to be tested includes:

[0021] A fault of a data line or an address line corresponding to the first storage space is located according to the first data and the second data.

[0022] In one embodiment, the third data includes 0x00000000000000000 and 0xFFFFFFFFFFFFFFFF;

[0023] The step of writing the third data to each DIE to be tested at the corresponding actual sampling interval, reading the data in the DIE to be tested at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or the address line according to the third data and the fourth data comprises:

[0024] Write one of 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0025] If the fourth data is inconsistent with the third data, find out the data bits with differences, that is, the storage unit with errors; if the fourth data is consistent with the third data, write the other of 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0026] If the fourth data is inconsistent with the third data, the data bits with differences are found, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, the first row address line is diagnosed as normal.

[0027] In one embodiment, the third data includes 0xAAAAAAAAAAAAAAAAAA and 0x55555555555555555;

[0028] The step of writing the third data to each DIE to be tested at the corresponding actual sampling interval, reading the data in the DIE to be tested at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or the address line according to the third data and the fourth data comprises:

[0029] write one of 0xAAAAAAAAAAAAAAAA and 0x55555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0030] If the fourth data is inconsistent with the third data, find out the data bits with differences, that is, the storage unit with errors; if the fourth data is consistent with the third data, write the other of 0xAAAAAAAAAAAAAAAA and 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0031] If the fourth data is inconsistent with the third data, the data bits with differences are found, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, the first row address line is diagnosed as normal.

[0032] In addition, to achieve the above purpose, the present application also proposes a DIE data line and address line fault testing system, including:

[0033] A host computer, which is in communication connection with the test board and is used to send a pattern vector test program, specification parameters of the DIE to be tested, and a test start / reset instruction to the test board;

[0034] The test board receives the pattern vector test program, the DIE specification parameters under test and the test start / reset instruction, and is used to output the timing bus signal of driving DRAM to the probe card board according to the pattern vector test program and the DIE specification parameters under test;

[0035] At least one probe card board, the probe card board receives the timing bus signal of the driving DRAM, and is used to perform DRAM bus timing training and calibration and read and write pattern vector testing on the DIE.

[0036] In one embodiment, the test board is further used to cache the test data read by the probe card board in a read operation and send it to the host computer;

[0037] The host computer is used to receive the test data, perform algorithm analysis, locate the address line or data line fault of the DIE, and obtain the test result.

[0038] In one embodiment, the test board comprises:

[0039] A control unit, the control unit is communicatively connected to the host computer and electrically connected to the functional test unit, and is used to receive the pattern vector test program, configuration parameters, test start instructions or test reset instructions issued by the host computer and issue them to the functional test unit;

[0040] A functional test unit, the functional test unit is electrically connected to the interface adapter unit, and is used to execute the pattern vector test program, parameter configuration, test start instruction or test reset instruction interactively issued by the control unit, and output a timing bus signal for driving the DRAM to the interface adapter unit,

[0041] And the test data read in the probe card board reading operation is cached and sent to the host computer through the interface adapter unit and the control unit;

[0042] The interface adapter unit is electrically connected to the probe card board and is used to convert the signals and instructions generated by the functional test unit and send them to the probe card board.

[0043] A power adapter unit is electrically connected to the function test unit and the interface adapter unit, and is used to supply power to the function test unit and the interface adapter unit, and provide the required core voltage and IO interface standard voltage.

[0044] The present application first determines the timing by pre-writing and / or pre-reading the multiple DIEs to be tested to determine the actual sampling interval of the read and write data of each DIE to be tested, so as to adapt to the test of DIEs of different brands and different capacities of DRAM, and ensure that the test data can be correctly written and read out so as to locate the faults of the data lines and address lines in the DIE. Secondly, the third data for testing the faults of the data lines and address lines is generated through the pattern vector test program, and then the third data is written to each DIE to be tested at the corresponding actual sampling interval, and then the data in the DIE to be tested is read at the actual sampling interval to obtain the fourth data, and the faults of the data lines or address lines are located according to the difference between the third data and the fourth data. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 A flow chart of a method for diagnosing DIE data line and address line faults according to Embodiment 1 of the present invention;

[0048] Figure 2A flow chart of a second embodiment of a method for diagnosing DIE data line and address line faults provided in the present application;

[0049] Figure 3 A flowchart diagram of a method for diagnosing DIE data line and address line faults according to Embodiment 3 of the present application;

[0050] Figure 4 A flowchart diagram of a fourth embodiment of a method for diagnosing a fault in a DIE data line and an address line of the present application is provided;

[0051] Figure 5 A flowchart diagram of a fifth embodiment of a method for diagnosing DIE data line and address line faults of the present application is provided;

[0052] Figure 6 A flowchart diagram of Embodiment 6 of the method for diagnosing DIE data line and address line faults of the present application is provided;

[0053] Figure 7 Schematic diagram of the equipment structure of the test system for DIE data line and address line failure in an embodiment of the present application.

[0054] Explanation of the accompanying figures: 1. Host computer; 2. Test board; 21. Control unit; 22. Functional test unit; 23. Interface adapter unit; 24. Power adapter unit; 3. Card probe board.

[0055] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0056] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0057] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0058] The main solution of the embodiment of the present application is: pre-write and / or pre-read the multiple DIEs to be tested to determine the actual sampling interval of the read and write data of each DIE to be tested; obtain a pattern vector test program, the pattern vector test program is used to generate third data for testing faults; write the third data to each DIE to be tested at the corresponding actual sampling interval; read the data in the DIE to be tested at the actual sampling interval to obtain fourth data, and locate the fault of the data line or address line according to the third data and the fourth data.

[0059] Die testing, or chip testing, is the functional and performance testing of a single chip (die) by automated testing equipment during the semiconductor manufacturing process. These tests are usually performed after the chip is cut from the wafer, but in some cases they may also be performed on the wafer (Wafer Level Test).

[0060] DDR (Double Data Rate) DRAM (Dynamic Random Access Memory) die testing is an important part of ensuring the quality of memory chips. DDR dies refer to the manufactured memory chip bare die, and a series of tests need to be performed on the dies before packaging. These tests are designed to verify the functional integrity of each die and ensure that they meet performance and reliability standards.

[0061] At present, the current DRAM die testing method is only a preliminary simple read and write test, which can only verify whether each memory cell can store and retrieve data. It is impossible to accurately locate the faulty data line and address line.

[0062] The present application can adapt to the testing of DIEs of different brands and different capacities of DRAM by pre-writing and / or pre-reading the multiple DIEs to be tested to determine the actual sampling interval of the read and write data of each DIE to be tested, thereby determining the timing, and ensure that the test data can be correctly written and read out so as to locate the faults of the data lines and address lines in the DIE. Secondly, a pattern vector test program is used to generate third data for testing the faults of the data lines and address lines, and then the third data is written to each DIE to be tested at the corresponding actual sampling interval, and then the data in the DIE to be tested is read at the actual sampling interval to obtain the fourth data, and the fault of the data line or address line is located according to the difference between the third data and the fourth data.

[0063] It should be noted that the execution subject of this embodiment can be a DI E test system, or a computing service device with data processing, network communication and program running functions, such as automated test equipment (ATE), or a DI E test device capable of realizing the above functions, etc. This embodiment does not specifically limit this. The following takes the automated test equipment as the execution subject as an example to illustrate this embodiment and the following embodiments.

[0064] Automated Test Equipment (ATE) is a highly integrated test platform used for automated testing of semiconductor devices. ATE systems usually include test heads, probe cards, test software, and various auxiliary equipment, which can automatically apply test signals to the chip under test and collect response signals for analysis. ATE can perform various types of tests, including functional tests, timing tests, performance tests, etc., to ensure that the functionality, reliability, and performance of the chip meet the specification requirements. ATE systems are widely used in wafer-level tests (WLT), chip-level tests (CP tests), and finished product tests after packaging (Final Test), and are one of the indispensable key equipment in the semiconductor manufacturing and testing process.

[0065] Based on this, the present application proposes a method for diagnosing DIE data line and address line faults in the first embodiment, which is used to test multiple DIEs to be tested. Figure 1 The method for diagnosing DIE data line and address line faults includes steps S100 to S300:

[0066] Step S100, pre-writing and / or pre-reading the plurality of DIEs to be tested to determine an actual sampling interval of the read and write data of each DIE to be tested;

[0067] Step S200, obtaining a pattern vector test program, wherein the pattern vector test program is used to generate third data for testing a fault;

[0068] Step S300, writing the third data to each DIE to be tested at the corresponding actual sampling interval, reading the data in the DIE to be tested at the actual sampling interval to obtain fourth data, and locating the fault of the data line or address line according to the third data and the fourth data.

[0069] DDR (Double Data Rate) memory transfers data twice in one clock cycle by transmitting data on the rising and falling edges of the clock signal. Therefore, the waveform of the written data is represented by two data bits in each clock cycle, which are sampled on the two edges of the clock. This design makes the transmission rate of DDR memory twice the clock frequency.

[0070] The sampling time is the critical moment to read or write data in DDR memory. The DDR memory controller samples data at the rising and falling edges of the clock, so the data waveform must be stable at these moments. In order to ensure the reliability of data transmission, DDR memory must strictly adhere to timing parameters, which define data validity, hold time, and delays for various operations.

[0071] Since the timing parameters directly affect the relationship between the data waveform and the sampling time. For example, t DQSS (deviation between data and clock signal) and t DQSQ Timing parameters such as (deviation between data and data strobe signal) determine the stability of data waveform at clock edge, which in turn affects whether memory controller can obtain data accurately during sampling. If timing is not set properly, data may not be stable at sampling time, thus causing errors.

[0072] Due to the different DIE timings of DRAMs of different brands and capacities, the timing of data writing or reading during testing does not match. The controller may sample data at the wrong time, resulting in the data not being correctly written into the memory. The read data is inconsistent with the actual stored data, resulting in data loss or inaccurate stored content, and even some data bits may not be written successfully.

[0073] In the actual testing process, due to differences in the test equipment hardware, such as PCB design, signal integrity, temperature, voltage and other factors, even if the test is performed with the standard timing in the design specifications provided by the manufacturer, the write operation may still not be successful, and the data waveform may be unstable, resulting in data write failure.

[0074] In this embodiment, firstly, the actual sampling interval of the read and write data of each DIE to be tested is determined by pre-writing and / or pre-reading the multiple DIEs to be tested, and the timing parameters are further adjusted and optimized to determine the timing parameters corresponding to the current hardware environment and chip characteristics, so as to adapt to the testing of DIEs of different brands and different capacities of DRAM, and ensure that the test data can be correctly written and read so as to locate the faults of the data lines and address lines in the DIE.

[0075] In this embodiment, after determining the actual sampling interval, the third data for testing the faults of the data lines and address lines is generated through the pattern vector test program, and then the third data is written to each DIE to be tested at the corresponding actual sampling interval, and then the data in the DIE to be tested is read at the actual sampling interval to obtain the fourth data, and the fault of the data line or address line is located according to the difference between the third data and the fourth data.

[0076] In DDR die (dynamic random access memory chip) testing, the pattern vector test program is used to generate test vectors. Test vectors refer to specific data patterns used to test memory, in other words, the third data used to test faults in this application. These vectors are usually a series of binary values ​​that are written to different locations of the memory and then read back to verify whether the behavior of the memory is as expected.

[0077] Exemplarily, the pattern vector test program generates a set of predetermined data patterns, which are usually simple binary sequences, such as all zeros (0x00), all ones (0xFF), alternating 01 sequences (such as 0x55, 0xAA), oblique sequences (such as 0x11, 0x22, etc.) and more complex pseudo-random sequences (PRBS), etc. The test program writes these predefined data patterns to a specific address or address range of the DDR memory. This process may cover the entire memory or only selectively test certain areas.

[0078] After writing is completed, the test program reads data from the same address, in other words, the fourth data in this application, and compares it with the third data written previously. If the read fourth data completely matches the written third data, it means that this part of the memory is working properly. If any mismatch is found, it indicates that the memory may be defective or faulty.

[0079] You can use known failure modes to test different address ranges one by one, gradually increasing or decreasing the address range to narrow down the location of the failure to determine at which address or addresses the failure occurs.

[0080] If the faulty address has been determined, the individual data lines at that address can be further tested. For example, different patterns can be written to each data line individually and the read results can be checked to see if they are correct. In this way, it can be determined which data line has a problem.

[0081] Example 1: Locating a data line fault

[0082] Assuming that the data read at a certain address is always wrong during the test, we can use the following steps to locate which data line has the problem:

[0083] 1. Select the test mode:

[0084] Select a simple test pattern, such as all zeros (0x00) or all ones (0xFF).

[0085] 2. Bit by bit test:

[0086] Write an all-zero pattern to a known fault address in memory.

[0087] Read the data and check if any bit has a value other than 0. If so, the data line corresponding to this bit may be faulty.

[0088] Repeat the above process, this time writing using the all-ones pattern and checking if any bit has a value other than 1.

[0089] 3. Locate the fault location:

[0090] If the same bit value is found to be different from what is expected in both tests, then there is probably a problem with that data line.

[0091] Note the location of the failed bit and perform similar tests on other addresses to confirm whether the failure is global or limited to a specific address.

[0092] Example 2: Locating address line faults

[0093] If the test shows that some addresses cannot be accessed correctly, we can use the following steps to locate which address line has a problem:

[0094] 1. Select the test mode:

[0095] Choose a simple test pattern, such as an alternating 01 sequence (0x55, 0xAA).

[0096] 2. Test address by address:

[0097] Use alternating 01 sequences to write to different addresses of the memory, and read the data.

[0098] Check that the data read out matches the pattern written in. If a certain address cannot always read data correctly, the address line associated with that address may be faulty.

[0099] 3. Mode change test:

[0100] Keeping the data pattern unchanged, modify the value of the address lines one by one to observe whether the change of a specific address line causes the failure.

[0101] If you find that changes to a certain address line always cause failures, then there is likely a problem with this address line.

[0102] Through the above method, after multiple iterations and adjustments to the test scheme, a specific data line or address line fault in the memory can be more accurately located.

[0103] Reference Figure 2 In another feasible implementation manner, step S100, the step of pre-writing and / or pre-reading the plurality of DIEs to be tested to determine the actual sampling interval of the read and write data of each of the DIEs to be tested may include steps S110 to S140:

[0104] Step S110, writing first data into a first storage space of the DIE to be tested at a first sampling interval in response to a write enable signal;

[0105] Step S120, in response to a read enable signal, reading the data in the DIE to be tested at a first sampling interval to obtain second data;

[0106] Step S130, when the second data is inconsistent with the first data, the first sampling interval is adjusted and then a step of writing the first data into the first storage space of the DIE to be tested at the first sampling interval in response to a write enable signal is executed;

[0107] Step S140: When the second data is consistent with the first data, the first sampling interval is recorded as the actual sampling interval.

[0108] In this embodiment, the write enable signal (Write Enable Signal, WE# or WE) is a signal used to control the write operation of the memory chip, which is used to indicate when the memory should receive data and write the data to the specified address. When the write enable signal is activated (usually a low level, represented as WE#, where "#" indicates that the low level is valid), it indicates that the memory chip is ready to accept data writing. At the same time, the signals on the address line and the data line, as well as possible other control signals (such as CAS#, column address selection signal) are used to determine the exact location of the data to be written. When the write enable signal is activated, after a first sampling interval, the rising edge and / or falling edge of the clock signal is sampled to obtain the first data to be written in the memory chip, and then the first data is written to the first storage space of the DIE to be tested. Among them, the first storage space is any storage capacity in the DDR die. It can be understood that a smaller value can be selected in this application to achieve the purpose of rapid verification. Preferably, the first storage space can be the first 32 bytes of address space of the DDR die.

[0109] In this embodiment, assuming that the starting address of the memory is 0x0000, the address range of the first 32 bytes is 0x0000 to 0x001F (hexadecimal representation). Generate a series of predetermined test patterns, such as all zeros, all ones, alternating 01 sequences, etc., and write these patterns into the address space of the first 32 bytes. After writing, read data from these addresses and compare them with the test patterns initially written. If the read data is completely consistent with the written pattern, it means that the sampling interval is correct, that is, the sampling time point of the read data is appropriate, and this part of the memory functions normally. If there is any mismatch, it indicates that this part of the memory may be defective or faulty. If the data is found to be inconsistent during the reading process, adjust the sampling interval (that is, the time point of reading the data) to try to find a suitable sampling time point so that the read data is consistent with the written data. When a sampling interval that makes the data consistent is found, record this sampling interval as the actual sampling interval for subsequent testing or other operations.

[0110] By pre-writing and / or pre-reading the first 32 bytes of address space of the memory, the sampling interval of the DDR die, i.e., the time point for reading data, can be quickly determined to ensure that the test data can be correctly written and read so as to locate the faults of the data lines and address lines in the DIE.

[0111] Reference Figure 3 In another feasible implementation manner, in step S130, when the second data is inconsistent with the first data, the step of adjusting the first sampling interval and executing the step of writing the first data to the first storage space of the DIE to be tested at the first sampling interval in response to the write enable signal may include step S131:

[0112] Step S131, increasing the value of the first sampling interval by a preset step value.

[0113] In this embodiment, in order to find a suitable sampling interval to ensure correct data reading, a method of gradually adjusting the sampling interval is adopted. The initial value of the first sampling interval can be set to 1ns, and one of 1ns, 2ns, 3ns...5ns can be used as a step value to gradually increase the value of the first sampling interval.

[0114] Specifically, the first sampling interval is set to 1ns. The first data is written into the first storage space of the DIE to be tested. The data is read at a sampling interval of 1ns to obtain the second data. Compare whether the second data is consistent with the first data. If they are consistent, execute step S140 to record the current sampling interval (1ns) as the actual sampling interval. If they are inconsistent, execute step S131, select a step value, such as 1ns, and increase the first sampling interval by 1ns, that is, to 2ns. Repeat the steps of writing the first data into the first storage space of the DIE to be tested and reading the data to obtain the second data, that is, write and read the data at a sampling interval of 2ns, and compare. Continue to gradually increase the sampling interval with the selected step value, such as 3ns, 4ns, 5ns... until a sampling interval that makes the second data consistent with the first data is found.

[0115] Because the sampling interval needs to leave enough room to meet the requirements of setup time and hold time. If the sampling interval is greater than a quarter of a cycle, the data may not be stable at the time of sampling, or may change immediately after sampling, resulting in a reading error. In order to prevent clock edge overlap, in this embodiment, the value of the first sampling interval is less than a quarter of a clock cycle. In this way, the sampling interval can be gradually adjusted until a sampling interval is found that can ensure that the data is read correctly but not too large, ensuring that the data has enough time to remain stable before and after the sampling point, and at the same time, the two sampling opportunities in each clock cycle can be fully utilized, thereby improving the efficiency and reliability of data transmission.

[0116] Reference Figure 4 In another feasible implementation manner, when the value of the first sampling interval is greater than a quarter of a clock cycle, and the second data is inconsistent with the first data, the step 100 of pre-writing and / or pre-reading the plurality of DIEs to be tested to determine the actual sampling interval of the read and write data of each of the DIEs to be tested includes step 150:

[0117] Step S150: locating a fault of a data line or an address line corresponding to the first storage space according to the first data and the second data.

[0118] In this embodiment, if the value of the first sampling interval is greater than a quarter of the clock cycle, and the second data is inconsistent with the first data, it means that there is a data line or address line fault in the first storage space, and the specific position of the data line or address line fault in the first storage space needs to be located.

[0119] Specifically, assuming that the first sampling interval is set to 0.5ns, the clock cycle is 1ns (i.e., one quarter cycle is 0.25ns), and it is found that the second data is inconsistent with the first data, a simple test pattern is selected, such as all zeros, all ones, alternating 01 sequences, etc., the all-zero pattern is written to the address 0x0000 in the memory, and the data is read at a sampling interval of 0.5ns. Test the data line bit by bit, and change the data pattern of only one bit at a time. If it is found that the data of a certain bit is always inconsistent, the data line corresponding to the bit may be faulty.

[0120] Use the same test pattern, but test each address one by one. If the data on a certain address is always inconsistent, there may be a fault in that address line. Record the specific location of the fault (for example, data line DQ[7], address line A

[10] ).

[0121] Through the above steps, the specific data line or address line fault can be gradually located, thus helping to determine the problem in the memory chip. This step-by-step location method can effectively narrow the scope of the fault and ultimately find the root cause of the problem.

[0122] Reference Figure 5 In another possible implementation,

[0123] In the step S300, the third data is written into each DIE to be tested at the corresponding actual sampling interval, the data in the DIE to be tested is read at the actual sampling interval to obtain fourth data, and the fault of the data line or address line is located according to the third data and the fourth data, wherein the third data includes 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF; the step S300 also includes steps S310 to S330:

[0124] Step S310, writing one of 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, reading the data of the second storage space to obtain the fourth data, and comparing each data bit in the fourth data with each data bit in the third data;

[0125] Step S320, if the fourth data is inconsistent with the third data, find out the data bits with differences, that is, the storage unit with errors; if the fourth data is consistent with the third data, write the other of 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0126] Step S330, if the fourth data is inconsistent with the third data, find out the data bits with differences, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, diagnose the first row address line as normal.

[0127] Since the internal structure of DRAM (Dynamic Random Access Memory) is composed of a series of storage units (cells), these cells are usually arranged in a matrix. Each storage cell can only store one bit (0 or 1). Each storage cell of DRAM is usually composed of a transistor and a capacitor. The capacitor is used to store charge, representing the data bit (0 or 1). The transistor is used to control the charging and discharging of the capacitor to realize the reading and writing operations of data. In order to access these storage cells, DRAM uses address lines and data lines to specify and transmit data. The storage cells of DRAM are arranged in a two-dimensional matrix to form a row (Row) and column (Column) structure. This matrix structure makes it possible to uniquely determine the location of a storage cell by row address and column address.

[0128] Among them, the address line is used to specify the location of the memory cell to be accessed. The address lines are divided into row address lines and column address lines. The row address line is used to select the row where the memory cell is located, and the column address line is used to select the column where the memory cell is located. Through the combination of row address lines and column address lines, the location of a memory cell can be uniquely determined. For example, a matrix with 8 rows and 8 columns requires 3 row address lines and 3 column address lines (because 2 3 =8).

[0129] The data line is used to transmit data. In a read operation, the data line transmits data from the storage unit to the external circuit; in a write operation, the data line transmits data from the external circuit to the storage unit.

[0130] In this embodiment, the third data includes first test data and second test data, wherein the second test data is the inverse code of the first test data. In order to detect the integrity and independence of the data line and the address line, the first test data is first written, and then the inverse code of the first test data, i.e., the second test data, is written, such as 0x00000000 and 0xFFFFFFFF, to ensure that each data line can correctly transmit 0 and 1. If a data line cannot correctly transmit 0 or 1, this will be detected immediately. For example, if 0x00000000 is written and 0x00000001 is read back, it means that a data line may be short-circuited with other data lines.

[0131] In addition, by writing 0x00000000 and 0xFFFFFFFF to different addresses, you can ensure the correctness of the address line. For example, if you write 0x00000000 to address 0x0000, and then write 0xFFFFFFFF to address 0x0001, you should get 0x00000000 and 0xFFFFFFFF when reading back the data. If the data read back is inconsistent, it means that the address line may be wrong.

[0132] Reference Figure 6In another possible implementation,

[0133] In the step S300, the third data is written to each of the DIEs to be tested at the corresponding actual sampling interval, the data in the DIEs to be tested are read at the actual sampling interval to obtain fourth data, and the fault of the data line or the address line is located according to the third data and the fourth data, wherein the third data includes 0xAAAAAAAAAAAAAAAA and 0x55555555555555555; the step S300 also includes steps S340 to S360:

[0134] S340, write one of 0xAAAAAAAAAAAAAAAA and 0x55555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0135] S350, if the fourth data is inconsistent with the third data, find out the data bits with differences, that is, the storage units with errors; if the fourth data is consistent with the third data, write the other of 0xAAAAAAAAAAAAAAAA and 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0136] S360, if the fourth data is inconsistent with the third data, find out the data bits with differences, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, diagnose the first row address line as normal.

[0137] In this embodiment, the third data includes first test data and second test data, wherein the second test data is the inverse code of the first test data. In order to detect the integrity and independence of the data line and the address line, the first test data is first written, and then the inverse code of the first test data, i.e., the second test data, is written, such as 0xAAAAAAAAAAAAAAAA and 0x55555555555555555, so as to detect the short circuit or interference between the data lines. If there is a short circuit between the data lines, the data read back after writing 0x00000000 may contain some 0s that are mistakenly read as 1s, and vice versa.

[0138] The following is an explanation using an 8-bit data line and a die with an address range from 0 to 7:

[0139] 0xAAAAAAAAAAAAAAAA is represented in binary as:

[0140] 101010101010101010101010101010101010101010101010101010101010101010101010.

[0141] 0x555555555555555 is represented in binary as:

[0142] 01010101010101010101010101010101010101010101010101010101010101010101010101.

[0143] If a short circuit occurs between two adjacent data lines, the written data may affect each other between the two lines, resulting in data errors. If there is electromagnetic interference between two adjacent data lines, the written data may be read or written incorrectly.

[0144] Detection steps

[0145] 1. Write alternate mode:

[0146] Write an alternating pattern of 0s and 1s (0xAAAAAAAAAAAAAAAA) to a certain address range of memory.

[0147] Write an alternating 1 and 0 pattern (0x55555555555555555) to another address range of memory.

[0148] 2. Read back the data:

[0149] Data is read back from an address range where an alternating pattern of 0s and 1s is written.

[0150] Data is read back from an address range where an alternating pattern of 1s and 0s is written.

[0151] 3. Verify data:

[0152] Compare the read data with the written data to see if they are consistent.

[0153] If the data read back is inconsistent with the data written, it may indicate a short circuit or interference problem.

[0154] Specific Examples

[0155] Assume we have an 8-bit data line with addresses ranging from 0 to 7.

[0156] 1. Write an alternating pattern of 0s and 1s:

[0157] Data written to address 0: 0xAAAAAAAA (binary: 10101010).

[0158] Data written to address 1: 0xAAAAAAAA (binary: 10101010).

[0159] Data written to address 2: 0xAAAAAAAA (binary: 10101010).

[0160] Data written to address 3: 0xAAAAAAAA (binary: 10101010).

[0161] 2. Write an alternating 1 and 0 pattern:

[0162] Data written to address 4: 0x55555555 (binary: 01010101).

[0163] Data written to address 5: 0x55555555 (binary: 01010101).

[0164] Data written to address 6: 0x55555555 (binary: 01010101).

[0165] Data written to address 7: 0x55555555 (binary: 01010101).

[0166] 3. Read back the data:

[0167] Read back data from address 0: 10101010.

[0168] Read back data from address 1: 10101010.

[0169] Read back data from address 2: 10101010.

[0170] Read back data from address 3: 10101010.

[0171] Read back data from address 4: 01010101.

[0172] Read back data from address 5: 01010101.

[0173] Read back data from address 6: 01010101.

[0174] Read back data from address 7: 01010101.

[0175] 4. Verify data:

[0176] Compare the read data with the written data to see if they are consistent.

[0177] If the data read back is inconsistent with the data written, it may indicate a short circuit or interference problem.

[0178] Analysis results Short circuit detection: If a short circuit occurs between adjacent data lines, the written data may affect each other between the two lines. For example, if a short circuit occurs between data line 0 and data line 1, writing 10101010 may become 11111111 or 00000000.

[0179] Interference detection: If there is electromagnetic interference between adjacent data lines, the written data may be read or written incorrectly. For example, writing 10101010 may read back 10101011 or 10101000.

[0180] In this way, it can help effectively detect and locate short circuits and interference problems between data lines.

[0181] In this embodiment, writing opposite data patterns can cover more test scenarios and ensure that all parts of the memory are fully tested. For example, writing 0x00000000 and 0xFFFFFFFF can detect all 0s and all 1s, while writing 0xAAAAAAAA and 0x55555555 can detect alternating patterns.

[0182] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the diagnostic method of DIE data line and address line faults of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0183] This application also provides a DIE data line and address line fault test system, please refer to Figure 7 The DIE data line and address line fault test system includes: a host computer, a test board and at least one probe card board.

[0184] Among them, the host computer is communicatively connected with the test board and is used to send pattern vector test program, tested DIE specification parameters and test start / reset instructions to the test board.

[0185] The test board is used to receive a pattern vector test program, a DIE specification parameter under test, and a test start / reset instruction, and is used to output a timing bus signal for driving the DRAM to a probe card board according to the pattern vector test program and the DIE specification parameter under test.

[0186] The probe card board receives the timing bus signal of the driving DRAM, and is used to perform DRAM bus timing training and calibration and read and write pattern vector testing on the DIE.

[0187] In some embodiments, the test board is further used to cache the test data read by the probe card board in the read operation and send it to the host computer. The host computer is used to receive the test data, perform algorithm analysis, locate the address line or data line fault of the DIE, and obtain the test result.

[0188] In some embodiments, the test board includes a control unit, a functional test unit, an interface adapter unit, and a power adapter unit.

[0189] Among them, the control unit is communicatively connected to the host computer and electrically connected to the functional test unit, and is used to receive the pattern vector test program, configuration parameters, test start instructions or test reset instructions issued by the host computer and issue them to the functional test unit.

[0190] The functional test unit is electrically connected to the interface adapter unit, and is used to execute the pattern vector test program, parameter configuration, test start instruction or test reset instruction interactively issued by the control unit, and output the timing bus signal driving the DRAM to the interface adapter unit.

[0191] The functional test unit caches the test data read in the probe card reading operation and sends it to the host computer through the interface adapter unit and the control unit.

[0192] The interface adapter unit is electrically connected to the probe card board, and is used for converting the signals and instructions generated by the functional test unit and sending them to the probe card board.

[0193] The power adapter unit is electrically connected to the function test unit and the interface adapter unit, and is used to supply power to the function test unit and the interface adapter unit, and provide the required core voltage and IO interface standard voltage.

[0194] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for diagnosing DIE data line and address line faults, used to test multiple DIEs to be tested, characterized in that: The method includes: Pre-writing and / or pre-reading the plurality of DIEs to be tested to determine an actual sampling interval of read and write data of each of the DIEs to be tested; Acquire a pattern vector test program, wherein the pattern vector test program is used to generate third data for testing a fault; The third data is written into each DIE to be tested at the corresponding actual sampling interval, the data in the DIE to be tested is read at the actual sampling interval to obtain fourth data, and the fault of the data line or address line is located according to the third data and the fourth data.

2. The method according to claim 1, characterized in that The step of pre-writing and / or pre-reading the plurality of DIEs to be tested to determine the actual sampling interval of the read and write data of each DIE to be tested comprises: Writing first data into a first storage space of the DIE to be tested at a first sampling interval in response to a write enable signal; In response to a read enable signal, reading the data in the DIE to be tested at a first sampling interval to obtain second data; When the second data is inconsistent with the first data, the first sampling interval is adjusted and then the step of writing the first data into the first storage space of the DIE to be tested at the first sampling interval in response to the write enable signal is performed; When the second data is consistent with the first data, the first sampling interval is recorded as the actual sampling interval.

3. The method according to claim 2, characterized in that When the second data is inconsistent with the first data, the step of adjusting the first sampling interval and then executing the step of writing the first data into the first storage space of the DIE to be tested at the first sampling interval in response to the write enable signal further includes: The value of the first sampling interval is increased by a preset step value.

4. The method according to claim 3, characterized in that In the step of adjusting the first sampling interval including increasing the value of the first sampling interval by a preset step value, The value of the first sampling interval is less than a quarter of a clock period.

5. The method according to claim 4, characterized in that When the value of the first sampling interval is greater than a quarter of a clock cycle, and the second data is inconsistent with the first data, the step of pre-writing and / or pre-reading the plurality of DIEs to be tested to determine an actual sampling interval of read and write data of each of the DIEs to be tested comprises: A fault of a data line or an address line corresponding to the first storage space is located according to the first data and the second data.

6. The method according to claim 1, characterized in that The third data includes 0x00000000000000000 and 0xFFFFFFFFFFFFFFFF; The step of writing the third data to each DIE to be tested at the corresponding actual sampling interval, reading the data in the DIE to be tested at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or the address line according to the third data and the fourth data comprises: Write one of 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data; If the fourth data is inconsistent with the third data, find out the data bits with differences, that is, the storage unit with errors; if the fourth data is consistent with the third data, write the other of 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data; If the fourth data is inconsistent with the third data, the data bits with differences are found, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, the first row address line is diagnosed as normal.

7. The method according to claim 6, characterized in that The third data includes 0xAAAAAAAAAAAAAAAA and 0x55555555555555555; The step of writing the third data to each DIE to be tested at the corresponding actual sampling interval, reading the data in the DIE to be tested at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or the address line according to the third data and the fourth data comprises: write one of 0xAAAAAAAAAAAAAAAA and 0x55555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data; If the fourth data is inconsistent with the third data, find out the data bits with differences, that is, the storage unit with errors; if the fourth data is consistent with the third data, write the other of 0xAAAAAAAAAAAAAAAA and 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data; If the fourth data is inconsistent with the third data, the data bits with differences are found, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, the first row address line is diagnosed as normal.

8. A DIE data line and address line fault testing system, characterized in that: include: A host computer, which is in communication connection with the test board and is used to send a pattern vector test program, specification parameters of the DIE to be tested, and a test start / reset instruction to the test board; The test board receives the pattern vector test program, the DIE specification parameters under test and the test start / reset instruction, and is used to output the timing bus signal of driving DRAM to the probe card board according to the pattern vector test program and the DIE specification parameters under test; At least one probe card board, the probe card board receives the timing bus signal of the driving DRAM, and is used to perform DRAM bus timing training and calibration and read and write pattern vector testing on the DIE.

9. The DIE data line and address line fault testing system as claimed in claim 8, characterized in that: The test board is also used to cache the test data read by the probe card board in the read operation and send it to the host computer; The host computer is used to receive the test data, perform algorithm analysis, locate the address line or data line fault of the DIE, and obtain the test result.

10. The DIE data line and address line fault testing system as claimed in claim 9, characterized in that: The test board comprises: A control unit, the control unit is communicatively connected to the host computer and electrically connected to the functional test unit, and is used to receive the pattern vector test program, configuration parameters, test start instructions or test reset instructions issued by the host computer and issue them to the functional test unit; Interface switching unit; A functional test unit, the functional test unit is electrically connected to the interface adapter unit, and is used to execute the pattern vector test program, parameter configuration, test start instruction or test reset instruction interactively issued by the control unit, and output a timing bus signal for driving the DRAM to the interface adapter unit, And the test data read in the probe card board reading operation is cached and sent to the host computer through the interface adapter unit and the control unit; The interface adapter unit is electrically connected to the probe card board and is used to convert the signals and instructions generated by the functional test unit and send them to the probe card board. A power adapter unit is electrically connected to the function test unit and the interface adapter unit, and is used to supply power to the function test unit and the interface adapter unit, and provide the required core voltage and IO interface standard voltage.

Images