Chip type NTC (Negative Temperature Coefficient) thermistor structure capable of preventing electrode flanging and preparation method of chip type NTC thermistor structure

Abstract

The invention discloses a chip type NTC (Negative Temperature Coefficient) thermistor structure for preventing an electrode from flanging and a preparation method of the chip type NTC thermistor structure. The chip type NTC thermistor structure comprises a substrate, a first conductive layer formed on a first surface of the substrate, and a second conductive layer formed on a second surface of the substrate, wherein the first surface is close to a carrier plate, so that the first conductive layer is in contact with the carrier plate, and the second surface is opposite to the first surface; the first conductive layer is divided into a plurality of blocks with the same size by a first cutting block; the first cutting block is arranged to be not covered by a conductive object, so that the substrate is exposed, and the first cutting block is used as a cutting reference position, so that the substrate is cut by aiming at the first cutting block to form a plurality of single bodies; the area of the block on each single body is smaller than the area of the surface where the block is located and is within the preset percentage range of the area of the surface where the block is located.

Description

Technical Field

[0001] The invention relates to a chip-type NTC thermistor structure capable of preventing electrode flanging and a preparation method thereof, belonging to the technical field of electronic components. Background Art

[0002] The basic process of chip-type NTC (Negative Temperature Coefficient) thermistor is to make a ceramic substrate, print, fire or sputter a conductive layer on the upper and lower sides of the substrate, and then use a blade (such as a diamond blade) to cut it to form a monomer, which includes a ceramic body and upper and lower electrodes located on the upper and lower sides of the ceramic body.

[0003] In the existing design, when the blade is cutting, it is difficult to completely grind off the conductive layer at the cutting position; especially the conductive layer on the lower surface of the substrate is in contact with the softer carrier board, and the conductive layer has good ductility, resulting in the conductive layer at the cutting position cannot be completely ground off, and is connected to the monomer electrode in the form of burrs or flanges, causing the product to show the phenomenon of electrode flanges. These burrs or flanges will cause the following problems: ① Irregular product appearance leads to dimensional tolerance; ② Too long flange debris will cause short circuit; ③ The product cannot slide smoothly on the guide rail during electrical testing, and frequent jamming occurs; ④ Due to the height difference of the product when placing the plate and assembling the material, the material falls off; ⑤ The product cannot be parallel to the pad during welding, resulting in product deviation during reflow soldering. Therefore, it is necessary to improve the existing design. Summary of the invention

[0004] The main purpose of the present invention is to provide a chip-type NTC thermistor structure that prevents electrode flanging, so as to solve the problems existing in the above-mentioned prior art.

[0005] To achieve the above object, the present invention proposes the following technical solutions:

[0006] A chip-type NTC thermistor structure for preventing electrode flanging comprises: a substrate, a first conductive layer formed on a first surface of the substrate, and a second conductive layer formed on a second surface of the substrate; wherein the first surface is a surface close to a carrier so that the first conductive layer contacts the carrier, and the second surface is a surface opposite to the first surface; the first conductive layer is divided into a plurality of blocks of the same size by a first cutting block; the first cutting block is arranged to be uncovered without conductive objects and expose the substrate, and is used as a cutting reference position to achieve: after the substrate is cut to form a plurality of monomers in alignment with the first cutting block, the area of ​​the block on each monomer is smaller than the area of ​​the surface where the block is located and is within a preset percentage range of the area of ​​the surface where the block is located.

[0007] Furthermore, a circle of the edge of the first surface of the substrate is configured to be uncovered without conductive objects so that the substrate is exposed and connected to the first scribe block.

[0008] Furthermore, the second conductive layer is divided into a number of blocks of the same size by a second cutting block, and the second cutting block has the same structure as the first cutting block and is arranged opposite to each other; the second cutting block is used to achieve: after the substrate is cut along the second cutting block and aligned with the first cutting block to form a number of monomers, the area of ​​the block on each monomer is smaller than the surface area of ​​the block and is within a preset percentage range of the surface area of ​​the block.

[0009] Furthermore, a circle of the edge of the second surface of the substrate is configured to be uncovered without conductive objects so that the substrate is exposed and connected to the second scribing block.

[0010] Furthermore, the area of ​​the block on each monomer is less than 99% of the area of ​​the surface where the block is located and greater than 60% of the area of ​​the surface where the block is located.

[0011] Furthermore, the first conductive layer is formed by electroplating or printing a conductive layer on the first surface of the substrate according to a first preset pattern, and the plurality of blocks on the first surface together constitute the first preset pattern.

[0012] Furthermore, the first conductive layer is formed by electroplating or printing a conductive layer on the second surface of the substrate according to a second preset pattern, and the plurality of blocks on the second surface together constitute the second preset pattern.

[0013] The beneficial effects of the technical solution of the present invention are embodied in: the first conductive layer in contact with the carrier board is separated into several blocks of the same size by using the first cutting block covered with no conductive material, and when cutting, the first cutting block is aligned with the cutting block from the second surface of the substrate, so that each block forms a surface electrode of a single body, and due to the existence of the first cutting block, when the blade cuts to the first surface of the substrate, it will not cut the first conductive layer, so no excess conductive material in the form of burrs or flanges will be formed, thereby solving the problem of dimensional tolerance caused by electrode flange, the problem of material jamming on the guide rail during testing, the problem of easy deviation during welding, the problem of easy material falling during plate swinging and assembly and material taking, and the problem of short circuit in the circuit due to too long flange debris.

[0014] In a further technical solution of the present invention, the second conductive layer on the second surface opposite to the first surface is also divided into several blocks by a second cutting block having the same structure and function. Since the second cutting block is arranged opposite to the first cutting block, when cutting, the second cutting block is cut opposite to the first cutting block, and the upper and lower surfaces of the obtained monomer each have one of the blocks, and each block forms a surface electrode on the surface where it is located. Due to the existence of the second cutting block, the formation of burrs or flanging when cutting the second conductive layer can be further avoided.

[0015] In a further technical solution of the present invention, the setting of the cutting blocks makes the area of ​​each block on the monomer formed by cutting smaller than 99% of the surface area of ​​the block, which can better solve the problem of flanging; at the same time, the area of ​​each block is larger than 60% of the surface area of ​​the block, which can avoid affecting the welding ability and electrical performance due to the small surface electrode.

[0016] The present invention also proposes a method for preparing the aforementioned anti-electrode flanging chip-type NTC thermistor structure, comprising: forming the first conductive layer on the first surface of the substrate according to a first predetermined pattern, and forming the second conductive layer on the second surface of the substrate according to a second predetermined pattern; wherein the first predetermined pattern is an array composed of a plurality of blocks of the same size, and the area on the first surface of the substrate not covered by the first predetermined pattern forms the first cut block. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a top view of the single structure of a chip-type NTC thermistor according to Embodiment 1 of the present invention;

[0018] Figure 2 It is a front view of the single structure of the chip-type NTC thermistor of Example 1 of the present invention;

[0019] Figure 3 It is a side view of the single structure of the chip-type NTC thermistor according to the first embodiment of the present invention.

[0020] Figure 4 is a top view of the single structure of a chip-type NTC thermistor according to Embodiment 2 of the present invention;

[0021] Figure 5 It is a front view of the structure of a single chip NTC thermistor according to Embodiment 2 of the present invention;

[0022] Figure 6 It is a side view of the single structure of a chip-type NTC thermistor according to Embodiment 2 of the present invention.

[0023] Figure 7 This is a flow chart of preparing a chip-type NTC thermistor monomer by using a lamination process in an embodiment of the present invention;

[0024] Figure 8 The present invention is a flowchart of preparing a chip-type NTC thermistor monomer by using a blank making process in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods and examples. It should be understood that the purpose of providing the examples is only for illustration and not for any limitation. In addition, the spatial orientation words such as "upper", "lower", "left", "right", "top", "bottom" etc. used in the description of the technical solution of the present invention are for the convenience of describing the relative position relationship between the components of the product, and do not mean that the product has only the orientation shown in the figure. In actual use, as the product orientation is different (for example, rotated 90 degrees or other orientations), the spatial description used to describe its orientation should also be interpreted in a similar manner.

[0026] In addition, terms such as "first" and "second" are only used to distinguish components. It should be understood that these components should not be limited by such terms. They themselves do not mean that these elements have the aforementioned ordinal numbers, nor do they represent the arrangement order of one component and another component or the order of the manufacturing method.

[0027] Example 1

[0028] The present embodiment provides a chip-type NTC thermistor structure for preventing electrode flanging, including a substrate, a first conductive layer formed on the first surface of the substrate, and a second conductive layer formed on the second surface of the substrate; wherein the first surface is a surface close to the carrier so that the first conductive layer contacts the carrier, and the second surface is a surface opposite to the first surface. Based on this understanding, the first surface is the lower surface of the substrate, and the second surface is the upper surface of the substrate. In this embodiment, the first conductive layer on the upper surface of the substrate presents a first predetermined pattern, and the first predetermined pattern is an array composed of a plurality of blocks of the same size. The area not covered by the first predetermined pattern forms a first cutting block. Based on this understanding, the first conductive layer formed on the upper surface of the substrate is divided into a plurality of blocks of the same size by the first cutting block. Since the first cutting block is not covered by a conductive object and the substrate is exposed, when cutting, the blade is cut from the upper surface to the first cutting block. When cutting to the lower surface, due to the existence of the first cutting block, the blade will not touch the first conductive layer, and there will be no burr and flanging problems caused by the blade being unable to completely grind when cutting the conductive layer as in the prior art. Furthermore, each of the blocks is a surface electrode of the lower surface of the monomer formed by cutting, and the area of ​​the block is less than 99% of the area of ​​the lower surface of the monomer and greater than 60% of the area of ​​the lower surface of the monomer.

[0029] In this embodiment, according to the above design, the top view, front view and side view of the monomer formed by cutting are respectively as follows: Figure 1 , Figure 2 and Figure 3 As shown, each chip-type NTC thermistor monomer includes a central NTC thermistor ceramic body 1, an electrode 1a on the upper surface of the ceramic body 1, and an electrode 1b on the lower surface. In this embodiment, the electrode 1b on the lower surface is a block.

[0030] Preferably, the edge of the lower surface of the substrate is not covered by any conductive material, the substrate is exposed, and is connected to the first scribing block.

[0031] Example 2

[0032] The chip-type NTC thermistor structure with anti-electrode flanging provided in this embodiment is the same as that in embodiment 1 in that the lower surface of the substrate has the same electrode pattern and flanging block as that of the lower surface, and the flanging blocks on the upper and lower surfaces are arranged opposite to each other. When cutting, the blade cuts from the flanging block on the upper surface to the flanging block on the lower surface, so that the blade will neither touch the electrode layer on the lower surface of the substrate nor the electrode layer on the upper surface of the substrate. Not only will the lower surface electrode layer in contact with the carrier not have burrs and flanging, but even the upper surface electrode layer can completely avoid burrs and flanging. The surface electrode on the upper surface of the cut monomer is a block of the upper surface electrode layer of the substrate, and the surface electrode on the lower surface of the monomer is a block of the lower surface electrode layer of the substrate. In addition, the surface electrodes on the upper and lower surfaces of the monomer both meet the requirement that the electrode area is less than 99% of the surface area and greater than 60% of the surface area.

[0033] In this embodiment, according to the above design, the top view, front view and side view of the monomer formed by cutting are respectively as follows: Figure 4 , Figure 5 and Figure 6 As shown, each chip-type NTC thermistor unit includes a central NTC thermistor ceramic body 1', an electrode 1a' on the upper surface of the ceramic body 1', and an electrode 1b' on the lower surface.

[0034] More preferably, in this embodiment, the edges of the upper and lower surfaces of the substrate are not covered with conductive materials, and the substrate is exposed and connected to the scribed blocks on the surface.

[0035] The following provides a method for preparing a chip-type NTC thermistor structure with anti-electrode flanging according to an embodiment of the present invention, wherein Example 3 is manufactured by a lamination process, and Example 4 is manufactured by a blanking process.

[0036] Example 3

[0037] In this embodiment, a lamination process is adopted, and the manufacturing process is as follows: Figure 7As shown, it includes: powder making, batching, casting, lamination, sintering, electrode preparation, cutting, appearance selection and electrical property sorting. The manufacturing process of the chip-type NTC thermistor with low resistance and high B value in this embodiment is as follows:

[0038] 1. Powder making: According to the chemical composition of Zn0.1Fe0.3Co1.5Mn1.1O4, use zirconium oxide balls and deionized water as the medium, mix by planetary ball mill for 4 hours, dry at 90℃, pre-sinter at 900℃ (keep warm for 4 hours), continue planetary ball milling for 5 hours, and dry at 90℃;

[0039] 2. Batching and casting: Mix the powder with solvent, adhesive and other materials into a slurry with a certain viscosity, and cast it into a sheet with a certain film thickness;

[0040] 3. Stacking: stack the sheets together according to the design;

[0041] 4. Sintering: Sintering according to the predetermined sintering temperature curve, the high temperature range is 1050 ~ 1250 ℃;

[0042] 5. Prepare electrodes: Electroplate or print electrodes (according to a preset pattern) on the sintered substrate by sputtering the base layer and then sinter it;

[0043] 6. Cutting: Cut the sintered BAR block along the cutting line;

[0044] 8. Appearance selection and electrical property sorting.

[0045] Example 4

[0046] In this embodiment, a blank making process is adopted, and the production process is as follows: Figure 8 As shown, it includes: powder making, blank making, sintering, slicing, electrode preparation, cutting, appearance selection and electrical property sorting. This embodiment realizes the manufacturing process of chip-type NTC thermistor with low resistance and high B value, and the specific steps are as follows:

[0047] 1. Powder making: According to the chemical composition of Zn0.1Fe0.3Co1.5Mn1.1O4, use zirconium oxide balls and deionized water as the medium, mix by planetary ball mill for 4 hours, dry at 90℃, pre-sinter at 900℃ (keep warm for 4 hours), continue planetary ball milling for 5 hours, and dry at 90℃;

[0048] 2. Blank making: statically press the powder into a certain shape;

[0049] 3. Sintering: Sintering according to the predetermined sintering temperature curve, the high temperature range is 1050~1250℃;

[0050] 4. Slicing: Slice the sintered ingot into substrates according to the designed thickness;

[0051] 5. Prepare electrodes: Electroplate or print electrodes (according to a preset pattern) on the sintered substrate by sputtering the base layer and then sinter it;

[0052] 6. Cutting: Cut the sintered BAR block along the cutting line;

[0053] 7. Appearance selection and electrical property sorting.

[0054] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art of the present invention, several equivalent substitutions or obvious variations can be made without departing from the concept of the present invention, and the performance or use is the same, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A chip-type NTC thermistor structure for preventing electrode flanging, characterized in that: include: A substrate, a first conductive layer formed on a first surface of the substrate, and a second conductive layer formed on a second surface of the substrate; wherein the first surface is a surface close to a carrier so that the first conductive layer contacts the carrier, and the second surface is a surface opposite to the first surface; The first conductive layer is divided into a number of blocks of the same size by a first cutting block; the first cutting block is set to be uncovered with no conductive material and expose the substrate, and is used as a cutting reference position to achieve: after the substrate is cut to form a number of monomers in alignment with the first cutting block, the area of ​​the block on each monomer is smaller than the surface area of ​​the block and is within a preset percentage range of the surface area of ​​the block.

2. The chip-type NTC thermistor structure according to claim 1, characterized in that: An edge of the first surface of the substrate is configured to be uncovered without conductive objects so that the substrate is exposed and connected to the first scribe block.

3. The chip-type NTC thermistor structure according to claim 1, characterized in that: The second conductive layer is divided into a number of blocks of the same size by a second cutting block, and the second cutting block has the same structure as the first cutting block and is arranged opposite to each other; the second cutting block is used to achieve: after the substrate is cut along the second cutting block and aligned with the first cutting block to form a number of monomers, the area of ​​the block on each monomer is smaller than the surface area of ​​the block and is within a preset percentage range of the surface area of ​​the block.

4. The chip-type NTC thermistor structure according to claim 3, characterized in that: An edge of the second surface of the substrate is configured to be uncovered without conductive objects so that the substrate is exposed and connected to the second scribe block.

5. The chip-type NTC thermistor structure according to claim 1 or 3, characterized in that: The area of ​​the block on each monomer is less than 99% of the surface area where the block is located and greater than 60% of the surface area where the block is located.

6. The chip-type NTC thermistor structure according to claim 1, characterized in that: The first conductive layer is formed by electroplating or printing a conductive layer on the first surface of the substrate according to a first preset pattern, and the plurality of blocks on the first surface together constitute the first preset pattern.

7. The chip-type NTC thermistor structure according to claim 3, characterized in that: The first conductive layer is formed by electroplating or printing a conductive layer according to a second preset pattern on the second surface of the substrate, and the plurality of blocks on the second surface together constitute the second preset pattern.

8. The method for preparing a chip-type NTC thermistor structure with anti-electrode flanging according to any one of claims 1 to 7, characterized in that: include: The first conductive layer is formed on the first surface of the substrate according to a first predetermined pattern, and the second conductive layer is formed on the second surface of the substrate according to a second predetermined pattern; wherein the first predetermined pattern is an array consisting of a plurality of blocks of the same size, and the area on the first surface of the substrate not covered by the first predetermined pattern forms the first cutting block.

9. The method for preparing a chip-type NTC thermistor structure with anti-electrode flanging according to claim 8, characterized in that: The second predetermined pattern is an array consisting of a plurality of blocks of the same size, and the area on the second surface of the substrate not covered by the second predetermined pattern forms a second scribing street block.

10. The method for preparing a chip-type NTC thermistor structure with anti-electrode flanging according to claim 8, characterized in that: The process for manufacturing the substrate is a lamination process or a blank making process.

Images