TMV fan-out particle, packaging method thereof and application of TMV fan-out particle in multi-chip packaging structure
Through TMV fan-out particles and its packaging method, the problem of excessively long wire length in multi-die stacking packages is solved, miniaturization and performance improvement of multi-chip vertical stacking packages is achieved, and the heat dissipation ability and electrical performance of the package are improved.
Patent Information
- Application Number
- CN202411508264.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-26
- Publication Date
- 2025-02-14
AI Technical Summary
In the existing multi-die stacking packaging technology, excessive wire length leads to large packaging thickness and poor heat dissipation capabilities. The FC+WB hybrid interconnection process is costly and technically difficult, which limits the packaging miniaturization and performance improvement.
TMV fan-out particles and their packaging methods are adopted to realize multi-chip vertical stacking packaging through wafer-level packaging and rewiring layer processes, eliminate top-layer wiring, and use FC technology to perform short-distance interconnection.
The package size and thickness are reduced, the electrical performance and heat dissipation ability are improved, and the injection molded punching and signal quality reduction caused by long wires is avoided, while reducing costs.
Smart Images
Figure CN119446932A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor packaging technology, electronic chip packaging technology, multi-die stacking packaging, wafer-level packaging, substrate packaging and other technologies, and specifically to a multi-chip packaging (WB+FC hybrid interconnect packaging) method and structure that reduces packaging size, improves electrical performance, and improves heat dissipation capability. Background Art
[0002] Electronic packaging technology is developing rapidly. In order to adapt to the development trend of electronic miniaturization, integration and systematization, packaging technology is gradually developing towards multi-chip die stacking packaging, so as to integrate chips with different functions into one package. Multi-die stacking packaging MCM (Multi-chip module) is now very mature and widely used in various product fields. The two most common packaging forms of multi-die vertical stacking packaging are: pure WB wire bonding interconnection and FC+WB hybrid interconnection. Figure 1 A size comparison diagram of a pure WB wire bonding interconnect packaging structure and a FC+WB hybrid interconnect packaging structure. In the figure, A represents a pure WB wire bonding interconnect packaging structure, and B to E represent four types of WB+FC hybrid interconnect packaging structures, respectively.
[0003] Pure WB bonding interconnection.
[0004] like Figure 1 As shown in the pure WB wire bonding interconnection packaging structure marked A in FIG, three dies (first die 1, second die 2, and third die 3) all use the WB wire bonding process to form signal interconnections on the substrate. Each die needs to pull out the WB wire and bond it to the bottom substrate 4, which will lead to some obvious disadvantages, such as:
[0005] 1) The bonding wire length of the second die2 / third die3 on the upper layer is too long. In the subsequent injection molding process, the bonding wire is easily bent, resulting in collision and short circuit between wires.
[0006] 2) Longer bonding wires affect the efficient communication between the first die1 and the second die2, and between the first die1 and the third die3. Especially for high-speed and high-frequency signals, the bonding wires will bring obvious parasitic inductance and capacitance, which seriously affects the signal transmission quality.
[0007] 3) The wire bonding has a certain arc height, which makes the package thickness large, which is not conducive to heat dissipation and package miniaturization.
[0008] 4) All three dies are wired to the substrate, which requires multiple dense circles of gold fingers for wire bonding to be distributed on the substrate, making it impossible to reduce the package size, which is not conducive to reducing costs.
[0009] FC+WB hybrid interconnection.
[0010] like Figure 1 As shown in the four FC+WB hybrid interconnect packaging structures marked B, C, D and E respectively, the three dies use both WB wire bonding process and flip chip process. The die using the WB process must face up, and the die using the FC process must face down. For two adjacent dies, either both use WB, or one uses WB and the other uses FC, but it is impossible to use FC for both. If two adjacent dies use FC, they must go through the through silicon via (TSV) process, but the TSV process is expensive and technically difficult, so it has not been widely popularized and applied, and is only used on a small scale in some cutting-edge industries such as artificial intelligence / 5G communications.
[0011] According to the above analysis, the FC+WB combination of the three dies can only be obtained as follows Figure 1 The four WB+FC hybrid interconnection package structures are marked with B~E. The characteristics of each of the four hybrid interconnection forms B~E are as follows.
[0012] In the package structure marked with B, the second die2 in the middle layer uses the FC process, and the other two dies can only use the WB process. The wire bonding of the third die3 is too long, which leads to the following disadvantages: it is easy to cause injection molding wire punching, affects the quality of high-speed and high-frequency signal transmission, and the package thickness cannot be reduced. However, since the second die2 does not need wire bonding, the package size and thickness are still reduced compared to the pure WB wire bonding interconnection package structure marked with A.
[0013] In the package structure marked C, the first die1 on the bottom layer uses the FC process, and the other two dies use the WB process. The wire bonding of the second die2 and the third die3 is too long, which leads to the following disadvantages: it is easy to cause injection molding wire punching, affects the quality of high-speed and high-frequency signal transmission, and the package thickness cannot be reduced. However, since the first die1 does not need wire bonding, the package size is reduced compared to the pure WB wire bonding interconnection package structure marked A.
[0014] In the package structure marked D, the top third die3 uses the FC process, and the other two dies use the WB process. The wire bonding of the second die2 is too long, which leads to the following disadvantages: it is easy to cause injection molding wire punching, affects the quality of high-speed and high-frequency signal transmission, and the package thickness cannot be minimized. However, since the third die3 does not need wire bonding, the package size and thickness are reduced compared to the pure WB wire bonding interconnection package structure marked A. And compared to the package structures marked B and C, the package thickness can be further reduced.
[0015] In the package structure marked E, the bottom die (i.e. the first die1) and the top die (i.e. the third die3) use the FC process, and only the second die2 uses the WB process. The wire bonding of the second die2 is too long, resulting in the following disadvantages: it is easy to cause injection molding wire punching, affects the quality of high-speed and high-frequency signal transmission, and the package thickness cannot be minimized. However, since the first die1 and the third die3 do not need wire bonding, the package size and thickness are reduced compared to the pure WB wire bonding interconnection package structure marked A. The package thickness is slightly larger than the package structure marked D, but smaller than the package structures marked B and C. The most important thing is that the package size can be further reduced compared to the package structures marked B, C and D. However, the cost of the package structure solution marked E will be more expensive than the package structures marked B, C and D, because two dies are FC, but the benefits obtained are still relatively limited. Summary of the invention
[0016] In order to solve the above problems existing in the prior art, the present invention proposes TMV fan-out particles and a packaging method thereof, as well as the application of the particles in a multi-chip packaging structure, which can ultimately obtain a multi-chip packaging structure with reduced wire bonding length, reduced packaging size, reduced packaging thickness, improved electrical performance, and improved packaging heat dissipation capability.
[0017] By means of the process method of the present invention, a multi-chip vertically stacked packaging structure is obtained, which can solve many disadvantages of the above pure WB interconnection and FC+WB mixed interconnection packaging.
[0018] The technical solution of the present invention is specifically as follows.
[0019] A packaging method for TMV fan-out particles, the packaging method being a wafer-level packaging method, comprising the following steps:
[0020] 1) Electroplating and growing through-molded vias (TMVs) on a first carrier; the first carrier has the same size as the wafer;
[0021] 2) Cutting the wafer containing the die, and attaching each of the cut die to the first carrier with the back side facing upward; the plastic sealing through hole corresponding to each die is located around the die;
[0022] 3) performing wafer-level injection molding on the first carrier to completely cover all the chips and plastic-sealed through holes to obtain a reconstructed wafer;
[0023] 4) Grinding the reconstructed wafer to expose the back side of each wafer and the plastic sealing through-hole;
[0024] 5) performing a redistribution layer (RDL) process on the back side of the reconstructed wafer to obtain a second redistribution layer; making a pad on the top surface of the second redistribution layer, and conducting a through-molded via (TMV) through the second redistribution layer to the corresponding pad;
[0025] For a chip and corresponding plastic-encapsulated through holes, each plastic-encapsulated through hole is redistributed to corresponding pads on the top surface of the second redistribution layer through the second redistribution layer, and these pads are located at the center above the chip;
[0026] These redistributed metal pads to the center will be used for flip-chip FC interconnection with the third die3.
[0027] 6) removing the first carrier, turning over the reconstructed wafer, and attaching the top surface of the second redistribution layer to the second carrier with the top surface facing downward to expose the front side of the wafer;
[0028] 7) Implementing a redistribution layer (RDL) process on the other side of the reconstructed wafer (i.e., the side where the front side of the wafer is located) to obtain a first redistribution layer; redistributing the pads on the front side of the wafer through the first redistribution layer and connecting them to the corresponding TMVs;
[0029] 8) Making a pad on the top surface of the first redistribution layer, and then making a bump on the pad;
[0030] 9) Remove the second carrier and attach the reconstructed wafer to the electronic grade tape (i.e., blue film) with the back of the wafer facing downward;
[0031] 10) Cutting and reconstructing the wafer to obtain the final single TMV fan-out particle;
[0032] The top surface of the second redistribution layer refers to a side away from the wafer, and the top surface of the first redistribution layer refers to a side away from the wafer.
[0033] In the prior art wafer removal and loading process, after wafer cutting, the blue film is half-cut through and the wafer is cut through into a single wafer, but the wafer is attached and carried on the half-cut blue film, and the whole is still a large round wafer. To remove the wafer, there is a pin under the blue film to push it up, and there is a suction nozzle on the wafer to suck it up. These two actions are performed simultaneously, and the wafer is picked up by the suction nozzle and then attached to the substrate.
[0034] In this solution, it is similar to the cutting and taking of wafers. After the wafer is cut and reconstructed, a single TMV fan-out particle is attached and carried on the half-cut blue film, and the whole is still a large round piece. For taking, there is a pin under the blue film to push it up, and there is a suction nozzle on the single TMV fan-out particle to suck it up. These two actions are carried out simultaneously, and the single TMV fan-out particle is picked up by the suction nozzle and then attached to the substrate.
[0035] A TMV fan-out particle comprises a chip (die), a first redistribution layer (RDL), a second redistribution layer (RDL), a through-molded via (TMV) and a molding compound;
[0036] The front side of the chip is connected to the first redistribution layer, the back side of the chip is connected to the second redistribution layer, a plurality of through-molding vias (TMVs) are connected between the first redistribution layer and the second redistribution layer, each of the through-molding vias is located at the periphery of the chip, and the gaps between the first and second redistribution layers and the chip and the through-molding vias are filled with plastic molding compound;
[0037] The pad on the front side of the chip is connected to the corresponding through-molded via (TMV) through the first redistribution layer; the first redistribution layer is also connected to a pad on the side facing away from the chip, and the pad has a bump;
[0038] A pad is provided on a side of the second redistribution layer facing away from the wafer, and a through molded via (TMV) is connected to a corresponding pad through the second redistribution layer.
[0039] The TMV fan-out particles of the present invention can be used as a separate unit carrying a die in a chip, which is beneficial to reducing the structural size of the chip.
[0040] An FC+WB hybrid interconnect packaging structure includes a substrate, a first die, a second die and a third die stacked sequentially from bottom to top;
[0041] The second die has one or more pieces; the second die is a chip in a TMV fan-out particle, and the corresponding TMV fan-out particle has one or more pieces;
[0042] The back surface of the first die is connected to the top surface of the substrate, and the pad on the front surface of the first die is connected to the pad on the top surface of the substrate through a bonding wire;
[0043] The first structure: if there is one TMV fan-out particle and one or more third dies;
[0044] The bump of the first redistribution layer of the TMV fan-out particle is connected to the pad on the front side of the first die;
[0045] A third die is connected to the top of the TMV fan-out particle, or multiple third dies are connected in a flat pattern on the top of the TMV fan-out particle;
[0046] The connection structure between the third die and the TMV fan-out particle is as follows: the bump on the front side of the third die is connected to the pad of the second redistribution layer of the TMV fan-out particle;
[0047] The second structure: if there are multiple TMV fan-out particles stacked, and the third die has one or more pieces;
[0048] A third die is connected to the top of the top TMV fan-out particle, or multiple third dies are connected to the top of the top TMV fan-out particle in a flat pattern;
[0049] The connection structure between the third die and the TMV fan-out particle is as follows: the bump on the front side of the third die is connected to the pad of the second redistribution layer of the TMV fan-out particle;
[0050] The bump of the first redistribution layer of the bottom TMV fan-out particle is connected to the pad on the front side of the first die;
[0051] The bump of the first redistribution layer of each middle TMV fan-out particle is connected to the pad of the second redistribution layer of the TMV fan-out particle below it; the pad of the second redistribution layer of each middle TMV fan-out particle is connected to the bump of the first redistribution layer of the TMV fan-out particle above it.
[0052] For the top TMV fan-out particle: the bumps of the first redistribution layer are used to interconnect its own wafer die with the pads of the second redistribution layer of the TMV fan-out particle below it, and to interconnect the third die above it with the pads of the second redistribution layer of the TMV fan-out particle below it;
[0053] For each TMV fan-out particle in the middle: the bumps of the first redistribution layer are used to interconnect the wafer die of the chip itself with the pads of the second redistribution layer of the TMV fan-out particle below it, and are used to interconnect the bumps of the first redistribution layer of the TMV fan-out particle above it with the pads of the second redistribution layer of the TMV fan-out particle below it;
[0054] For the bottom TMV fan-out particle: the bumps of the first redistribution layer are used to interconnect its own wafer die with the pads of the first die below it, and are used to interconnect the bumps of the first redistribution layer of the TMV fan-out particle above it with the first die.
[0055] Solder balls are connected to corresponding pads on the bottom surface of the substrate.
[0056] A packaging method for an FC+WB hybrid interconnect packaging structure, comprising the steps of:
[0057] 2.1) Place the first die on the substrate with the front side facing upwards; then perform wire bonding from the first die to the substrate;
[0058] 2.2) If there is only one TMV fan-out particle, flip-chip the TMV fan-out particle onto the front side of the first die using a flip chip process;
[0059] If there are multiple TMV fan-out particles, the bottom TMV fan-out particle is flip-chip mounted on the front side of the first die using the flip chip process; then, other TMV fan-out particles are flip-chip mounted on the top of the bottom TMV fan-out particle using the flip chip process;
[0060] 2.3) Flip-chip the third die onto the top TMV Fan-out chip using the flip chip process;
[0061] 2.4) Overall injection molding, surface silk screen printing, ball planting, and finally cutting into single pieces to form the final packaged chip.
[0062] Technical effects of the present invention:
[0063] This process method does not require the use of TSV process, so that two vertically adjacent dies can use FC process at the same time, which brings the following advantages:
[0064] 1) Eliminates the bonding wires of the two dies on the top layer, and avoids the long bonding wires on the top layer from being affected by the injection molding punch line.
[0065] 2) The two dies on the top layer have no bonding wires and are interconnected over a short distance via FC bump, which improves the transmission quality of high-speed and high-frequency signals.
[0066] 3) The two dies on the top layer have no bonding wires, so the thickness of the plastic package and the package can be minimized.
[0067] 4) The two top dies are not wired to the substrate, so the substrate size and package size are smaller, which helps reduce packaging costs.
[0068] 5) The top die does not use bonding wires. After plastic encapsulation, it can be ground to expose the silicon on the back of the top die, which is more conducive to heat dissipation, reduces the thermal resistance of the package, and improves the heat dissipation performance of the package.
[0069] 6) If gold wire is used for top-layer bonding, eliminating these long bonding wires also reduces the amount of gold used and reduces some costs.
[0070] like Figure 5 As shown, the WB+FC hybrid interconnection process method of the present invention marked F can achieve the smallest package size and thickness, and because there is no bonding wire on the top layer, the plastic packaging material can be ground off to expose the silicon back side, thereby improving heat dissipation.
[0071] Under the existing packaging process technology conditions, general wire-bonding packaging basically reaches its limit at the 3rd layer. After the 4th layer, the top layer wire is too long and the curvature is too large, and the manufacturability is very poor, and it is basically impossible to produce.
[0072] In this technical solution, stacking 4 layers can be increased to more than 4 layers, and even higher stacking can achieve production. BRIEF DESCRIPTION OF THE DRAWINGS
[0073] Figure 1 This is a size comparison chart of a pure WB wire bonding interconnect packaging structure and a FC+WB hybrid interconnect packaging structure;
[0074] Figure 2a is a schematic diagram of the TMV fan-out particle structure in this example;
[0075] Figure 2b This is a schematic diagram of the FC+WB hybrid interconnect packaging structure of this example;
[0076] Figure 3 It is a schematic diagram of the process of processing and manufacturing TMV fan-out particles of the present invention;
[0077] Figure 4 It is a schematic diagram of the substrate-level packaging manufacturing process of the present invention;
[0078] Figure 5 It is a size comparison diagram of a pure WB wire bonding interconnect packaging structure, a FC+WB hybrid interconnect packaging structure, and a packaging structure of the present invention;
[0079] In the figure, A represents a pure WB wire bonding interconnect packaging structure, B to E represent four types of WB+FC mixed interconnect group packaging structures, and F represents the packaging structure of the present invention.
[0080] First die1, second die2, third die3, substrate 4, wire bonding 5, first carrier board 6, second carrier board 7, through molded via (TMV) 8, first redistribution layer (RDL) 9, second redistribution layer (RDL) 10, pad 11, bump 12, solder ball 13, plastic encapsulation material 14, TMV fan-out particles 15, blue film 16. DETAILED DESCRIPTION
[0081] The present invention is further described below in conjunction with specific implementation modes.
[0082] In this embodiment, a single TMV fan-out particle is taken as an example for description.
[0083] refer to Figure 2a , a TMV fan-out particle, including a die (in Figure 2a 2 ), a first redistribution layer (RDL) 9, a second redistribution layer (RDL) 10, a through molded via (TMV) 8, and a molding compound;
[0084] The front side of the chip is connected to the second side of the first redistribution layer, the back side of the chip is connected to the first side of the second redistribution layer, a plurality of through-molding vias (TMVs) are connected between the first redistribution layer and the second redistribution layer, each of the through-molding vias is at the periphery of the chip, and the gaps between the first and second redistribution layers and the chip and the through-molding vias are filled with a plastic material 14;
[0085] The pad on the front side of the chip is connected to the corresponding through-molded via (TMV) 8 through the first redistribution layer 9; the first side of the first redistribution layer is also connected to the pad;
[0086] A pad is connected to the center of the second surface of the second redistribution layer, and a through molded via (TMV) is connected to the corresponding pad through the second redistribution layer.
[0087] The pad on the first surface of the first redistribution layer is located at the center of the first redistribution layer;
[0088] Or Figure 2a In this example, a bump 12 is connected to the pad on the first surface of the first redistribution layer.
[0089] The TMV fan-out particles of the present invention can be used in a chip as a separate unit carrying a die, which is beneficial to reducing the structural size of the chip.
[0090] refer to Figure 2b, an FC+WB hybrid interconnect packaging structure, comprising a substrate, a first die1, a second die2 and a third die3 stacked sequentially from bottom to top;
[0091] The second die2 has one or more pieces (one piece in this example); the second die2 is a chip in the TMV fan-out particle 15, and the corresponding TMV fan-out particle has one or more pieces (one piece in this example);
[0092] The back surface of the first die 1 is connected to the top surface of the substrate 4, and the pad on the front surface of the first die 1 is connected to the pad on the top surface of the substrate 4 through the bonding wire 5;
[0093] If there is one TMV fan-out particle (as in this example), the bump 12 of the first redistribution layer of the TMV fan-out particle is connected to the pad on the front side of the first die 1;
[0094] If there are multiple TMV fan-out particles stacked together, then:
[0095] For the bottom TMV fan-out particle: the bump of its first redistribution layer is connected to the pad on the front side of the first die, and the pad on its second redistribution layer is connected to the pad of the first redistribution layer of the TMV fan-out particle above it;
[0096] For the top TMV fan-out particle: the pad on its second redistribution layer is connected to the pad on the front side of the third die, and the pad on its first redistribution layer is connected to the pad on the second redistribution layer of the TMV fan-out particle below it;
[0097] For each middle TMV fan-out particle: the pad on its second redistribution layer is connected to the pad on the first redistribution layer of the TMV fan-out particle above it; the pad on its first redistribution layer is connected to the pad on the second redistribution layer of the TMV fan-out particle below it.
[0098] Solder balls 13 are connected to corresponding pads on the bottom surface of the substrate.
[0099] The most critical part of the FC+WB hybrid interconnect packaging process method of the present invention is to perform specific wafer-level packaging on the second die2 of the middle layer in advance, and the second die2 after such processing is called TMV (Through Molding Via) fan-out particles.
[0100] The manufacturing steps of the novel FC+WB hybrid interconnect package of this embodiment are divided into two major steps, namely, first, manufacturing the TMV fan-out particle 15 where the second die 2 is located; and second, substrate-level packaging.
[0101] 1. The processing flow of TMV fan-out particles where the second die2 is located is as follows Figure 3 , the steps include:
[0102] 1.1) Electroplating and growing plastic sealing through hole TMV (through molding via) 8 on the first carrier (carrier 6). The size of the first carrier is the same as that of the wafer. For example, if the second die 2 is a 12-inch wafer, the first carrier also uses a round 12-inch wafer.
[0103] 1.2) Cut the wafer where the second die 2 is located, and attach the cut second die 2 original particles to the first carrier 6 with the back side facing upward.
[0104] 1.3) Perform wafer-level injection molding on the first carrier 6 to completely cover the second die 2 and TMV 8 to form a reconstructed wafer.
[0105] 1.4) Grind the reconstructed wafer after injection molding to expose the back side of the second die2 and TMV8 again.
[0106] 1.5) Perform the second redistribution layer (RDL) 10 process on the back side of the second die 2 to redistribute the edge TMV contacts to the center. These redistributed metal pads to the center will be used for FC interconnection with the third die 3.
[0107] 1.6) Remove the first carrier, flip the reconstructed wafer, and attach the second redistribution layer (RDL) to the second carrier 7 to expose the front side of the second die 2.
[0108] 1.7) Perform the first redistribution layer (RDL) 9 process on the front side of the second die2 to redistribute the pad on the front side of the second die2 and connect it to the TMV.
[0109] 1.8) A bump is grown on the surface of the first redistribution layer (RDL) 9.
[0110] 1.9) Remove the second carrier plate 7 and attach the reconstructed wafer to the blue film 16 .
[0111] 1.10) Cut the wafer to obtain the final second die2 TMV fan-out particles.
[0112] 2. Substrate Level Packaging:
[0113] After the TMV fan-out particle 15 where the second die 2 is located is manufactured, conventional substrate-level packaging can begin. Figure 4 As shown, the steps include:
[0114] 2.1) The first die1 is mounted on the substrate with the front side facing up, and then the first die1 is wire-bonded to the substrate.
[0115] 2.2) The second die2 TMV Fan-out particle flip chip is mounted on the front side of the first die1. The second die2 forms a short-distance and efficient interconnection with the first die1 through the first redistribution layer (RDL9) and bump on the front side.
[0116] 2.3) The third die3 is flip-chipped to the back of the second die2 (i.e., the TMV fan-out particle 15). The third die3 forms a short-distance and efficient interconnection with the first die1 through the second redistribution layer RDL10 on the back of the second die2 and the first redistribution layer RDL9 on the front of the TMV and the second die2.
[0117] 2.4) Overall injection molding, surface silk screen printing, ball planting, and finally cutting into single pieces to form the final packaged chip.
[0118] Although the TMV fan-out particle process for the second die2 alone will increase some costs, the traditional FC+WB interconnection process requires wafer packaging of the die used for FC in advance, such as RDL process and bump growth, and the advantages brought are far inferior to the method of the present invention.
[0119] If the same method is used for the first die1 to form the first die1 TMV fan-out particles, the bonding wires of the first die1 can be eliminated, making it completely free of bonding wires, so that the package size can be further reduced. However, since the first die1 is at the bottom layer, the bonding wires themselves are short, and the high arc of the bonding wires does not affect the overall package thickness. In addition, the first die1 also uses the TMV fan-out process, and the cost will increase accordingly. Therefore, in actual applications, it is necessary to focus on evaluating whether the cost increase brought by the production of TMV fan-out particles for the first die1 matches the performance improvement it brings, and whether it is necessary to do it. The most valuable application of this TMV fan-out process is for the vertically stacked middle die, which can simultaneously open up the interconnection between the upper and lower dies adjacent to it, and minimize the electrical and physical impact of the bonding wires on the package.
[0120] The advantages of the packaging structure made by this method are:
[0121] 1) Two adjacent dies, the second die2 and the third die3, can use the FC process at the same time, but do not need to go through TSV, so that the second die2 and the third die3 do not need to use bonding wires, avoiding many problems caused by bonding wires, such as injection molding wire punching, degradation of high-speed and high-frequency signal quality, excessive package thickness, and excessive package size.
[0122] 2) The surface of the third die3 can be ground after injection molding to expose the silicon on the back of the third die3, which is very beneficial for heat dissipation and improves the heat dissipation capacity of the package.
[0123] Application description of the vertical multi-die stacking package of this embodiment:
[0124] 1) Structurally. Generally speaking, the bottom chip has a larger size, the middle chip has a smaller size, and the top chip has the smallest size, and they are stacked up like this.
[0125] 2) Interconnection. Generally, the bottom chip is a SOC chip with a larger size and area, which has complex functions, multiple functions, and multiple signal networks, so there are many pads and bumps (if it is WB, then there are many wire bonding). The middle and upper chips are generally smaller auxiliary chips, similar to memory chips, used to store data when the SOC is working.
[0126] 3) Figure 2b For example, if the first die1 is SOC, the second die2 is memory, and the third die3 is memory, then there are three situations in interconnection communication:
[0127] ① The functional signal IO pin of the first die1 SOC itself is connected to the substrate through wire bonding, and communicates with the outside through the solder ball outside the substrate 4.
[0128] ② The IO pins of the third die3 extend to the bumps on the first redistribution layer (RDL) 9 through the second redistribution layer (RDL) 10 and TMV8, forming interconnect communication with the first die1.
[0129] ③ The second die2 forms interconnect communication with the first die1 through the bumps on the first redistribution layer (RDL).
[0130] 4) The second die 2 and the third die 3 are generally not interconnected and communicated with each other, and the second die 2 and the third die 3 are generally interconnected and communicated with the first die 1.
Claims
1. A method for packaging TMV fan-out particles, characterized in that The packaging method is a wafer-level packaging method, and the steps include: 1) Electroplating and growing plastic-sealed through-holes TMV on a first carrier; the size of the first carrier is the same as that of the wafer; 2) Cutting the wafer where the die is located, and attaching each of the cut die to the first carrier with the back side facing upward; the plastic sealing through hole corresponding to each die is located around the die; 3) performing wafer-level injection molding on the first carrier to completely cover all the chips and plastic-sealed through holes to obtain a reconstructed wafer; 4) Grinding the reconstructed wafer to expose the back side of each wafer and the plastic sealing through-hole; 5) performing a redistribution layer RDL process on the back side of the reconstructed wafer to obtain a second redistribution layer; making pads on the top surface of the second redistribution layer, and conducting plastic-sealed through holes TMV to corresponding pads through the second redistribution layer; For a chip and corresponding plastic-encapsulated through holes, each plastic-encapsulated through hole is redistributed to a corresponding pad on the top surface of the second redistribution layer through the second redistribution layer; 6) removing the first carrier, turning over the reconstructed wafer, and attaching the top surface of the second redistribution layer to the second carrier with the top surface facing downward to expose the front side of the wafer; 7) Implementing a redistribution layer RDL process on the other side of the reconstructed wafer (i.e., the side where the front side of the wafer is located) to obtain a first redistribution layer; redistributing the pads on the front side of the wafer through the first redistribution layer and conducting with the corresponding TMVs; 8) Making a pad on the top surface of the first redistribution layer, and then making a bump on the pad; 9) Remove the second carrier plate and attach the reconstructed wafer to the electronic grade tape, i.e., blue film, with the back of the wafer facing downward; 10) Cutting and reconstructing the wafer to obtain the final single TMV fan-out particle; The top surface of the second redistribution layer refers to a side away from the wafer, and the top surface of the first redistribution layer refers to a side away from the wafer.
2. A TMV fan-out particle, characterized in that It includes a chip die, a first redistribution layer RDL, a second redistribution layer RDL, a plastic through hole TMV and a plastic packaging material; The front side of the chip is connected to the first redistribution layer, the back side of the chip is connected to the second redistribution layer, a plurality of plastic sealing through holes TMV are connected between the first redistribution layer and the second redistribution layer, each plastic sealing through hole is on the periphery of the chip, and the gaps between the first and second redistribution layers and the chip and the plastic sealing through holes are filled with plastic sealing material; The pad on the front side of the chip is connected to the corresponding plastic through hole TMV through the first redistribution layer; the first redistribution layer is also connected to a pad on the side facing away from the chip, and a bump is provided on the pad; A pad is provided on a side of the second redistribution layer facing away from the wafer, and the plastic-encapsulated through-hole TMV is conducted to the corresponding pad through the second redistribution layer.
3. A FC+WB hybrid interconnect packaging structure, characterized in that It includes a substrate, a first die, a second die, and a third die stacked sequentially from bottom to top; The second die has one or more pieces; the second die is a chip in a TMV fan-out particle, and the corresponding TMV fan-out particle has one or more pieces; The back surface of the first die is connected to the top surface of the substrate, and the pad on the front surface of the first die is connected to the pad on the top surface of the substrate through a bonding wire; The first structure: if there is one TMV fan-out particle and one or more third dies; The bump of the first redistribution layer of the TMV fan-out particle is connected to the pad on the front side of the first die; A third die is connected to the top of the TMV fan-out particle, or multiple third dies are connected in a flat pattern on the top of the TMV fan-out particle; The connection structure between the third die and the TMV fan-out particle is as follows: the bump on the front side of the third die is connected to the pad of the second redistribution layer of the TMV fan-out particle; The second structure: if there are multiple TMV fan-out particles stacked, and the third die has one or more pieces; A third die is connected to the top of the top TMV fan-out particle, or multiple third dies are connected to the top of the top TMV fan-out particle in a flat pattern; The connection structure between the third die and the TMV fan-out particle is as follows: the bump on the front side of the third die is connected to the pad of the second redistribution layer of the TMV fan-out particle; The bump of the first redistribution layer of the bottom TMV fan-out particle is connected to the pad on the front side of the first die; The bump of the first redistribution layer of each TMV fan-out particle in the middle is connected to the pad of the second redistribution layer of the TMV fan-out particle below it; the pad of the second redistribution layer of each TMV fan-out particle in the middle is connected to the bump of the first redistribution layer of the TMV fan-out particle above it.
4. The FC+WB hybrid interconnect packaging structure according to claim 3 is characterized in that For the top TMV fan-out particle: the bumps of the first redistribution layer are used to interconnect its own wafer die with the pads of the second redistribution layer of the TMV fan-out particle below it, and to interconnect the third die above it with the pads of the second redistribution layer of the TMV fan-out particle below it; For each TMV fan-out particle in the middle: the bumps of the first redistribution layer are used to interconnect the wafer die of the chip itself with the pads of the second redistribution layer of the TMV fan-out particle below it, and are used to interconnect the bumps of the first redistribution layer of the TMV fan-out particle above it with the pads of the second redistribution layer of the TMV fan-out particle below it; For the bottom TMV fan-out particle: the bumps of the first redistribution layer are used to interconnect its own wafer die with the pads of the first die below it, and are used to interconnect the bumps of the first redistribution layer of the TMV fan-out particle above it with the first die.
5. The FC+WB hybrid interconnect packaging structure according to claim 3 is characterized in that Solder balls are connected to corresponding pads on the bottom surface of the substrate.
6. A packaging method for a FC+WB hybrid interconnect packaging structure, characterized in that Includes steps: 2.1) Place the first die on the substrate with the front side facing upwards; then perform wire bonding from the first die to the substrate; 2.2) If there is only one TMV fan-out particle, flip-chip the TMV fan-out particle onto the front side of the first die using a flip chip process; If there are multiple TMV fan-out particles, the bottom TMV fan-out particle is flip-chip mounted on the front side of the first die using the flip chip process; then, other TMV fan-out particles are flip-chip mounted on the top of the bottom TMV fan-out particle using the flip chip process; 2.3) Flip-chip the third die onto the top TMV Fan-out chip using the flip chip process; 2.4) Overall injection molding and ball planting, and finally cutting into single pieces to form the final packaged chip.