Method for preparing radio frequency power amplifier, structure and circuit

Abstract

The present application discloses a method for manufacturing a radio frequency power amplifier, a radio frequency power amplifier structure, and a radio frequency power amplifier circuit. The manufacturing method includes: providing a first wafer on which a multi-stage cascaded field effect transistor structure is formed, the first wafer being a silicon-on-insulator wafer; providing a second wafer on which a silicon-germanium heterojunction bipolar transistor structure is formed, the second wafer being a bulk silicon wafer; bonding the multi-stage cascaded field effect transistor structure and the silicon-germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; forming a metal wiring structure on the initial power amplifier structure, the metal wiring structure being electrically connected to a radio frequency input end and a radio frequency output end respectively to form a radio frequency power amplifier. The corresponding structure and circuit manufactured by this manufacturing method have good radio frequency performance, relatively low manufacturing cost, and good compatibility with CMOS circuits.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method for fabricating a radio-frequency power amplifier, a radio-frequency power amplifier structure, and a radio-frequency power amplifier circuit. Background Art

[0002] A transmitting system is a system for transmitting signals into space. In this transmitting system, the transmitter, as the core part of the transmitting system, is responsible for processing and amplifying the information signals to be transmitted, and sending them into space through an antenna. The transmitter usually includes a pre-stage circuit, a modulation and oscillation circuit, and a radio-frequency power amplifier (RF PA) etc. The pre-stage circuit is mainly responsible for the preparation of the input baseband signal, such as filtering and preliminary amplification. The modulation and oscillation circuit is responsible for modulating the input baseband signal (such as audio, video, data, etc.) into a carrier signal. The modulated carrier signal is usually weak, so it needs to be boosted to a sufficient signal strength by a radio-frequency power amplifier so as to be effectively transmitted through the antenna. The main technical indicators of the above radio-frequency power amplifier are output power and efficiency. Therefore, how to improve the output power and efficiency is the core of the design goal of the radio-frequency power amplifier and also the key topic of relevant researchers.

[0003] Traditional linear power amplifiers have high gain and linearity, but relatively low efficiency. While switching power amplifiers have high efficiency and output power, but relatively poor linearity.

[0004] In view of this, improving the device performance of power amplifiers is an urgent problem to be solved at the present stage. Summary of the Invention

[0005] The purpose of this application is to provide a method for fabricating a radio-frequency power amplifier, a radio-frequency power amplifier structure, and a radio-frequency power amplifier circuit, which can not only effectively solve the problems existing in the prior art, but also have good performance (can provide sufficient gain, large output power, and high conversion efficiency), relatively low fabrication cost, and good compatibility with CMOS circuits.

[0006] According to a first aspect of the present application, embodiments of the present application provide a method for manufacturing a radio frequency power amplifier, including: providing a first wafer on which a multi-stage cascaded field effect transistor structure is formed, wherein the first wafer is a silicon-on-insulator wafer; providing a second wafer on which a silicon germanium heterojunction bipolar transistor structure is formed, wherein the second wafer is a bulk silicon wafer; bonding the multi-stage cascaded field effect transistor structure and the silicon germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; forming a metal wiring structure on the initial power amplifier structure, and the metal wiring structure is electrically connected to a radio frequency input end and a radio frequency output end respectively to form a radio frequency power amplifier.

[0007] According to a second aspect of the present application, embodiments of the present application provide a radio frequency power amplifier structure, including: a first semiconductor substrate; a first semiconductor layer located above the first semiconductor substrate, the first semiconductor layer includes a plurality of device regions, each of the device regions has a well region and a doped region, above each of the well regions there is a first polysilicon layer, and above each of the doped regions and each of the first polysilicon layers there is a first metal silicide layer; a first dielectric layer located above the first semiconductor layer, the first dielectric layer covers the first metal silicide layer and the first semiconductor layer, the first dielectric layer has a through first contact hole, and the first contact hole is in contact with the surface of the first metal silicide layer to connect the source electrode, drain electrode and gate electrode of the field effect transistor device; a second dielectric layer located above the first dielectric layer, the second dielectric layer has a first metal interconnection structure, and the first metal interconnection structure is electrically connected to the first contact hole; a fourth dielectric layer located above the second dielectric layer, the fourth dielectric layer has a second metal silicide layer and a through second contact hole, and the second contact hole is used to electrically connect the second metal silicide layer and the first metal interconnection structure; above the second metal silicide layer there are a third polysilicon layer and a second polysilicon layer respectively; the third polysilicon layer is used to form the emitter of the silicon germanium heterojunction bipolar transistor; a second semiconductor layer located above the fourth dielectric layer, the second semiconductor layer has a stacked silicon germanium crystal layer and a collector layer, the silicon germanium crystal layer is used to form the base of the silicon germanium heterojunction bipolar transistor, and the collector layer is used to form the collector of the silicon germanium heterojunction bipolar transistor; a fifth dielectric layer located above the second semiconductor layer, the fifth dielectric layer has a metal wiring structure, and the metal wiring structure is electrically connected to the gate terminal of the field effect transistor device and the radio frequency input end, and is electrically connected to the collector terminal of the silicon germanium heterojunction bipolar transistor and the radio frequency output end.

[0008] According to a third aspect of the present application, an embodiment of the present application provides a radio frequency power amplifier circuit. The radio frequency power amplifier circuit includes: an input unit configured as a common-source amplifier of a field effect transistor, the common-source amplifier of the field effect transistor including a first field effect transistor device; an intermediate unit coupled to the input unit, the intermediate unit configured as a common-gate amplifier of a field effect transistor, the common-gate amplifier of the field effect transistor including a second field effect transistor device; the second field effect transistor device being configured as at least one cascaded field effect transistor; and a final stage unit coupled to the intermediate unit, the final stage unit including a triode device, the triode device being a silicon germanium heterojunction bipolar transistor.

[0009] In the radio frequency power amplifier preparation method, radio frequency power amplifier structure, and radio frequency power amplifier circuit provided by the embodiments of the present application, the radio frequency power amplifier includes a silicon germanium heterojunction bipolar transistor (SiGe HBT) structure made of silicon germanium (SiGe) material. The silicon germanium (SiGe) material has a high electron mobility, so that the radio frequency power amplifier can operate at high frequencies with lower power, which can improve the device performance of the radio frequency power amplifier, and make the silicon germanium heterojunction bipolar transistor structure exhibit higher reliability and better voltage resistance performance. Moreover, the silicon germanium material has good thermal diffusivity and can effectively conduct heat to other regions inside the device structure, thereby reducing local overheating. Further, by introducing a silicon germanium (SiGe) base region into the silicon germanium heterojunction bipolar transistor structure, the silicon germanium heterojunction bipolar transistor structure has a higher current gain and a lower base region resistance, can reduce power consumption, and further reduce the self-effect. Brief Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1 It is a flowchart of the steps of a radio frequency power amplifier preparation method in an embodiment of the present application.

[0012] Figure 2 For Figure 1 It is a schematic diagram of an embodiment of step S100 shown.

[0013] Figure 3 For Figure 1 It is a schematic diagram of an embodiment of step S200 shown.

[0014] Figure 4 For Figure 1Schematic diagram of an embodiment of step S300 shown.

[0015] Figure 5 For Figure 1 Schematic diagram of an embodiment of step S400 shown.

[0016] Figures 6A to 6F For Figure 1 Process flow diagram of an embodiment of step S100 shown.

[0017] Figures 7A to 7F For Figure 1 Process flow diagram of an embodiment of step S200 shown.

[0018] Figure 8 And Figure 9 Respectively for Figure 1 Process flow diagrams of an embodiment of step S300 and step S400 shown.

[0019] Figure 10 Schematic diagram of the radio frequency power amplifier structure in an embodiment of the present application.

[0020] Figure 11 Schematic diagram of the radio frequency power amplifier circuit in an embodiment of the present application. Specific implementation manners

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0022] Refer to Figure 1 As shown, an embodiment of the present application provides a method for manufacturing a radio frequency power amplifier. The manufacturing method includes: Step S100: Provide a first wafer, on which a multi-stage cascaded field effect transistor structure is formed, where the first wafer is a silicon-on-insulator wafer (i.e., SOI wafer, the same hereinafter); Step S200: Provide a second wafer, on which a silicon germanium heterojunction bipolar transistor structure is formed, where the second wafer is a bulk silicon wafer (i.e., Bulk wafer); Step S300: Bond the multi-stage cascaded field effect transistor structure and the silicon germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; Step S400: Form a metal wiring structure on the initial power amplifier structure, and the metal wiring structure is electrically connected to the radio frequency input end and the radio frequency output end respectively to form a radio frequency power amplifier.

[0023] The following will further describe steps S100, S200, S300, and S400 respectively.

[0024] Referring to Figure 2 and Figures 6A to 6F as shown, providing a first wafer, on which a multi-stage cascaded field effect transistor structure is formed (i.e., step S100), includes the following steps S110 to S160.

[0025] Specifically, step S110: providing a semiconductor-on-insulator substrate, which includes a first semiconductor substrate 101 and a first semiconductor layer 102 arranged in a stacked manner; the first semiconductor layer 102 includes a plurality of device regions, where the device regions are used to form field effect transistor devices (i.e., MOS transistor devices, the same hereinafter), as Figure 6A shown. The semiconductor-on-insulator substrate is the SOI substrate, which can specifically be silicon-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator, etc. The first semiconductor substrate 101 can be undoped or doped (such as N-type, P-type, or a combination of both) silicon. The first semiconductor layer 102 can be silicon. In some embodiments, a buried oxide layer (Buried Oxide, abbreviated as BOX) (not shown in the figure) is arranged in a stacked manner between the first semiconductor substrate 101 and the first semiconductor layer 102, and the buried oxide layer is used to strengthen the isolation of semiconductor devices (here MOS transistor devices), so as to reduce parasitic effects and help improve the switching speed of semiconductor devices. The buried oxide layer can be silicon oxide or silicon oxynitride. The MOS transistor device is, for example, an NMOS transistor or a PMOS transistor.

[0026] Step S120: performing ion implantation at the first position and the second position of each device region respectively to form a well region at each first position and a doped region at each second position, where the doping types of the well region and the doped region in the same device region are opposite.

[0027] In this embodiment, the well region 104 includes a first type well region 104A and a second type well region 104B. The doped region 105 includes a first type doped region 105A and a second type doped region 105B, as Figure 6B shown.

[0028] Specifically, first type ions or second type ions can be implanted at the first position of each device region to correspondingly form a first type well region 104A or a second type well region 104B. Similarly, second type ions or first type ions can be implanted at the second position of each device region to correspondingly form a second type doped region 105B or a first type doped region 105A, as Figure 6BAs shown. Among them, the doping types of the first-type well region 104A and the second-type well region 104B are opposite, the doping types of the first-type well region 104A and the first-type doping region 105A are the same, and the doping types of the second-type well region 104B and the second-type doping region 105B are the same. The positions of the first position and the second position in the device region are different. For example, when a first-type ion implantation is performed at the first position in the first device region 1021, and the first-type ion is a P ion, such as boron (B), gallium (Ga), or indium (In), etc., the formed first-type well region 104A is a P-type well region (i.e., PW). When a second-type ion implantation is performed at the second position in the first device region 1021, and the second-type ion is an N ion, such as phosphorus (P), antimony (Sb), or arsenic (As), etc., the formed second-type doping region 105B is an N-type doping region (N+). With such a configuration, the MOS transistor device formed in the first device region 1021 is an NMOS transistor. Also, for example, when a second-type ion implantation is performed at the first position in the second device region 1022, and the second-type ion is an N ion, such as phosphorus (P), antimony (Sb), or arsenic (As), etc., the formed second-type well region 104B is an N-type well region (i.e., NW). When a first-type ion implantation is performed at the second position in the second device region 1022, and the first-type ion is a P ion, such as boron (B), gallium (Ga), or indium (In), etc., the formed first-type doping region 105A is a P-type doping region (P+). With such a configuration, the MOS transistor device formed in the second device region 1022 is a PMOS transistor.

[0029] In the above example, the first-type ion is configured as a P ion, and the second-type ion is configured as an N ion. Of course, the first-type ion can also be configured as an N ion, and the second-type ion can be configured as a P ion, so that the MOS transistor device formed in the above first device region is a PMOS transistor, and the MOS transistor device formed in the second device region is an NMOS transistor.

[0030] In an embodiment of the present application, before ion implantations are respectively performed at the first position and the second position in each device region to form a well region located at each first position and a doping region located at each second position (i.e., step S120), the preparation method may further include: forming a first trench isolation region (Shallow Trench Isolation, abbreviated as STI) 103 around the device region of the first semiconductor layer 102, as Figure 6AAs shown. Specifically, at the periphery of the device area on the first semiconductor layer 102, photolithography technology is used to define the areas that need to be isolated on the surface of the SOI wafer, and these areas are etched into grooves by using dry etching (RIE) technology, and oxide (for example, silicon dioxide) material is filled in the etched grooves by using chemical vapor deposition (CVD) technology to form a first trench isolation region 103. Further, a chemical mechanical polishing (CMP) process can be used to remove excess oxide material so that the surface of the SOI wafer is flat, and only the oxide in the trench remains. In this embodiment, the first trench isolation region 103 surrounds the device area and isolates the MOS tube device formed in the device area from other areas, thereby achieving electrical isolation between different devices. Furthermore, the first trench isolation region 103 is also located between the first device region 1021 and the second device region 1022 of the first semiconductor layer 102, and the doping type of the doping region in the first device region 1021 is opposite to that of the doping region in the second device region 1022, as shown in FIG. Figure 6B shown.

[0031] Step S130: forming a first polysilicon layer 107 on a side of each well region away from the first semiconductor substrate, wherein the doping type of each first polysilicon layer is opposite to that of the corresponding well region.

[0032] In this embodiment, the first polysilicon layer 107 may include a first type polysilicon 107A and a second type polysilicon 107B. Figure 6B and Figure 6C As shown, the second type polysilicon 107B and the first type polysilicon 107A may be formed respectively on the side of the first type well region 104A and the second type well region 104B away from the first semiconductor substrate 101 .

[0033] Specifically, when the MOS transistor device to be formed in the first device region is an NMOS transistor, a second type of polysilicon 107B is formed above the first type of well region 104A (here, a P-type well region), i.e., on the side facing away from the first semiconductor substrate 101. Further, the second type of polysilicon 107B is N-type doped (e.g., doped with phosphorus or arsenic) to form N-type doped polysilicon, which is used as the gate material of the NMOS transistor. That is to say, the doping type (N-type) of the second type of polysilicon 107B is opposite to the doping type (P-type) of the first type of well region 104A. When the MOS transistor device to be formed in the second device region is a PMOS transistor, a first type of polysilicon 107A is formed above the second type of well region 104B (here, an N-type well region), i.e., on the side facing away from the first semiconductor substrate 101. Further, the first type of polysilicon 107A is P-type doped (e.g., doped with boron) to form P-type doped polysilicon, which is used as the gate material of the PMOS transistor. That is to say, the doping type (P-type) of the first type of polysilicon 107A is opposite to the doping type (N-type) of the second type of well region 104B.

[0034] In an embodiment of the present application, before forming the first polysilicon layer on the side of each well region facing away from the first semiconductor substrate, and the doping type of each first polysilicon layer is opposite to that of the corresponding well region (i.e., step S130), the preparation method may further include: forming a gate oxide layer 106 on the sides of the first type of well region 104A and the second type of well region 104B facing away from the first semiconductor substrate 101, as Figure 6C shown. The gate oxide layer 106 can be silicon dioxide (SiO2) or a high-K material, which can serve as the insulating layer of the MOS transistor device. Specifically, a thinner silicon dioxide layer is grown on the active silicon layer on the surface of the SOI wafer through a thermal oxidation process as the gate oxide layer 106. The thickness of the gate oxide layer 106 is several tens of nanometers, and the smaller the thickness, the more beneficial it is to improve the performance of the device. It should be noted that in the present application, according to actual requirements, a stepped gate oxide layer 106 can be realized by using the oxidation and etching processes multiple times, so as to optimize the electrical performance of different regions.

[0035] Step S140: Deposit a metal on the sides of each doping region and each first polysilicon layer facing away from the first semiconductor substrate to form a first metal silicide layer.

[0036] In this embodiment, as shown in Figures 6B to 6D a metal is deposited on the sides of the first type of doping region 105A, the second type of doping region 105B, the second type of polysilicon 107B, and the first type of polysilicon 107A facing away from the first semiconductor substrate 101 to form a first metal silicide layer 108.

[0037] Specifically, in the case where the second type of doped region 105B is an N-type doped region, the first type of doped region 105A is a P-type doped region, the second type of polysilicon 107B is N-type doped polysilicon, and the first type of polysilicon 107A is P-type doped polysilicon, a layer of nickel is deposited over the N-type doped region, P-type doped region, N-type doped polysilicon, and P-type doped polysilicon by using sputtering or physical vapor deposition (PVD) technology, and rapid thermal annealing (RTA) is performed to react the nickel with the silicon in the source, drain, and gate regions to form a low-resistance nickel silicide layer, as Figure 6D shown, and the unreacted nickel is removed by selective etching to ensure the formation of nickel silicide at the desired positions.

[0038] Step S150: Form a first dielectric layer 109 covering the first metal silicide layer 108 and the first semiconductor layer 102. The first dielectric layer 109 has first contact holes (111, 112, 113) therein. The first contact holes penetrate the first dielectric layer 109 and are in contact with the surface of the first metal silicide layer 108 to connect the source, drain, and gate of the field effect transistor device.

[0039] Combined with Figures 6B to 6E shown, a first dielectric layer 109 is formed over the first metal silicide layer 108 and the first semiconductor layer 102 (i.e., on the side away from the first semiconductor substrate 101). That is to say, the first dielectric layer 109 covers the first metal silicide layer 108 and the first semiconductor layer 102. The first dielectric layer 109 has a plurality of first contact holes (111, 112, 113) therein. These first contact holes (111, 112, 113) penetrate the first dielectric layer 109 and are in contact with the surface of the first metal silicide layer 108 to connect the source (Source), drain (Drain), and gate (Gate) of the field effect transistor device. The first metal silicide layer 108 is used to reduce the contact resistance of the source, drain, and gate, thereby improving the electrical performance of the device.

[0040] The specific implementation of this step is as follows. A first dielectric layer 109 (such as silicon dioxide or silicon nitride) is formed above the first metal silicide layer 108 and the first semiconductor layer 102 (i.e., on the side away from the first semiconductor substrate 101). Using photolithography and etching techniques, first contact holes (111, 112, 113) are formed in the first dielectric layer 109 corresponding to the source, gate, and drain regions to expose the first metal silicide layer 108 (here, a nickel silicide layer). Then, a metal (such as titanium / titanium nitride, aluminum, or copper) is deposited in the first contact holes using physical vapor deposition or chemical vapor deposition techniques, and the excess metal deposition is removed using a chemical mechanical polishing (CMP) process, leaving only the metal in the first contact holes. In this way, first contact holes (such as the reference numerals 111, 112, 113 shown in Figure 6E ) for connecting the source, drain, and gate of the MOS transistor device can be correspondingly formed inside the first dielectric layer 109 and on the surface of the first metal silicide layer 108.

[0041] Step S160: A second dielectric layer 114 is formed on the side of the first dielectric layer 109 away from the first semiconductor substrate, and a first metal interconnect structure 115 is formed in the second dielectric layer 114. As shown in Figure 6F , the first metal interconnect structure 115 is used to electrically connect to the source, drain, and gate of the field effect transistor device. With such a configuration, the first metal interconnect structure 115 can electrically connect the source, drain, and gate of the MOS transistor device to other devices or circuits to achieve signal transmission.

[0042] Specifically, a second dielectric layer 114 (such as silicon dioxide or silicon nitride) is deposited above the first dielectric layer 109 (i.e., on the side away from the first semiconductor substrate 101), and photolithography and etching techniques are used to define the first metal interconnect structure 115 (such as vias or trenches of the metal interconnect structure) to expose the areas to be connected. Then, a metal (such as copper or aluminum) is filled in the vias of the metal interconnect structure using electroplating or chemical vapor deposition techniques to form a metal interconnect path, and the excess metal is removed using a chemical mechanical polishing process. It should be noted that when performing this step S160, according to the design of the relevant circuit, the above steps can be repeatedly executed to achieve a metal interconnect structure with a multi-layer arrangement.

[0043] In addition, it is worth noting that when multiple MOS transistor devices formed in multiple device regions are configured to be cascaded in a corresponding circuit, for example, the drain of the first cascaded MOS transistor is electrically connected to the source of the second cascaded MOS transistor, the drain of the second cascaded MOS transistor is electrically connected to the source of the third cascaded MOS transistor, the drain of the third cascaded MOS transistor is electrically connected to the source of the fourth cascaded MOS transistor, and so on. The drain of the (N - 1)th cascaded MOS transistor is electrically connected to the source of the Nth cascaded MOS transistor. In this case, the second-type doped regions 105B in each device region are configured to be integrally formed with the second-type doped regions 105B in adjacent device regions. Similarly, according to the corresponding circuit design, the first-type doped regions 105A in each device region are configured to be integrally formed with the first-type doped regions 105A in adjacent device regions.

[0044] Refer to Figure 3 and Figures 7A to 7F As shown, a second wafer is provided, and forming a silicon-germanium heterojunction bipolar transistor structure (i.e., step S200) on the second wafer includes the following steps S210 to S260.

[0045] Step S210: Provide a second semiconductor substrate 201.

[0046] Step S220: Form a second semiconductor layer 202 on the second semiconductor substrate 201, and a heavily doped collector layer 204 is formed in the second semiconductor layer 202 to obtain the collector of the silicon-germanium heterojunction bipolar transistor, as Figure 7A shown.

[0047] Specifically, a second semiconductor substrate 201 is provided on the surface of the second wafer (here, a bulk wafer). On this second semiconductor substrate 201, silicon or silicon-germanium material is grown on the second semiconductor substrate 201 (such as a silicon substrate) by epitaxial growth. During the growth process, high doping is achieved by controlling the concentration of doping sources (such as N-type dopants like phosphorus and arsenic), and a highly doped collector layer 204 is formed. It should be noted that epitaxial growth refers to depositing a layer of material with the same structure as the substrate (usually silicon) on the substrate. The epitaxial layer, as the second semiconductor layer 202, can precisely control the thickness, doping concentration, and material composition, thereby forming the desired electrical characteristics. High doping means that by controlling the flow rate of the doping source and epitaxial growth parameters, the collector layer 204 has high conductivity. The heavy doping of the collector helps to increase the carrier concentration in the collector region, reduce the resistance of the collector region, and accelerate the current transmission speed. It is worth noting that excessive doping will lead to current leakage and a reduction in breakdown voltage, while too low doping will result in too large a resistance in the collector region, affecting device performance. Therefore, in this embodiment, the heavily doped collector layer 204 ensures obtaining the desired doping concentration in the collector region through precise process control, and by controlling the thickness of the collector layer 204 (such as being relatively thin), the time for carriers to pass through the collector is shortened, while the resistance of the collector region is reduced, achieving the effects of meeting high-frequency performance and low power consumption.

[0048] In some embodiments, by using ion implantation technology, that is, using a high-energy particle accelerator to directly inject a dopant (such as phosphorus or arsenic) into the silicon layer on the second semiconductor substrate 201, a heavily doped collector layer 204 is formed. This method can be carried out after epitaxial growth to further enhance the doping concentration in the collector region. Further, an annealing treatment is performed after ion implantation to allow the dopant atoms to diffuse and activate, thereby ensuring that the dopant reaches the desired depth and distribution, and further optimizing the electrical performance of the device.

[0049] Optionally, in some embodiments, before step S210, the preparation method further includes the following step: forming a second trench isolation region 203 around the collector region of the second semiconductor layer 202, as Figure 7A shown. The formation method of this second trench isolation region 203 is the same as that of the above-mentioned first trench isolation region 103, and will not be elaborated here.

[0050] Step S230: Form a silicon-germanium crystal layer 205 covering the collector layer 204 to obtain the base of the silicon-germanium heterojunction bipolar transistor, as Figure 7BAs shown. In a bipolar transistor, the base region is the region that controls the collector and emitter currents. Specifically, after forming the heavily doped collector layer 204, a silicon-germanium material can be grown on top of the collector layer 204 to obtain the base of the silicon-germanium heterojunction bipolar transistor. Silicon-germanium has a higher mobility and better frequency characteristics, which helps to improve the performance of the device. Further, the silicon-germanium crystal layer 205 has a lower doping concentration to achieve current control between the emitter and the collector.

[0051] Step S240: Form a second polysilicon layer 206 on the second semiconductor layer 202. The second polysilicon layer 206 has a patterned opening that exposes the surface of a portion of the silicon-germanium crystal layer 205. See Figure 7B and Figure 7C As shown. Specifically, by forming a second polysilicon layer 206 on the surface of the second wafer (i.e., the bulk wafer), here above the second semiconductor layer 202, and performing P-type doping (such as doping with boron) on the second polysilicon layer 206 to form a P-type doped polysilicon layer. In this step, the specific pattern of the P-type doped polysilicon layer is defined by using photolithography and etching techniques. As Figure 7C shown, the second polysilicon layer 206 (here the P-type doped polysilicon layer) has a patterned opening that exposes the upper surface of a portion of the silicon-germanium crystal layer 205.

[0052] Step S250: Deposit a third dielectric layer 207 on the second polysilicon layer 206 and the silicon-germanium crystal layer 205. A through contact window is formed in the third dielectric layer 207, and the contact window is filled with a third polysilicon layer 208. The third polysilicon layer 208 is in contact with the silicon-germanium crystal layer 205 to obtain the emitter of the silicon-germanium heterojunction bipolar transistor, as Figure 7D shown.

[0053] Specifically, first, a layer of oxide (such as silicon dioxide or other dielectric materials) is deposited above the doped and patterned second polysilicon layer 206 and silicon germanium crystal layer 205 (i.e., on the side away from the second semiconductor substrate 201) to form a third dielectric layer 207 (or an insulating layer), which is used to isolate different functional regions and prevent unnecessary current leakage. Then, the surface is planarized using a chemical mechanical polishing (CMP) process to provide a flat surface for subsequent process steps. Next, photolithography and etching techniques are used to form a through contact window in the third dielectric layer 207. It should be noted that this contact window serves as the contact area between the base region and the emitter region, enabling the emitter to be electrically connected to the base. After the contact window is formed in the third dielectric layer 207, a third polysilicon layer 208 is filled in the contact window. The third polysilicon layer 208 contacts the silicon germanium crystal layer 205 to obtain the emitter of the silicon germanium heterojunction bipolar transistor and establish an electrical connection with the base of the silicon germanium heterojunction bipolar transistor obtained in step S230. It should be noted that after the third polysilicon layer 208 is deposited and formed, the third polysilicon layer 208 is N-type doped (such as doped with phosphorus or arsenic) to form an N-type doped polysilicon layer. Further, by using photolithography and etching techniques, the specific pattern of the N-type doped polysilicon layer is defined again to ensure the precise positioning of the emitter region.

[0054] Step S260: Form a second metal silicide layer 210 that contacts the second polysilicon layer 206 and the third polysilicon layer 208, as Figure 7E shown.

[0055] Specifically, first, photolithography and etching techniques are used to remove a portion of the third dielectric layer 207 to form a metal contact window, thereby exposing the contact areas of the emitter, base, and collector. Subsequently, a layer of metal (such as nickel silicide (NiSi) or cobalt silicide (CoSi)) is deposited to form a second metal silicide layer 210, and the metal silicide therein is used to reduce the contact resistance, thereby improving the device performance. It should be noted that in the embodiment shown as Figure 7E shown, photolithography and etching techniques are used to remove a portion of the third dielectric layer 207 and a portion of the third polysilicon layer 208 to form the required contact area, and a layer of metal (specifically nickel Ni) is deposited on the contact area to form a second metal silicide layer 210. If the metal deposited on the contact area is cobalt Co, there is no need to remove a portion of the third polysilicon layer 208, that is, cobalt is deposited on the second polysilicon layer 206 and the third polysilicon layer 208, and cobalt reacts with silicon to form a cobalt silicide alloy, thereby forming a second metal silicide layer 210.

[0056] Step S270: A fourth dielectric layer 211 covering the second metal silicide layer 210 and the third dielectric layer 207 is formed, and a second contact hole 209 penetrating the fourth dielectric layer 211 is formed. The second contact hole 209 is in contact with the second metal silicide layer 210. As Figure 7F shown, the fourth dielectric layer 211 is formed above the second metal silicide layer 210 and the third dielectric layer 207 (i.e., on the side away from the second semiconductor substrate 201), and the second contact hole 209 is formed in the fourth dielectric layer 211. The second contact hole 209 includes a contact hole for forming the conductive pillar 212 and a contact hole for forming the first metal interconnect layer 213.

[0057] Specifically, a layer of dielectric material (such as silicon dioxide SiO2, a low dielectric constant material (low-K material), or a fluorosilicate glass FSG material) is deposited above the second metal silicide layer 210 and the third dielectric layer 207 to form the fourth dielectric layer 211, which is used to prevent electrical short circuits and provide support for subsequent metal wiring. Then, photolithography and etching techniques are used to form the second contact hole 209 in this dielectric layer. The first part 209A of the second contact hole in the second contact hole 209 can be used to form the conductive pillar 212, and the second part 209B of the second contact hole can be used to form the first metal interconnect layer 213. The conductive pillar 212 and the first metal interconnect layer 213 will be further described below.

[0058] In this embodiment, in the fourth dielectric layer 211, first, photolithography and etching techniques are used to form the first part 209A of the second contact hole. The first part 209A of the second contact hole can expose the surfaces of the emitter, base, and collector or the previously formed second metal silicide layer 210 (such as NiSi or CoSi), preparing for subsequent metal deposition. Optionally, after forming the first part 209A of the second contact hole, physical vapor deposition techniques are used to deposit titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) on the inner wall of the first part 209A of the second contact hole. Among them, titanium or tantalum serves as an adhesion layer (Glue Layer) to enhance the adhesion between the subsequent metal (such as tungsten) and the dielectric material; titanium nitride or tantalum nitride serves as a barrier layer to prevent metal atoms from diffusing into the dielectric layer and avoid performance degradation. Subsequently, a layer of metal (here tungsten, which has low resistance and good thermal stability and maintains performance under high-temperature conditions) is deposited by using chemical vapor deposition or physical vapor deposition techniques to fill the first part 209A of the second contact hole and cover the wafer surface. It should be noted that the tungsten inside the first part 209A of the second contact hole is used to ensure electrical connection with the contact areas of the exposed emitter, base, and collector. That is to say, the first part 209A of the second contact hole serves as the conductive pillar 212. After that, the excess tungsten is removed by using chemical mechanical polishing. Further, by using photolithography and etching techniques, the precise pattern of tungsten is defined again to remove the unnecessary tungsten to meet the design requirements of the relevant circuit.

[0059] In this embodiment, after the tungsten filling of the first part 209A of the second contact hole is completed, photolithography and etching techniques can be used to form the second part 209B of the second contact hole, and a metal (such as copper or aluminum, which has good electrical conductivity, processability, and cost-effectiveness) is deposited on the second part 209B of the second contact hole by using physical vapor deposition or chemical vapor deposition techniques, and the deposited metal is converted into a specific interconnect pattern by using photolithography and etching techniques to form the first metal interconnect layer 213. In this way, the key parts (emitter, base, and collector) in the silicon-germanium heterojunction bipolar transistor structure can be electrically connected to the external circuit through the first metal interconnect layer 213. It should be noted that the first metal interconnect layer 213 usually refers to the first layer in the metal interconnect layer, and other layers in the metal interconnect layer (such as the second metal interconnect layer M2, the third metal interconnect layer M3, etc.) can also be formed by the above processes. Further, these metal interconnect layers are separated by dielectric materials and are interconnected through vias.

[0060] Refer to Figure 4 and Figure 8As shown, bonding the multi-stage cascaded field effect transistor structure and the silicon germanium heterojunction bipolar transistor structure to form the initial power amplifier structure (i.e., step S300) includes the following steps S310 to S320.

[0061] Specifically, step S310: Invert (or flip) the silicon germanium heterojunction bipolar transistor structure formed on the second wafer.

[0062] Step S320: Electrically connect the inverted silicon germanium heterojunction bipolar transistor structure and the multi-stage cascaded field effect transistor structure to obtain the initial power amplifier structure. Specifically, the flip-chip technology can be used to electrically connect the inverted silicon germanium heterojunction bipolar transistor structure (i.e., the emitter 208, base 205, and collector 204 in the SiGe HBT structure) to the multi-stage cascaded field effect transistor structure (i.e., the source, gate, and drain of the MOS transistor device) through the interconnect metal (such as the first metal interconnect structure 115 mentioned above) for physical and electrical integration, so as to effectively combine the high-frequency characteristics of the SiGe HBT with the high-efficiency switching characteristics of the MOS transistor device. Of course, in other partial embodiments, the through-silicon via (TSV) technology can also be used to achieve the physical and electrical connection between the above-mentioned silicon germanium heterojunction bipolar transistor structure and the multi-stage cascaded field effect transistor structure.

[0063] It should be noted that discrete devices (such as RF switches, low-noise amplifiers, RF power amplifiers, etc.) are usually combined together through packaging technology, but may be limited by packaging, interconnection, circuit complexity, and size between devices. With the development of 5G technology, the requirements for the performance, power consumption, and volume of the transmitter system are getting higher and higher. This requires integrating more discrete devices on the same wafer to improve system efficiency, reduce power consumption, and signal loss. Due to the high operating voltage, large power consumption, and requirements for efficiency and thermal management of RF power amplifiers, it is difficult to integrate RF power amplifiers with RF switches and low-noise amplifiers on the same wafer. Moreover, the current technologies for RF power amplifiers include gallium arsenide (GaAs) or gallium nitride (NAs). These materials can achieve high-efficiency power amplification, but they are not compatible with the mainstream silicon (Si)-based CMOS process and cannot be integrated on the same wafer. In particular, silicon-on-insulator and gallium arsenide processes are not compatible, and the size of silicon-on-insulator wafers in the current technology is usually 12 inches (300 mm), while the size of gallium arsenide wafers is usually 6 inches (150 mm). This means that integrating these two different technologies on the same production line faces huge process challenges. In other words, the differences in material characteristics and wafer size between silicon-on-insulator wafers and gallium arsenide wafers further hinder the integration of these two technologies. In this solution, the SiGe HBT structure and the multi-stage cascaded field-effect transistor structure are independently fabricated. The multi-stage cascaded field-effect transistor structure is fabricated on a silicon-on-insulator wafer, and the SiGe HBT structure is fabricated on a bulk wafer. In this way, they can be fabricated on different wafers and then the wafers with the above structures are bonded and integrated, which can improve the fabrication efficiency and also solve the problems that the power amplifiers made of gallium arsenide process in the existing technology are expensive, have poor process integration, and the power amplifiers made of complementary metal oxide semiconductor (CMOS) process have low electron mobility, relatively poor performance, and are difficult to be applied to high-output power occasions.

[0064] Moreover, the SiGe HBT structure formed on the bulk wafer of this application is bonded (i.e., integrated together) with the multi-stage cascaded field-effect transistor structure formed on the silicon-on-insulator wafer, thereby providing better utilization of the silicon-on-insulator wafer and also reducing the fabrication cost of the entire device (the cost of the silicon-on-insulator wafer is relatively high).

[0065] Furthermore, the heterojunction bipolar transistor (HBT) of the present application scheme uses silicon germanium material. Compared with silicon material, silicon germanium has higher mobility (the introduction of germanium increases the mobility of electrons and holes, making the carrier transmission speed faster), so that the operating frequency of the circuit can be increased while reducing power consumption; the SiGe HBT structure made of silicon germanium material has better electron mobility, so it can work at a lower power at a high frequency, while also providing higher performance indicators (for example, higher conversion efficiency, higher power amplification efficiency (PAE) (can reach more than 40%), and higher power output), and makes the SiGe HBT structure show higher reliability and better voltage resistance. Furthermore, by optimizing the thickness, alloy composition and device structure of silicon germanium material, silicon germanium material can show higher thermal stability and higher breakdown voltage in high-frequency applications.

[0066] In addition, the present application forms a SiGe HBT structure on the bulk wafer and a multi-stage cascade field effect transistor structure on the silicon-on-insulator wafer, so that high-power devices can be kept away from other RF devices (for example, an RF switch, which can be prepared on a silicon-on-insulator wafer, because the silicon-on-insulator wafer can provide better high-frequency performance, isolation, lower parasitic effects and higher switching speeds), thereby improving isolation and achieving less interference in the signals received and transmitted by the RF power amplifier.

[0067] See also Figure 5 and Figure 9 As shown, a metal wiring structure is formed on the initial power amplifier structure, and the metal wiring structure is electrically connected to the RF input terminal and the RF output terminal respectively to form a RF power amplifier (ie, step S400) including the following steps S410 to S420.

[0068] Step S410: forming a fifth dielectric layer 401 on the side of the initial power amplifier structure away from the first semiconductor substrate 101, and forming a metal wiring structure 402 located within the fifth dielectric layer 401 and the initial power amplifier structure. The metal wiring structure 402 includes a metal contact layer 4021 and a metal wiring layer 4022 described below.

[0069] Specifically, after integrating the above SiGe HBT structure and the multi-stage cascaded field effect transistor structure, a dielectric material (such as silicon dioxide or other dielectric materials) is deposited on top of them to form the fifth dielectric layer 401. The fifth dielectric layer 401 is used to prevent electrical short circuits and provide mechanical support for subsequent photolithography, etching, and metal wiring. After depositing the fifth dielectric layer 401, photolithography and etching techniques are used to open contact windows (or contact holes, contact via) in the areas where electrical connections are required, for exposing the emitter, base, collector in the SiGe HBT structure or the source, drain, and gate of the MOS transistor devices in the multi-stage cascaded field effect transistor structure. The formation of these contact areas is to enable the metal contact layer 4021 described below to be directly electrically connected to the functional areas of the SiGe HBT structure and the multi-stage cascaded field effect transistor structure. That is to say, this process enables the metal contact layer 4021 to establish electrical connections with various parts (source, gate, and drain) of the MOS transistor devices in the SiGe HBT structure and the multi-stage cascaded field effect transistor structure, ensuring that current and signals are transmitted through the metal contact layer 4021 to serve as the basis for radio frequency signal transmission (such as radio frequency input and radio frequency output). After the contact windows are formed, a low-resistance metal (such as copper or aluminum) is deposited using physical vapor deposition or chemical vapor deposition techniques to form the metal contact layer 4021. The metal contact layer 4021 fills the contact windows (or contact holes) to achieve local electrical connections with the functional areas of the SiGe HBT structure and the MOS transistor devices, thus constituting part of the metal wiring structure. It should be noted that the formation of the above metal contact layer 4021 is used to provide electrical connection points between the SiGe HBT structure and the multi-stage cascaded field effect transistor structure, and to form a signal transmission path through further metal wiring.

[0070] Step S420: Form a metal wiring structure located within the fifth dielectric layer and the initial power amplifier structure. The metal wiring structure is electrically connected to the gate terminal and the radio frequency input terminal of the multi-stage cascaded field effect transistor structure, and is also electrically connected to the collector terminal and the radio frequency output terminal of the silicon germanium heterojunction bipolar transistor.

[0071] Specifically, after completing step S410, that is, providing electrical connection points between the SiGe HBT structure and the multi-stage cascaded field effect transistor structure, global signal transmission and device interconnection are achieved by stacking multiple metal wiring layers 4022. In this embodiment, the radio frequency input terminal (RF IN) is connected to the gate terminal of the MOS transistor device in the multi-stage cascaded field effect transistor structure, and the radio frequency output terminal (RF OUT) is connected to the collector terminal of the SiGe HBT structure. It should be noted that an insulating layer is deposited between the metal wiring layers 4022, and vias are formed using photolithography and etching techniques. These vias are used to connect the metal wiring layers 4022 of different layers, and the metal (such as copper or aluminum) in the vias is used to form the required wiring paths to achieve complex interconnection and signal transmission. After establishing the radio frequency input and radio frequency output paths, electrical connection with the radio frequency input terminal (RF IN) and the radio frequency output terminal (RF OUT) can be achieved and connected to an external circuit.

[0072] Referring to Figure 10 As shown, an embodiment of the present application provides a radio frequency power amplifier structure, and this radio frequency power amplifier structure is fabricated using the radio frequency power amplifier preparation method described in the embodiment of the present application. The preparation method has been specifically described above and will not be elaborated here.

[0073] In this embodiment, this radio frequency power amplifier structure may at least include:

[0074] A first semiconductor substrate 101;

[0075] A first semiconductor layer 102, located above the first semiconductor substrate 101. The first semiconductor layer 102 includes a plurality of device regions, and each device region has a well region 104 and a doped region 105 (as shown in Figure 6B ), a first polysilicon layer 107 is disposed above each well region 104 (as shown in Figure 6C ), and a first metal silicide layer 108 is disposed above each doped region 105 and each first polysilicon layer 107 (as shown in Figure 6D ); wherein, the device regions are used to form field effect transistor devices (i.e., MOS transistor devices); a well region 104 is provided at a first position in each device region, and the well region 104 includes a first type well region 104A and a second type well region 104B. A doped region 105 is provided at a second position in each device region, and the doped region 105 includes a first type doped region 105A and a second type doped region 105B; a first polysilicon layer 107 is disposed above the first type well region 104A and the second type well region 104B, and the first polysilicon layer 107 includes a first type polysilicon 107A and a second type polysilicon 107B; a first metal silicide layer 108 is disposed above the first type doped region 105A, the second type doped region 105B, the second type polysilicon 107B, and the first type polysilicon 107A;

[0076] The first dielectric layer 109 is located above the first semiconductor layer 102. The first dielectric layer 109 covers the first metal silicide layer 108 and the first semiconductor layer 102. The first dielectric layer 109 has through first contact holes (111, 112, 113) that are in contact with the surface of the first metal silicide layer 108 to connect the source, drain, and gate of the field effect transistor device.

[0077] The second dielectric layer 114 is located above the first dielectric layer 109. The second dielectric layer 114 has a first metal interconnect structure 115, and the first metal interconnect structure 115 is electrically connected to the first contact holes (111, 112, 113).

[0078] The fourth dielectric layer 211 is located above the second dielectric layer 114. The fourth dielectric layer 211 has a second metal silicide layer 210 and through second contact holes 209 for electrically connecting the second metal silicide layer 210 and the first metal interconnect structure 115. Above the second metal silicide layer 210, there are a third polysilicon layer 208 and a second polysilicon layer 206 respectively. The third polysilicon layer 208 is used to form the emitter of the silicon-germanium heterojunction bipolar transistor. It should be noted that there is also a third dielectric layer 207 between the third polysilicon layer 208 and the second polysilicon layer 206. For details, refer to the description of the preparation method above.

[0079] The second semiconductor layer 202 is located above the fourth dielectric layer 211. The second semiconductor layer 202 has a stacked silicon-germanium crystal layer 205 and a collector layer 204, and the collector layer 204 is used to form the collector of the silicon-germanium heterojunction bipolar transistor.

[0080] The fifth dielectric layer 401 is located above the second semiconductor layer 202. The fifth dielectric layer 401 has a metal wiring structure 402. The metal wiring structure 402 is electrically connected to the gate terminal of the field effect transistor device and the RF input terminal (RF IN), and is also electrically connected to the collector terminal of the silicon-germanium heterojunction bipolar transistor and the RF output terminal (RF OUT). Specifically, the gate terminal of the field effect transistor device is electrically connected to the RF input terminal (RF IN) through the first metal interconnect structure 115 and the metal wiring structure 402. The metal contact layer 4021 of the metal wiring structure 402 is disposed in the second dielectric layer 114, the fourth dielectric layer 211, and the fifth dielectric layer 401. The drain terminal of the field effect transistor device is electrically connected to the first metal interconnect layer 213 through the first metal interconnect structure 115. The collector terminal of the silicon-germanium heterojunction bipolar transistor is electrically connected to the RF output terminal (RF OUT) through the metal wiring layer 4022 of the metal wiring structure 402.

[0081] In the radio frequency power amplifier structure provided by the embodiments of the present application, the base (i.e., the silicon-germanium crystal layer) 205 of the silicon-germanium heterojunction bipolar transistor is made of silicon-germanium material, which helps to integrate the SiGe HBT structure into the CMOS logic circuit (here is a multi-stage cascaded field effect transistor structure) easily, so as to achieve the purpose of mixed signals. Further, the germanium content in the SiGe HBT structure is relatively low, the overall structure has a relatively high thermal conductivity, and good heat conduction performance can be maintained. Moreover, the silicon-germanium material has good thermal diffusivity, which can more effectively conduct heat to other areas inside the device and reduce local overheating. Compared with the traditional silicon-based bipolar transistor, introducing the silicon-germanium crystal layer 205 in the SiGe HBT structure as the base region has higher current gain and lower base region resistance, thus reducing power consumption and further alleviating the self-heating effect. In addition, the silicon-germanium crystal layer 205 is relatively thin and has a fast heat dissipation speed, and the vertical structure design of the SiGe HBT structure enables the collector to dissipate heat directly. Therefore, the high thermal conductivity material and low thermal resistance design adopted in the SiGe HBT structure further optimize the heat dissipation path.

[0082] It should be noted that in the radio frequency power amplifier structure provided by the embodiments of the present application, the collector of the silicon-germanium heterojunction bipolar transistor is directly electrically connected using a metal with high conductivity (such as copper). Aluminum is not used because the conductivity of aluminum is relatively low compared to other metals (such as copper, tungsten, or other more advanced metals), and the electromigration problem of aluminum will reduce the reliability of the interconnection under high current density and easily lead to an increase in power loss in high-frequency applications. Therefore, in the radio frequency power amplifier structure of the embodiments of the present application, the collector of the silicon-germanium heterojunction bipolar transistor directly uses copper material, which can reduce resistance, parasitic capacitance, and inductance.

[0083] Refer to Figure 11 As shown, the embodiments of the present application provide a radio frequency power amplifier circuit, which is made by using the radio frequency power amplifier preparation method described in the embodiments of the present application. The preparation method has been specifically described above and will not be elaborated here.

[0084] In this embodiment, the radio frequency power amplifier circuit may include: an input unit 10, an intermediate unit 20, and a final stage unit 30.

[0085] Among them, the input unit 10 is configured as a common-source amplifier of a field-effect transistor, which is used to provide sufficient gain. The common-source amplifier of the field-effect transistor may include a first field-effect transistor device Q1. The intermediate unit 20 is coupled to the input unit 10, and the intermediate unit 20 is configured as a common-gate amplifier of a field-effect transistor, which is used to provide sufficient input impedance. The common-gate amplifier of the field-effect transistor includes a second field-effect transistor device Q2; the second field-effect transistor device Q2 is configured as at least one cascaded field-effect transistor. The final-stage unit 30 is coupled to the intermediate unit 20, and the final-stage unit 30 includes a triode device T1, where the triode device T1 is a silicon-germanium (SiGe) heterojunction bipolar transistor, which is used to provide high-power output and high conversion rate.

[0086] As Figure 11 shown, the source of the first field-effect transistor device Q1 is grounded, the drain of the first field-effect transistor device Q1 is electrically connected to the source of the second field-effect transistor device Q2, and the gate of the first field-effect transistor device Q1 is electrically connected to an input resistor R i electrically, and the resistance value of the input resistor R i is greater than a preset resistance value. That is to say, the resistance value of the input resistor Ri is set to be relatively large (for example, infinite), that is, the input resistor is a high resistor. In this way, it helps the first field-effect transistor device Q1 to provide a large gain. An input voltage V i is applied to the input resistor R i , as Figure 11 shown.

[0087] The drain of the second field-effect transistor device Q2 is electrically connected to the first power supply terminal VDD1 and the base of the triode device T1 respectively. Further, in the Figure 11 embodiment shown, a current source I is provided between the drain of the second field-effect transistor device Q2 and the first power supply terminal VDD1.

[0088] The emitter of the triode device T1 is grounded, and the collector of the triode device T1 is electrically connected to the second power supply terminal VDD2 and the radio frequency output terminal (RF OUT) respectively.

[0089] In this embodiment, the second field-effect transistor device Q2 is configured as a single cascaded field-effect transistor. In other partial embodiments, the second field-effect transistor device Q2 is configured as multiple cascaded field-effect transistors. In this configuration, the following matching operations need to be carried out in combination with specific situations. For example, impedance matching, specifically using matching networks such as capacitors and inductors to form Π-type, L-type, and T-type; for another example, gain matching, specifically adjusting the working voltage and bias voltage of each stage of MOS transistor; for another example, load matching, specifically using inductors and capacitors for tuning. In addition, noise matching can also be carried out, specifically using an appropriate source impedance or inductors and capacitors to complete.

[0090] In this embodiment, the radio frequency power amplifier circuit may further include a first capacitor C1, a first inductor L1, and a second capacitor C2. Wherein, the first end of the first capacitor C1 is electrically connected to the collector of the triode device T1 and the second power supply terminal VDD2 respectively, the second end of the first capacitor C1 is electrically connected to the first end of the first inductor L1, the second end of the first inductor L1 is electrically connected to the first end of the second capacitor C2 and the radio frequency output terminal (RF OUT) respectively, and the second end of the second capacitor C2 is grounded. The first capacitor C1 is used to isolate direct current, and the second capacitor C2 is used to filter specific frequency signals (such as noise). As Figure 11 shown, in this embodiment, the first field effect transistor device Q1 is an NMOS transistor, and the second field effect transistor device Q2 is an NMOS transistor. It should be noted that in this embodiment, the first capacitor C1, the first inductor L1, and the second capacitor C2 are all externally disposed in the final stage unit 30. In other different embodiments, the first capacitor C1, the first inductor L1, and the second capacitor C2 may also be internally disposed in the final stage unit 30.

[0091] In other partial embodiments, when the second field effect transistor device Q2 is configured as multiple cascaded field effect transistors, that is, the drain of the second cascaded field effect transistor (i.e., the second cascaded MOS transistor) is electrically connected to the source of the third cascaded field effect transistor (i.e., the third cascaded MOS transistor), the drain of the third cascaded field effect transistor is electrically connected to the source of the fourth cascaded field effect transistor (i.e., the fourth cascaded MOS transistor), the drain of the fourth cascaded field effect transistor is electrically connected to the source of the fifth cascaded field effect transistor (i.e., the fifth cascaded MOS transistor), and so on, the drain of the (N - 1)th cascaded field effect transistor (i.e., the (N - 1)th cascaded MOS transistor) is electrically connected to the source of the Nth cascaded field effect transistor (i.e., the Nth cascaded MOS transistor). Such a cascading method can be achieved by means of Figure 6F shown. Of course, as in the above embodiment, the drain of the first field effect transistor device Q1 (here is the first cascaded field effect transistor) is electrically connected to the source of the second field effect transistor device Q2 (here is the second cascaded field effect transistor), and it can also be achieved by means of Figure 6F shown.

[0092] The above has introduced in detail a method for manufacturing a radio frequency power amplifier, the structure of a radio frequency power amplifier, and a radio frequency power amplifier circuit provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A method for preparing a radio frequency power amplifier, characterized in that Comprising: Providing a first wafer, on which a multi-stage cascaded field effect transistor structure is formed, wherein the first wafer is a silicon-on-insulator wafer; Providing a second wafer, on which a silicon-germanium heterojunction bipolar transistor structure is formed, wherein the second wafer is a bulk silicon wafer; Bonding the multi-stage cascaded field effect transistor structure and the silicon-germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; Forming a metal wiring structure on the initial power amplifier structure, the metal wiring structure being electrically connected to a radio frequency input end and a radio frequency output end respectively to form a radio frequency power amplifier; Wherein, the second wafer includes a second semiconductor layer, and a collector layer is formed in the second semiconductor layer; Wherein, the formation of the silicon-germanium heterojunction bipolar transistor structure includes: Forming a silicon-germanium crystal layer on the collector layer as the base of the silicon-germanium heterojunction bipolar transistor; Forming a second polysilicon layer with a pattern opening on the second semiconductor layer, the pattern opening exposing a part of the surface of the silicon-germanium crystal layer; Depositing a third dielectric layer on the second polysilicon layer and the silicon-germanium crystal layer, and forming a through contact window in the third dielectric layer; filling a third polysilicon layer in the contact window, the third polysilicon layer being in contact with the silicon-germanium crystal layer to form the emitter of the silicon-germanium heterojunction bipolar transistor.

2. The preparation method according to claim 1, characterized in that, The providing the first wafer includes: Providing a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate including a first semiconductor substrate and a first semiconductor layer stacked, the first semiconductor layer including a plurality of device regions, wherein the device regions are used to form field effect transistor devices; Performing ion implantation at a first position and a second position of each of the device regions respectively to form a well region at each of the first positions and a doped region at each of the second positions, wherein the doping types of the well region and the doped region in the same device region are opposite; Forming a first polysilicon layer on a side of each of the well regions facing away from the first semiconductor substrate, and the doping type of each of the first polysilicon layers is opposite to that of the corresponding well region; Depositing metal on a side of each of the doped regions and each of the first polysilicon layers facing away from the first semiconductor substrate to form a first metal silicide layer; Forming a first dielectric layer covering the first metal silicide layer and the first semiconductor layer, the first dielectric layer having a first contact hole, the first contact hole penetrating through the first dielectric layer and being in contact with the surface of the first metal silicide layer to connect the source electrode, drain electrode and gate electrode of the field effect transistor device; Forming a second dielectric layer on a side of the first dielectric layer facing away from the first semiconductor substrate, and forming a first metal interconnection structure in the second dielectric layer, the first metal interconnection structure being used to be electrically connected to the source electrode, drain electrode and gate electrode of the field effect transistor device.

3. The preparation method according to claim 2, characterized in that, Before performing ion implantation at the first position and the second position of each of the device regions respectively to form a well region at each of the first positions and a doped region at each of the second positions, the manufacturing method further includes: forming a first trench isolation region around the device regions of the first semiconductor layer.

4. The preparation method according to claim 3, characterized in that, The first trench isolation region is also located between a first device region and a second device region of the first semiconductor layer, and doping types of the doped regions in the first device region and the second device region are opposite to each other.

5. The preparation method according to claim 2, characterized in that, Before forming the first polysilicon layer on a side of each of the well regions facing away from the first semiconductor substrate, the manufacturing method further includes: forming a gate oxide layer on the side of each of the well regions facing away from the first semiconductor substrate.

6. The preparation method according to claim 1, characterized in that, The providing the second wafer includes: providing a second semiconductor substrate; forming a second semiconductor layer on the second semiconductor substrate, and forming a heavily doped collector layer in the second semiconductor layer to obtain a collector of a silicon germanium heterojunction bipolar transistor; forming a second metal silicide layer in contact with the second polysilicon layer and the third polysilicon layer; forming a fourth dielectric layer covering the second metal silicide layer and the third dielectric layer, and forming a second contact hole penetrating through the fourth dielectric layer, where the second contact hole is in contact with the second metal silicide layer.

7. The preparation method according to claim 1, characterized in that, The forming the metal wiring structure on the initial power amplifier structure includes: forming a fifth dielectric layer on a side of the initial power amplifier structure facing away from the first semiconductor substrate; forming a metal wiring structure located in the fifth dielectric layer and the initial power amplifier structure, where the metal wiring structure is electrically connected to a gate terminal of the multi-stage cascaded field effect transistor structure and a radio frequency input terminal, and is also electrically connected to a collector terminal and a radio frequency output terminal of the silicon germanium heterojunction bipolar transistor.

8. A radio frequency power amplifier structure, characterized in that, The radio frequency power amplifier structure includes: a first semiconductor substrate; a first semiconductor layer located above the first semiconductor substrate, where the first semiconductor layer includes a plurality of device regions, each of the device regions has a well region and a doped region, a first polysilicon layer is disposed above each of the well regions, and a first metal silicide layer is disposed above each of the doped regions and each of the first polysilicon layers; a first dielectric layer located above the first semiconductor layer, where the first dielectric layer covers the first metal silicide layer and the first semiconductor layer, and the first dielectric layer has a penetrating first contact hole, and the first contact hole is in contact with a surface of the first metal silicide layer to connect a source electrode, a drain electrode, and a gate electrode of a field effect transistor device; a second dielectric layer located above the first dielectric layer, where the second dielectric layer has a first metal interconnection structure, and the first metal interconnection structure is electrically connected to the first contact hole; a fourth dielectric layer located above the second dielectric layer, where the fourth dielectric layer has a second metal silicide layer and a penetrating second contact hole, and the second contact hole is used for electrically connecting the second metal silicide layer and the first metal interconnection structure; a third polysilicon layer and a second polysilicon layer are respectively disposed above the second metal silicide layer; and the third polysilicon layer is used for forming an emitter of a silicon germanium heterojunction bipolar transistor. A second semiconductor layer, located above the fourth dielectric layer, the second semiconductor layer having a silicon-germanium crystal layer and a collector layer arranged in a stacked manner, the silicon-germanium crystal layer being configured to form the base of the silicon-germanium heterojunction bipolar transistor, and the collector layer being configured to form the collector of the silicon-germanium heterojunction bipolar transistor; A fifth dielectric layer, located above the second semiconductor layer, the fifth dielectric layer having a metal wiring structure, the metal wiring structure being electrically connected to the gate terminal of the field effect transistor device and the radio frequency input terminal, and being electrically connected to the collector terminal of the silicon-germanium heterojunction bipolar transistor and the radio frequency output terminal.

9. A radio frequency power amplifier circuit, characterized in that, The radio frequency power amplifier circuit includes: An input unit, the input unit being configured as a field effect transistor common-source amplifier, the field effect transistor common-source amplifier including a first field effect transistor device; An intermediate unit, the intermediate unit being coupled to the input unit, the intermediate unit being configured as a field effect transistor common-gate amplifier, the field effect transistor common-gate amplifier including a second field effect transistor device; the second field effect transistor device being configured as at least one cascaded field effect transistor; A final stage unit, the final stage unit being coupled to the intermediate unit, the final stage unit including a triode device, the triode device being a silicon-germanium heterojunction bipolar transistor; Wherein, the first field effect transistor device and the second field effect transistor device are formed by the device regions of the first semiconductor layer described in claim 8, and the silicon-germanium heterojunction bipolar transistor is formed by the stacked silicon-germanium crystal layer and the collector layer of the second semiconductor layer described in claim 8.

10. The radio frequency power amplifier circuit according to claim 9, wherein, The source of the first field effect transistor device is grounded, the drain of the first field effect transistor device is electrically connected to the source of the second field effect transistor device, the gate of the first field effect transistor device is electrically connected to an input resistor, and the resistance value of the input resistor is greater than a preset resistance value; The drain of the second field effect transistor device is electrically connected to the first power supply terminal and the base of the triode device respectively; The emitter of the triode device is grounded, and the collector of the triode device is electrically connected to the second power supply terminal and the radio frequency output terminal respectively.

Images