Method of manufacturing semiconductor structure

Abstract

A method of fabricating a semiconductor structure includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through silicon vias are connected in parallel. A second plurality of through silicon vias is merged into a large through silicon via to produce a second layout of the wafer.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of manufacturing semiconductor structures. Background Art

[0002] Through-silicon vias (TSVs) are used as electrical paths in a device die so that conductive features on opposite sides of the device die can be interconnected. The formation process of the TSVs may include etching a semiconductor substrate to form an opening, filling the opening with a conductive material to form the TSV, performing a backside grinding process to remove a portion of the semiconductor substrate from the backside and expose the TSV, and forming an electrical connector on the backside of the semiconductor substrate to connect to the TSV. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising: finding a first plurality of through-silicon vias from a first layout of a wafer; finding a second plurality of through-silicon vias from the first plurality of through-silicon vias, wherein the second plurality of through-silicon vias are connected in parallel; and merging the second plurality of through-silicon vias into a large through-silicon via to produce a second layout of the wafer.

[0004] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising: providing a first layout, the first layout comprising a first plurality of through-holes and a second plurality of through-holes, wherein the first plurality of through-holes and the second plurality of through-holes have the same top-view size; generating a second layout, wherein generating the second layout comprises merging the first plurality of through-holes to generate large through-holes in the second layout, and wherein the second plurality of through-holes remain as discrete through-holes in the second layout; and manufacturing a wafer implementing the second layout.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising: finding a first plurality of through-holes from a first layout of an integrated circuit, wherein, in the first layout, the first plurality of through-holes are in contact with metal pads; merging the first plurality of through-holes to form a large through-hole and generating a second layout; finding a second plurality of through-holes from the first layout, wherein, in the first layout, the second plurality of through-holes are in contact with a plurality of metal pads, and wherein, in the second layout, the second plurality of through-holes are discrete through-holes; and manufacturing the large through-holes and the second plurality of through-holes in a wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1AA cross-sectional view of a device die including through silicon vias (TSVs) is shown in accordance with some embodiments.

[0008] Figure 1B A cross-sectional view of a device die including merged through-silicon vias (TSVs) is shown in accordance with some embodiments.

[0009] Figure 2A , Figure 2B and Figure 2C A process for merging TSV cells according to some embodiments is shown.

[0010] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Screening of TSVs for merging is shown in accordance with some embodiments.

[0011] Figure 4A and Figure 4B Some TSVs to be merged and some TSVs not to be merged are shown according to some embodiments.

[0012] Figure 5 Merged and unmerged TSVs are shown in accordance with some embodiments.

[0013] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H Screening for merging TSVs and some merged TSVs according to some embodiments is shown.

[0014] Fig. 7A and Figure 7B A top view and a cross-sectional view are shown, respectively, of a merged TSV and corresponding package in accordance with some embodiments.

[0015] Figure 8-Figure 10 The formation of TSVs by a via-first process is shown in accordance with some embodiments.

[0016] Figure 11-13 The formation of TSVs by a through-the-middle via process is shown in accordance with some embodiments.

[0017] Figure 14-16 The formation of TSVs by a via last process is shown in accordance with some embodiments.

[0018] Figure 17-Figure 21 A diagram illustrating a package that may employ merged TSVs in accordance with some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0021] A method for determining and merging through-silicon vias (TSVs) and the resulting structure are provided. According to some embodiments of the present disclosure, a first layout of a wafer including a TSV layout is provided. TSVs that meet certain predetermined criteria are determined. The determined TSVs are then merged to form a second layout of a wafer including the merged TSVs. Wafers including large TSVs are then manufactured. By merging TSVs, the resistance of the TSVs is reduced without violating design rules and without spending more chip area. The embodiments discussed herein are intended to provide examples of the subject matter of the present disclosure that can be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of different embodiments. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0022] Figure 1A 2 shows a cross-sectional view of wafer 20. It can be understood that Figure 1A The wafer 20 shown may be manufactured as a physical entity. Figure 1AThe wafer 20 and the components therein discussed may be a physical entity that is laid out and manufactured. Alternatively, the wafer 20 is laid out but not manufactured as a physical entity. Therefore, the wafer 20 and the components therein discussed below may be a layout of the wafer 20 but not a physical wafer.

[0023] like Figure 1A As shown, the layout of TSVs and / or TSV cells in the wafer 20 is modified, and the resulting modified layout is implemented as a physical entity and in a physical wafer through manufacturing. The wafer 20 manufactured by the modified layout is as shown in FIG. Figure 1B Therefore, refer to Figure 1B The wafer 20 and components therein discussed may be physical entities that are laid out and manufactured.

[0024] According to some embodiments of the present disclosure, wafer 20 is or includes a device wafer that includes active devices and possibly passive devices, which are represented as integrated circuit devices 26. Wafer 20 may include a plurality of chips / dies 22 therein, of which one of chips 22 is shown. According to alternative embodiments of the present disclosure, wafer 20 is an interposer wafer without active devices and may or may not include passive devices.

[0025] According to some embodiments of the present disclosure, the wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 24 to isolate an active region of the semiconductor substrate 24.

[0026] According to some embodiments of the present disclosure, wafer 20 includes integrated circuit devices 26 formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown here. According to an alternative embodiment, wafer 20 is used to form an interposer (which does not have active devices).

[0027] An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, fluorine-doped silicate glass, etc. The ILD 28 can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present disclosure, the ILD 28 can also be formed using deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0028] Contact plug 30 is formed in ILD 28 for electrically connecting integrated circuit device 26 to overlying metal lines and vias. According to some embodiments of the present disclosure, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plug 30 may include forming a contact opening in ILD 28, filling the contact opening with a conductive material, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0029] An interconnect structure 32 is formed over the ILD 28 and the contact plugs 30. The interconnect structure 32 includes metal lines 34 and vias 36, which are formed in a dielectric layer 38 (also referred to as an intermetallic dielectric (IMD)) and an etch stop layer 37. Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments of the present disclosure, the interconnect structure 32 includes a plurality of metal layers, which include metal lines 34 interconnected by vias 36. The metal lines 34 and vias 36 may be formed of copper or a copper alloy, or may be formed of other metals.

[0030] According to some embodiments of the present disclosure, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.5. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methylsiloxane (MSQ), etc. Etch stop layer 37 is formed below the corresponding dielectric layer 38 and may be formed of aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, etc. or a multilayer thereof or include the above-mentioned materials.

[0031] Forming metal lines 34 and vias 36 in dielectric layer 38 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 38, and then the trench or via opening is filled with a conductive material. A planarization process such as a CMP process is then performed to remove excess portions of the conductive material above the top surface of the dielectric layer, leaving metal lines or vias in the corresponding trenches or via openings. In a dual damascene process, trenches and via openings are formed in the dielectric layer, and the via openings are located below the trenches and connected to the trenches. Conductive materials are then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0032] Metal line 34 includes a top conductive (metal) feature, such as a metal line, metal pad, or via (denoted as 34T) in a top dielectric layer (denoted as dielectric layer 38T), which is the topmost layer in dielectric layer 38. According to some embodiments, the low-k dielectric material constituting top dielectric layer 38T is similar to the material constituting the lower dielectric layers in dielectric layer 38. Metal feature 34T in top dielectric layer 38T may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0033] According to some embodiments, an etch stop layer 40 is deposited on the top dielectric layer 38T and the top metal layer. The etch stop layer 40 may be formed of or include silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, or the like.

[0034] A passivation layer 42 (sometimes referred to as passivation-1 or pass-1) is formed on the etch stop layer 40. According to some embodiments, the passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than that of silicon oxide. The passivation layer 42 may be formed of or include an inorganic dielectric material, which may include a material selected from (but not limited to) undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), etc., combinations thereof, and / or multilayers thereof. According to some embodiments, the top surfaces of the top dielectric layer 38T and the metal line 34 are flush with each other. Therefore, the passivation layer 42 may be a planar layer.

[0035] According to some embodiments, a via 44 is formed in the passivation layer 42 and the etch stop layer to electrically connect to the top metal feature 34T below. A metal pad 46 is further formed above the via 44. According to some embodiments, the metal pad 46 includes aluminum, aluminum copper, etc. A passivation layer 48 (sometimes referred to as passivation-2 or pass-2) is also formed, and the passivation layer 48 may extend on the sidewalls and top surface of the metal pad 46. The passivation layer 48 may be formed of or include silicon oxide, silicon nitride, etc. or multiple layers thereof.

[0036] According to some embodiments, dielectric layer 50 is formed, for example, by dispensing a polymer in a flowable form and then curing the polymer layer. Dielectric layer 50 is patterned to expose metal pad 46. When dielectric layer 50 is formed of a polymer, dielectric layer 50 may be formed of or include polyimide, polybenzoxazole (PBO), or the like. Alternatively, dielectric layer 50 may be formed of or include an organic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0037] Under bump metallization (UBM) 52 and bonding pad 54 are then formed to electrically connect to underlying metal pad 46. The formation process of UBM 52 and bonding pad 54 may include depositing a blanket metal seed layer extending into the openings of passivation layer 48 and dielectric layer 50, forming a patterned plating mask on the metal seed layer, plating the bonding pad, removing the plating mask, and etching the portion of the blanket metal seed layer previously covered by the plating mask. According to some embodiments, dielectric layer 56 is formed to have a top surface coplanar with the top surface of bonding pad 54 and may be used for hybrid bonding.

[0038] TSVs 60 (including TSVs 60A, 60B, 60C, and 60D) are formed to penetrate semiconductor substrate 24. Each of TSVs 60 is surrounded by a dielectric isolation layer 62, which electrically decouples the corresponding TSV 60 from semiconductor substrate 24. In the example embodiments discussed below, it is assumed that TSVs 60 extend to the bottom surface of top metal feature 34T. According to alternative embodiments, TSVs 60 may extend to any level, including the top surface of semiconductor substrate 24, the top surface of ILD 28, the top surface of any dielectric layer 38, or a level higher than top dielectric layer 38T.

[0039] Although not shown, the TSV 60 may be tapered with a top width greater than a corresponding bottom width, or a bottom width greater than a corresponding top width, depending on whether the TSV 60 is formed by a via first process, a via middle process, or a via last process, as will be described with reference to FIG. Figures 8 to 16 discussed.

[0040] On the back side of semiconductor substrate 24, a back side redistribution structure 68 is formed. In accordance with some embodiments, back side redistribution structure 68 includes a dielectric layer 70 and redistribution lines (RDL) 72. RDL 72 may include bonding pads, also referred to as bonding pads 72. Although one RDL layer is shown, back side redistribution structure 68 may include more RDL layers.

[0041] Figure 1A Also included is a package assembly 74 bonded to the device die 22 according to some embodiments. The package assembly 74 may be a device die (which may be a discrete device die that has been sawn from a wafer), or may be a portion of an unsawn wafer that includes multiple device dies. The package assembly 74 may include a bonding pad 76 bonded to the bonding pad 72 and a through-hole 78 connected to the bonding pad 76.

[0042] According to some embodiments, TSV 60A is a single TSV, which is not connected in parallel with any other TSV 60. TSV 60A can be used to conduct signals. TSV 60B, 60C and 60D are in a multi-TSV group, and when packaged and powered on at the corresponding package, TSV 60B, 60C and 60D are connected in parallel and conduct the same voltage and / or the same signal. According to some embodiments, the tops of TSV 60B, 60C and 60D are physically connected to the same top metal component (pad) 34T, so the tops are also electrically interconnected. According to alternative embodiments, the tops of TSV 60B, 60C and 60D are physically connected to different overlying metal components, and are indirectly interconnected through another overlying metal structure. According to some embodiments, TSV 60B, 60C and 60D are used to conduct power, such as VDD, electrical grounding, etc., which may be related to large currents.

[0043] According to some embodiments, as shown, the bottom ends of TSVs 60B, 60C, and 60D are physically connected to different bond pads 72, but are electrically interconnected through the same metal pad 80, which is located in package assembly 74 instead of in device die 22. According to some embodiments, the bond pad that electrically interconnects TSVs 60B, 60C, and 60D may also be a backside interconnect structure 68 of wafer 20.

[0044] According to some embodiments, each of TSVs 60A, 60B, 60C, and 60D is surrounded by a guard ring 64 that completely surrounds the corresponding TSV 60 when viewed from the top. According to some embodiments, each guard ring 64 includes a metal ring in each of the metal layers and via layers through which it extends. The metal rings in multiple via layers and multiple metal layers are interconnected to form a solid metal ring. Throughout the description, guard rings 64 and TSVs surrounded by guard rings 64 are collectively referred to as TSV cells 65. Example TSV cells 65 are shown in FIG. Figure 4A , Figure 4B and Figure 5 shown.

[0045] According to some embodiments, the topmost portion of guard ring 64 is located in a metal layer below the top of TSV 60. For example, as shown, when TSV 60 extends to the bottom of the top metal layer, guard ring 64 includes a portion in the metal layer immediately below the top metal layer and a portion in the metal below. According to some embodiments, guard ring 64 includes a contact plug portion in ILD 28 and is at the same level as contact plug 30. There may or may not be a metal silicide ring below the contact plug portion of guard ring 64. According to alternative embodiments, guard ring 64 has a bottommost surface that is higher than ILD 28. Guard ring 64 may be electrically grounded.

[0046] The area separating each guard ring 64 from the corresponding surrounding TSV 60 is called a first buffer zone. Adjacent guard rings 64 are also separated from each other by a second buffer zone. The width W1A of the first buffer zone and the spacing S1A of the second buffer zone need to be greater than certain critical values ​​so that problems such as electrical short circuits do not occur. Retaining the buffer zone results in the chip area available for TSV 60 being limited, and it is difficult to form a large TSV. Since it is difficult to increase the lateral size of the TSV, the resistance of the TSV is therefore difficult to reduce.

[0047] Figure 2A , Figure 2B and Figure 2C Intermediate stages are shown: screening TSV cells, finding candidate TSV cells that meet certain criteria, and redesigning the found TSV layouts to increase the top-view area of ​​the resulting TSVs in the candidate TSV cells without increasing the chip area. Figure 2A , Figure 2B and Figure 2C The TSV cells shown in are candidate TSV cells to be merged. These components are labeled using the legend.

[0048] refer to Figure 2A , showing a plurality of TSV cell groups 80A, 80B, and 80C. The TSV cell groups may be located Figure 1A Each of the TSV cell groups 80A, 80B, and 80C includes an array of TSV cells 65. The TSV cell groups 80A, 80B, and 80C include a 2x1 array (with two rows and one column), a 2x2 array (with two rows and two columns), and a 1x2 array (with one row and two columns).

[0049] Figure 2BTSV cells 80A′, 80B′, and 80C′ are shown, each including a guard ring 64 and a plurality of TSVs 60 therein. Similarly, TSV cells 80A′, 80B′, and 80C′ include a 1×2 array, a 2×2 array, and a 2×1 array of TSVs 60 . Figure 2B It can also be redesigned Figure 2A An intermediate stage of the layout of FIG. 8 is shown in FIG. 1 , wherein the respective guard rings in the same TSV cell group 80A′, 80B′, or 80C′ are removed and replaced with a merged large guard ring 64′ that surrounds all TSVs 60 (whose guard rings have been removed).

[0050] Figure 2C 1 shows a merged TSV 60' according to some embodiments. The merged TSV 60' also has a first buffer zone between the TSV 60' and the corresponding surrounding guard ring 64' and a second buffer zone between adjacent guard rings 64'. According to some embodiments, the width W1A' of the first buffer zone is equal to or greater than the width W1A of the first buffer zone ( Figure 2A The width S1A' of the second buffer zone may also be equal to or greater than the spacing S1A of the second buffer zone ( Figure 2A ).

[0051] According to some embodiments, when the layout of the TSV is modified, the chip area occupied by the TSV is not modified. For example, the outline width W2 ( Figure 2A ) can be equal to or less than Figure 2B and Figure 2C The width W2 of the TSV unit 65 to be merged is L2 ( Figure 2A ) can be equal to or less than Figure 2B and Figure 2C Keeping the area and size of the TSV unchanged or smaller has the advantage of not changing the layout of the surrounding components, overlying components, and underlying components. This will significantly reduce the complexity of redesign.

[0052] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Some examples are shown showing criteria for finding (determining) candidate TSV cells to be merged according to some embodiments. Some TSVs are grouped and shown as being surrounded by dashed boxes, and an "O" symbol may be placed near the dashed boxes to indicate that the TSVs in the corresponding boxes can be merged. An "X" symbol may be placed near the dashed boxes to indicate that the TSVs in the corresponding boxes cannot be merged. Although not shown, each of the TSVs 60 in these components may be surrounded by a guard ring. Therefore, the TSVs 60 shown represent corresponding TSV cells 65.

[0053] The TSV cells to be merged are connected in parallel so they always have the same voltage. Figure 3A As shown, the two TSV cells in the dashed box 82A that can be merged are connected to the same metal component 34T1, while the two TSV cells in the dashed box 82B are connected to two different metal components 34T1 and 34T2, which are electrically decoupled from each other and can carry different voltages. Therefore, the two TSV cells in the dashed box 82B will not be merged.

[0054] The TSVs to be merged cannot extend too far. According to some embodiments, for the TSV array to be merged, the counts of TSVs in rows and columns are equal to or less than the critical count. According to some embodiments, the critical count is 2, so TSVs forming a 1×2 array, a 2×2 array, and a 2×1 array can be merged, while TSVs in a larger TSV array may not be merged. According to alternative embodiments, the critical count may also be slightly greater than 2, for example, equal to 3. Figure 3B In FIG. 8 , when the critical count is equal to 2, the two TSVs in the dashed box 82C1 can be merged, the two TSVs in the dashed box 82C2 can be merged, and the four TSVs in the dashed box 82D will not be merged into one TSV, although they can be merged into two large TSVs. Maintaining the critical count will ensure that the merged TSVs do not have too large an area (which may cause problems due to excessive pattern loading effects).

[0055] Figure 3C An example is shown in which three TSVs 60 are connected to the same metal feature 34T1. According to some embodiments, the two TSVs in the dashed box 82E will be merged, while the TSVs 60 outside the dashed box 82E are not merged. Figure 3C As shown, three TSVs 60 are connected to the same metal feature 34T2 and are represented by dashed box 82F. According to some embodiments with a critical count of 2, these three TSVs will not be merged into a single large TSV and may remain as discrete TSVs.

[0056] Figure 3D Six TSVs 60 are shown connected to the same metal feature 34T1. According to some embodiments, the six TSVs 60 are divided into a 2x2 array (as shown in dashed box 82G) and a 1x2 array (as shown in dashed box 82H). Four TSVs 60 in the same dashed box 82G can be merged together to form a large TSV, and two TSVs 60 in the same dashed box 82H can be merged together to form a large TSV. Figure 3DAs shown, six more TSVs 60 are connected to the same metal feature 34T2. The six TSVs 60 in the same dashed box 82I will not all be merged together. However, these TSVs 60 can be merged like the TSVs in dashed boxes 82G and 82H, or can remain as discrete TSVs.

[0057] Figure 3E Some embodiments are shown in which the spacing between some TSVs is too large and greater than a predetermined threshold. According to some embodiments, assuming that the diameter (or lateral width or length if the TSV is not circular) of TSV 60 is equal to D1, and the pitch of adjacent TSVs 60 is equal to P, when the ratio P / D1 of the pitch P relative to the diameter D1 is greater than a critical ratio, the TSVs 60 will not be merged. Otherwise, the TSVs 60 may be merged. According to some embodiments, the ratio P / D1 is equal to about 2 (or may be set to a value greater than 1 and less than 2) as a critical value. In Figure 3E In the example shown, assuming that the ratio P1 / D1 is greater than the critical ratio and the ratio P2 / D1 is less than the critical ratio, the TSVs 60 in the dashed box 82J will not be merged, and the TSVs 60 in the dashed box 82K will be merged.

[0058] In addition to reference Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Outside of the discussed criteria, the TSVs to be merged have no other conductive features between them and at the same level as them.

[0059] In addition, the priority of merging can be determined, and merging can be performed based on the priority. For example, if merging more TSVs has the highest priority, then Figure 3D As shown, the four TSVs in the dashed box 82G are merged into one large TSV, and the remaining two TSVs in the dashed box 82H are merged into one large TSV.

[0060] However, if merging horizontally positioned TSVs has the highest priority, the two top TSVs in the dashed box 82G are merged into one large TSV, and the two bottom TSVs in the dashed box 82H are merged into one large TSV. The two TSVs in the dashed box 82H are also merged into one large TSV.

[0061] When merging vertically positioned TSVs has the highest priority, the two left TSVs in the dashed box 82G are merged into one large TSV, and the two right TSVs in the dashed box 82G are merged into one large TSV. The two TSVs in the dashed box 82H are also merged into one large TSV. Examples of different types of priorities and corresponding merged TSVs are shown in FIG. Fig. 6F , Figure 6G and Figure 6H is shown as an example and will be discussed later.

[0062] Figure 4A , Figure 4B and Figure 5 The TSVs (and TSV cells) to be merged and the resulting merged TSVs and TSV cells are shown according to some embodiments. These components are labeled using the legend. Figure 4A , showing a plurality of TSVs 60 (marked with legends), a guard ring 64, and corresponding metal features 34T. The first column 1 of the TSV cells 65 is separated from the second column 2 of the TSV cells by the metal feature 34T. The third column 3 of the TSV cells 65 is divided into two groups, and the TSV cells 65 of each group are closely positioned with a corresponding pitch to diameter P / D ratio less than the critical ratio. The pitch to diameter P / D ratio of the TSV cells 65 in the adjacent group is greater than the critical ratio. The fourth column 4 of the TSV cells 65 is spaced far apart, and the corresponding pitch to diameter P / D ratio is greater than the critical ratio. Another four TSV cells 65 are arranged in an array 1 and are closely positioned. Another two TSV cells 65 are closely positioned to each other and form a row 1.

[0063] Figure 4B An alternative layout is shown in which closely positioned TSVs 60 are surrounded by the same guard ring 64. This layout may also be from Figure 4A The modified intermediate layout modified from the layout in .

[0064] Figure 5 Shows from Figure 4A and / or Figure 4B The layout shown is modified from the layout in which the TSVs 60 are merged into large TSVs, and the guard rings 64 may also be merged. According to some embodiments, the 2×2 array TSVs are merged into large circular TSVs. The 1×2 array TSVs and the 2×1 array TSVs are merged into oval TSVs so that their size increases while the width of the resulting buffer zone can remain unchanged.

[0065] Figure 1B 2 shows a cross-sectional view of a fabricated wafer 20 and device die 22, wherein a modified layout includes merged TSVs and merged TSV cells. Figure 1B As shown, Figure 1A The layout of TSVs 60C and 60D shown is modified and merged to form Figure 1B The large TSV 60C' shown in Figure 1B In the example structure shown, TSVs 60A and 60B are not merged and may have a circular top view shape. The top view shape of TSV 60C' may be an ellipse, such as Figure 5 shown. Figure 1B The layout of TSVs 60B and 60C' shown can be obtained from Figure 6C The cross section 1B-1B of FIG. 1 is obtained, which will be discussed later. TSVs 60B and 60C′ carry the same voltage and are connected in parallel.

[0066] According to some embodiments, Figure 1B The layout of the structure shown in Figure 1A The layout of the structure shown in is the same as that in Figure 1A Some TSVs in the structure shown are incorporated into Figure 1B The TSV shown in Figure 1 and the corresponding guard ring are also merged. Figure 1B Components around, above, and below the TSV Figure 1A The corresponding parts in are the same.

[0067] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E It is shown that the TSVs that can be merged have been merged. Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E Corresponding to Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E . These components are labeled using the legend. It should be understood that due to the criteria described above, some of the merged TSVs are electrically connected to the same conductive component 34T and may sometimes be in physical contact with the same conductive component 34T. Therefore, adjacent TSVs connected to the same conductive component 34T may have different sizes and / or different shapes.

[0068] Fig. 6F The merged TSVs are shown, with merging more TSVs being the highest priority. Figure 6G The merged TSVs are shown, where merging horizontally positioned TSVs is the highest priority. Figure 6H Merged TSVs are shown, where merging vertically positioned TSVs is the highest priority.

[0069] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6HThe merging scheme shown can be performed for the same layout and can be manufactured in any combination on the same wafer. 6A to 6H The corresponding large TSVs and single TSVs shown in FIG. 5 may be present in any combination in the same wafer and the same device die.

[0070] The merged TSVs and unmerged TSVs discussed in accordance with the embodiments of the present application are fabricated on semiconductor wafers that are sawn into discrete device dies and packaged in various types of packages. Fig. 7A Schematically illustrates a cross-sectional view of a package including merged TSVs according to some embodiments. Package 86 includes a supporting silicon substrate without active and passive devices. Package 86 also includes a dummy die 88 formed of silicon and may also not include active and passive devices. Dummy die 88 and top device die 74 (see also Figure 1A and Fig. 7A ) (including bonding pads 76, dummy bonding pads 76' and metal lines 80) are encapsulated in gap fill material 89. Device die 22 is located below device die 74 and is bonded to the device die through bonding pads 72 and dummy bonding pads 72'. Unmerged TSV 60A and merged TSV 60C' are also formed to connect to bonding pads 72 and 76.

[0071] like Fig. 7A The cross-section shown is from Figure 7B The cross section 7A-7A in Fig. Figure 7B A top view of dummy bond pads 72' / 76', active bond pads 72 / 76, unmerged TSVs 60A, and merged TSVs 60C' is shown. The circular pattern in merged TSVs 60C' shows the shape of the TSVs that would have been formed if the TSVs were not merged.

[0072] The merged and unmerged TSVs according to the embodiments of the present disclosure may be formed by any one of a via first process, a via middle process, and a via last process. Figure 8 , Fig. 9 and Fig.10 A schematic process of forming TSVs by a through-hole first process is shown. Figure 8 The formation of via openings 60A" and 60C" extending into semiconductor substrate 24 is shown. The locations where TSVs 60C and 60D would have been formed are as shown. Fig. 9 The formation of TSVs 60A and 60C' is shown, as well as the formation of front-end-of-line (FEOL) structures such as integrated circuit device 26 after the formation of TSVs 60A and 60C'. Back-end-of-line (BEOL) structures 34 / 36 / 38 including metal lines 34, vias 36, and dielectric layer 38 are then formed. Fig.10The bonding of another component, such as a carrier 89 , to the underlying device wafer 20 is shown.

[0073] Fig.11 , Fig.12 and Fig.13 The formation of vias is shown by an intermediate via process, where TSVs 60A and 60C′ are formed after the formation of FEOL structure 26 and before the BEOL structures 34 / 36 / 38 .

[0074] Fig.14 , Fig.15 and Fig.16 The vias formed by a via last process are shown, where TSVs 60A and 60C' are formed after the FEOL structure 26 is formed and after the BEOL structures 34 / 36 / 38 are formed. TSVs 60A and 60C' are formed from the back side of semiconductor substrate 24.

[0075] Figures 17 to 21 Some example packages are shown where both merged and unmerged TSVs may be employed. Fig.17 Shown with Fig. 7A The package is similar to the package in the , which includes a supporting substrate, a dummy die, a top die and a bottom die. The top die is bonded to the bottom die by face-to-back bonding. Fig.18 The package is shown with a top die bonded to a bottom die via face-to-face bonding. Fig.19 A package including a bridge die 90 is shown. Fig. 20 An Integrated Fan-Out (InFO) package is shown. Fig.21 Packages are shown that include multiple types of package components bonded to an interposer, where the interposer is further bonded to an integrated fan-out package.

[0076] In the above embodiments, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of a 3D package or 3DIC, using a probe and / or a probe card, and the like. Verification testing may be performed on both an intermediate structure and a final structure. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to increase yield and reduce cost.

[0077] Embodiments of the present disclosure have some advantageous features. By merging some closely positioned TSVs, the resistance of the TSVs can be reduced without increasing the chip area occupied by the TSVs. The manufacturing cost is not increased. When the resistance value of the TSVs is reduced, the occupied chip area can also be reduced, thereby freeing up some chip area for forming other circuits.

[0078] According to some embodiments of the present disclosure, a method includes: finding a first plurality of through-silicon vias from a first layout of a wafer; finding a second plurality of through-silicon vias from the first plurality of through-silicon vias, wherein the second plurality of through-silicon vias are connected in parallel; and merging the second plurality of through-silicon vias into a large through-silicon via to generate a second layout of the wafer. In one embodiment, in the first layout, each of the second plurality of through-silicon vias is surrounded by a guard ring, and wherein the method further includes merging the guard rings surrounding the second plurality of through-silicon vias into a large guard ring surrounding the large through-silicon via.

[0079] In one embodiment, the chip area occupied by the large guard ring is the same as the contour area of ​​the guard ring surrounding the second plurality of through-silicon vias. In one embodiment, the method further includes: implementing the second layout by a manufacturing process to manufacture a wafer, wherein the manufacturing process includes forming a large through-silicon via that penetrates a semiconductor substrate in the wafer. In one embodiment, the first plurality of through-silicon vias have the same shape and the same size, and the shape of the large through-silicon via is the same as one of the first plurality of through-silicon vias and is larger than one of the first plurality of through-silicon vias. In one embodiment, the first plurality of through-silicon vias have a circular top-view shape, and the large through-silicon via has an elliptical top-view shape.

[0080] In one embodiment, in the first layout, the second plurality of through silicon vias are bonded to the same metal pad. In one embodiment, the method further comprises: finding a third plurality of through silicon vias from the first plurality of through silicon vias, wherein the second plurality of through silicon vias are connected in parallel with the third plurality of through silicon vias; and merging the third plurality of through silicon vias into additional large through silicon vias in the second layout of the wafer. In one embodiment, the first total count of the second plurality of through silicon vias is equal to the second total count of the third plurality of through silicon vias.

[0081] In one embodiment, the first total count of the second plurality of through silicon vias is greater than the second total count of the third plurality of through silicon vias. In one embodiment, the method further comprises implementing a second layout to manufacture a wafer, wherein, in the wafer, the large through silicon via and the additional large through silicon via are in physical contact with the metal pad. In one embodiment, the method further comprises: finding an additional through silicon via from the first plurality of through silicon vias, wherein in the second layout, the additional through silicon via is physically separated from the large through silicon via and connected in parallel.

[0082] According to some embodiments of the present disclosure, a method includes: providing a first layout, the first layout including a first plurality of through-holes and a second plurality of through-holes, wherein the first plurality of through-holes and the second plurality of through-holes have the same top-view size; generating a second layout, wherein generating the second layout includes merging the first plurality of through-holes to generate large through-holes in the second layout, and wherein the second plurality of through-holes remain as discrete through-holes in the second layout; and manufacturing a wafer implementing the second layout.

[0083] In one embodiment, in the wafer, the first plurality of through-vias are bonded to the same metal pad, and wherein the same metal pad has the same size and shape in the first layout and the second layout. In one embodiment, generating the second layout further comprises merging the guard rings around the first plurality of through-vias to form a large guard ring around the large through-via. In one embodiment, the large through-via has a top-view area that is larger than the total area of ​​the first plurality of through-vias. In one embodiment, the top-view area of ​​the large guard ring is the same as the contour area of ​​the guard ring around the first plurality of through-vias.

[0084] According to some embodiments of the present disclosure, a method includes: finding a first plurality of through-vias from a first layout of an integrated circuit, wherein, in the first layout, the first plurality of through-vias are in contact with metal pads; merging the first plurality of through-vias to form a large through-via and generating a second layout; finding a second plurality of through-vias from the first layout, wherein, in the first layout, the second plurality of through-vias are in contact with a plurality of metal pads, and wherein, in the second layout, the second plurality of through-vias are discrete through-vias; and manufacturing the large through-via and the second plurality of through-vias in a wafer.

[0085] In one embodiment, the first layout further comprises an additional through via in contact with the metal pad, and wherein, in the wafer, the additional through via and the large through via are separate through vias connected in parallel. In one embodiment, the second plurality of through vias are arranged in rows.

[0086] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Finding a first plurality of through silicon vias from a first layout of a wafer; Finding a second plurality of through-silicon vias from the first plurality of through-silicon vias, wherein the second plurality of through-silicon vias are connected in parallel; and The second plurality of through silicon vias are merged into a large through silicon via to produce a second layout of the wafer.

2. The method according to claim 1, wherein: In the first layout, each of the second plurality of through silicon vias is surrounded by a guard ring, and wherein the method further comprises merging the guard rings surrounding the second plurality of through silicon vias into a large guard ring surrounding the large through silicon via.

3. The method according to claim 2, wherein: The large guard ring occupies the same chip area as a contour area of ​​the guard ring surrounding the second plurality of through-silicon vias.

4. The method according to claim 1, wherein: The first plurality of through silicon vias have the same shape and the same size, and the large through silicon via has the same shape as one of the first plurality of through silicon vias and is larger than one of the first plurality of through silicon vias.

5. The method according to claim 1, wherein: In the first layout, the second plurality of through silicon vias are bonded to the same metal pad.

6. The method according to claim 1, further comprising: Finding a third plurality of through-silicon vias from the first plurality of through-silicon vias, wherein the second plurality of through-silicon vias are connected in parallel with the third plurality of through-silicon vias; and The third plurality of through silicon vias are merged into additional large through silicon vias in the second layout of the wafer.

7. The method according to claim 1, further comprising: An additional through-silicon via is found from the first plurality of through-silicon vias, wherein the additional through-silicon via is physically separated from the large through-silicon via and connected in parallel in the second layout.

8. A method for manufacturing a semiconductor structure, comprising: A first layout is provided, the first layout comprising: a first plurality of through holes; a second plurality of through-holes, wherein the first plurality of through-holes and the second plurality of through-holes have the same top-view dimensions; generating a second layout, wherein generating the second layout includes merging the first plurality of through-vias to generate a large through-via in the second layout, and wherein the second plurality of through-vias remain as discrete through-vias in the second layout; and A wafer implementing the second layout is fabricated.

9. The method according to claim 8, wherein: In the wafer, the first plurality of through vias are bonded to a same metal pad, and wherein the same metal pad has a same size and shape in the first layout and the second layout.

10. A method for manufacturing a semiconductor structure, comprising: Finding a first plurality of through-vias from a first layout of the integrated circuit, wherein in the first layout, the first plurality of through-vias are in contact with the metal pads; merging the first plurality of through-vias to form a large through-via and generating a second layout; Finding a second plurality of through-vias from the first layout, wherein, in the first layout, the second plurality of through-vias contact a plurality of metal pads, and wherein, in the second layout, the second plurality of through-vias are discrete through-vias; and The large through via and the second plurality of through vias are fabricated in a wafer.

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