Dielectric structure with air gap and manufacturing method thereof
By adopting specific process steps in semiconductor manufacturing, including patterning the mask layer and selectively removing the dielectric layer, forming the dielectric trench and covering the dielectric cover layer, the air gap introduction process in the prior art is solved by damaging the conductive features and shapes of the air gap introduction process in the prior art. The problem of poor consistency achieves lower parasitic capacitance and higher electrical performance.
Patent Information
- Application Number
- CN202411445979.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-02-14
AI Technical Summary
The process sequences that introduce air gaps into existing interconnection processes are prone to damage to conductive features, and the geometric and dimensional consistency of the air gaps is poor.
By providing a substrate, a dielectric structure and a mask layer are formed, the patterned mask layer reveals a preset area of the dielectric structure, selectively removing the first dielectric layer to form a dielectric trench, covering the dielectric cover layer to form in the dielectric trench Air gap.
It effectively prevents the diffusion and migration of copper, reduces power consumption, improves the geometric parameter adjustment ability of the air gap, reduces the parasitic capacitance value, and simplifies the process flow.
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Figure CN119447026A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing; in particular, to a dielectric structure with an air gap and a manufacturing method thereof. Background Art
[0002] As the device size of integrated circuits continues to shrink and the density of integrated circuits continues to increase, the line width of interconnects and the size of through-hole contacts are getting smaller and smaller, and resistance-capacitance (RC) delay and crosstalk will negatively affect the performance of integrated circuits. RC delay and crosstalk are each affected by the capacitive coupling between adjacent conductive features. It has been recognized that by reducing the resistivity of metal interconnect materials and using interconnect dielectric materials with relatively low dielectric constants to weaken the capacitive coupling between adjacent conductive features, the RC delay of integrated circuits can be reduced.
[0003] At present, the common means to reduce the K value of interconnect dielectric materials is to construct porous ultra-low dielectric constant (pULK) materials by changing the chemical composition of the dielectric or by introducing porosity. Although materials with lower K values can be obtained, they require relatively high costs. Some patent documents also report that the low dielectric constant of air (K value ~ 1) is used to reduce the parasitic capacitance effect. By replacing part of the dielectric material with an air gap or a vacuum gap, the capacitance can be significantly reduced, and increasing the volume of the air gap or vacuum gap can effectively reduce the parasitic capacitance. Figures 1A to 1C Schematic diagram showing air gaps in interconnect structures with various geometric parameters. Figure 2 The following is a curve showing the relationship between the parasitic capacitance value of the interconnect structure with air gaps and the volume and damage depth of the air gaps obtained by simulation verification of the structure shown in FIG1. Figure 2 As shown, the parasitic capacitance value is inversely proportional to the volume of the air gap; specifically, when the volume of the air gap is larger, the parasitic capacitance value is lower.
[0004] In the existing interconnection process, air gaps or vacuum gaps are generally introduced into the interconnection dielectric material using photolithography and reactive ion etching processes. However, the existing interconnection structure often uses a Ta-based diffusion barrier layer. Since such a diffusion barrier layer will be removed during the ion etching process, it is very easy to cause undesirable damage to the interconnection structure, and an additional step is required to introduce a dielectric barrier layer. In addition, the shape consistency of the air gap formed in the existing process is poor.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an interconnect structure with an air gap and a method for manufacturing the same, so as to solve the problem that the process sequence used to introduce the air gap in the existing interconnect process is prone to damage the conductive characteristics, and the resulting air gap has poor geometric shape and size consistency.
[0007] To achieve the above object and other related objects, the present invention provides a method for manufacturing an interconnect structure with an air gap, comprising the following steps:
[0008] A substrate is provided, on which a dielectric structure and a mask layer are sequentially formed, wherein the dielectric structure at least comprises a first dielectric layer located at a side away from the substrate, and a conductive feature is formed through the dielectric structure, wherein the conductive feature comprises a metallization layer and a ruthenium-containing diffusion barrier layer for separating the metallization layer from the dielectric structure;
[0009] Patterning the mask layer to expose a first predetermined region of the dielectric structure and a first conductive feature within the first predetermined region;
[0010] Based on the patterned mask layer, the first dielectric layer within the first preset area is selectively removed by a wet etching process to form a dielectric trench defined by the ruthenium-containing diffusion barrier layer as a sidewall;
[0011] The patterned mask layer is removed to form a dielectric cover layer covering the first preset area, wherein the dielectric cover layer extends into the dielectric trench to enclose an air gap in the dielectric trench.
[0012] Optionally, the step of forming the conductive feature comprises:
[0013] patterning the first dielectric layer to form interconnect trenches penetrating the first dielectric layer;
[0014] forming a ruthenium-containing diffusion barrier layer on the inner surface of the interconnection trench;
[0015] forming a metallization layer filling the interconnect trench;
[0016] The ruthenium-containing diffusion barrier layer is formed by a physical vapor deposition process or an atomic layer deposition process; and the metallization layer is formed by an electrochemical plating process or an electroplating process or a combination thereof.
[0017] Optionally, the mask layer includes a hard mask layer and a photoresist layer stacked in sequence from the first dielectric layer upward, and the step of forming the patterned mask layer includes: patterning the hard mask layer by a wet etching process based on the opening defined in the developed photoresist layer; then, wet cleaning the patterned hard mask layer, and the exposed top surface of the first dielectric layer within the first preset area is lower than the top surface of the first conductive feature.
[0018] Optionally, before the step of selectively removing the first dielectric layer, the patterned mask layer covers the area outside the first preset area of the dielectric structure and the second conductive feature.
[0019] Optionally, the material of the hard mask layer is selected from one of silicon-containing oxides, nitrides, and oxynitrides; the first dielectric layer within the first preset area is selectively removed, and at the same time, the patterned hard mask layer is laterally corroded so that the opening defined in the patterned hard mask layer is expanded to partially expose the top surface of the second conductive feature.
[0020] Optionally, the ruthenium-containing diffusion barrier layer includes a single layer composed of ruthenium metal or ruthenium alloy, and the step of forming the dielectric covering layer includes: non-conformally covering the first preset area and the patterned mask layer with a second dielectric material; wherein the second dielectric material is attached to and covers the sidewalls of the dielectric trench, and the dielectric covering layer includes an overhang extending into the dielectric trench to enclose an air gap in the dielectric trench.
[0021] Optionally, the second dielectric material is deposited by a chemical vapor deposition process, wherein a deposition rate of the second dielectric material near the opening of the dielectric groove is greater than a deposition rate inside the dielectric groove, causing the overhang to close near the opening of the dielectric groove; wherein the chemical vapor deposition process is performed under a condition where the substrate temperature is greater than 300°C, and the precursor gas is introduced into the reaction chamber at a flow rate greater than 1000sccm.
[0022] Optionally, the step of forming the dielectric cover layer further includes: performing a planarization process on the dielectric cover layer until the dielectric cover layer and the patterned hard mask layer covering the dielectric structure are removed.
[0023] Optionally, after the wet etching process is performed, a portion of the surface of the metallization layer is corroded; the dielectric cover layer is planarized by a chemical mechanical polishing process to remove the dielectric cover layer covering the dielectric structure, and the first conductive feature and the second conductive feature are simultaneously thinned to a target thickness to remove the corroded surface of the metallization layer; wherein the metallization layer is thinned to a thickness greater than The material of the metallization layer includes one of Al, Cu and W.
[0024] The present invention also provides an interconnect structure with an air gap, and the interconnect structure is manufactured according to the aforementioned method for manufacturing the interconnect structure with an air gap.
[0025] As described above, the present invention provides an interconnect structure with an air gap and a method for manufacturing the same. After a step of defining a first preset area of a dielectric structure by a graphic process, a first dielectric layer within the first preset area is selectively removed by a wet etching process. A ruthenium-containing diffusion barrier layer covers a metallization layer to prevent diffusion and migration of copper. Moreover, in the process of etching a dielectric groove by a wet etching process, the ruthenium-containing diffusion barrier layer can block the corrosion of chemical liquid on a metallization layer such as copper, effectively avoiding the influence on the electrical properties of the interconnect structure and reducing power consumption. In addition, in the process of forming a dielectric covering layer, a second dielectric material is used to non-conformally cover the first preset area. Since ruthenium metal has adhesion to both metal and dielectric materials, the second dielectric material extends into the dielectric groove and mainly covers the sidewalls of the diffusion barrier layer, which is conducive to improving the ability to adjust the geometric parameters of the air gap, thereby reducing the parasitic capacitance value, and has broad application prospects.
[0026] By applying the method for manufacturing the interconnect structure with air gaps of the present invention, air gaps are introduced into the dielectric structure, thereby reducing the dielectric constant of the dielectric structure and lowering the RC delay. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figures 1A to 1C Schematic diagram showing air gaps with different geometric parameters in an interconnect structure; Figure 1A The air gaps shown are normalized to a volume of 1. Figure 1B The normalized volume number of the air gap shown is 1.4, Figure 1C The air gaps shown are normalized to a volume number of 2.
[0028] Figure 2 FIG. 1 is a graph showing the relationship between the parasitic capacitance value of the interconnect structure with air gaps as well as the volume of the air gaps and the damage depth.
[0029] Figure 3A to Figure 3D Schematic diagram showing the structures obtained at various stages of the method for manufacturing an interconnect structure with an air gap in a comparative example of the present invention.
[0030] Figure 4 The flowchart is a method for manufacturing an interconnect structure with an air gap according to an embodiment of the present invention.
[0031] FIG. 5A to FIG. 5E Schematic diagram showing structures obtained at various stages of a method for manufacturing an interconnect structure with an air gap according to an embodiment of the present invention.
[0032] Component number description
[0033] 20 Dielectric structure
[0034] 210 Etch stop layer
[0035] 310 Hard mask layer
[0036] 32 Photoresist
[0037] 131, 31, 31e Patterned hard mask layer
[0038] 220 First dielectric layer
[0039] 230 Conductive Characteristics
[0040] 230a first conductive feature
[0041] 230b second conductive feature
[0042] 234 Ruthenium-containing diffusion barrier
[0043] 236 Metallization layer
[0044] 238a Dielectric barrier layer
[0045] 240 Dielectric Groove
[0046] 410 Overhang
[0047] 40 Dielectric Cover
[0048] 150, 50 air gap
[0049] Steps S1~S5, S100~S400 DETAILED DESCRIPTION
[0050] Hereinafter, the embodiments of the present invention are described by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For the purpose of clarity, parts and steps familiar to those skilled in the art are omitted to avoid unnecessary confusion of the elements of the present invention.
[0051] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0052] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0054] The comparative example of the present invention provides a method for manufacturing an interconnect structure with an air gap, comprising:
[0055] Step S1, providing a substrate, on which a dielectric structure and a mask layer are formed, wherein the dielectric structure includes a first dielectric layer located at a side away from the substrate, and a conductive feature is formed through the dielectric structure;
[0056] Step S2, patterning the mask layer to expose a first preset region of the dielectric structure and a first conductive feature within the first preset region;
[0057] Step S3, exposing the first preset area to an etching gas containing active particles, selectively removing the first dielectric layer within the first preset area to form a dielectric trench, and simultaneously exposing a portion of the metallization layer of the conductive feature;
[0058] Step S4, forming a dielectric barrier layer on the patterned mask layer, wherein the dielectric barrier layer conformally covers the exposed portion of the metallization layer;
[0059] Step S5 , non-conformally covering the patterned mask layer with a second dielectric material to form a dielectric cover layer, wherein a portion of the dielectric cover layer entering the dielectric trench does not completely fill the dielectric trench to define an air gap.
[0060] Figure 3A and Figure 3D A schematic diagram showing a structure obtained by a method for manufacturing an interconnect structure with an air gap in a comparative example.
[0061] like Figure 3A As shown, a dielectric structure and an interconnection groove in the dielectric structure are sequentially formed on the substrate, a metal diffusion barrier layer, a seed layer (if any) and a metallization layer are sequentially formed in the interconnection groove, and at step S2, a patterned mask layer 131 is formed on the dielectric structure based on the patterned mask layer to define a first preset area; the window defined in the patterned mask layer shows a portion of the surface of the first dielectric layer and the top surface of at least one conductive feature. Typically, the diffusion barrier layer adopts a Ta-based diffusion barrier layer, and the commonly used barrier materials such as tantalum nitride have the disadvantages of high resistivity and more sidewall electron scattering. The term "conductive feature" mentioned herein means to include interconnection vias, interconnection lines or similar conductive components.
[0062] like Figure 3B As shown, in step S3, a reactive ion etching process is performed on the layer not covered with the mask layer to selectively remove the first dielectric layer within the first preset area. Since the existing conductive features mostly use a Ta-based diffusion barrier layer as a metal diffusion barrier layer, during the etching of the dielectric layer, the first conductive feature in the first preset area is exposed to reactive ion etching, which may cause re-sputtering of the metal in the reactive ion etching chamber and contamination of the interconnect structure itself. The exposed Ta-based diffusion barrier layer will also be removed by the etching gas, exposing a portion of the metallization layer, which will also increase the risk of damage to the metallization layer such as copper in subsequent processes.
[0063] like Figure 3C As shown, in step S4, a dielectric barrier layer 238a is formed on the patterned mask layer, and the dielectric barrier layer 238a conformally covers the exposed portion of the metallization layer, provides mechanical support for the metallization layer, and can also prevent the fluorine-based etchant from damaging the conductive features, thereby reducing and / or preventing the formation of metal ions, which can reduce and / or prevent time-dependent dielectric breakdown (TDDB) of the dielectric layer adjacent to the conductive line.
[0064] like Figure 3D As shown, in step S5, the patterned mask layer is non-conformally covered with a second dielectric material. Since the deposition rate of the second dielectric material near the opening of the dielectric groove is greater than the deposition rate inside the dielectric groove, the opening of the dielectric groove is closed to form a seam extending into the interior thereof, thereby defining an air gap.
[0065] Compared with the above process, the present invention utilizes a ruthenium-containing diffusion barrier layer to coat the metallization layer to construct conductive features, prevent the diffusion and migration of metals such as copper, and can also effectively alleviate the increase in resistivity when the line width is narrow and the area is small; in the process of etching to form a dielectric trench using a wet etching process, the ruthenium-containing diffusion barrier layer acts as a barrier to prevent water and chemical solutions from corroding the metallization layer; in addition, while forming a dielectric covering layer, the dielectric covering layer extends into the dielectric trench to enclose an air gap in the dielectric trench, without the need to additionally introduce a dielectric barrier layer, effectively preventing the etchant or process environment from damaging the conductive features, and also simplifying the process.
[0066] Hereinafter, the interconnect structure with air gap and the manufacturing method thereof of the present invention will be described in detail with reference to the accompanying drawings.
[0067] Embodiment 1
[0068] See also Figure 4 , this embodiment provides a method for manufacturing an interconnect structure with an air gap.
[0069] First, step S100 is performed to provide a substrate, on which a dielectric structure and a mask layer are sequentially formed, the dielectric structure at least includes a first dielectric layer located on a side away from the substrate, and a conductive feature is formed through the first dielectric layer, the conductive feature includes a metallization layer and a ruthenium-containing diffusion barrier layer for separating the metallization layer and the dielectric structure.
[0070] Specifically, the material of the substrate can be selected as a semiconductor material, such as one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and indium phosphide; or include an insulating material, such as an SOI substrate. Various isolation elements and various doping regions are formed on the substrate to form the necessary parts or structures of the semiconductor device. The isolation element is, for example, a shallow trench isolation structure (STI), and the doping region is, for example, an N-well, a P-well and a lightly doped source and drain region (LDD). The above structure is determined according to the actual semiconductor device manufacturing process, which is a well-known technical content to those skilled in the art and will not be repeated here.
[0071] In an exemplary embodiment, a first dielectric layer is provided to begin the process of manufacturing an integrated circuit. In a typical process, the first dielectric layer is deposited over the transistor device on the substrate after the front-end-of-line (FEOL) processing is completed. Figure 5AAs shown, the first dielectric layer 220 has a surface. Conventionally, the first dielectric layer 220 is deposited by chemical vapor deposition (CVD), however, the present invention may use any desired deposition process to deposit the first dielectric material. Although the first dielectric material may be any suitable material for insulating or isolating transistors and back-end-of-line (BEOL) conductive features, in an exemplary embodiment, the first dielectric material is an ultra low-k (ULK) dielectric material, such as Black Diamond developed by Applied Materials, Inc. in Santa Clara, California, USA. TM ), fluorine silicon glass, etc.
[0072] After forming a semiconductor device on the substrate, Figure 5A As shown, a dielectric structure is formed, the dielectric structure includes an etch stop layer 210 and a first dielectric layer 220; wherein the etch stop layer 210 is selected to be a dielectric material containing silicon material, nitrogen-containing material, carbon-containing material or the like, such as SiCN.
[0073] At step S100, the step of forming the conductive feature includes: patterning the first dielectric layer 220 to form an interconnection groove penetrating the first dielectric layer; forming a ruthenium-containing diffusion barrier layer 234 on the inner surface of the interconnection groove; forming a metallization layer 236 filling the interconnection groove; wherein the ruthenium-containing diffusion barrier layer 234 can be a single layer composed of ruthenium metal or ruthenium alloy, such as ruthenium-tantalum alloy, or a composite layer composed of the above single layer and other metal materials that have a barrier effect on metal atoms such as copper, and the material of the metallization layer 236 includes one of Al, Cu, and W. By utilizing the good barrier performance of ruthenium metal to the diffusion of copper atoms or the drift of copper ions, the thickness required for the use of Ru-based diffusion barrier layer can be reduced by more than half compared to the conventionally used Ta-based diffusion barrier layer, and its unique performance allows the deposition of ultra-thin layers with adjustable thickness by different technologies. For example, in a copper interconnect structure, the thickness of the diffusion barrier layer composed of Ta / TaN material is approximately in the range of to By using Ru metal as the diffusion barrier layer, its thickness can be reduced to and between them, thereby reducing the resistor-capacitor (RC) delay.
[0074] In an exemplary embodiment, Figure 5AAs shown, the interconnection trench penetrates the first dielectric layer 220 and the etch stop layer 210, and the ruthenium-containing diffusion barrier layer 234 is formed on the inner surface of the interconnection trench by a physical vapor deposition (PVD) process or an atomic layer deposition (ALD) process; and / or, a metallization layer is used to fill the interconnection trench and cover the first dielectric layer 220 by an electrochemical plating (ECP) process or an electroplating process or a combination thereof. When the metallization layer 236 is selected as Cu, the ruthenium metal diffusion barrier layer used may have a thickness as low as The thickness, in particular, does not exceed More specifically, its thickness is to Compared with the commonly used tantalum-based diffusion barrier layer, the resistance-capacitance (RC) delay is reduced.
[0075] Furthermore, after the step of forming the metallization layer 236, the metallization layer covering the first dielectric layer is planarized by a process such as chemical mechanical polishing, and the obtained metallization layer is flush with the top surface of the first dielectric layer, thereby obtaining a conductive feature. In this embodiment, the metallization layer obtained by the planarization process has a total thickness exceeding the target thickness, which is used to provide a process margin for subsequent planarization.
[0076] Next, step S200 is performed to pattern the mask layer to expose a first predetermined region of the dielectric structure and a first conductive feature within the first predetermined region.
[0077] See also Figure 5B , the mask layer includes a hard mask layer 310 and a photoresist layer stacked in sequence from the first dielectric layer upward. In an exemplary embodiment, the photoresist layer is defined to correspond to the first preset area by a photolithography process. The standard photolithography process may include processing steps such as photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development and hard baking. The step of patterning the mask layer also includes: patterning the hard mask layer 310 by a wet etching process or a dry etching process to form an opening that exposes the first preset area. In a specific example, the material of the hard mask layer is selected from one of silicon-containing oxides, nitrides, and oxynitrides.
[0078] In this embodiment, the hard mask layer 310 includes silicon nitride, and a wet etching process is performed using a phosphoric acid (H3PO4) solution. At this time, the developed photoresist layer will not be affected, and the opening portion can be confined to the photolithography developing area. However, since the wet etching process is an isotropic etching process, the hard mask layer below the developed photoresist layer will still be slightly undercut.
[0079] Further, the patterned hard mask layer is wet cleaned, and the exposed top surface of the first dielectric layer within the first preset area is lower than the top surface of the first conductive feature. After the pattern is transferred to the hard mask layer by an etching process, a cleaning agent whose main components are sulfuric acid and H2O2 is used to remove the residual photoresist and polymer, such as SPM, but the metallization layer is exposed to a strong oxidizing chemical solution and corroded, such as sulfuric acid, which makes the copper surface rough. In an exemplary embodiment, the material of the first dielectric layer is selected to be or include black diamond or fluorosilicic glass, both of which are silicon-containing oxides. In the back-end process, the post-etching cleaning solution used mainly includes: one type of cleaning solution with hydroxylamine as the main active ingredient, such as EKC265, EKC270, EKC270T, etc., and the other type of cleaning solution with F ions as the main active ingredient, such as ST250. The former is mainly used as a photoresist remover, and the latter not only consumes the first dielectric material, but also may remove CuO and TiN. Due to the corrosion resistance of ruthenium metal itself, the above-mentioned cleaning solution has an extremely low etching selectivity for ruthenium metal. The use of a diffusion barrier layer composed of ruthenium metal or ruthenium alloy can reduce the loss of etchants and cleaning solutions to metallization layers such as copper in subsequent processes.
[0080] like Figure 5B As shown, the patterned hard mask layer 31 defines an opening corresponding to the first preset area, and shields the area and conductive features outside the first preset area of the dielectric structure, that is, a portion of the first dielectric layer and the second conductive feature 230b; preferably, the edge of the opening defined in the patterned hard mask layer completely shields the second conductive feature located thereunder.
[0081] Next, step S300 is performed to selectively remove the first dielectric layer within the first preset area through a wet etching process based on the patterned mask layer to form a dielectric trench with the ruthenium-containing diffusion barrier layer as a sidewall definition.
[0082] At step S300, the wet etching process is performed using an etchant that is selective to the first dielectric material to reduce damage to the conductive features, which include a first conductive feature 230a and a second conductive feature 230b covered with the patterned hard mask layer. In an exemplary embodiment, an HF solution is used as an etchant, and the wet etching process is performed using the opening defined in the patterned hard mask layer as a mask to selectively remove the first dielectric layer exposed from within the first preset area. The ruthenium-containing diffusion barrier layer can play a blocking role during the wet etching process, so that the exposed top surface of the first dielectric layer is recessed downward until it is completely removed, thereby forming a dielectric trench 240, such as Figure 5COn the other hand, since the hard mask layer composed of silicon-containing oxide or nitride will also be affected by the etching solution, the patterned hard mask layer will be lateral-etched along its opening edge, as shown in FIG. Figure 5B The extended opening defined by the patterned hard mask layer 31e is shown so that the opening edge that originally completely shields the second conductive feature thereunder is extended to expose a portion of the top surface of the second conductive feature, thereby increasing the probability of the metallization layer such as copper being exposed to the chemical solution.
[0083] The first preset area is defined by the patterned mask layer, and the number of the first preset areas can be plural; accordingly, the number and distribution of dielectric grooves formed by selectively removing the first dielectric layer within the first preset area through a wet etching process can be determined according to the electrical performance required by the integrated circuit.
[0084] Then, step S400 is performed to remove the patterned mask layer, and to form a dielectric cover layer covering the first predetermined area, wherein the dielectric cover layer extends into the dielectric trench to form an air gap in the dielectric trench.
[0085] Specifically, step S400 includes: non-conformally covering the patterned mask layer with a second dielectric material to form a dielectric cover layer, wherein the dielectric cover layer includes an overhang 410 extending into the dielectric trench to define an air gap 50 in the dielectric trench 240; wherein the second dielectric material can preferably be formed of an oxygen-containing material with a low dielectric constant, such as carbon-doped silicon oxide, fluorine silicate glass (FSG), silicon oxycarbide, SiCOH-based dielectric materials, fluorine-doped silicon oxide, spin-on glass, black diamond (BD), etc.; more preferably, the second dielectric material is a dielectric material with a dielectric constant lower than 4.
[0086] At step S400, the step of removing the patterned hard mask layer can be performed before forming the dielectric cover layer, or can be performed simultaneously in the step of flattening the dielectric cover layer; preferably, after performing a wet cleaning process on the dielectric trench obtained by etching, the first preset area and the patterned mask layer are non-conformally covered with a second dielectric material to form a dielectric cover layer 40; since ruthenium metal has good adhesion to dielectrics with low dielectric constants or ultra-low dielectric constants, the second dielectric material enters the dielectric trench mainly by sidewall deposition, adheres to and covers the sidewalls of the dielectric trench. By depositing the second dielectric material along the sidewall to define an air gap 50 in the dielectric trench, there is no need to introduce an additional step of forming a dielectric barrier layer, and mechanical support for the conductive features can also be provided. The resulting interconnect structure has good mechanical properties, and the thickness, length, and number of the defined air gaps can be adjusted, which can be adjusted according to the required dielectric constant of the interconnect structure.
[0087] Figure 5D The schematic diagram of the structure obtained after the dielectric cover layer is formed at step S400 is shown. In an exemplary embodiment, at step S400, the second dielectric material is deposited by chemical vapor deposition, and the deposition rate of the second dielectric material near the opening of the dielectric trench is greater than the deposition rate inside the dielectric trench, causing the overhang 410 to close near the opening of the dielectric trench. The obtained structure is as shown in FIG. Figure 5D In a specific embodiment, the dielectric cover layer 40 is formed by the following steps: -2 torr, and the substrate temperature is greater than 300°C, the precursor gas is introduced into the reaction chamber at a flow rate greater than 1000 sccm, and the deposition rate of the second dielectric material can reach 25nm / min. For example, when the material of the dielectric cover layer 40 is selected as fluorosilicone glass, the precursor gas includes tetraethyl orthosilicate (TEOS), or a combination of SiH4, SiF4 and O2. By utilizing the adhesion of ruthenium metal to the dielectric material, by adjusting the ratio and flow rate of the precursor gas used to deposit the second dielectric material, the difference in the deposition rate of the second dielectric material near the opening of the dielectric groove and at its bottom is increased, so that the closure near the opening occurs as early as possible, and the air gap volume defined by the resulting overhang is maximized, thereby further reducing the dielectric constant of the dielectric structure and reducing the RC delay.
[0088] At step S400 , after the step of forming the dielectric cover layer 40 , the dielectric cover layer 40 is planarized until the dielectric cover layer and the patterned hard mask layer covering the dielectric structure are removed.
[0089] Specifically, the dielectric cover layer 40 is planarized by a process such as chemical mechanical polishing to thin the dielectric cover layer 40 until the patterned hard mask layer is completely removed, and the top surface of the dielectric cover layer obtained by planarization is flush with the top surface of the conductive feature, which is helpful for performing subsequent processes.
[0090] Figure 5E The schematic diagram of the structure obtained after the dielectric cover layer is planarized in step S400 is shown. Figure 5E As shown, in the planarization process of the dielectric cover layer, in addition to the dielectric cover layer covering the dielectric structure, the corroded surface of the metallization layer is also removed, and the chemical mechanical polishing process is performed using a polishing solution containing H2O2 to at least remove the corroded surface of the metallization layer and thin the conductive feature 230 to a target thickness, wherein the thinned thickness of the metallization layer is greater than
[0091] This embodiment further provides an interconnect structure with an air gap, and the interconnect structure is preferably manufactured by using the aforementioned method for manufacturing the interconnect structure with an air gap.
[0092] like Figure 5E As shown, the interconnect structure with an air gap comprises: a dielectric structure, a conductive feature is arranged through the dielectric structure, and the conductive feature comprises a metallization layer and a ruthenium-containing diffusion barrier layer between the metallization layer and the dielectric structure; the ruthenium-containing diffusion barrier layer in a first preset area of the dielectric structure serves as a sidewall to define a dielectric trench, and covers the first preset area to form a dielectric covering layer, and the dielectric covering layer comprises an overhang extending into the dielectric trench to enclose an air gap in the dielectric trench.
[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing an interconnect structure with an air gap, characterized in that: The following steps are involved: A substrate is provided, on which a dielectric structure and a mask layer are sequentially formed, wherein the dielectric structure at least comprises a first dielectric layer located at a side away from the substrate, and a conductive feature is formed through the dielectric structure, wherein the conductive feature comprises a metallization layer and a ruthenium-containing diffusion barrier layer for separating the metallization layer from the dielectric structure; Patterning the mask layer to expose a first predetermined region of the dielectric structure and a first conductive feature within the first predetermined region; Based on the patterned mask layer, the first dielectric layer within the first preset area is selectively removed by a wet etching process to form a dielectric trench defined by the ruthenium-containing diffusion barrier layer as a sidewall; The patterned mask layer is removed to form a dielectric cover layer covering the first preset area, wherein the dielectric cover layer extends into the dielectric trench to enclose an air gap in the dielectric trench.
2. The method according to claim 1, characterized in that: The step of forming the conductive feature comprises: patterning the first dielectric layer to form interconnect trenches penetrating the first dielectric layer; forming a ruthenium-containing diffusion barrier layer on the inner surface of the interconnection trench; forming a metallization layer filling the interconnect trench; The ruthenium-containing diffusion barrier layer is formed by a physical vapor deposition process or an atomic layer deposition process; and the metallization layer is formed by an electrochemical plating process or an electroplating process or a combination thereof.
3. The method according to claim 1, characterized in that: The mask layer includes a hard mask layer and a photoresist layer stacked in sequence from the first dielectric layer upward, and the step of forming the patterned mask layer includes: patterning the hard mask layer by a wet etching process based on the opening defined in the developed photoresist layer; then, wet cleaning the patterned hard mask layer, and the exposed top surface of the first dielectric layer within the first preset area is lower than the top surface of the first conductive feature.
4. The method according to claim 1, characterized in that: Before the step of selectively removing the first dielectric layer, the patterned mask layer covers the area outside the first preset area of the dielectric structure and the second conductive feature.
5. The method according to claim 4, characterized in that: The material of the hard mask layer is selected from one of silicon-containing oxides, nitrides, and oxynitrides; the first dielectric layer within the first preset area is selectively removed, and at the same time, the patterned hard mask layer is laterally corroded so that the opening defined in the patterned hard mask layer is expanded to partially expose the top surface of the second conductive feature.
6. The method according to claim 1, characterized in that: The ruthenium-containing diffusion barrier layer includes a single layer composed of ruthenium metal or ruthenium alloy, and the step of forming the dielectric covering layer includes: non-conformally covering the first preset area and the patterned mask layer with a second dielectric material; wherein the second dielectric material is attached to and covers the sidewalls of the dielectric trench, and the dielectric covering layer includes an overhang extending into the dielectric trench to enclose an air gap in the dielectric trench.
7. The method according to claim 6, characterized in that: The second dielectric material is deposited by a chemical vapor deposition process, wherein a deposition rate of the second dielectric material near the opening of the dielectric groove is greater than a deposition rate inside the dielectric groove, causing the overhang to close near the opening of the dielectric groove; wherein the chemical vapor deposition process is performed under a condition where the substrate temperature is greater than 300°C, and a precursor gas is introduced into a reaction chamber at a flow rate greater than 1000sccm.
8. The manufacturing method according to claim 3, characterized in that: The step of forming the dielectric cover layer also includes: performing a planarization process on the dielectric cover layer until the dielectric cover layer and the patterned hard mask layer covering the dielectric structure are removed.
9. The manufacturing method according to claim 4, characterized in that: Also includes: After the wet etching process is performed, a portion of the surface of the metallization layer is corroded; The dielectric cover layer is planarized by a chemical mechanical polishing process to remove the dielectric cover layer covering the dielectric structure, and the first conductive feature and the second conductive feature are simultaneously thinned to a target thickness to remove the corroded surface of the metallization layer; wherein the metallization layer is thinned to a thickness greater than The material of the metallization layer includes one of Al, Cu and W.
10. An interconnect structure with an air gap, characterized in that: The interconnect structure is manufactured according to the method for manufacturing an interconnect structure with an air gap according to any one of claims 1 to 9.