Method for improving durability of passivation layer

Abstract

The invention relates to a method for improving passivation layer durability. Methods, systems, and apparatus for improving passivation layer durability are described. An apparatus may include a semiconductor substrate elongated along a first direction and a second direction. The first direction may be parallel to a width of the semiconductor substrate, and the second direction may be parallel to a depth of the semiconductor substrate. The device may include one or more layers formed over the semiconductor substrate with respect to a third direction parallel to the height of the semiconductor substrate. Regions of the at least one or more layers may include circuitry. The device may include a passivation layer formed over the one or more layers relative to the third direction. The passivation layer may include a plurality of cavities each extending through the passivation layer. The plurality of cavities and the circuitry may not overlap with respect to the first direction and the second direction.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to semiconductor devices and manufacturing techniques. More particularly, the present disclosure relates to methods for improving the durability of a passivation layer. Background Art

[0002] Some semiconductor devices may include layers of various materials formed in a stack on a semiconductor substrate. Such semiconductor devices may be formed using various techniques such as photolithography, etching, deposition, doping, and other techniques. These techniques may be used to form various materials into patterns and configurations that enable the operation of the semiconductor device. In some cases, the semiconductor device may include various structures for coupling with other devices (such as other semiconductor devices). For example, the semiconductor device may include one or more layers that are formed in such a manner that the semiconductor device can be coupled to another semiconductor device (e.g., via welding, via flip-chip bonding). In some cases, the semiconductor device may include different materials with geometric discontinuities (including interfaces, corners, and edges). Such semiconductor devices may be subject to non-uniform thermal cycling during manufacturing, testing, storage, and operation. Due to differences in the thermochemical properties of each material and the geometric discontinuities, the interfaces between the materials may be prone to various types of failures, such as delamination. Summary of the Invention

[0003] Various embodiments described herein relate to methods, devices, and systems for improving the durability of a passivation layer. In one aspect, a device includes: a semiconductor substrate elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; one or more layers formed on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; and a passivation layer formed on the one or more layers relative to the third direction, the passivation layer including a plurality of cavities, each of the plurality of cavities extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

[0004] In some embodiments, one or more layers may include an insulating layer formed between the circuit device and the passivation layer, wherein each cavity in the plurality of cavities exposes the surface of the insulating layer. In some embodiments, each cavity in the plurality of cavities is formed in the shape of an elliptical cylinder, and the elliptical cylinder includes a height axis parallel to the third direction. In some embodiments, the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern, and the rectangular pattern includes uniform spacing between each cavity in the plurality of cavities. In some cases, all four sides of the rectangular pattern can have equal length (for example, the rectangular pattern can be a square). In some other cases, the sides of the rectangular pattern can have different lengths (for example, the rectangular pattern can be a rectangle).

[0005] In some embodiments, the semiconductor substrate comprises a silicon carbide material. In some embodiments, one or more layers comprise a silicon carbide layer, a metal layer, and a silicon nitride layer, wherein the silicon carbide layer is formed in contact with the semiconductor substrate, the metal layer is formed at least partially in contact with the silicon carbide layer, and the silicon nitride layer is formed at least partially in contact with the metal layer. In some embodiments, the circuit device may comprise a transistor circuit device. Other technical features can be readily inferred by those skilled in the art from the accompanying drawings, the following description, and the claims.

[0006] In one aspect, a method may include forming a semiconductor substrate that is elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; and forming a passivation layer on the one or more layers relative to the third direction, the passivation layer including a plurality of cavities, each of the plurality of cavities extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

[0007] In some embodiments, forming one or more layers may include forming an insulating layer between the circuit device and the passivation layer, wherein each of the plurality of cavities exposes a surface of the insulating layer. In some embodiments, forming each of the plurality of cavities may include forming a cavity in the shape of an elliptical cylinder having a height axis parallel to a third direction. In some embodiments, the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern having uniform spacing between each of the plurality of cavities. The method may further include forming the semiconductor substrate using a silicon carbide material.

[0008] In some embodiments, forming one or more layers may include forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer at least partially in contact with the silicon carbide layer, and forming a silicon nitride layer at least partially in contact with the metal layer. Other technical features can be readily inferred by those skilled in the art from the accompanying drawings, the following description, and the claims.

[0009] In one aspect, a method for forming a product may include: forming a semiconductor substrate that is elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; and forming a passivation layer on the one or more layers relative to the third direction, the passivation layer including a plurality of cavities, each of the plurality of cavities extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

[0010] In some embodiments, forming one or more layers may include forming an insulating layer between the circuit device and the passivation layer, wherein each cavity in the plurality of cavities exposes a surface of the insulating layer. In some embodiments, forming each cavity in the plurality of cavities may include forming a cavity in the shape of an elliptical cylinder, the elliptical cylinder including a height axis parallel to the third direction. In some embodiments, the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity in the plurality of cavities. Other technical features can be easily derived by those skilled in the art from the accompanying drawings, the following description, and the claims.

[0011] In some embodiments, a non-transitory computer-readable storage medium may include instructions that, when executed by a computer, cause the computer to: form a semiconductor substrate that is elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; form one or more layers on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, wherein a region of at least one or more of the layers includes a circuit device; and form a passivation layer on the one or more layers relative to the third direction, the passivation layer including a plurality of cavities, each of the plurality of cavities extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

[0012] In some cases, forming the one or more layers may include forming an insulating layer between the circuit device and the passivation layer, wherein each cavity in the plurality of cavities exposes a surface of the insulating layer. In some cases, forming each cavity in the plurality of cavities includes forming a cavity in the shape of an elliptical cylinder, the elliptical cylinder shape including a height axis parallel to the third direction. In some cases, the plurality of cavities are arranged in a rectangular pattern including uniform spaces between each of the plurality of cavities. In some cases, forming the semiconductor substrate includes forming the semiconductor substrate using a silicon carbide material.

[0013] In some cases, forming the one or more layers includes forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer at least partially in contact with the silicon carbide layer, and forming a silicon nitride layer at least partially in contact with the metal layer. In some cases, the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1. Other technical features can be readily inferred by those skilled in the art from the drawings, the following description, and the claims.

[0014] In some embodiments, a device includes a processor. The device also includes a memory storing instructions that, when executed by the processor, configure the device to: form a semiconductor substrate that is elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; form one or more layers on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; and form a passivation layer on the one or more layers relative to the third direction, the passivation layer including a plurality of cavities, each of the plurality of cavities extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

[0015] The device may also be configured to form one or more layers, wherein forming the one or more layers includes forming an insulating layer between the circuit device and the passivation layer, wherein each cavity in the plurality of cavities exposes a surface of the insulating layer. The device may also be configured to form each of the plurality of cavities, wherein forming each of the plurality of cavities includes forming the cavity in the shape of an elliptical cylinder, wherein the elliptical cylinder shape includes a height axis parallel to the third direction. The device may also be configured to arrange the plurality of cavities in a rectangular pattern, wherein the rectangular pattern includes uniform spacing between each of the plurality of cavities. In some cases, forming the semiconductor substrate includes forming the semiconductor substrate using a silicon carbide material.

[0016] In some cases, forming the one or more layers includes forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer at least partially in contact with the silicon carbide layer, and forming a silicon nitride layer at least partially in contact with the metal layer. Other technical features can be readily inferred by those skilled in the art from the accompanying drawings, the following description, and the claims. In some cases, the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1. Other technical features can be readily inferred by those skilled in the art from the accompanying drawings, the following description, and the claims.

[0017] The foregoing illustrative summary, as well as other exemplary objects and / or advantages of the present disclosure and the manner in which these objects and / or advantages are achieved, will be further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The description of the illustrative embodiments may be read in conjunction with the accompanying drawings. It should be understood that for simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale unless otherwise noted. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise noted. Embodiments incorporating the teachings of the present disclosure are shown and described in conjunction with the drawings presented herein, in which:

[0019] Figure 1 illustrates an example of a material arrangement that supports a method for improving passivation layer durability;

[0020] Figure 2 illustrates an example of a material arrangement that supports a method for improving passivation layer durability;

[0021] Figure 3 illustrates an example of a material arrangement that supports a method for improving passivation layer durability;

[0022] Figure 4 An example of a flow chart supporting a method for improving passivation layer durability is illustrated; and

[0023] Figure 5 An example of a flow chart supporting a method for improving passivation layer durability is illustrated. DETAILED DESCRIPTION

[0024] Some embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the present disclosure. Indeed, these disclosures may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0025] As used herein, in the examples provided below, for purposes of explanation, terms such as "front," "back," "top," etc., are used to describe the relative positions of certain components or parts of components. In addition, based on this disclosure, one of ordinary skill in the art will understand that the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within applicable engineering tolerances.

[0026] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. It should be understood that the use of broader terms such as including, comprising, and having is intended to provide support for narrower terms such as consisting of, consisting essentially of, and consisting substantially of.

[0027] The phrases "in one embodiment," "according to one embodiment," etc. generally mean that the particular feature, structure, or characteristic following the phrase can be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, these phrases are not necessarily referring to the same embodiment).

[0028] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0029] If the specification states that a component or feature "may," "could," "might," "should," "will," "preferably," "likely," "typically," "optionally," "for example," "often," or "might" (or other such language) be included or have a characteristic, that particular component or feature is not required to be included or have that characteristic. Such a component or feature may optionally be included in some embodiments, or it may be excluded.

[0030] Figure 1An example of a material arrangement 100 that supports a method for improving the durability of a passivation layer is illustrated. In some cases, the material arrangement 100 may illustrate one or more portions of a semiconductor device or any other electronic device. For example, the material arrangement 100 may illustrate multiple portions of a silicon carbide power device (such as a diode or a transistor). The material arrangement 100 may be an example of a device or one or more portions of a device used in various applications (such as power electronics applications). The material arrangement 100 may illustrate one or more cross-sectional views of a semiconductor device, wherein some portions of the semiconductor device may be truncated or not shown. For example, the material arrangement 100 may illustrate six portions of a semiconductor device, which may be shown separately to illustrate that an intermediate material 110 or layer 105 may be included between the portions. However, in some cases, the six portions may not include the intermediate material 110 or layer 105, but may be formed in contact with each other. As described herein, each layer 105 of the material arrangement 100 may correspond to a corresponding material 110. Additionally, layer 105 - d may include implanted regions 115 , which may be portions of layer 105 - d that are implanted or doped according to a particular implantation or doping method. Although some examples of particular materials 110 or material compounds are described herein, material arrangement 100 may include any combination of materials 110 .

[0031] Material arrangement 100 may include layer 105-a. Layer 105-a may be an example of a passivation layer that may insulate or otherwise protect one or more layers 105 of material arrangement 100 (e.g., layer 105 located below layer 105-a with respect to the y-direction). In some cases, layer 105-a may electrically insulate one or more layers of material arrangement 100 or otherwise prevent radio waves (e.g., electromagnetic fields) or electrical signals from being transmitted through layer 105-a. Layer 105-a may also be used to protect material arrangement 100 from damage caused by weathering or mechanical stress. Layer 105-a may be formed using material 110-a (e.g., a passivation material, an insulating material). In some cases, material 110-a may be examples of polyimide, silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. Layer 105-a may be formed in contact with layer 105-b.

[0032] Material arrangement 100 may include layer 105-b. Layer 105-b may be an example of an insulating layer (e.g., a second insulating layer) that may be included in material arrangement 100 (e.g., in addition to layer 105-a) to improve the adhesion of layer 105-a. For example, layer 105-a may adhere to layer 105-b more easily than layer 105-c. Layer 105-b may insulate or otherwise protect one or more layers 105 of material arrangement 100 (e.g., one or more layers 105 located below layer 105-b with respect to the y-direction). In some cases, layer 105-b may electrically insulate one or more layers 105 of material arrangement 100 or otherwise prevent radio waves (e.g., electromagnetic fields) or electrical signals from being transmitted through layer 105-b. Layer 105-b may be formed using material 110-b, which may be an example of an insulating material such as polyimide, silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. In one illustrative example, material 110-a may be polyimide, and material 110-b may be silicon nitride. However, in some other examples, layer 105-a and layer 105-b may be formed using the same material (e.g., polyimide). As described herein, layer 105-b may be formed in contact with layer 105-c, layer 105-a, layer 105-g, and layer 105-d.

[0033] Material arrangement 100 may include layer 105-c. Layer 105-c may be an example of a metal layer that may be used to route electrical signals. Layer 105-c may be an example of a redistribution layer or any other type of conductive layer or conductive trace. Layer 105-c may be formed using material 110-c. Material 110-c may be an example of copper, tungsten, aluminum, titanium, silver, or any other conductive material. As described herein, layer 105-c may be formed in contact with any combination of layer 105-b, layer 105-d, and layer 105-g.

[0034] Material arrangement 100 may include layer 105-d. Layer 105-d may be an example of a semiconductor layer that may be used to form a circuit device. Layer 105-d may include implant regions 115 (e.g., implant regions 115-a, implant regions 115-b, and implant regions 115-c). Implant regions 115 may be examples of doped regions of layer 105-d and depletion regions of layer 105-d. For example, implant region 115-a may be an example of a halo implant region, which may be a region of layer 105-d doped according to a particular process (e.g., n-type doping). Implant region 115-b may be an example of an anode implant region, which may be doped differently from implant region 115-a (e.g., using p-type doping). Implant region 115-b may be an example of an anode or positive terminal of material arrangement 100 (e.g., a diode). Layer 105-d may also include implant region 115-c, which may be an example of a depletion region. Layer 105-d can be formed using material 110-e (e.g., a semiconductor material). Material 110-e can be examples of silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, germanium, or any other semiconductor material. As described herein, layer 105-d can be formed in contact with layers 105-e, 105-c, 105-g, and 105-b.

[0035] Material arrangement 100 may include layer 105-g. Layer 105-g may be an example of an oxide layer, which may provide electrical insulation. In some cases, layer 105-g may be an example of an interlayer dielectric (ILD) or a gate dielectric. Layer 105-g may be formed using material 110-d. Material 110-d may be an example of an oxide material, such as silicon dioxide, aluminum oxide, or any other dielectric material. As described herein, layer 105-g may be formed in contact with layers 105-b, 105-c, and 105-d.

[0036] Material arrangement 100 may include layer 105-e. Layer 105-e may be an example of a semiconductor substrate. In some cases, layer 105-c may be formed using material 110-f. Material 110-f may be an example of any semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, or germanium. In some cases, material 110-f and material 110-e may be different. However, in some other cases, material 110-f and material 110-e may be the same material, such as silicon carbide. As described herein, layer 105-e may be formed in contact with layer 105-d and layer 105f.

[0037] The material arrangement 100 may include a layer 105-f. The layer 105-f may be an example of a solder alloy layer. Figure 1100 is shown as a single material (e.g., material 110-g), but a combination of materials 110 may be used to form layer 105-f. For example, material 110-g may be an example of an alloy including titanium, nickel, vanadium, and silver. Layer 105-f may be used to interconnect or couple material arrangement 100 to a semiconductor package (e.g., via soldering). As described herein, layer 105-f may be formed in contact with layer 105-e.

[0038] In some cases, material arrangement 100 can be formed using one or more operations, such as photolithography, etching, deposition, doping, metallization, soldering, or any other type of operation. In some cases, layer 105-e can be deposited on layer 105-f, layer 105-d can be deposited on layer 105-e, layer 105-g can be deposited on layer 105-d, and so on. In some cases, material arrangement 100 can include one or more layers 105, and one or more layers 105 are used to couple layer 105-d, a region of layer 105-d, or layer 105-e (e.g., a redistribution layer) with circuitry of one or more other devices, such as another semiconductor device (not shown).

[0039] As described herein, the material arrangement 100 can include a variety of different materials with geometric discontinuities, including interfaces, corners, and edges. The material arrangement 100 may be subjected to non-uniform thermal cycling during manufacturing, testing, storage, and operation. Due to differences in the thermochemical properties of each material 110 and the geometric discontinuities, the interfaces between the materials 110 (e.g., layer 105) may be prone to failure. In some cases, the layer 105-a (e.g., a passivation layer) that electrically insulates the stack of materials may be particularly prone to mechanical failure (e.g., delamination). Additional layers 105 (such as layer 105-b (e.g., silicon nitride)) can be formed in contact with layer 105-a to improve adhesion (e.g., between layer 105-a and layer 105-b). However, if a crack forms in layer 105-b and the delamination of layer 105-a extends to layer 105-c (e.g., a metal layer), discharge may occur, as shown below.

[0040] The present disclosure provides techniques for improving the durability of layer 105-a by forming stress relief cavities through layer 105-a. The cavities can be arranged along the periphery of material arrangement 100. For example, the cavities can be positioned so that they do not overlap with layer 105-c, implant region 115-a, implant region 115-b, or implant region 115-c (e.g., in the xz plane). For example, the position of the cavities can be selected so that the position of the cavities in the xz plane does not overlap with the area of ​​material arrangement 100 that includes active circuit devices. As described herein, positioning the cavities in areas that do not overlap with the active circuit devices of material arrangement 100 can ensure that the active circuit devices are effectively insulated by layer 105-c (e.g., so that electromagnetic fields do not escape through the cavities). In addition, each cavity can be formed in the shape of an ellipse (e.g., an elliptical cylinder) and can extend downward through the passivation layer (e.g., in the negative y direction). Although the examples described herein generally relate to cavities formed in an elliptical shape, any cavity shape or geometry can be used. Similarly, the relative distances between cavities or the relative positioning of cavities may be modified based on one or more characteristics of the material arrangement 100 .

[0041] Figure 2 An example of a material arrangement 200 that supports a method for improving the durability of a passivation layer is illustrated. For example, material arrangement 200-a may illustrate a layer 205-a (e.g., a passivation layer) without a cavity 215, and material arrangement 200-b may illustrate a layer 205-a with a cavity 215 that may improve the durability of the layer 205-a. Material arrangement 200-a and material arrangement 200-b may be as described in reference to Figure 1 An example of a material arrangement 100 is depicted, or a portion of a material arrangement 100. Material arrangement 200-b may illustrate a portion of material arrangement 100 after one or more operations have been performed (eg, to form cavity 215).

[0042] Material arrangement 200-a may include one or more layers 205. For example, material arrangement 200-a may include layer 205-a (e.g., a passivation layer) and layer 205-b. Layer 205-b may be an example of layer 205 that is located below layer 205-a with respect to the y-direction. Layer 205-b may be formed using material 210-b. Material 210-b may be an insulating material such as silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. In some other cases, material 210-b may be a conductive material such as aluminum. Layer 205-a may be formed using material 210-a, which may be an example of an insulating material (e.g., different from material 210-b). For example, material 210-a may be an example of polyimide.

[0043] Layer 205-a may be formed around the periphery of the semiconductor device (e.g., the periphery of material arrangement 200). In some cases, layer 205-a may be formed by initially depositing material 210-a (e.g., uniformly) on layer 205-b. A central portion of layer 205-a may then be removed, thereby forming a void (e.g., with respect to the y-direction) that exposes the top surface of layer 205-b. Figure 2 ). In some cases, the void formed through layer 205-a can be an example of a stud pad opening. The stud pad opening can enable material arrangement 200-a to be secured to another device via one or more bolts or fasteners connected to layer 205-b.

[0044] As shown, layer 205-a of material arrangement 200-a may not include cavity 215 (e.g., a peripheral cavity). Therefore, non-uniform thermal cycling during manufacturing, testing, storage, and operation may cause mechanical stress in layer 205-a or mechanical stress between layer 205-a and layer 205-b. For example, increasing temperature may cause layer 205-a and layer 205-b to expand. However, material 210-a may have a different coefficient of thermal expansion than material 210-b, which may cause stress between layer 205-a and layer 205-b. Such stress may increase the likelihood of delamination between layer 205-a and layer 205-b, which may cause failure of material arrangement 200-a.

[0045] According to one or more aspects of the present disclosure, and as shown in material arrangement 200-b, one or more cavities 215 can be formed in layer 205-a, and one or more cavities 215 can relieve stress (e.g., mechanical stress) in layer 205-a or stress between layer 205-a and layer 205-b. As shown, material arrangement 200-b can include multiple cavities 215 (e.g., cavity 215-a to cavity 215-jj). Each cavity 215 can expose a surface of layer 205-b. Additionally or alternatively, each cavity 215 can be formed in a position that avoids overlapping with a circuit device (e.g., an active circuit device). For example, the circuit device can be located within region 220 (e.g., below layer 205-b). Thus, cavity 215 can be formed outside region 220 (e.g., along the periphery of material arrangement 200-b).

[0046] Figure 3 An example of a material arrangement 300 supporting a method for improving the durability of a passivation layer is shown. The material arrangement 300 may be shown as shown in FIG. Figure 2For example, region 325 of material arrangement 300 may be an example of an expanded view of a portion of material arrangement 200-b. Material arrangement 300 may include layer 305-a (e.g., a passivation layer) and layer 305-b, which may be as described in reference to FIG. Figure 2 Examples of layers 205-a and 205-b are described. Thus, layer 305-a may be formed using material 310-a, and layer 305-b may be formed using material 310-b. Material 310-a and material 310-b may be respectively as described in reference Figure 2 Examples of materials 210-a and 210-b are described. In addition, the material arrangement 300 may include a plurality of cavities 315, which may be as described in reference Figure 2 An example of cavity 215 is depicted.

[0047] According to one or more aspects of the present disclosure, each cavity 315 can be formed in the shape of an elliptical cylinder. For example, each cavity 315 can have a dimension 320-b (e.g., a minor diameter, a short axis) and a dimension 320-c (e.g., a major diameter, a long axis). For one or more cavities 315 (e.g., cavity 315-a, cavity 315-b), dimension 320-b can be parallel to the z-direction, and dimension 320-c can be parallel to the x-direction. However, the orientation of dimension 320 for each cavity 315 can correspond to the orientation of each cavity 315. For example, cavity 315-e can be oriented differently from cavity 315-a. Thus, dimension 320-b of cavity 315-e can be parallel to the x-direction, and dimension 320-c of cavity 315-e can be parallel to the z-direction.

[0048] In addition, each cavity 315 may have a height dimension (not shown). The height dimension of each cavity 315 may be parallel to the y-direction. As described herein, each cavity 315 may extend through (e.g., completely through) layer 305-a. Additionally or alternatively, the cavities 315 may be spaced or positioned according to dimension 320-a and dimension 320-d. For example, dimension 320-a may be an example of the distance between a corresponding cavity 315 (e.g., cavity 315-a) and the extent of layer 305-a. Dimension 320-a may be selected based on the location of the circuit device. For example, dimension 320-a may be selected so that each cavity 315 is located sufficiently far from the circuit device. Although not shown, dimension 320-a may be the same for each cavity 315. That is, each cavity 315 may be located at the same distance from the extent of layer 305-a. Dimension 320-d may represent the distance or spacing between corresponding cavities 315. In some cases, dimension 320-d may be uniform across multiple cavities 315. That is, the spacing between each cavity 315 may be the same.

[0049] Dimension 320 may be determined based on a mathematical relationship, algorithm, modeling, or test results. For example, a modeling operation may be performed to determine the stresses present in layer 305-a. The modeling operation may output various stress values ​​for a given dimension 320. Thus, the modeling operation may select dimension 320 such that one or more stresses in layer 305 are minimized. In some cases, a specific ratio of dimension 320-c to dimension 320-b may be utilized. For example, dimension 320-c may be approximately three times dimension 320-b. This ratio of dimension 320-c to dimension 320-b may be selected based on one or more stress values ​​output by the modeling operation. For example, selecting dimension 320-c to be approximately three times dimension 320-b may significantly reduce or eliminate stresses in layer 305-a.

[0050] While some examples described herein relate to cavities 315, other examples may include forming (e.g., depositing) various materials 310 within cavities 315. For example, each cavity 315 may be filled (e.g., partially filled or completely filled) with a material 310 different from material 310-a. For example, material 310 may be configured for stress relief applications, or more generally, may have one or more properties that enable stress reduction in layer 305-a. Material 310 may have a hardness or stiffness that is less than that of material 310-a, which may enable material 310 to relieve or relieve stress. For example, material 310 may be relatively flexible when compared to material 310-a. In some cases, one or more dimensions 320 may be selected or otherwise varied based on one or more dimensions of material arrangement 300. For example, dimension 320 may be selected to be proportional to the dimensions of material arrangement 300. In some cases, one or more dimensions 320 may be selected or otherwise varied based on the material 310 selected for material arrangement 300. For example, one or more dimensions 320 may be selected based on one or more properties of material 310 - a , material 310 - b , or both.

[0051] Figure 4 An example of a flow chart illustrating a method 400 for improving the durability of a passivation layer is illustrated. The operations of method 400 can be implemented by a manufacturing system or machine configured to perform one or more operations described herein. For example, a machine or manufacturing system configured to perform one or more deposition operations, etching operations, or any other material forming or material removing operations can perform the operations of method 400. In some cases, the manufacturing system or machine can execute instructions to control one or more functional elements to perform the described operations. Additionally or alternatively, the machine or manufacturing system can use dedicated hardware to perform aspects of the described operations.

[0052] At 405, method 400 may include forming a semiconductor substrate that is elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate. The operations may be performed according to examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0053] At 410, method 400 may include forming one or more layers on a semiconductor substrate relative to a third direction parallel to the height of the semiconductor substrate. In some cases, at least a region of the one or more layers includes circuitry (e.g., active circuitry). Operations may be performed according to examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0054] At 415, method 400 may include forming a passivation layer on the one or more layers relative to the third direction. The passivation layer may include a plurality of cavities, each of which extends through the passivation layer. The plurality of cavities may not overlap with the circuit device relative to the first direction and the second direction. Operations may be performed according to examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0055] Figure 5 An example of a flow chart illustrating a method 500 for improving the durability of a passivation layer is illustrated. The operations of method 500 can be implemented by a manufacturing system or machine configured to perform one or more operations described herein. For example, a machine or manufacturing system configured to perform one or more material removal operations or one or more material forming operations can perform the operations of method 500. In some cases, the manufacturing system or machine can execute instructions to control one or more functional elements to perform the described operations. Additionally or alternatively, the machine or manufacturing system can use dedicated hardware to perform aspects of the described operations.

[0056] At 505, method 500 may include forming a semiconductor substrate that is elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate. The operations may be performed according to examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0057] At 510, method 500 may include forming one or more layers on a semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate. In some cases, at least a region of the one or more layers includes circuitry (e.g., active circuitry). Operations may be performed according to examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0058] At 515, method 500 may include forming an insulating layer between the circuit device and the passivation layer. Each cavity in the plurality of cavities may expose a surface of the insulating layer. In some cases, forming one or more layers may include forming an insulating layer between the circuit device and the passivation layer. Operations may be performed according to examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0059] At 520, method 500 may include forming a passivation layer on the one or more layers relative to the third direction. The passivation layer may include a plurality of cavities, each of which extends through the passivation layer. The plurality of cavities may not overlap with the circuit device relative to the first direction and the second direction. The operations may be performed according to the examples described herein. In some examples, aspects of the operations may be performed using a dedicated machine or manufacturing system.

[0060] Although this detailed description has set forth certain embodiments of the present invention, the appended claims also cover other embodiments of the invention, which may differ from the described embodiments according to various modifications and improvements. In the appended claims, unless the specific terms "means for..." or "step for..." are used in a given claim, it is not intended that the claim be interpreted under 35 U.S.C. 112, paragraph 6.

Claims

1. A device comprising: a semiconductor substrate, the semiconductor substrate being elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate, and the second direction being parallel to a depth of the semiconductor substrate; one or more layers, the one or more layers being formed on the semiconductor substrate relative to a third direction, the third direction being parallel to the height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; as well as A passivation layer is formed on the one or more layers relative to the third direction, the passivation layer comprising a plurality of cavities, each of the plurality of cavities extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

2. The apparatus of claim 1, wherein the one or more layers comprise: An insulating layer is formed between the circuit device and the passivation layer, wherein each of the plurality of cavities exposes a surface of the insulating layer. 3 . The device of claim 1 , wherein each of the plurality of cavities is formed in the shape of an elliptical cylinder including a height axis parallel to the third direction.

4. The device of claim 3, wherein the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1. 5 . The device of claim 1 , wherein the plurality of cavities are arranged in a rectangular pattern comprising uniform spacing between each of the plurality of cavities. The apparatus of claim 1 , wherein the semiconductor substrate comprises a silicon carbide material.

7. The apparatus of claim 1, wherein the one or more layers comprise: a silicon carbide layer formed in contact with the semiconductor substrate; a metal layer formed at least partially in contact with the silicon carbide layer; as well as A silicon nitride layer is formed at least partially in contact with the metal layer.

8. The device of claim 1, wherein the circuit device comprises a transistor circuit device.

9. A method comprising: forming a semiconductor substrate, the semiconductor substrate being elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate, and the second direction being parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate relative to a third direction, the third direction being parallel to the height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; as well as A passivation layer is formed over the one or more layers relative to the third direction, the passivation layer comprising a plurality of cavities each extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

10. The method of claim 9, wherein forming the one or more layers comprises: An insulating layer is formed between the circuit device and the passivation layer, wherein each of the plurality of cavities exposes a surface of the insulating layer.

11. The method of claim 9, wherein forming each cavity of the plurality of cavities comprises: A cavity is formed in the shape of an elliptical cylinder including a height axis parallel to the third direction.

12. The method of claim 11, wherein the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1.

13. The method of claim 9, wherein the plurality of cavities are arranged in a rectangular pattern comprising uniform spacing between each of the plurality of cavities.

14. The method according to claim 9, wherein forming the semiconductor substrate comprises: The semiconductor substrate is formed using a silicon carbide material.

15. The method of claim 9, wherein forming the one or more layers comprises: forming a silicon carbide layer in contact with the semiconductor substrate; forming a metal layer at least partially in contact with the silicon carbide layer; as well as A silicon nitride layer is formed at least partially in contact with the metal layer.

16. A product formed by a method comprising: forming a semiconductor substrate, the semiconductor substrate being elongated along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate, and the second direction being parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate relative to a third direction, the third direction being parallel to the height of the semiconductor substrate, wherein at least a region of the one or more layers includes a circuit device; as well as A passivation layer is formed over the one or more layers relative to the third direction, the passivation layer comprising a plurality of cavities each extending through the passivation layer, wherein the plurality of cavities do not overlap with the circuit device relative to the first direction and the second direction.

17. The product formed by the method of claim 16, wherein forming the one or more layers comprises: An insulating layer is formed between the circuit device and the passivation layer, wherein each of the plurality of cavities exposes a surface of the insulating layer.

18. The product formed by the method of claim 16, wherein forming each cavity of the plurality of cavities comprises: A cavity is formed in the shape of an elliptical cylinder including a height axis parallel to the third direction.

19. The product formed by the method of claim 18, wherein the ratio between the major axis and the minor axis of each elliptical cylinder is 3 to 1.

20. The product formed by the method of claim 16, wherein the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each of the plurality of cavities.

Images