Semiconductor test structure and test method thereof

Abstract

The invention provides a semiconductor test structure and a test method thereof. The semiconductor test structure comprises a polycrystalline silicon cut-off region extending along a first direction and at least one double-transistor structure, the double-transistor structure comprises two transistors symmetrically distributed along the polycrystalline silicon cut-off region, and each transistor comprises a first active region extending along the first direction and having a first distance with the polycrystalline silicon cut-off region; the grid electrode comprises a first extension part and a second extension part located at the first end of the first extension part, the first extension part extends in the second direction and partially overlaps with the first active region, and the second extension part is parallel to the first active region; the first active region forms a source electrode and a drain electrode on two sides of the first extension part of the grid electrode; the second active region comprises a body and bending parts at the two ends of the body, the body is located on the side, away from the first active region, of the second extension part, and the two bending parts surround the two ends of the second extension part; the semiconductor test structure monitors the polycrystalline silicon registration precision of the polycrystalline silicon cut-off region by performing an electrical test on the transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor test structure and a test method thereof. Background Art

[0002] In order to increase the number of wafer chips and improve performance, metal-oxide semiconductor field-effect transistors (MOS) are gradually developing in the direction of miniaturization. In the process, in addition to the characteristic dimension (CD) of the line itself, the dimension of the end of the line must also be strictly controlled. Figure 1 As shown in part (a), the photolithography and etching of the line end 12 are affected by multiple directions compared to the line center 11, and the photoresist retreats quickly, resulting in line end shortness (LES), increasing the risk of leakage during MOS, and further affecting the miniaturization of process dimensions, such as Figure 1 As shown in part (b), due to the influence of LES, the end of the gate 13 forms a rounded corner, which affects the MOS performance. Figure 2 As shown, in order to improve LES, a double pattern is introduced to solve this problem through an etching cut-off process. Figure 2 As shown in part (a), firstly, continuous long strips of polysilicon 21 are formed by etching, and then a polysilicon cut mask 22 is used to form a Figure 2 (b) shows the gate 23. However, there is no good way to monitor the size of the poly endcap and MOS leakage when etching with a poly cut mask.

[0003] Therefore, how to monitor the polysilicon cutting process is a problem that needs to be solved at present. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to monitor the polysilicon cutting process, and provides a semiconductor test structure and a test method thereof.

[0005] In order to solve the above problems, the present invention provides a semiconductor test structure, comprising a polysilicon cut-off region extending along a first direction and at least one dual-transistor structure, wherein the dual-transistor structure comprises two transistors symmetrically distributed along the polysilicon cut-off region, each of the transistors comprising: a first active region extending along the first direction, wherein a first spacing is provided between the first active region and the polysilicon cut-off region; a gate comprising a first extension portion and a second extension portion located at a first end of the first extension portion, wherein the first end of the first extension portion is an end away from another transistor, the first extension portion extends along a second direction and partially overlaps with the first active region, and the second extension portion is parallel to the first active region, wherein the second direction forms an angle with the first direction; the first active region forms a source and a drain on both sides of the first extension portion of the gate; the second active region comprises a body and bending portions located at both ends of the body, wherein the body is located on a side of the second extension portion of the gate away from the first active region, and the two bending portions surround the two ends of the second extension portion of the gate; the semiconductor test structure monitors the polysilicon overlay accuracy of the polysilicon cut-off region by performing electrical tests on the transistors.

[0006] In order to solve the above problems, the present invention provides a semiconductor testing method, comprising the following steps: providing multiple first test units, the first test unit adopting the first test unit described in the present invention; applying a test voltage at the first pad, the second pad and the third pad to perform an electrical test on the transistor; and statistically analyzing the first spacing corresponding to the first test unit whose electrical test parameters meet process requirements to obtain the process window parameters of the first spacing.

[0007] The above technical solution forms a semiconductor test structure by simulating the process structure of the polysilicon cutting process, and monitors the polysilicon cutting process by performing electrical tests on transistors in the semiconductor test structure.

[0008] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following is a brief introduction to the drawings required for the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 It is a schematic diagram of the structure of the end retreat of polysilicon etching lines in the prior art.

[0011] Figure 2 It is a structural schematic diagram of a polysilicon etching and cutting process in the prior art.

[0012] Figure 3 A schematic structural diagram of a dual-transistor structure of an embodiment of the semiconductor test structure of the present invention.

[0013] Figure 4 It is a structural schematic diagram of the first embodiment of the semiconductor test structure of the present invention.

[0014] Figure 5 It is a structural schematic diagram of a second embodiment of the semiconductor test structure of the present invention.

[0015] Figure 6 It is a structural schematic diagram of a third embodiment of the semiconductor test structure of the present invention.

[0016] Figure 7 This is a flowchart of the steps of the first embodiment of the semiconductor testing method of the present invention.

[0017] Figure 8 This is a flow chart of the steps of the second embodiment of the semiconductor testing method of the present invention.

[0018] Fig. 9 This is a flowchart of the steps of the third embodiment of the semiconductor testing method of the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0020] The present invention designs a semiconductor test structure and monitors transistor leakage current (MOS Leakage) through wafer acceptance test (WAT) to perform process optimization.

[0021] See also Figure 3 , which is a schematic diagram of a dual transistor structure of an embodiment of the semiconductor test structure of the present invention. Figure 3As shown, the semiconductor test structure includes a polysilicon cut-off region 39 extending along a first direction and at least one dual-transistor structure 31. The dual-transistor structure 31 includes two transistors 32 symmetrically distributed in the polysilicon cut-off region 39. Each of the transistors 32 includes: a first active region 33, a gate 34, and a second active region 35. The first active region 33 extends along the first direction D1, and a first spacing X1 is provided between the first active region 33 and the polysilicon cut-off region 39. The gate 34 includes a first extension portion 341 and a second extension portion 342 located at a first end of the first extension portion 341. The first end of the first extension portion 341 is an end away from another transistor 32. The first extension portion 341 extends along a second direction D2 and partially overlaps with the first active region 33. The second extension portion 342 is parallel to the first active region 33, wherein the second direction D2 forms an angle with the first direction D1. The first active region 33 forms a source 331 and a drain 332 on both sides of the first extension portion 341 of the gate 34. The second active region 35 includes a body 351 and bent portions 352 located at two ends of the body 351. The body 351 is located on a side of the second extension portion 342 of the gate 34 away from the first active region 33. The two bent portions 352 surround two ends of the second extension portion 342 of the gate 34. The semiconductor test structure monitors the polysilicon alignment accuracy of the polysilicon cut-off region by performing an electrical test on the transistor 32.

[0022] The above technical solution forms a semiconductor test structure by simulating the process structure of the polysilicon cutting process, and monitors the polysilicon cutting process by performing electrical tests on transistors in the semiconductor test structure.

[0023] See also Figure 3-4 ,in, Figure 4 FIG. 1 is a schematic diagram of the structure of the first embodiment of the semiconductor test structure of the present invention. Figure 3-4 As shown, the semiconductor test structure includes a plurality of first test units 100, each of which includes: a plurality of dual transistor structures 31 arranged along a first direction D1. The gates 34 of all the transistors 32 are connected in parallel to the first pad 41. The sources 331 of all the transistors 32 are connected in parallel to the second pad 42. The drains 332 of all the transistors 32 are connected in parallel to the third pad 43. The first spacing X1 of the plurality of first test units 100 is gradually increased, and the transistor 32 is electrically tested by applying a test voltage to the first pad 41, the second pad 42, and the third pad 43, to obtain the process window parameters of the first spacing X1.

[0024] In some embodiments, the first test unit 100 adjusts the first interval X1 by adjusting the width of the polysilicon cutting region 39 in the second direction D2.

[0025] In some embodiments, a gate contact structure 340 is formed on the surface of the second extension portion 342 of the gate 34, and the first pad 41 is electrically connected to the gate 34 through the gate contact structure 340. A source contact structure 3310 is formed on the surface of the source 331 of the first active region 33, and the second pad 42 is electrically connected to the source 331 through the source contact structure 3310. A drain contact structure 3320 is formed on the surface of the drain 332 of the first active region 33, and the third pad 43 is electrically connected to the drain 332 through the drain contact structure 3320.

[0026] See also Figure 3 and Figure 5 ,in, Figure 5 FIG. 2 is a schematic diagram of the structure of the second embodiment of the semiconductor test structure of the present invention. Figure 3 and Figure 5 As shown, the semiconductor test structure includes a plurality of second test units 200, each of which includes: a plurality of the dual transistor structures 31 arranged along the first direction D1, a body contact structure 3510 is formed on the surface of the body 51 of the second active area 35 of the dual transistor structure 31, and a second spacing X2 is provided between the body contact structure 3510 and the second extension 342 of the gate 34. The gates 34 of all the transistors 32 are connected in parallel to the first pad 52. The second active areas 35 of all the transistors 32 are connected in parallel to the fourth pad 54 through the body contact structure 3510. The second spacing X2 of the plurality of the second test units 200 is gradually increased, and the transistor 32 is electrically tested by applying a test voltage at the first pad 52 and the fourth pad 54, so as to obtain the process window parameters of the second spacing X2.

[0027] See also Figure 3 and Figure 6 ,in, Figure 6 FIG. 1 is a schematic diagram of the structure of the third embodiment of the semiconductor test structure of the present invention. Figure 3 and Figure 6As shown, the semiconductor test structure of the present invention also provides an embodiment, including a plurality of third test units 300, each of the third test units 300 includes: a plurality of the dual transistor structures 31 arranged along the first direction D1, a bending portion contact structure 3520 is formed on the surface of the bending portion 352 of the second active area 35 of the dual transistor structure 31, and the bending portion contact structure 3520 and the second extension portion 342 of the gate 34 have a third spacing X3. The gates 34 of all the transistors 32 are connected in parallel to the first pad 61. The second active areas 35 of all the transistors 32 are connected in parallel to the fourth pad 64 through the bending portion contact structure 3520. Among them, the third spacing X3 of the plurality of the third test units 300 gradually increases, and the process window parameters of the third spacing X3 are obtained by applying a test voltage to the first pad 61 and the fourth pad 64 to perform an electrical test on the transistor 32.

[0028] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor testing method.

[0029] See also Figure 7 , which is a flow chart of the steps of the first embodiment of the semiconductor testing method of the present invention. Figure 7 As shown, the semiconductor testing method includes the following steps: step S71, providing multiple first test units, the first test unit adopts the first test unit described in the present invention; step S72, applying a test voltage at the first pad, the second pad and the third pad to perform an electrical test on the transistor; step S73, statistically analyzing the first spacing corresponding to the first test unit whose electrical test parameters meet the process requirements, so as to obtain the process window parameters of the first spacing.

[0030] Please refer to Figure 3-4 And step S71, providing a plurality of first test units 100, wherein the first test units 100 adopt the present invention Figure 3-4 The first test unit 100.

[0031] Please refer to Figure 3-4 And step S72 , applying a test voltage to the first pad 41 , the second pad 42 , and the third pad 43 to perform an electrical test on the transistor 32 .

[0032] In some embodiments, in the step of applying a test voltage to the first pad 41, the second pad 42, and the third pad 43 to perform an electrical test on the transistor 32, a gate voltage is applied to the first pad 41, a first voltage is applied to the second pad 42, and a second voltage is applied to the third pad 43, and the first voltage is greater than the second voltage. In this embodiment, the first voltage is a positive voltage, and the second voltage is a ground voltage.

[0033] In some embodiments, the electrical test is to test the leakage current of the transistor 31. The first test unit 100 is used to test the overlay accuracy of the mask and polysilicon in the polysilicon cutting process. If the leakage current reaches the mA level, it means that the overlay accuracy of the mask and polysilicon in the polysilicon cutting process has a large deviation, and the first spacing X1 of the first test unit 100 does not meet the process requirements, and the parameters of the first spacing X1 need to be adjusted.

[0034] Please refer to Figure 3-4 And step S73, counting the first spacing X1 corresponding to the first test unit 100 whose electrical test parameters meet the process requirements, to obtain the process window parameters of the first spacing X1.

[0035] See also Figure 8 , which is a flow chart of the steps of the second embodiment of the semiconductor testing method of the present invention. Figure 8 As shown, the semiconductor testing method also includes the following steps: step S81, providing multiple second test units, the second test units adopting the second test units described in the present invention; step S82, applying a test voltage at the first pad and the fourth pad to perform an electrical test on the transistor; step S83, statistically analyzing the second spacing corresponding to the second test unit whose electrical test parameters meet the process requirements, so as to obtain the process window parameters of the second spacing.

[0036] See also Figure 3 and Figure 5 And step S81, providing a plurality of second test units 200, wherein the second test units 200 adopt the present invention Figure 3 and Figure 5 The second testing unit 200.

[0037] See also Figure 3 and Figure 5 And step S82 , applying a test voltage to the first pad 51 and the fourth pad 54 to perform an electrical test on the transistor 32 .

[0038] In some embodiments, in the step of applying a test voltage to the first pad 51 and the fourth pad 54 to perform an electrical test on the transistor 31, a third voltage is applied to the first pad 51, a fourth voltage is applied to the fourth pad 54, and the third voltage is greater than the fourth voltage. In this embodiment, the third voltage is a positive voltage, and the fourth voltage is a ground voltage.

[0039] In some embodiments, the electrical test is to test the leakage current of the transistor 31. The second test unit 200 is used to test the registration accuracy of the active area contact structure and the gate in the polysilicon cutting process. If the leakage current reaches the milliampere (mA) level, it means that the registration accuracy of the active area contact structure and the gate in the second direction D2 has a large deviation, and the second spacing X2 of the second test unit 200 does not meet the process requirements, and the parameters of the second spacing X2 need to be adjusted.

[0040] See also Figure 3 and Figure 5 And step S83, statistically analyzing the second spacing X2 corresponding to the second test units 200 whose electrical test parameters meet the process requirements, so as to obtain the process window parameters of the second spacing X2.

[0041] See also Fig. 9 , which is a flow chart of the steps of the third embodiment of the semiconductor testing method of the present invention. Fig. 9 As shown, the semiconductor testing method also includes the following steps: step S91, providing multiple third test units, the third test unit adopts the third test unit described in the present invention; step S92, applying a test voltage at the first pad and the fourth pad to perform an electrical test on the transistor; step S93, statistically analyzing the third spacing corresponding to the third test unit whose electrical test parameters meet the process requirements, so as to obtain the process window parameters of the third spacing.

[0042] See also Figure 3 and Figure 6 And step S91, providing a plurality of third test units 300, wherein the third test units 300 adopt the present invention Figure 6 The third testing unit 300.

[0043] See also Figure 3 and Figure 6 And step S92 , applying a test voltage to the first pad 61 and the fourth pad 64 to perform an electrical test on the transistor 31 .

[0044] In some embodiments, in the step of applying a test voltage to the first pad 51 and the fourth pad 54 to perform an electrical test on the transistor 31, a third voltage is applied to the first pad 51, a fourth voltage is applied to the fourth pad 54, and the third voltage is greater than the fourth voltage. In this embodiment, the third voltage is a positive voltage, and the fourth voltage is a ground voltage.

[0045] In some embodiments, the electrical test is to test the leakage current of the transistor 31. The third test unit 300 is used to test the registration accuracy of the active area contact structure and the gate in the polysilicon cutting process. If the leakage current reaches the milliampere (mA) level, it means that the registration accuracy of the active area contact structure and the gate in the first direction D1 has a large deviation, and the third spacing X3 of the third test unit 300 does not meet the process requirements, and the parameters of the third spacing X3 need to be adjusted.

[0046] See also Figure 3 and Figure 6 And step S93, statistically analyzing the third spacing X3 corresponding to the third test unit 300 whose electrical test parameters meet the process requirements, so as to obtain the process window parameters of the third spacing X3.

[0047] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0048] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0049] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0050] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor test structure, characterized in that: It includes a polysilicon cut-off region extending along a first direction and at least one dual-transistor structure, wherein the dual-transistor structure includes two transistors symmetrically distributed along the polysilicon cut-off region, and each of the transistors includes: A first active region extending along the first direction, wherein a first distance exists between the first active region and the polysilicon cut-off region; a gate, comprising a first extension portion and a second extension portion located at a first end of the first extension portion, wherein the first end of the first extension portion is an end away from the other transistor, the first extension portion extends along a second direction and partially overlaps with the first active region, and the second extension portion is parallel to the first active region, wherein the second direction forms an angle with the first direction; The first active region is formed with a source and a drain on both sides of the first extension portion of the gate; A second active region, comprising a body and bent portions located at two ends of the body, the body being located at a side of the second extension portion of the gate away from the first active region, and the two bent portions surrounding two ends of the second extension portion of the gate; The semiconductor test structure monitors the polysilicon overlay accuracy of the polysilicon cut-off region by performing an electrical test on the transistor.

2. The semiconductor test structure according to claim 1, characterized in that: The semiconductor test structure includes a plurality of first test units, each of which includes: A plurality of the dual transistor structures arranged along a first direction, the gates of all the transistors are connected in parallel to the first pad, the sources of all the transistors are connected in parallel to the second pad, and the drains of all the transistors are connected in parallel to the third pad; The first spacing of the plurality of first test units is gradually increased, and the transistor is electrically tested by applying a test voltage to the first pad, the second pad and the third pad to obtain a process window parameter of the first spacing.

3. The semiconductor test structure according to claim 2, characterized in that: A gate contact structure is formed on the surface of the second extension portion of the gate, and the first pad is electrically connected to the gate through the gate contact structure; A source contact structure is formed on the surface of the source of the first active region, and the second pad is electrically connected to the source through the source contact structure; A drain contact structure is formed on the drain surface of the first active region, and the third pad is electrically connected to the drain through the drain contact structure.

4. The semiconductor test structure according to claim 1, characterized in that: The semiconductor test structure includes a plurality of second test units, each of which includes: A plurality of the dual transistor structures arranged along a first direction, a body contact structure is formed on a body surface of the second active region of the dual transistor structure, a second distance is provided between the body contact structure and the second extension portion of the gate, the gates of all the transistors are connected in parallel to the first pad, and the second active regions of all the transistors are connected in parallel to the fourth pad through the body contact structure; The second spacing of the plurality of second test units is gradually increased, and the process window parameters of the second spacing are obtained by applying a test voltage to the first pad and the fourth pad to perform an electrical test on the transistor.

5. The semiconductor test structure according to claim 1, characterized in that: The method comprises a plurality of third test units, each of the third test units comprising: A plurality of dual transistor structures arranged along a first direction, wherein a bent portion contact structure is formed on a bent portion surface of the second active region of the dual transistor structure, the bent portion contact structure and the second extension portion of the gate have a third spacing, the gates of all the transistors are connected in parallel to the first pad, and the second active regions of all the transistors are connected in parallel to the fourth pad through the bent portion contact structure; The third spacing of the plurality of third test units is gradually increased, and the process window parameters of the third spacing are obtained by applying a test voltage to the first pad and the fourth pad to perform an electrical test on the transistor.

6. A semiconductor testing method, characterized in that: The steps include: Providing a plurality of first test units, wherein the first test unit is the first test unit according to claim 2; Applying a test voltage to the first pad, the second pad, and the third pad to perform an electrical test on the transistor; The first spacing corresponding to the first test unit whose electrical test parameters meet process requirements is statistically analyzed to obtain a process window parameter of the first spacing.

7. The method according to claim 6, characterized in that In the step of applying test voltages to the first pad, the second pad and the third pad to perform electrical testing on the transistor, a gate voltage is applied to the first pad, a first voltage is applied to the second pad, a second voltage is applied to the third pad, and the first voltage is greater than the second voltage.

8. The method according to claim 6, characterized in that The electrical property test is to test the leakage current of the transistor.

9. The method according to claim 6, characterized in that The following steps are also included: Providing a plurality of second test units, wherein the second test units are the second test units according to claim 4; Applying a test voltage to the first pad and the fourth pad to perform an electrical test on the transistor; The second spacing corresponding to the second test unit whose electrical test parameters meet the process requirement is statistically analyzed to obtain a process window parameter of the second spacing.

10. The method according to claim 9, characterized in that In the step of applying test voltages to the first pad and the fourth pad to perform electrical testing on the transistor, a third voltage is applied to the first pad, a fourth voltage is applied to the fourth pad, and the third voltage is greater than the fourth voltage.

11. The method according to claim 6, characterized in that The following steps are also included: Providing a plurality of third test units, wherein the third test unit is the third test unit according to claim 5; Applying a test voltage to the first pad and the fourth pad to perform an electrical test on the transistor; The third spacing corresponding to the third test unit whose electrical test parameters meet the process requirements is statistically analyzed to obtain a process window parameter of the third spacing.

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