Package and method of forming same

Abstract

A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch including a first source / drain region, a second source / drain region, a second bond pad electrically connected to the first source / drain region, and a third bond pad electrically connected to the second source / drain region. The method further includes bonding the first device die with the second device die to form a first package, wherein the first bond pad is bonded to the third bond pad; and bonding the first package to the package assembly. Embodiments of the disclosure also relate to a package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to packages and methods of forming the same. Background Art

[0002] A head unit (power switch) is used in an integrated circuit to gate the power supplied to certain circuits. The head unit may include a transistor whose source may be connected to a power node such as VDD. The drain may serve as another power node, and its voltage is determined by whether the transistor is on or off. When the head unit is on, the drain receives power and thus powers the circuit. When the head unit is off, no power is supplied to the circuit. Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a package, comprising: forming a first device die, the first device die comprising: a first integrated circuit; a first bonding pad located at a first surface of the first device die, wherein the first integrated circuit is electrically connected to the first bonding pad; forming a second device die, the second device die comprising: a power switch, the power switch comprising: a first source / drain region; a second source / drain region; a second bonding pad electrically connected to the first source / drain region; and a third bonding pad electrically connected to the second source / drain region; bonding the first device die to the second device die to form a first package, wherein the first bonding pad is bonded to the third bonding pad; and bonding the first package to a packaging assembly.

[0004] Another embodiment of the present disclosure provides a package, comprising: a first device die, comprising: a first integrated circuit; and a second device die, comprising a power switch electrically connected to the first integrated circuit, wherein the power switch is configured to: cut off power to the first integrated circuit in response to a first control signal; and provide power to the first integrated circuit in response to a second control signal.

[0005] Another embodiment of the present disclosure provides a package, comprising: a packaging substrate; a first device die located above the packaging substrate and bonded to the packaging substrate, wherein the first device die comprises: a semiconductor substrate; an integrated circuit located on the semiconductor substrate; a through hole penetrating the semiconductor substrate; and a second device die located above the first device die and bonded to the first device die, wherein the second device die comprises a power switch, and wherein the power switch comprises: a first source / drain region electrically connected to the through hole in the first device die; and a second source / drain region connected to the integrated circuit in the first device die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 5 A cross-sectional view of an intermediate stage in the formation of a package including a power switch and power user circuitry separated into separate dies is shown in accordance with some embodiments.

[0008] Figures 6 to 11 A cross-sectional view of an intermediate stage in the formation of a package including a power switch and power user circuitry separated into separate dies is shown in accordance with some embodiments.

[0009] Fig.12 and Fig.13 A cross-sectional view of a package including a power switch and corresponding power user circuitry separated into different dies is shown according to some embodiments.

[0010] Fig.14 A process flow for forming a package including a power switch and power user circuitry separated into different dies is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] A package and a method for forming the same are provided, the package including a power switch and a power user circuit divided in different dies. According to some embodiments of the present disclosure, a first device die is formed to include a power switch, and a second device die is formed and includes a power user circuit. The first device die is bonded to the second device die so that the power switch in the first device die provides and controls power to the power user circuit. By placing the power switch in the first device die instead of the second device die including the power user circuit of the power supply, the chip area of ​​the second device die is saved, and the second device die includes advanced circuits and therefore requires chip area. The embodiments discussed herein are intended to provide examples of the subject matter of the present disclosure that can be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0014] Figures 1 to 5 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure, the package including a power switch and a power user circuit. The corresponding process is also schematically reflected in FIG. Fig.14 In the process flow 200 shown.

[0015] Figure 1 The formation of a device wafer 20 according to some embodiments is shown. The corresponding process is shown as follows Fig.14 The process 201 in the process flow 200 shown in FIG. 1 also forms the device wafer 120. The corresponding process is shown as follows: Fig.14 Process 202 in process flow 200 is shown. Wafer 20 may include multiple device dies 20'. Wafer 120 may include multiple device dies 120'. According to some embodiments, wafer 120 has different circuits and designs from wafer 20. According to some embodiments, wafer 20 includes input / output (IO) circuits, memory circuits (such as dynamic random access memory (DRAM) circuits), static random access memory circuits (SRAM), etc. Wafer 120 may include logic circuits such as a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0016] According to some embodiments, wafer 120 is manufactured using a more advanced (and possibly newer) technology than wafer 20. For example, wafer 20 may be a non-advanced wafer formed using 10 nm or older technology, while wafer 120 may be an advanced wafer manufactured using 7 nm or newer technology. The critical dimensions (the width of the gate) of the transistors in wafer 120 are correspondingly smaller than the critical dimensions of the transistors in wafer 20.

[0017] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and features formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0018] According to some embodiments, wafer 20 includes integrated circuit devices 26 formed at a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown here.

[0019] An interlayer dielectric (ILD) 28 is formed over semiconductor substrate 24 and fills spaces between gate stacks of transistors (not shown) in integrated circuit device 26. According to some embodiments, ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, etc. ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0020] Contact plug 30 is formed in ILD 28 and is used to electrically connect integrated circuit device 26 to overlying metal line 44 and via 46. According to some embodiments, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0021] Figure 1 Also shown is a head unit 32 (optionally referred to as a power switch) according to some embodiments. The power switch 32 may include a transistor, which may include a source region 34, a drain region 36, and a gate 38. The source region 34 and the drain region 36 are collectively referred to as source / drain regions. The power switch 32 has the function of receiving power (referred to as true VDD (TVDD)) on the source region 34, which is optionally referred to as a TVDD node. The drain region 36 is referred to as a virtual VDD (VVDD) node, which receives power when the power switch 32 is turned on and is disconnected from the power when the power switch 32 is turned off. The power on the VVDD node 36 is provided to the power user circuit in the device die 120', as will be discussed in subsequent paragraphs.

[0022] Interconnect structure 42 is formed over ILD 28 and contact plug 30. Interconnect structure 42 may include metal lines 44 and vias 46 formed in dielectric layer 48 (also referred to as intermetallic dielectric (IMD)). Metal lines 44 at the same level are collectively referred to as metal layers hereinafter. According to some embodiments, interconnect structure 42 includes a plurality of metal layers interconnected by vias 46. Metal lines 44 and vias 46 may be formed of copper, copper alloys and / or another metal. According to some embodiments, dielectric layer 48 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.5 or lower than about 3.0. Dielectric layer 48 may include a low-k dielectric material containing carbon.

[0023] According to some embodiments, the formation of metal lines 44 and vias 46 may include a single damascene process or a dual damascene process. According to some embodiments, the formation of the bottom metal layer (including metal lines 44) may be performed by a single damascene process, which includes depositing a dielectric layer 48, etching the dielectric layer 48 to form a trench, filling the trench with a conductive material, and then performing a planarization process such as a CMP process to remove excess portions of the conductive material. The upper metal lines and vias may be formed by a dual damascene process, which includes forming a dielectric layer, forming a via opening and a trench in the dielectric layer, filling the via opening and the trench with a conductive material, and performing a planarization process.

[0024] A passivation layer (not shown separately) may be included above the interconnect structure 42 and may be formed of a non-low-k dielectric material. The passivation layer may be formed of or include undoped silicate glass (USG), silicon nitride, silicon oxide, or the like, or multiple layers thereof. Metal pads (such as aluminum copper pads), post-passivation interconnects (PPIs), and the like may also be present.

[0025] Bonding film 54 is deposited over interconnect structure 42. Top surfaces of bonding film 54 are coplanar. According to some embodiments, bonding film 54 may be formed of a silicon-based dielectric material, which may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc.

[0026] The bonding pad 56 is formed in the bonding film 54 and is electrically connected to the power switch 32 and the integrated circuit 26. The bonding pad 56 may have a top surface coplanar with a top surface of the bonding film 54, which may be achieved by a planarization process. According to some embodiments, the bonding pad 56 is formed in a damascene process that includes etching the bonding film 54 to form an opening, filling the opening with a conductive material, and performing a planarization process.

[0027] Figure 1 The formation of wafer 120 is also shown. According to some embodiments, wafer 120 has layers similar to those of wafer 20. The structures and materials of components in wafer 120 can be found with reference to the same components in wafer 20, where the same components in wafer 120 are indicated by adding the number "1" in front of the reference number of the corresponding components in wafer 20. For example, the substrate in wafer 20 is indicated as 24, and therefore, the substrate in wafer 120 is indicated as 124. Wafer 120 may include integrated circuit devices 126, ILDs 128, contact plugs 130, interconnect structures 142, dielectric layers 148, metal lines 144, and vias 146. Wafer 120 also includes a bonding film 154 and bonding pads 156 located in the bonding film 154. The details of these components may be similar to the corresponding components in wafer 20 and are not repeated here.

[0028] According to some embodiments, wafer 120 includes integrated circuit 126, which also includes active devices and passive devices to form functional circuits. Integrated circuit 126 may include integrated circuit 126A, integrated circuit 126B, and integrated circuit 126C. According to some embodiments, integrated circuit 126A constantly receives power (such as TVDD) during its operation. On the other hand, integrated circuit 126C is a power user circuit that receives a gate voltage VVDD from device die 20' when the power is used. Therefore, depending on whether the power switch 32 is turned on or off, integrated circuit 126C can be powered or not powered. Integrated circuit 126B can be a control circuit that provides a control signal to control whether the power switch 32 is turned on or off, and provides a control signal to control whether the power user circuit 126C receives power.

[0029] According to some embodiments, through-holes 127 (optionally referred to as through-silicon vias (TSVs) or through-semiconductor vias (also referred to as TSVs)) are formed in wafer 120. Through-holes 127 extend from the top surface of semiconductor substrate 124 to an intermediate level between the top surface and the bottom surface of semiconductor substrate 124. The top end of through-holes 127 may extend to the top surface of ILD 128. Alternatively, the top end of through-holes 127 may be at any available level, such as the top surface level of the semiconductor substrate or the top surface level of any one of dielectric layers 148.

[0030] According to some embodiments, such as Figures 1 to 4 As shown, the packaging process is a through-hole first process, in which through-holes 127 are formed before wafer 20 is bonded to wafer 120. According to an alternative embodiment, a through-hole last process may be used to form through-holes 127, so that the through-holes are formed after the wafer bonding process. According to some embodiments, Figure 8 and Fig. 9 An example via-last process is shown in FIG.

[0031] refer to Figure 2 , flipping wafer 20 upside down and bonding it to wafer 120 to form composite wafer 68. The corresponding process is shown as follows Fig.14 Process 204 in process flow 200 is shown. The bonding can be achieved by hybrid bonding, which includes metal-to-metal direct bonding of bonding pad 56 to bonding pad 156, and fusion bonding of bonding film 54 to bonding film 154 (e.g., forming Si-O-Si bonds). According to alternative embodiments, wafers 20 and 120 can be bonded by solder bonding, metal-to-metal direct bonding (of metal bumps), etc. In the example shown, the bonding is face-to-face bonding, where the front side (face) of wafer 20 is bonded to the front side of wafer 120. Figure 2 Arrows 33 on the right are shown pointing towards each other to indicate face-to-face bonding.The front side is the side of the respective semiconductor substrate on which the integrated circuit is formed.

[0032] According to some embodiments, wafer-on-wafer bonding is performed to bond wafer 20 to wafer 120, and thus device die 20' to device die 120'. According to alternative embodiments, bonding may be performed by wafer-on-die bonding (where discrete die 20' is bonded to wafer 120) or die-on-die bonding (where discrete die 20' is bonded to discrete die 120').

[0033] Figure 3 A backside thinning process is shown to thin the semiconductor substrate 124 from the back side of the semiconductor substrate 124. The corresponding process is shown as Fig.14 The process 206 in the process flow 200 is shown. The backside thinning process may be performed by a chemical mechanical polishing (CMP) process or a mechanical grinding process. According to some embodiments, after the through via 127 is exposed from the backside of the semiconductor substrate 124, the backside thinning process is stopped.

[0034] Next, if Figure 4 As shown in FIG. 1 , the semiconductor substrate 124 may be recessed from the back side so that some end portions of the through holes 127 protrude from the semiconductor substrate 124. Figure 4 As shown, a dielectric layer 160 is formed to surround and contact the protruding portion of the through hole 127. According to some embodiments, the formation of the dielectric layer 160 includes depositing a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc. to embed the protruding portion of the through hole 127. A photoplanarization process is then performed to remove excess portions of the dielectric layer and expose the through hole 127 again. The remaining portion of the dielectric material thus forms the dielectric layer 160.

[0035] Next, a backside interconnect structure including a dielectric layer 162 and a metal pad 164 is formed. The corresponding process is shown as follows. Fig.14 Process 208 in process flow 200 is shown. The formation process may include depositing a metal layer, such as an aluminum layer, an aluminum copper layer, a nickel layer, a titanium layer, etc., and then patterning the metal layer and forming metal pads 164. Dielectric layer 162 is then deposited. Alternatively, dielectric layer 162 may be deposited first, and metal pads 164 may be subsequently formed in dielectric layer 162 by a damascene process. It should be understood that although one metal layer (the layer of metal pads 164) is shown, the backside interconnect structure may include multiple metal layers for backside routing of electrical signals / voltages.

[0036] Electrical connectors 166 are then formed. According to some embodiments, electrical connectors 166 include metal pillars, solder regions, etc. Electrical connectors 166 may include electrical connectors (power bumps) 166A and 166B, which will be discussed in subsequent paragraphs.

[0037] In subsequent processes, for example, the die can be separated in a die sawing process. Figure 4 The composite wafer 68 shown in the figure is used to form a plurality of identical packages 68' into discrete packages. The corresponding process is shown as follows Fig.14 Process 210 of process flow 200 is shown. Wafers 20 and 120 in composite wafer 68 are also singulated into device dies 20' and device dies 120', respectively.

[0038] refer to Figure 5 According to some embodiments, one of the discrete packages 68' is bonded to the package assembly 70 to form the package 74. The corresponding process is shown as follows Fig.14 Process 212 in process flow 200 is shown. Package component 70 may be a package substrate, a silicon interposer, an organic interposer, a package with a device die therein, etc. Bonding may be accomplished by solder bonding, metal-to-metal direct bonding, etc. An underfill 72 may then be dispensed between package 68' and package component 70.

[0039] In package 74, electrical connector 166A may be used as a first power bump, and power is supplied to electrical connector 166A from package assembly 70. Power is then supplied through electrical path 76, which includes through-hole 127A, metal line 144 and via 146 of device die 120', and metal line 44 and via 46 of device die 20'. Thus, power (also referred to as non-gated voltage TVDD) is supplied to TVDD node 34.

[0040] When power switch 32 is turned on, power is provided to VVDD node 36, and the corresponding voltage on VVDD node 36 (also referred to as gate voltage / power VVDD) is transmitted back to device die 120' through electrical path 78, which includes metal lines 44 and vias 46 of device die 20' and metal lines 144 and vias 146 of device die 120'. Integrated circuit 126C (also referred to as a power user circuit of gate voltage VVDD) can therefore receive gate voltage VVDD when power switch 32 is turned on. When power switch 32 is turned off, integrated circuit 126C is cut off from power.

[0041] According to some embodiments, by forming the power switch 32 in the device die 20' instead of in the device die 120' where the power user circuit 126C is located, the chip area of ​​the device die 120' is saved. For example, the device die 120' can be a CPU die or a GPU die, which has chip area requirements for its high-density circuits. In addition, the power switch 32 can occupy a large chip area, for example, up to 10% of the chip area of ​​the device die 120'. Therefore, by moving the power switch to the device die 20' where the chip area requirement is lower, the chip area can be used more efficiently. In addition, since the device density of the device die 20' is lower, the metal lines in the device die can be formed wider and thicker, and the voltage drop of the power transmission path in the device die 20' is lower.

[0042] According to some embodiments, the power switch 32 is controlled by the control circuit 35, which can provide a control signal to the gate 38 of the power switch 32 so as to control the on / off state of the power switch 32. According to some embodiments, the control circuit 35 can be located outside the device die 20'. For example, the control circuit 35 can include an integrated circuit 126B that is physically located in the device die 120'. Therefore, the control circuit 35 is shown as a dotted line to indicate that it may not be physically located in the device die 20'. When the control circuit 35 includes the integrated circuit 126B, an additional signal path (not shown) including the metal line 44 and the via 46 in the device die 20', the metal line 44 and the via 146 in the device die 120', and the bonding pads 56 and 156 can electrically connect the integrated circuit 126B to the gate 38 of the power switch 32.

[0043] According to some embodiments, the second power bump 166B is used to provide power to the integrated circuit 126A through the electrical path 80, which includes the through-hole 127B, the metal line 144 and the contact plug 130. Therefore, the device die 120' includes the integrated circuit 126A driven by the non-gated power supply (which may or may not have the non-gated voltage TVDD), and the integrated circuit 126C driven by the gate voltage VVDD. In addition, the integrated circuit 126B (control circuit) can also be connected to the non-gated power supply, for example, by connecting to the power bump 166B, so that the integrated circuit 126B can generate a control signal for controlling the power switch 32 even when the power switch 32 is turned off.

[0044] Figures 6 to 11 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to an alternative embodiment of the present disclosure. Figures 1 to 5 The embodiment shown, except that the device die 120 '(including the power user circuit) is the top die, and the device die 20 'including the power switch is the bottom die. The bonding of the device die 20 'and 120 'is also through face-to-face bonding. Unless otherwise specified, the materials, structures and formation processes of the components in these embodiments are basically the same as the same components represented by the same reference numerals in the previous embodiments. The details about materials, structures and formation processes provided in each embodiment of the entire description can be applied to any other embodiment applicable.

[0045] In the initial process, Figure 6 As shown, wafers 20 and 120 are formed. The materials, structures, and formation processes of wafers 20 and 120 can be found with reference to the discussion of the previous embodiments. However, according to these embodiments, contrary to the previous embodiments, wafer 20 is located at the bottom, and wafer 120 is located at the top. According to some embodiments, through holes can be formed using a through-hole-later process, and no through holes are formed at this time. According to an optional embodiment, through holes can also be formed by a through-hole-first process, and through holes can be formed in wafer 20 at this time. The corresponding process of forming through holes in wafer 120 using a through-hole-first process can be similar to Figures 2 to 4 Process shown.

[0046] Next, refer to Figure 7 For example, wafer 120 is bonded to wafer 20 by hybrid bonding, and other suitable bonding schemes may also be used to form composite wafer 68 .

[0047] refer to Figure 8 , a backside thinning process is performed to thin the semiconductor substrate 24. Then, as Fig. 9As shown, a dielectric layer 60 is formed on the back side of the semiconductor substrate 24 , and a through hole 27 is formed to penetrate the dielectric layer 60 and the semiconductor substrate 24 .

[0048] According to some embodiments, the formation of through hole 27 includes depositing dielectric layer 60 on the back side of semiconductor substrate 24, and etching dielectric layer 60 and semiconductor substrate 24 to form a deep opening. Metal line 44 (metal pad) is exposed in the deep opening. Next, a dielectric liner (not shown) is deposited in a conformal deposition process and extends into the opening, followed by an anisotropic etching process, so that the horizontal portion of the dielectric liner is removed and the vertical portion is left as a dielectric liner. The metal pad of metal line 44 is exposed again. The deep opening is then filled with a conductive material to form through hole 27.

[0049] According to an alternative embodiment, the formation of the through hole 27 includes etching the semiconductor substrate 24 to form a deep opening, forming a dielectric liner lining the deep opening, and forming the through hole 27 surrounded by the dielectric liner in the opening. Then, the semiconductor substrate 24 can be recessed so that some end portions of the through hole 27 protrude from the recessed semiconductor substrate 24. Then, a dielectric layer 60 is formed. The dielectric layer 60 can also be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0050] Next, a backside interconnect structure including a metal pad 64 and a dielectric layer 62 is formed, wherein the metal pad 64 is connected to the through hole 27. The materials and formation processes of the metal pad 64 and the dielectric layer 62 may be respectively the same as those of the Figure 4 The metal pad 164 and the dielectric layer 162 are substantially the same as in the embodiment. Therefore, the details are not repeated here. Then, an electrical connector 166 is formed. The electrical connector 166 can be substantially the same as the electrical connector in the previous embodiment.

[0051] In a subsequent process, for example, the components can be separated in a sawing process. Fig.10 Composite wafer 68 is shown so as to form a plurality of discrete packages 68'. Wafers 20 and 120 are also singulated into device dies 20' and 120', respectively.

[0052] refer to Fig.11 , one of the discrete packages 68' is bonded to a package assembly 70, which may be a package substrate, an interposer (such as a silicon interposer or an organic interposer), a package with a device die therein, etc. Thus, a package 74 is formed. The bonding may be achieved by solder bonding, metal-to-metal direct bonding, etc. An underfill 72 may then be dispensed between the package 68' and the package assembly 70.

[0053] In the package 74, the electrical connector 166A can be used as a first power bump, and power is supplied to the electrical connector 166A from the package component 70. Then the power is supplied through the electrical path 84, which includes the through-hole 27A, the metal line 44 and the contact plug 30. Therefore, the non-selected voltage TVDD is supplied to the TVDD node 34, which can be the source region of the power switch 32. When the power switch 32 is turned on, power is supplied to the VVDD node 36, and the select voltage VVDD is supplied to the integrated circuit 126C through the electrical path 86. The electrical path 86 includes the metal line 44 and the through hole 46 of the device die 20' and the metal line 144 and the through hole 146 of the device die 120'. Therefore, the integrated circuit 126C (also referred to as the power user circuit powered by the select voltage VVDD) can receive the select voltage VVDD when the power switch 32 is turned on, and the power is cut off when the power switch 32 is turned off.

[0054] According to some embodiments, by forming power switch 32 in device die 20 ′ instead of in device die 120 ′ where power user circuit 126C is located, chip area of ​​device die 120 ′ is conserved.

[0055] According to some embodiments, the power switch 32 is located in the device die 20' and is controlled by the control circuit 35, which can provide a control signal to the gate 38 of the power switch 32 and control the on / off state of the power switch 32. According to some embodiments, the control circuit 35 can be located outside the device die 20'. For example, the control circuit 35 can include an integrated circuit 126B that is physically located in the device die 120'. Therefore, the control circuit 35 is shown as a dotted line to indicate that it may not (or may) be physically located in the device die 20'. When the control circuit 35 includes the integrated circuit 126B, an additional signal path (not shown) can electrically connect the integrated circuit 126B to the gate 38 of the power switch 32.

[0056] According to some embodiments, the second power bump 166B is used to provide power to the integrated circuit 26 through the electrical path 88 including the through-hole 27B. In addition, the device die 120' includes an integrated circuit 126A, which receives a non-gated power supply through an electrical path 90, which includes the through-hole 27B of the device die 20', the metal line 44 and the through-hole 46, and the metal line 144 and the through-hole 146 of the device die 120'. The integrated circuit 126A is driven by the non-gated power supply. In addition, the integrated circuit 126B (control circuit) can also be connected to the non-gated power supply, for example, by connecting to the power bump 166B, so that when the power switch 32 is closed, the integrated circuit 126B can be able to generate a signal for controlling the power switch 32.

[0057] Fig.12 An encapsulation 74 formed in accordance with yet another alternative embodiment is shown. Fig.12 A package formed by a facing-to-back bonding scheme is shown, wherein the front side of device die 120 ′ faces the back side of device die 20 ′. Fig.12 Arrow 33 on the right side indicates the facing direction of wafers 20 (and device die 20') and 120 (and device die 120'). In addition, in package 74, device die 20' where power switch 32 is located is located at the bottom, while device die 120' including power user circuits for gating power is located at the top. Fig.12 The package 74 can be formed by Figures 1 to 11 This is achieved by discussing the formation process shown.

[0058] In the package 74, the electrical connector 166A can be used as a first power bump, and power is supplied to the electrical connector 166A from the package component 70. The power is then supplied through the electrical path 94, which includes the metal line 44 and the via 46 in the device die 20' and the contact plug 30. The power is supplied to the TVDD node 34, which can be the source region of the power switch 32. When the power switch 32 is turned on, the gate power is provided to the VVDD node 36. The gate voltage VVDD can be provided to the device die 120' through the electrical path 96. The electrical path 96 includes the metal line 44 and the via 46 of the device die 20', the through hole 27A, the bonding pad, and the metal line 144 and the via 146 of the device die 120'. The integrated circuit 126C (which is also a power user circuit of the gate voltage VVDD) can therefore receive the gate voltage VVDD when the power switch 32 is turned on, and is cut off from the power when the power switch 32 is turned off.

[0059] According to some embodiments, the power switch 32 is located in the device die 20' and can be controlled by a control circuit 35 (such as an integrated circuit 126B), which can provide a control signal to the gate 38 of the power switch 32 and control the on / off state of the power switch 32. According to some embodiments, the control circuit 35 can be located outside the device die 20'. For example, the control circuit 35 can include an integrated circuit 126B that is physically located in the device die 120'. Therefore, the control circuit 35 is shown as a dotted line to indicate that it may not (or may) be physically located in the device die 20'. When the control circuit 35 includes the integrated circuit 126B, an additional signal path can electrically connect the integrated circuit 126B to the gate 38 of the power switch 32.

[0060] According to some embodiments, the second power bump 166B is used to provide power to the integrated circuit 26 through the electrical path 98, which includes the metal line 44 and the through hole 46 of the device tube core 20' and the contact plug 30. In addition, the device tube core 120' includes an integrated circuit 126A, and the integrated circuit 126A receives power through the electrical path 112, which includes the through hole 27B of the device tube core 120', the metal line 144 and the through hole 146, the metal line 44 and the through hole 46 of the device tube core 20', and the bonding pads 56 and 156. The integrated circuit 126A is driven by a non-gated power supply. In addition, the integrated circuit 126B (control circuit) can also be connected to the non-gated voltage, for example, by connecting to the power bump 166B, so that when the power switch 32 is closed, the integrated circuit 126B can be able to generate a signal for controlling the power switch 32.

[0061] Fig.13 An encapsulation 74 is shown formed in accordance with an alternative embodiment. Fig.13 Also shown is a package formed by a facing-to-back bonding scheme, where the front side of device die 20 ′ faces the back side of device die 120 ′. Fig.13 Arrow 33 on the right side indicates the facing direction of wafers 20 (and device die 20') and 120 (and device die 120'). In addition, in package 74, device die 20' where power switch 32 is located is located at the top, while device die 120' including power user circuit 126C of gate voltage VVDD is located at the bottom. Fig.13 The package 74 can be formed by Figures 1 to 11 This is achieved by discussing the formation process shown.

[0062] In package 74, electrical connector 166A may be used as a first power bump, and power is supplied to electrical connector 166A from package assembly 70. Power is then supplied through electrical path 114, which includes metal line 144 and via 146 in device die 120', through via 127A1, and metal line 44 and via 46 in device die 20'. Power is supplied to TVDD node 34, which may be a source region of power switch 32. When power switch 32 is turned on, gate power is supplied to VVDD node 36.

[0063] The gate voltage VVDD may be provided to the device die 120' through the electrical path 116. The electrical path 116 includes the metal lines 44 and vias 46 of the device die 20', the through via 127A2, and the bonding pads 56 and 156. Thus, according to these embodiments, before the gate power is provided to the integrated circuit 126C, the power passes through the two through vias 127A1 and 127A2.

[0064] According to some embodiments, the second power bump 166B is used to provide power to the integrated circuits 126A and 126B through the electrical path 118, which includes the metal line 144 and the through hole 146 of the device tube core 120' and the metal line 44 and the through hole 46 in the device tube core 20'. The device tube core 20' includes the integrated circuit 26 that receives power through the electrical path 122, and the electrical path 122 includes the metal line 144 and the through hole 146 of the device tube core 120', the through hole 127B, and the metal line 44 and the through hole 46 of the device tube core 20'. The integrated circuit 26 is driven by a non-gated power supply. In addition, the integrated circuit 126B (control circuit) can also be connected to the non-gated power supply, for example, by connecting to the power bump 166B, so that when the power switch 32 is closed, the integrated circuit 126B can be able to generate a signal for controlling the power switch 32.

[0065] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, and the test pad allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes intermediate verification of known good dies to increase yield and reduce costs.

[0066] Embodiments of the present disclosure have several advantageous features. By forming the power switch outside the advanced device die, the advanced device die has power user circuits that use gated power, saving chip area that would otherwise be occupied by the power switch requiring chip area. The power switch is moved to a less advanced device die, which has more space to allocate the power switch. In addition, because the metal lines in the less advanced device die can be thicker and wider, the voltage drop of the less advanced device die is lower.

[0067] According to some embodiments of the present disclosure, a method includes forming a first device die, the first device die including a first integrated circuit; a first bonding pad located at a first surface of the first device die, wherein the first integrated circuit is electrically connected to the first bonding pad; forming a second device die including a power switch, the power switch including a first source / drain region; a second source / drain region; a second bonding pad electrically connected to the first source / drain region; and a third bonding pad electrically connected to the second source / drain region; bonding the first device die to the second device die to form a first package, wherein the first bonding pad is bonded to the third bonding pad; and bonding the first package to a packaging assembly.

[0068] In an embodiment, forming the first device die further comprises forming a through hole penetrating the semiconductor substrate of the first device die, wherein after the first device die is bonded to the second device die, the through hole is electrically coupled to the first source / drain region. In an embodiment, the through hole is formed before the first device die is bonded to the second device die. In an embodiment, the through hole is formed after the first device die is bonded to the second device die. In an embodiment, the first device die is bonded between the second device die and the packaging assembly.

[0069] In an embodiment, the first device die is bonded to the package assembly via a power bump, the power bump receives a non-gated voltage from the package assembly and is connected to the first integrated circuit via an electrical path, and wherein the electrical path includes a first portion from the power bump to a power switch; and a second portion from the power switch to the first integrated circuit. In an embodiment, the first device die is bonded to the second device die via a face-to-face bond.

[0070] In an embodiment, the first device die is bonded to the second device die by face-to-back bonding. In an embodiment, the second device die is bonded between the first device die and the package assembly. In an embodiment, the first device die further comprises a second integrated circuit, wherein the second integrated circuit is configured to receive power when the first integrated circuit is powered off by the power switch.

[0071] According to some embodiments of the present disclosure, a structure includes: a first device die including a first integrated circuit; and a second device die including a power switch electrically connected to the first integrated circuit, wherein the power switch is configured to cut off power to the first integrated circuit in response to a first control signal; and to provide power to the first integrated circuit in response to a second control signal. In an embodiment, the first device die includes a logic die, and the second device die includes an input / output die or a memory die. In an embodiment, the structure further includes a control circuit configured to provide a first control signal and a second control signal, wherein the control circuit is located outside the first device die.

[0072] In an embodiment, the control circuit is located in the second device die. In an embodiment, the first device die is bonded to the second device die by face-to-face bonding. In an embodiment, the first device die is bonded to the second device die by face-to-back bonding. In an embodiment, a power supply path for supplying power to the first integrated circuit includes: a first portion that penetrates the first device die to reach a power switch; and a second portion, the second portion having a first portion located in the first device die and a second portion located in the second device die. In an embodiment, the first device die also includes a second integrated circuit, wherein the power supply path for supplying power to the second integrated circuit is decoupled from the power switch.

[0073] According to some embodiments of the present disclosure, a structure includes: a package substrate; a first device die located above the package substrate and bonded to the package substrate, wherein the first device die includes a semiconductor substrate; an integrated circuit located on the semiconductor substrate; a through-hole penetrating the semiconductor substrate; and a second device die located above the first device die and bonded to the first device die, wherein the second device die includes a power switch, and wherein the power switch includes a first source / drain region electrically connected to the through-hole in the first device die; and a second source / drain region connected to the integrated circuit in the first device die. In an embodiment, the power switch is configured to cut off power to the integrated circuit or provide power to the integrated circuit in response to different control signals that control the operation of the power switch.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a package, comprising: A first device die is formed, the first device die comprising: First integrated circuit; a first bonding pad located at a first surface of the first device die, wherein the first integrated circuit is electrically connected to the first bonding pad; A second device die is formed, the second device die comprising: A power switch, the power switch comprising: a first source / drain region; a second source / drain region; a second bonding pad electrically connected to the first source / drain region; and a third bonding pad electrically connected to the second source / drain region; bonding the first device die to the second device die to form a first package, wherein the first bonding pad is bonded to the third bonding pad; and The first package is bonded to a package assembly.

2. The method according to claim 1, wherein: Forming the first device die further includes forming a through-via penetrating a semiconductor substrate of the first device die, wherein the through-via is electrically coupled to the first source / drain region after the first device die is bonded to the second device die.

3. The method according to claim 2, wherein: The through via is formed before the first device die is bonded to the second device die.

4. The method according to claim 2, wherein: The through via is formed after the first device die is bonded to the second device die.

5. The method according to claim 1, wherein: The first device die is bonded between the second device die and the package assembly.

6. The method according to claim 5, wherein: The first device die is bonded to the package assembly via a power bump, the power bump receives a non-gated voltage from the package assembly and is connected to the first integrated circuit via an electrical path, and wherein the electrical path includes: A first portion, from the power bump to the power switch; and The second part is from the power switch to the first integrated circuit.

7. The method according to claim 1, wherein: The first device die is bonded to the second device die via face-to-face bonding.

8. The method according to claim 1, wherein: The first device die is bonded to the second device die by face-to-back bonding.

9. A package comprising: A first device die, comprising: a first integrated circuit; and A second device die comprising a power switch electrically connected to the first integrated circuit, wherein the power switch is configured as: cutting off power to the first integrated circuit in response to a first control signal; and Power is provided to the first integrated circuit in response to a second control signal.

10. A package comprising: Package substrate; A first device die is located above the package substrate and bonded to the package substrate, wherein the first device die comprises: Semiconductor substrate; an integrated circuit, located on the semiconductor substrate; a through hole penetrating the semiconductor substrate; and a second device die located above and bonded to the first device die, wherein the second device die comprises a power switch, and wherein the power switch comprises: a first source / drain region electrically connected to the through via in the first device die; and A second source / drain region is coupled to the integrated circuit in the first device die.

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