Operational amplifier with low noise and wide output swing

Abstract

The invention relates to an operational amplifier with low noise and wide output swing. Various examples in accordance with the present disclosure provide operational amplifiers with low noise and wide output swing.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 516,713 filed on July 31, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate generally to operational amplifiers, and more particularly to low noise inverter based amplifiers with wide output swing. Background Art

[0004] Applicants have discovered many technical challenges and difficulties associated with operational amplifiers. Through effort, ingenuity, and innovation, Applicants have addressed many of these identified problems by developing embodiments of the present disclosure, which are described in detail below. Summary of the invention

[0005] Various embodiments described herein are provided that relate to operational amplifiers having low noise and wide output swing.

[0006] According to one aspect of the present disclosure, an operational amplifier is provided. In some embodiments, the operational amplifier includes an input stage. The input stage includes: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor selectively coupled to the first inverter and the second inverter via a first switch, the first common-tail transistor being configured to limit a bias current; and a second common-tail transistor selectively coupled to the first inverter and the second inverter via a second switch. The operational amplifier also includes an output stage. The output stage includes: a third inverter and a fourth inverter coupled together, the third inverter and the fourth inverter selectively coupled to a supply voltage via a third switch and selectively coupled to ground via a fourth switch; a first capacitive coupling element configured to couple the third inverter to a first output of the input stage; and a second capacitive coupling element configured to couple the fourth inverter to a second output of the input stage.

[0007] In some embodiments, the first inverter includes a first PMOS transistor and a first NMOS transistor, which are coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and the second inverter includes a second PMOS transistor and a second NMOS transistor, which are coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

[0008] In some embodiments, the first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; and the first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

[0009] In some embodiments, the third inverter includes a third PMOS transistor and a third NMOS transistor, which are coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and the fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, which are coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

[0010] In some embodiments, the third PMOS transistor and the fourth PMOS transistor are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor; and the third NMOS transistor and the fourth NMOS transistor are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor.

[0011] In some embodiments, the gate terminal of the third PMOS transistor and the gate terminal of the third NMOS transistor are coupled to the first output of the input stage via a first capacitive coupling; and the gate terminal of the fourth PMOS transistor and the gate terminal of the fourth NMOS transistor are coupled to the second output of the input stage via a second capacitive coupling.

[0012] In some embodiments, the first capacitive coupling comprises a first switched capacitor circuit.

[0013] In some embodiments, the second capacitive coupling comprises a second switched capacitor circuit.

[0014] In some embodiments, the operational amplifier further includes a bias current circuit coupled to the first common-tail transistor.

[0015] In some embodiments, a common-mode feedback circuit coupled to the second common-tail transistor is also included.

[0016] In some embodiments, the operational amplifier is configured to operate in one or more of a biasing phase and an amplification phase.

[0017] In some embodiments, in the biasing phase, each of the first switch, the second switch, the third switch, and the fourth switch is in an open state.

[0018] According to another aspect of the present disclosure, an operational amplifier is provided. In some embodiments, the operational amplifier includes an input stage. The input stage includes: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor coupled to the first inverter and the second inverter, the first common-tail transistor configured to limit a bias current; and a second common-tail transistor coupled to the first inverter and the second inverter. The operational amplifier also includes an output stage. The output stage includes: a third inverter and a fourth inverter coupled together; a first capacitive coupling configured to couple the third inverter to a first output of the input stage; and a second capacitive coupling configured to couple the fourth inverter to a second output of the input stage.

[0019] In some embodiments, the first inverter includes a first PMOS transistor and a first NMOS transistor, which are coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and the second inverter includes a second PMOS transistor and a second NMOS transistor, which are coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

[0020] In some embodiments, the first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; and the first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

[0021] In some embodiments, the third inverter includes a third PMOS transistor and a third NMOS transistor, which are coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and the fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, which are coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

[0022] In some embodiments, the third PMOS transistor and the fourth PMOS transistor are coupled together via source terminals of the third PMOS transistor and the fourth PMOS transistor; and the third NMOS transistor and the fourth NMOS transistor are coupled together via source terminals of the third NMOS transistor and the fourth NMOS transistor.

[0023] In some embodiments, the gate terminal of the third PMOS transistor and the gate terminal of the third NMOS transistor are coupled to the first output of the input stage via a first capacitive coupling; and the gate terminal of the fourth PMOS transistor and the gate terminal of the fourth NMOS transistor are coupled to the second output of the input stage via a second capacitive coupling.

[0024] In some embodiments, the operational amplifier further includes a bias current circuit coupled to the first common-tail transistor.

[0025] In some embodiments, the operational amplifier further includes a common-mode feedback circuit coupled to the second common-tail transistor.

[0026] The foregoing illustrative summary as well as other exemplary objects and / or advantages of the present disclosure and embodiments thereof are further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The description of the illustrative embodiments may be read in conjunction with the accompanying drawings. It should be appreciated that, for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale unless otherwise described. For example, unless otherwise described, the dimensions of some elements may be exaggerated relative to other elements. Embodiments incorporating the teachings of the present disclosure are shown and described with respect to the drawings presented herein, in which:

[0028] Figure 1 An example multiplying digital-to-analog converter (MDAC) of a pipeline digital-to-analog converter (ADC) is provided in which an operational amplifier may be used.

[0029] Figure 2 An example operational amplifier in accordance with at least one embodiment of the present disclosure is illustrated.

[0030] Figure 3 A flow chart depicting the operation of an example operational amplifier during a bias phase in accordance with at least one example embodiment of the present disclosure is provided.

[0031] Figure 4A A flow chart is provided that depicts the operation of an example operational amplifier during an amplification phase in accordance with at least one example embodiment of the present disclosure.

[0032] Figure 4B An example timing diagram corresponding to a bias phase and an amplification phase is provided in accordance with at least one example embodiment of the present disclosure.

[0033] Figure 5 An example operational amplifier in accordance with at least one embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0034] Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, these disclosures may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout the text.

[0035] As used herein, terms such as "front", "rear", "top", etc. are used for explanation purposes in the examples provided below to describe the relative positions of certain components or parts of components. In addition, based on this disclosure, it will be clear to one of ordinary skill in the art that the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within applicable engineering tolerances.

[0036] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and composed essentially of.

[0037] The phrases "in one embodiment," "according to one embodiment," and the like generally mean that a particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases are not necessarily referring to the same embodiment).

[0038] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0039] If the specification states that a component or feature "may", "could", "might", "should", "will", "preferably", "likely", "usually", "optionally", "for example", "often", or "might" (or other such language) be included or have a certain property, then the particular component or feature is not required to be included or have that property. Such components or features may optionally be included in some embodiments, or may be excluded.

[0040] As used herein, the term "or" is used in an alternative sense and a connecting sense, unless otherwise indicated. The terms "illustrative" and "example" are used as examples, without indicating a quality level. Terms such as "calculate," "determine," "generate," and / or similar words are used interchangeably herein to refer to the creation, modification, or identification of data. In addition, "based on," "partially based on," "at least based on," "based on," and / or similar words are used interchangeably herein in an open manner, so that they do not indicate only based on or only based on one or more elements cited, unless so indicated. Similar reference numerals refer to similar elements throughout the text.

[0041] In some examples, an operational amplifier may refer to an electronic component that increases the amplitude or strength of an input signal, for example, without changing its original shape or characteristics. As described above, there are many technical challenges and difficulties associated with operational amplifiers. For example, many applications such as high-speed analog-to-digital converters (ADCs) require operational amplifiers with high bandwidth and high gain. However, in order to meet such high bandwidth and high gain requirements, operational amplifiers may consume a lot of power. As another example, the amount of current consumed may vary significantly between processes, voltages, and temperatures (PVT), which in turn may result in significant changes in other parameters associated with the operational amplifier (e.g., gain, bandwidth, noise, and / or other parameters). As yet another example, in order to meet high bandwidth and high gain requirements, a large amount of sample noise voltage variance (e.g., KT / C noise) may be generated, which may have a negative impact on the overall noise performance of the operational amplifier.

[0042] Embodiments of the present disclosure solve the challenges and difficulties mentioned above and other challenges and difficulties associated with operational amplifiers. Specifically, embodiments of the present disclosure provide operational amplifiers with low noise and wide output swing, which can meet the high bandwidth and high gain requirements associated with many applications using operational amplifiers. Moreover, embodiments of the present disclosure provide to mitigate the amount of power consumed. Some embodiments include two amplifier stages, wherein the first amplifier stage (e.g., input stage) includes a current-biased inverting amplifier, and the second amplifier stage (e.g., output stage) includes a capacitively biased inverting amplifier. In some embodiments, the current-biased inverting amplifier includes (one or more) inverters including PMOS and NMOS transistors. In some embodiments, the capacitively biased inverting amplifier includes (one or more) inverters including PMOS and NMOS transistors. In some embodiments, the PMOS and NMOS transistors of the first amplifier stage and / or the PMOS and NMOS transistors of the second amplifier stage are configured as drivers. For example, some embodiments utilize the corresponding PMOS and NMOS transistors of the first amplifier stage to drive the second amplifier stage and / or the load. Some embodiments utilize common-tail transistors at the first amplifier stage to define a bias current for the operational amplifier.

[0043] By using a current biased inverting amplifier (e.g., with a common-tail transistor) at the first amplifier stage and a capacitive biased inverting amplifier at the second amplifier stage, embodiments of the present disclosure avoid any KT / C noise at the input of the first amplifier stage and mitigate / reduce the effects of KT / C noise generated at the input of the second amplifier stage. In this regard, embodiments of the present disclosure improve the overall noise performance of the operational amplifier, thereby providing a low noise operational amplifier that can be used in a variety of applications, environments, systems, etc.

[0044] Furthermore, by using a common-tail transistor at the first amplifier stage of the operational amplifier for the purpose of current biasing and for the purpose of applying common-mode feedback, respectively, the embodiments of the present disclosure have a good common-mode rejection ratio, especially for the first amplifier stage. When used in an external feedback loop, such as in the case of a multiplying DAC in a pipeline ADC, this mitigates the impact of any changes in the input common mode of the operational amplifier on its performance and helps ensure the common-mode stability of the two-stage operational amplifier.

[0045] In addition, by using a capacitively biased inverting amplifier at the second amplifier stage corresponding to the output stage of the operational amplifier, embodiments of the present disclosure provide a wide output swing with a stable output common mode. This is possible because the effective supply of the output stage, which is the difference between the potentials of the source terminals of the PMOS and NMOS transistors of the output stage, remains almost fixed to the difference between the external supply and ground, and does not vary with process and temperature. This ensures maximum headroom for the transistors of the output stage, thereby achieving a wide output swing that can be centered around the midpoint of the supply.

[0046] Furthermore, by using both PMOS and NMOS transistors as drivers, the transconductance (e.g., g m ) is effectively doubled. It will be appreciated that noise, bandwidth, and current consumption are generally related to (e.g., linked to) the transconductance (e.g., input gm) of the operational amplifier. Thus, by using both PMOS and NMOS transistors of the amplifier stage as drivers, embodiments of the present disclosure provide lower noise, higher bandwidth, and lower current consumption, e.g., due at least in part to the increased transconductance achieved by utilizing a dual PMOS and NMOS driver configuration.

[0047] As described above, operational amplifiers can be used in various applications, environments, and / or systems. Non-limiting examples of applications, environments, and / or systems in which operational amplifiers can be used include pipeline ADCs, pipeline SAR ADCs, and the like. Various applications, environments, and / or systems can have different operational amplifier requirements (e.g., different bandwidth requirements, different noise requirements, etc.). Additionally or alternatively, various applications, environments, and / or systems can use operational amplifiers in different ways. For example, in the example context, a pipeline ADC can use an operational amplifier as a residual amplifier.

[0048] Figure 1 The diagram shows example applications where operational amplifiers can be used. Specifically, Figure 1 An example MDAC circuit 100 for a pipeline ADC is shown. Figure 1 As shown in , the MDAC circuit includes an operational amplifier 102, which is used as the core of the gain in the MDAC. In various embodiments, in order to use the operational amplifier in the pipeline ADC as a residual amplifier, the pipeline ADC requires the operational amplifier to have high gain, low noise and wide output swing. Moreover, it is expected to meet these operational amplifier requirements (e.g., high gain, low noise and wide output swing) while efficiently consuming power. The example operational amplifier according to the embodiment of the present disclosure can be used to meet the above-mentioned high gain, low noise and wide output swing requirements, while also reducing the amount of power consumed. In some embodiments, the example operational amplifier is a two-stage operational amplifier.

[0049] Although the above description provides example MDAC and / or pipeline ADC, it should be noted that the scope of the present disclosure is not limited to the above description. The example embodiments of the present disclosure can be implemented in other applications and / or systems. For example, in addition to using an operational amplifier as a residual amplifier, other applications and / or systems may require an operational amplifier with high gain, low noise and wide output swing for various reasons.

[0050] Figure 2 An example operational amplifier 200 is shown in accordance with at least one embodiment of the present disclosure. Specifically, Figure 2 An example discrete-time implementation of an example operational amplifier circuit in accordance with at least one embodiment of the present disclosure is illustrated. In some embodiments, the example operational amplifier 200 includes a first amplifier stage 20a representing an input stage of the operational amplifier and a second amplifier stage 20b representing an output stage of the operational amplifier 200. For example, in some embodiments, the first amplifier stage 20a is the input stage of the operational amplifier 200, and the second amplifier stage 20b is the output stage of the operational amplifier 200. In this regard, the first amplifier stage 20a may include a first gain stage of the operational amplifier 200, and the second amplifier stage 20b may include a second gain stage of the operational amplifier 200.

[0051] In some embodiments, the first amplifier stage 20a includes a first inverter 22a and a second inverter 22b. In some embodiments, the first inverter 22a includes a first PMOS transistor 224a and a first NMOS transistor 226a. In some embodiments, the second inverter 22b includes a second PMOS transistor 224b and a second NMOS transistor 226b. The first inverter 22a and the second inverter 22b can be configured to operate in a differential manner. For example, in some embodiments, the first inverter 22a and the second inverter 22b include differential inverters or are otherwise used as differential inverters. It should be appreciated that in some embodiments, the first inverter 22a and the second inverter 22b can include different inverter configurations. For example, in some embodiments, the first inverter 22a can include transistors of different types and / or transistors arranged in different configurations.

[0052] In some embodiments, the gate terminal of the first PMOS transistor 224a and the gate terminal of the first NMOS transistor 226a form or otherwise define the first input 220a. In some embodiments, the gate terminal of the second PMOS transistor 224b and the gate terminal of the second NMOS transistor 226b form or otherwise define the second input 220b. For example, in some embodiments, the gate terminals of each of the first PMOS transistor 224a and the first NMOS transistor 226a are coupled together, while the gate terminals of each of the second PMOS transistor 224b and the second NMOS transistor 226b are coupled together.

[0053] In some embodiments, the drain terminal of the first PMOS transistor 224a and the drain terminal of the first NMOS transistor 226a are coupled together and form or otherwise define a first output 232a of the first amplifier stage 20a. In some embodiments, the drain terminal of the second PMOS transistor 224b and the drain terminal of the second NMOS transistor 226b are coupled together and form or otherwise define a second output 232b of the first amplifier stage 20a. For example, in some embodiments, the first amplifier stage 20a is configured to output the first output 232a via the drain terminals of the first PMOS transistor 224a and the first NMOS transistor 226a, and to output the second output 232b via the drain terminals of the second PMOS transistor 224b and the second NMOS transistor 226b.

[0054] In some embodiments, the first output 232a and the second output 232b of the first amplifier stage 20a are coupled to the second amplifier stage 20b. As described herein, in some embodiments, the first output 232a and the second output 232b are provided as inputs to the second amplifier stage 20b. In some embodiments, the first output 232a is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the first output 232a is coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b) via a first RC circuit, wherein the first RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the first output 232a is selectively coupled to the voltage 278 via a switch 276a. The switch 276a may be referred to as a bias switch.

[0055] In some embodiments, the second output 232b is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the second output 232b is coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b) via a second RC circuit, wherein the second RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the second output 232b is selectively coupled to the voltage 278 via a switch 276b. The switch 276b may be referred to as a bias switch.

[0056] In some embodiments, the source terminal of the first NMOS transistor 226a and the source terminal of the second NMOS transistor 226b are selectively coupled to the first common-end transistor 222a configured to define a bias current. Figure 2 As shown in , in some embodiments, the gate terminal of the first common-tail transistor 222a is coupled to the bias voltage 230. For example, the first common-tail transistor 222a can be connected to the bias current circuit 201. In this regard, the first inverter 22a and the second inverter 22b can have an input current (e.g., defining the gate potential of the first common-tail transistor 222a) through the respective first and second inverters 22a, 22b biased with the first common-tail transistor 222a. Figure 2 Although depicted as an NMOS type transistor, it should be appreciated that the first common-tail transistor 222a may be of a different type, such as a PMOS type.

[0057] In some embodiments, the first switch 228a is disposed between the drain terminal of the first common-tail transistor 222a and the source terminals of the first and second NMOS transistors 226a, 226b to facilitate selectively coupling the first common-tail transistor 222a to the first and second NMOS transistors 226a, 226b. In some embodiments, the first end of the first switch 228a is coupled to the drain terminal of the first common-tail transistor 222a, and the second end of the first switch 228a is coupled to the source terminals of the first and second NMOS transistors 226a, 226b. The first switch 228a may be referred to as an amplifier switch.

[0058] In some embodiments, by utilizing a common-tail transistor, such as utilizing a first common-tail transistor 222a at a first amplifier stage (e.g., input stage) to limit a bias current and utilizing a second common-tail transistor 222b to apply common-mode feedback, embodiments of the present disclosure mitigate or reduce the impact of any changes in the input common mode of the amplifier on its performance. Thus, embodiments of the present disclosure provide a good common-mode rejection ratio, and thereby provide good common-mode stability. For example, the absence of a common-tail transistor may result in a poor common-mode rejection ratio (CMRR). In various contexts, when used within an external feedback loop, a poor CMRR is particularly undesirable in a two-stage operational amplifier. Here, the external loop may provide negative feedback in differential mode, while in common mode, the operational amplifier will be in positive feedback. Thus, a poor CMRR coupled with positive feedback may result in common-mode instability.

[0059] In some embodiments, the source terminal of the first PMOS transistor 224a and the source terminal of the second PMOS transistor 224b are selectively coupled to the second common-end transistor 222b. Figure 2 As shown in FIG. 2 , in some embodiments, the gate terminal of the second common-tail transistor 222 b is coupled to a common-mode feedback circuit (CMFB) 30 (which is depicted as a functional block for ease of illustrating the example operational amplifier 200 ). For example, the gate voltage of the second common-tail transistor 222 b can be controlled by the output of the common-mode feedback circuit 30. Although the second common-tail transistor 222 b is Figure 2 Although depicted as a PMOS type transistor, it should be appreciated that the second common-tail transistor 222 b may be an NMOS type.

[0060] In some embodiments, the second switch 228b is disposed between the drain terminal of the second common-tail transistor 222b and the source terminals of the first and second PMOS transistors 224a, 224b to facilitate selectively coupling the second common-tail transistor 222b to the first and second PMOS transistors 224a, 224b. In some embodiments, the first end of the second switch 228b is coupled to the drain terminal of the second common-tail transistor 222b, and the second end of the first switch 228a is coupled to the source terminals of the first and second PMOS transistors 224a, 224b. The second switch 228b may be referred to as an amplifier switch.

[0061] In some embodiments, and as Figure 2 As shown in , the first amplifier stage 20a does not include a bias capacitor. In this regard, the first amplifier stage 20a will not be associated with a bias capacitor or otherwise generate KT / C noise that is generally associated with a bias capacitor. Thus, embodiments of the present disclosure provide an operational amplifier with low noise, at least in part due to the absence of (one or more) bias capacitors in the first amplifier stage.

[0062] In some embodiments, the first and second switches 228a, 228b are configured to facilitate multi-phase operation of the example operational amplifier 200. For example, in some embodiments, the operational amplifier 200 is configured to operate in a first phase corresponding to a bias phase and a second phase corresponding to an amplification phase. In some embodiments, the switches 228a and 228b are open (e.g., in an open state) during the bias phase.

[0063] like Figure 2 As shown in FIG. 1 , in some embodiments, the PMOS and NMOS transistors of both the first and second amplifier stages are used as drivers, thereby effectively making the transconductance (e.g., g) of the amplifier stage m ) is doubled. For example, when both the NMOS transistor and the PMOS transistor have the same transconductance, the transconductance of the operational amplifier 200 is effectively doubled, which in turn facilitates reduced noise, increased bandwidth, and reduced current consumption.

[0064] In some embodiments, the second amplifier stage 20b corresponding to the output stage of the example operational amplifier 200 includes a third inverter 24a and a fourth inverter 24b. In some embodiments, the third inverter 24a includes a third PMOS transistor 244a and a third NMOS transistor 246a. In some embodiments, the fourth inverter 24b includes a fourth PMOS transistor 244b and a fourth NMOS transistor 246b. In some embodiments, the third inverter 24a and the fourth inverter 24b are configured to operate in a differential manner. For example, in some embodiments, the third inverter 24a and the fourth inverter 24b include differential inverters or are otherwise used as differential inverters. It should be appreciated that in some embodiments, the third inverter 24a and the fourth inverter 24b may include different inverter configurations. For example, in some embodiments, the third inverter 24a may include transistors of different types and / or transistors arranged in different configurations.

[0065] In some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are each coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are each coupled to the second output 232b of the first amplifier stage 20a. As further described herein, in some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a.

[0066] In some embodiments, the drain terminal of the third PMOS transistor 244a and the drain terminal of the third NMOS transistor 246a are coupled together and define a first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are coupled together and define a second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and to output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b. Figure 2 As shown in , in some embodiments, the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are coupled to the first output 232a of the first amplifier stage 20a via a first RC circuit, and the drain terminal of the fourth NMOS transistor 246b is coupled to the second output 232b of the first amplifier stage 20a via a second RC circuit.

[0067] In some embodiments, the source terminal of the third NMOS transistor 246a and the source terminal of the fourth NMOS transistor 246b are selectively coupled to the ground 290a. In some embodiments, the third switch 248a is disposed between the ground 290a and the source terminals of the third and fourth NMOS transistors 246a, 246b to facilitate selectively coupling the ground 290a to the third and fourth NMOS transistors 246a, 246b. The third switch 248a may be referred to as an amplifier switch. In some embodiments, the first end of the third switch 248a is coupled to the ground 290a, and the second end of the third switch 248a is coupled to the source terminals of the third and fourth NMOS transistors 246a, 246b.

[0068] In some embodiments, the source terminal of the third PMOS transistor 244a and the source terminal of the fourth PMOS transistor 244b are selectively coupled to the voltage supply 290b. In some embodiments, the fourth switch 248b is disposed between the voltage supply 290b and the source terminals of the third and fourth PMOS transistors 244a, 244b to facilitate the selective coupling of the voltage supply 290b to the third and fourth NMOS transistors 246a, 246b. The fourth switch 248b may be referred to as an amplifier switch. In some embodiments, the first end of the fourth switch 248b is coupled to the voltage supply 290b, and the second end of the fourth switch 248b is coupled to the source terminals of the third and fourth PMOS transistors 244a, 244b. In some embodiments, the third and fourth switches 248a, 248b are configured to facilitate multi-stage operation of the example operational amplifier 200. For example, as described above, in some embodiments, the operational amplifier 200 is configured to operate in a first stage corresponding to the bias stage and a second stage corresponding to the amplification stage. In some embodiments, the third switch 248a and the fourth switch 248b are open (eg, open state) during the bias phase and closed (eg, closed state) during the amplification phase.

[0069] As described above, in some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a. In this regard, in some embodiments, the second amplifier stage 20b is capacitively biased. In some embodiments and as Figure 2As depicted in , the second amplifier stage 20b includes a first switched capacitor circuit coupled to the third inverter 24a. For example, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a via the first switched capacitor circuit, wherein a portion of the first switched capacitor circuit can be coupled to the gate terminal of the third PMOS transistor 244a, and a portion of the first switched capacitor circuit can be coupled to the gate terminal of the third NMOS transistor 246a. Additionally or alternatively, in some embodiments, the second amplifier stage 20b includes a second switched capacitor circuit coupled to the fourth inverter 24b. For example, the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b via the second switched capacitor circuit, wherein a portion of the second switched capacitor circuit can be coupled to the gate terminal of the fourth PMOS transistor 244b, and a portion of the second switched capacitor circuit can be coupled to the gate terminal of the fourth NMOS transistor 246b.

[0070] In some embodiments, the first switched capacitor circuit includes a first capacitor 272a and a second capacitor 272b, each coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the first capacitor 272a is coupled to the gate terminal of the third NMOS transistor 246a. In some embodiments, the second capacitor 272b is coupled to the gate terminal of the third PMOS transistor 244a. In some embodiments, the second switched capacitor circuit includes a third capacitor 274a and a fourth capacitor 274b, each coupled to the second output 232b of the first amplifier stage 20a. In some embodiments, the third capacitor 274a is coupled to the gate terminal of the fourth NMOS transistor 246b. In some embodiments, the fourth capacitor 274b is coupled to the gate terminal of the fourth PMOS transistor 244b.

[0071] In some embodiments, the first switched capacitor circuit includes a first switch 262a and a second switch 262b. The first switch 262a and the second switch 262b may each be referred to as a bias switch. The first end of the first switch 262a may be coupled to the capacitor 272a and the gate of the third NMOS transistor 246a, and the second end of the first switch 262a may be coupled to the bias voltage 282a. The first end of the second bias switch 262b may be coupled to the capacitor 272b and the gate of the third PMOS transistor 244a, and the second end of the second bias switch 262b may be coupled to the bias voltage 282b.

[0072] In some embodiments, the second switch capacitor circuit includes a third switch 264a and a fourth switch 264b. The third switch 264a and the fourth switch 264b can each be referred to as a bias switch. The first end of the third switch 264a can be coupled to the gate of the capacitor 274a and the fourth NMOS transistor 246b, and the second end of the third switch 264a can be coupled to the bias voltage 282a. The first end of the fourth switch 264b can be coupled to the gate of the capacitor 274b and the fourth PMOS transistor 244b, and the second end of the fourth switch 264b can be coupled to the bias voltage 282b. In some embodiments, the bias voltage 282a corresponds to the gate potential of the third NMOS transistor 246a and the fourth NMOS transistor 246b or otherwise defines the gate potential. In some embodiments, the bias voltage 282b corresponds to the gate potential of the third PMOS transistor 244a and the fourth PMOS transistor 244b or otherwise defines the gate potential.

[0073] In this regard, the gate terminals of the third NMOS transistor 246a and the fourth NMOS transistor 246b are selectively coupled to the bias voltage 282a via the first switch 262a and the third switch 264a, and the gate terminals of the third PMOS transistor 244a and the fourth PMOS transistor 244b are selectively coupled to the bias voltage 282b via the first switch 262a and the fourth switch 264b.

[0074] In some embodiments, the switches 262a, 262b, 264a, 264b are configured to facilitate multi-phase operation of the example operational amplifier 200. For example, as described above, in some embodiments, the operational amplifier 200 can be configured to operate in a first phase corresponding to a bias phase and a second phase corresponding to an amplification phase. In some embodiments, in the first phase (e.g., the bias phase), the switches 262a, 262b, 264a, 264b are closed (e.g., in a closed state), thereby coupling the third NMOS transistor 246a and the fourth NMOS transistor 246b to the bias voltage 282a, and coupling the gate terminal of the third PMOS transistor 244a and the gate terminal of the fourth PMOS transistor 244b to the bias voltage 282b. In some embodiments, in the second stage (e.g., amplification stage), switches 262a, 262b, 264a, 264b are opened (e.g., in an open state), so that changes in the input are reflected on the gates of each PMOS and NMOS transistor (e.g., 244a, 244b, 246a, 246b) of the inverter pair 24a, 24b of the second amplifier stage 20b, while they are maintained at the gate potential / bias voltage 282a, 282b around the center point of their changes.

[0075] In some embodiments, the bias capacitors 272a, 272b, 274a, 274b may be refreshed (e.g., periodically) with the bias voltages 282a, 282b during a bias phase (e.g., when the operational amplifier 200 is not in use) and used as floating batteries between the inputs and the gate terminals of the PMOS and NMOS transistors of the inverter pair 24a, 24b of the second amplifier stage 20b. As described above, the inputs may include or otherwise correspond to the first output 232a and the second output 232b of the first amplifier stage 20a.

[0076] In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a. In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a first RC circuit including a resistor and a capacitor. In some embodiments, the second output 232b of the first amplifier stage is coupled to the fourth capacitor 274b of the second amplifier stage 20b and the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a. In some embodiments, the second output 232b of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a second RC circuit including a resistor and a capacitor.

[0077] In some embodiments, the drain terminal of the third PMOS transistor 244a and the drain terminal of the third NMOS transistor 246a are coupled together and form or otherwise define the first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the drain terminal of the fourth NMOS transistor 246b are coupled together and form or otherwise define the second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and to output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b. In some embodiments, the first output 252a and the second output 252b of the second amplifier stage 20b are coupled to the common-mode feedback circuit 30. For example, in some embodiments, the first output 252a and the second output 252b are provided as inputs to the common-mode feedback circuit 30.

[0078] As described above, the example operational amplifier 200 is capable of operating in two phases. In some embodiments, the operational amplifier 200 is capable of operating in a first phase representing a bias phase and a second phase representing an amplification phase. Figure 3 A flow chart illustrating the operation of an example operational amplifier in a bias phase according to at least one example embodiment of the present disclosure is illustrated. Specifically, Figure 3 An example process 300 is depicted. In some embodiments, the example method 300 may be combined with Figure 2 The example operational amplifier 200 is described to be implemented.

[0079] According to some examples, the method includes placing amplification switches of the operational amplifier in an open state at operation 302. For example, the example method includes placing switches 228a, 228b coupled to the inverters of the first amplifier stage 20a in an open state, and placing switches 248a and 248b coupled to the second amplifier stage 20b in an open state, so that the inverter pair of the first amplifier stage and the inverter pair of the second amplifier stage are disconnected from their respective supplies and grounds.

[0080] According to some examples, the method includes placing bias switches of the operational amplifier in a closed state at operation 304. For example, the example method includes placing switches 262a, 262b, 264a, 264b coupled to the inverter of the second amplifier stage 20b in a closed state, and placing switches 276a, 276b coupled to the first output and the second output of the first amplifier stage 20a in a closed state. In this regard, by placing bias switches coupled to the PMOS and NMOS transistors of the second stage in a closed state, a corresponding bias potential is applied to each gate of the PMOS and NMOS transistors of the second stage. For example, in some embodiments, the gate terminals of the PMOS and NMOS transistors of the inverter of the second amplifier stage are coupled to their corresponding bias potentials during the bias phase. For example, the PMOS transistors 244a, 244b are coupled to the bias voltage 282b, and the NMOS transistors 246a, 246b are coupled to the bias voltage 282a. In this regard, the first and second outputs of the first amplifier stage are coupled to a voltage 278, e.g., switched to a fixed voltage, by placing bias switches coupled to the first output 232a and the second output 232b of the first amplifier stage 20a in a closed state. In this regard, in some embodiments, a voltage drop (e.g., "Vbp-VCM1" and "Vbn-VCM1") is stored across the bias capacitors. In some embodiments, this stored voltage drop is used as a floating battery during the amplification phase to set an appropriate current bias in the second amplifier stage.

[0081] In this regard, during the bias phase, both the first amplifier stage and the second amplifier stage are turned off. For example, during the bias phase, the first amplifier stage and the second amplifier stage do not consume current. Thus, embodiments of the present disclosure promote efficient power consumption in various applications. For example, in a pipeline ADC including a sampling phase and a multiplication phase, where the operational amplifier is used during the multiplication phase but not during the sampling phase. In such an example, the operational amplifier can be operated in the bias phase described herein during the sampling phase of the pipeline ADC.

[0082] Figure 4A A flowchart depicting the operation of an example operational amplifier during an amplification phase according to at least one example embodiment of the present disclosure is illustrated. Specifically, Figure 4A An example process 400 is depicted. In some embodiments, the example method 400 may be incorporated herein by reference. Figure 2 The example operational amplifier 200 is described to be implemented.

[0083] According to some examples, the method includes causing bias switches of the operational amplifier to be in an open state at operation 402. For example, the example method includes causing switches 262a, 262b, 264a, 264b coupled to the inverter of the second amplifier stage 20b to be in an open state, and causing switches 276a, 276b coupled to the first output and the second output of the first amplifier stage 20a to be in an open state. In this regard, by causing the bias switches of the PMOS and NMOS transistors coupled to the second amplifier stage 20b to be in an open state, the corresponding bias potentials are not applied to the gates of the PMOS and NMOS transistors of the second amplifier stage 20b. For example, in some embodiments, during the amplification phase, the gate terminals of the PMOS and NMOS transistors of the inverter of the second amplifier stage 20b are not coupled to their corresponding bias potentials. For example, the PMOS transistors 244a, 244b are not coupled to the bias voltage 282b, and the NMOS transistors 246a, 246b are not coupled to the bias voltage 282a. In this regard, by leaving the bias switches coupled to the first and second outputs of the first amplifier in an open state, the first and second outputs of the first amplifier stage are not coupled to the voltage 278, eg, are not switched to a fixed voltage.

[0084] According to some examples, the method includes placing amplification switches of the operational amplifier in a closed state at operation 404. For example, the example method includes placing switches 228a, 228b coupled to the inverters of the first amplifier stage 20a in a closed state, and placing switches 248a and 248b coupled to the second amplifier stage 20b in a closed state, so that the inverter pair of the first amplifier stage and the inverter pair of the second amplifier stage are connected to their respective supplies and grounds.

[0085] According to some examples, the method includes applying an operational amplifier at operation 406. In some embodiments, applying the operational amplifier includes causing the first inverter stage to generate an output voltage that is input to a second amplifier stage, and causing the second amplifier stage to generate output(s).

[0086] Figure 4B An example timing diagram corresponding to a bias phase and an amplification phase is provided according to at least one example embodiment of the present disclosure. Figure 4B As shown in , in some embodiments, the operation phases (eg, bias phase 420 and amplification phase 440) are non-overlapping.

[0087] Figure 5 An example operational amplifier 200 is shown in accordance with at least one embodiment of the present disclosure. Specifically, Figure 5 1 illustrates an example continuous-time implementation of an example operational amplifier circuit in accordance with at least one embodiment of the present disclosure. Operational amplifier 500 includes aspects, portions, etc. similar to example operational amplifier 500. Thus, similar to Figure 2 Similar and combined Figure 2 The part shown is Figure 5 The same reference numerals may be used to depict the same.

[0088] Figure 5 The example operational amplifier 500 shown in can be configured to have a continuous current flowing through the operational amplifier 500. In this regard, the operational amplifier 500 can be operated in a single phase. In some embodiments, Figure 5 The operational amplifier 500 shown in FIG. 1 includes a first amplifier stage 20 a corresponding to an input stage of the operational amplifier and a second amplifier stage 20 b corresponding to an output stage of the operational amplifier 500. The first amplifier stage 20 a and the second amplifier stage 20 b may include a gain stage of the operational amplifier 500. In some embodiments and as shown in FIG. Figure 5 As shown in FIG. 1 , each amplifier stage (eg, first amplifier stage 20 a and second amplifier stage 20 b ) includes an inverter.

[0089] In some embodiments, the first amplifier stage 20a representing the input stage of the example operational amplifier includes a first inverter 22a and a second inverter 22b. In some embodiments, the first inverter 22a includes a first PMOS transistor 224a and a first NMOS transistor 226a. In some embodiments, the second inverter 22b includes a second PMOS transistor 224b and a second NMOS transistor 226b. The first inverter 22a and the second inverter 22b can be configured to operate in a differential manner. For example, in some embodiments, the first inverter 22a and the second inverter 22b include differential inverters or are otherwise used as differential inverters. It should be appreciated that in some embodiments, the first inverter 22a and the second inverter 22b may include different inverter configurations. For example, in some embodiments, the first inverter 22a may include transistors of different types and / or transistors arranged in different configurations.

[0090] In some embodiments, the gate terminal of the first PMOS transistor 224a and the gate terminal of the first NMOS transistor 226a are each coupled to the first input 220a. In some embodiments, the gate terminal of the second PMOS transistor 224b and the gate terminal of the second NMOS transistor 226b are each coupled to the second input 220b. For example, in some embodiments, the gate terminals of each of the first PMOS transistor 224a and the first NMOS transistor 226a are coupled together, while the gate terminals of each of the second PMOS transistor 224b and the second NMOS transistor 226b are coupled together.

[0091] In some embodiments, the drain terminal of the first PMOS transistor 224a and the drain terminal of the first NMOS transistor 226a are coupled together and define a first output 232a of the first amplifier stage 20a. In some embodiments, the drain terminal of the second PMOS transistor 224b and the gate terminal of the second NMOS transistor 226b are coupled together and define a second output 232b of the first amplifier stage 20a. For example, in some embodiments, the first amplifier stage 20a is configured to output the first output 232a via the drain terminals of the first PMOS transistor 224a and the first NMOS transistor 226a, and to output the second output 232b via the drain terminals of the second PMOS transistor 224b and the second NMOS transistor 226b. In some embodiments, the first output 232a and the second output 232b of the first inverter stage are coupled to the second amplifier stage 20b. For example, in some embodiments, the first output 232a and the second output 232b are provided as inputs to the second amplifier stage 20b.

[0092] In some embodiments, the first output 232a and the second output 232b of the first amplifier stage 20a are coupled to the second amplifier stage 20b. As described herein, in some embodiments, the first output 232a and the second output 232b are provided as inputs to the second amplifier stage 20b. In some embodiments, the first output 232a is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the first output 232a is coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b) via a first RC circuit, wherein the first RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the first output 232a is coupled to a first resistor, wherein the resistor is coupled to the voltage 278.

[0093] In some embodiments, the second output 232 b is capacitively coupled to a portion of the second amplifier stage 20 b (e.g., coupled to one or more components of the second amplifier stage 20 b). Additionally or alternatively, in some embodiments, the second output 232 b is coupled to a portion of the second amplifier stage 20 b (e.g., coupled to one or more components of the second amplifier stage 20 b) via a second RC circuit, wherein the second RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the second output 232 b is coupled to a second resistor, wherein the resistor is coupled to the voltage 278.

[0094] In some embodiments, the source terminal of the first NMOS transistor 226a and the source terminal of the second NMOS transistor 226b are coupled to the first common-end transistor 222a configured to define a bias current. Figure 5 As shown in , in some embodiments, the gate terminal of the first common-tail transistor 222a is coupled to the bias voltage 230 (e.g., defining the gate potential of the first common-tail transistor 222a). For example, the first common-tail transistor 222a can be connected to the bias current circuit 201. In this regard, the first inverter 22a and the second inverter 22b can have an input current through the first and second inverters 22a, 22b biased with the first common-tail transistor 222a. Although the first common-tail transistor 222a is Figure 2 2 is depicted as an NMOS type transistor, but it should be appreciated that the first common-tail transistor 222a may be of a different type, such as a PMOS type.

[0095] As above combined Figure 2As described, by using a common-tail transistor 222a at the first amplifier stage (e.g., input stage) to define the bias current at the input stage of the operational amplifier 500 and using another common-tail transistor 222b at the input stage to apply common-mode feedback, the embodiments of the present disclosure mitigate the effects of any changes in the input common mode, thereby providing common-mode stability. For example, the absence of a common-tail transistor may result in a poor common-mode rejection ratio (CMRR).

[0096] In some embodiments, the source terminal of the first PMOS transistor 224a and the source terminal of the second PMOS transistor 224b are coupled to the second common-end transistor 222b. In some embodiments, the gate terminal of the second common-end transistor 222b is coupled to the common-mode feedback circuit 30 (which is depicted as a functional block for ease of illustration of the example operational amplifier 500). For example, the gate voltage of the second common-end transistor 222b can be controlled by the output of the common-mode feedback circuit 30. Although the second common-end transistor 222b is Figure 5 Although depicted as a PMOS type transistor, it should be appreciated that the second common-tail transistor 222 b may be an NMOS type.

[0097] In some embodiments, and as Figure 2 As shown in , the first amplifier stage 20a does not include a bias capacitor. In this regard, the first amplifier stage 20a will not be associated with a bias capacitor or otherwise generate KT / C noise caused by the bias capacitor. Thus, embodiments of the present disclosure provide an operational amplifier with low noise, which is at least in part due to the absence of a bias capacitor in the first amplifier stage (e.g., input stage).

[0098] As shown, in some embodiments, the PMOS and NMOS transistors of the first amplifier stage are configured to function as drivers. By using both PMOS and NMOS transistors as drivers, the transconductance (e.g., g m ) is effectively doubled. For example, when both the NMOS transistor and the PMOS transistor have the same transconductance, the transconductance of the operational amplifier 500 is effectively doubled, which in turn promotes lower noise, higher bandwidth, and lower current consumption.

[0099] In some embodiments, the second amplifier stage 20b corresponding to the output stage of the example operational amplifier 500 includes a third inverter 24a and a fourth inverter 24b. In some embodiments, the third inverter 24a includes a third PMOS transistor 244a and a third NMOS transistor 246a. In some embodiments, the fourth inverter 24b includes a fourth PMOS transistor 244b and a fourth NMOS transistor 246b. In some embodiments, the third inverter 24a and the fourth inverter 24b are configured to operate in a differential manner. For example, in some embodiments, the third inverter 24a and the fourth inverter 24b include differential inverters or are otherwise used as differential inverters. It should be appreciated that in some embodiments, the third inverter 24a and the fourth inverter 24b may include different inverter configurations. For example, in some embodiments, the third inverter 24a may include transistors of different types and / or transistors arranged in different configurations.

[0100] In some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are each coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are each coupled to the second output 232b of the first amplifier stage 20a. As further described herein, in some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a.

[0101] In some embodiments, the drain terminal of the third PMOS transistor 244a and the drain terminal of the third NMOS transistor 246a are coupled together and define a first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are coupled together and define a second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and to output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b.

[0102] In some embodiments, the source terminal of the fourth NMOS transistor 246b and the source terminal of the fourth NMOS transistor 246b are coupled to ground 290a. In some embodiments, the source terminal of the third PMOS transistor 244a and the source terminal of the fourth PMOS transistor 244b are coupled to a voltage supply 290b.

[0103] As described above, in some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a. In this regard, in some embodiments, the second amplifier stage 20b is capacitively biased. In some embodiments and as Figure 5 As depicted in , the second amplifier stage 20b includes a first capacitor circuit (which may also be referred to as a first RC circuit) coupled to the third inverter 24a. For example, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a via the first capacitor circuit, wherein a portion of the first capacitor circuit may be coupled to the gate terminal of the third PMOS transistor 244a, and a portion of the first capacitor circuit may be coupled to the gate terminal of the third NMOS transistor 246a. Additionally or alternatively, in some embodiments, the second amplifier stage 20b includes a second capacitor circuit (which may also be referred to as a second RC circuit) coupled to the fourth inverter 24b. For example, the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b via the second capacitor circuit, wherein a portion of the second capacitor circuit may be coupled to the gate terminal of the fourth PMOS transistor 244b, and a portion of the second capacitor circuit may be coupled to the gate terminal of the fourth NMOS transistor 246b.

[0104] In some embodiments, the first capacitor circuit includes a first capacitor 272a and a second capacitor 272b, each coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the second capacitor circuit includes a third capacitor 274a and a fourth capacitor 274b, each coupled to the second output 232b of the first amplifier stage 20a.

[0105] In some embodiments, the first capacitor circuit includes a first resistor 562a and a second resistor 562b, which are configured to facilitate biasing of the third PMOS transistor 244a and the third NMOS transistor 246a, respectively. The first end of the first resistor 562a can be coupled to the gate of the capacitor 272a and the third NMOS transistor 246a, and the second end of the first resistor 562a can be coupled to the bias voltage 282a. The first end of the second resistor 562b can be coupled to the gate of the capacitor 272b and the third PMOS transistor 244a, and the second end of the second resistor 562b can be coupled to the bias voltage 582b.

[0106] In some embodiments, the second capacitor circuit includes a third resistor 564a and a fourth resistor 564b, which are configured to facilitate biasing of the fourth MOS transistor 244b and the fourth NMOS transistor 246b, respectively. The first end of the third resistor 564a can be coupled to the gate of the capacitor 274a and the fourth NMOS transistor 246b, and the second end of the third resistor 564a can be coupled to the bias voltage 282a. The first end of the fourth resistor 564b can be coupled to the gate of the capacitor 274b and the fourth PMOS transistor 244b, and the second end of the fourth resistor 564b can be coupled to the bias voltage 582b. In some embodiments, the bias voltage 282a corresponds to or otherwise defines the gate potential of the third NMOS transistor 246a and the fourth NMOS transistor 246b. In some embodiments, the bias voltage 282b corresponds to or otherwise defines the gate potential of the third PMOS transistor 244a and the fourth PMOS transistor 244b.

[0107] In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the first capacitor circuit of the second amplifier stage 20b (e.g., at a node between the first capacitor 272a and the second capacitor 272b) and to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a. In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a first RC circuit including a resistor and a capacitor.

[0108] In some embodiments, the second output 232 b of the first amplifier stage is coupled to a second capacitor circuit of the second amplifier stage 20 b (e.g., at a node between the third capacitor 274 a and the fourth capacitor 274 b) and to drain terminals of the third PMOS transistor 244 a and the third NMOS transistor 246 a. In some embodiments, the second output 232 b of the first amplifier stage 20 a is coupled to drain terminals of the third PMOS transistor 244 a and the third NMOS transistor 246 a via a second RC circuit including a resistor and a capacitor.

[0109] In some embodiments, the drain terminal of the third PMOS transistor 244a and the drain terminal of the third NMOS transistor 246a are coupled together and define a first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are coupled together and define a second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and to output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b. In some embodiments, the first output 252a and the second output 252b of the second amplifier stage 20b are coupled to the common-mode feedback circuit 30. For example, in some embodiments, the first output 252a and the second output 252b are provided as inputs to the common-mode feedback circuit 30.

[0110] in conclusion

[0111] Those skilled in the art of the present disclosure who benefit from the teachings presented in the foregoing description and the related drawings will think of many modifications and other embodiments of the present disclosure set forth herein. Therefore, it should be understood that the embodiments are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing description and the related drawings describe example embodiments in the context of certain example combinations of elements and / or functions, it should be appreciated that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, combinations of elements and / or functions different from those explicitly described above may also be envisioned, as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used only in a general and descriptive sense, and not for purposes of limitation.

[0112] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any disclosure or the scope that can be claimed, but rather as descriptions of features that are peculiar to a particular disclosed specific embodiment. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Moreover, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0113] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the operations shown be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of the various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products.

[0114] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing can be advantageous.

[0115] In addition, although this detailed description has set forth some embodiments of the present disclosure, the appended claims may cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, in some embodiments, the first amplifier stage and / or the second amplifier stage may include transistors or different types. As another example, in some embodiments, the transistors of the first amplifier stage and / or the transistors of the second amplifier may be arranged in a different manner and / or coupled in other ways without departing from the scope of the present disclosure.

[0116] Additionally, within the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that 35 USC §112, paragraph (f) be invoked to interpret the claim.

Claims

1. An operational amplifier, comprising: An input stage, the input stage comprising: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor selectively coupled to the first inverter and the second inverter via a first switch, the first common-tail transistor being configured to define a bias current; and a second common-tail transistor selectively coupled to the first inverter and the second inverter via a second switch; and An output stage, the output stage comprising: a third inverter and a fourth inverter coupled together, the third inverter and the fourth inverter selectively coupled to a supply voltage via a third switch and selectively coupled to ground via a fourth switch; a first capacitive coupling configured to couple the third inverter to a first output of the input stage; and A second capacitive coupling is configured to couple the fourth inverter to a second output of the input stage.

2. The operational amplifier of claim 1, wherein: The first inverter includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and The second inverter includes a second PMOS transistor and a second NMOS transistor, which are coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

3. The operational amplifier of claim 2, wherein: The first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; as well as The first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

4. The operational amplifier of claim 1, wherein: The third inverter includes a third PMOS transistor and a third NMOS transistor, the third PMOS transistor and the third NMOS transistor being coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, which are coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

5. The operational amplifier of claim 4, wherein: The third PMOS transistor and the fourth PMOS transistor are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor; as well as The third NMOS transistor and the fourth NMOS transistor are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor.

6. The operational amplifier of claim 5, wherein: a gate terminal of the third PMOS transistor and a gate terminal of the third NMOS transistor coupled to a first output of the input stage via the first capacitive coupling; as well as A gate terminal of the fourth PMOS transistor and a gate terminal of the fourth NMOS transistor are coupled to a second output of the input stage via the second capacitive coupling.

7. The operational amplifier of claim 1, wherein: The first capacitive coupling includes a first switched capacitor circuit.

8. The operational amplifier of claim 1, wherein: The second capacitive coupling includes a second switched capacitor circuit.

9. The operational amplifier of claim 1, further comprising: A bias current circuit is coupled to the first common-tail transistor.

10. The operational amplifier of claim 1, further comprising: A common-mode feedback circuit is coupled to the second common-tail transistor.

11. The operational amplifier of claim 1, wherein: The operational amplifier is configured to operate in one or more of a biasing phase and an amplification phase.

12. The operational amplifier of claim 11, wherein: In the bias phase, each of the first switch, the second switch, the third switch, and the fourth switch is in an open state.

13. An operational amplifier, comprising: An input stage, the input stage comprising: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor coupled to the first inverter and the second inverter, the first common-tail transistor being configured to define a bias current; and a second common-tail transistor coupled to the first inverter and the second inverter; and An output stage, the output stage comprising: a third inverter and a fourth inverter coupled together; a first capacitive coupling configured to couple the third inverter to a first output of the input stage; and A second capacitive coupling is configured to couple the fourth inverter to a second output of the input stage.

14. The operational amplifier of claim 13, wherein: The first inverter includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and The second inverter includes a second PMOS transistor and a second NMOS transistor, which are coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

15. The operational amplifier of claim 14, wherein: The first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; as well as The first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

16. The operational amplifier of claim 13, wherein: The third inverter includes a third PMOS transistor and a third NMOS transistor, the third PMOS transistor and the third NMOS transistor being coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, which are coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

17. The operational amplifier of claim 16, wherein: The third PMOS transistor and the fourth PMOS transistor are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor; as well as The third NMOS transistor and the fourth NMOS transistor are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor.

18. The operational amplifier of claim 17, wherein: a gate terminal of the third PMOS transistor and a gate terminal of the third NMOS transistor coupled to a first output of the input stage via the first capacitive coupling; as well as A gate terminal of the fourth PMOS transistor and a gate terminal of the fourth NMOS transistor are coupled to a second output of the input stage via the second capacitive coupling.

19. The operational amplifier of claim 13, further comprising: A bias current circuit is coupled to the first common-tail transistor.

20. The operational amplifier of claim 13, further comprising: A common-mode feedback circuit is coupled to the second common-tail transistor.

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