Two-piece type amplitude-limiting low-noise amplifier circuit based on new topological fusion structure

Abstract

The invention discloses a two-piece amplitude-limiting low-noise amplifier circuit based on a new topological fusion structure. The two-piece amplitude-limiting low-noise amplifier circuit comprises an amplitude limiter chip circuit with the new topological fusion structure and a low-noise amplifier chip circuit with the new topological fusion structure, wherein the amplitude limiter chip circuit and the low-noise amplifier chip circuit are connected with each other; the amplitude limiter chip circuit comprises a first amplitude limiting circuit branch knot, an input matching network and a second amplitude limiting circuit branch knot which are sequentially connected from an input end to an output end, and the first amplitude limiting circuit branch knot and the second amplitude limiting circuit branch knot are used for limiting the amplitude of an input signal. The input matching network is used for realizing impedance matching between the whole circuit and the input end; the low-noise amplifier chip circuit comprises a low-noise amplifier circuit and an output matching network which are sequentially connected from the input end to the output end, the low-noise amplifier circuit is used for amplifying input signals, and the output matching network is used for achieving impedance matching of the whole circuit and the output end. According to the invention, the noise index performance of the two-piece amplitude-limiting low-noise amplifier circuit can be improved.

Description

Technical Field

[0001] The invention relates to a low noise amplifier technology, and in particular to a two-chip limiting low noise amplifier circuit based on a new topology fusion structure. Background Art

[0002] In the information age, the transmission and reception of signals are key steps in information transmission. As the first-stage active device of the RF receiving system, the low-noise amplifier will amplify the received signal for the first time. Its noise index performance affects the receiving sensitivity and channel capacity of the entire receiving system, so it is particularly critical.

[0003] Due to the increasingly complex electromagnetic environment, in order to protect high-precision electronic equipment such as low-noise amplifiers from being interfered by high-power microwaves, a limiter is usually added to the front stage of the low-noise amplifier, which allows small signals to pass through with lower insertion loss while large signals will be absorbed or reflected. Therefore, the two-chip limiting low-noise amplifier circuit is widely used in fields such as communications and radar. However, adding a limiter to the first stage of the system will undoubtedly directly affect the noise figure and insertion loss of the entire system. Therefore, it is of great research significance to study the design method of the two-chip limiting low-noise amplifier to reduce the impact of the limiter.

[0004] At present, the fusion design of limiters and LNAs is basically focused on integrated limiter LNAs, and there is little research on two-chip fusion design. Although integrated limiter LNAs are easier to implement fusion design, there are process restrictions, and the limiter's withstand power is difficult to reach the indicator level of independent limiter chips. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a two-chip limiting low noise amplifier circuit based on a new topology fusion structure, which can improve the noise index performance of the two-chip limiting low noise amplifier circuit.

[0006] Technical solution: A two-chip limiting low-noise amplifier circuit based on a new topological fusion structure of the present invention comprises a limiter chip circuit with a new topological fusion structure and a low-noise amplifier chip circuit with a new topological fusion structure connected to each other;

[0007] The limiter chip circuit comprises a first limiter circuit branch, an input matching network and a second limiter circuit branch connected in sequence from the input end to the output end, wherein the first limiter circuit branch and the second limiter circuit branch are used to limit the amplitude of the input signal, and the input matching network is used to achieve impedance matching between the overall circuit and the input end;

[0008] The low noise amplifier chip circuit includes a low noise amplifier circuit and an output matching network connected in sequence from the input end to the output end, wherein the low noise amplifier circuit is used to amplify the input signal, and the output matching network is used to achieve impedance matching between the overall circuit and the output end.

[0009] Furthermore, the insertion loss of the limiter chip circuit is reduced by optimizing the input matching network.

[0010] Furthermore, when the RF small signal is working, the diodes of the first limiting circuit branch and the second limiting circuit branch are not turned on, which is equivalent to a capacitor to ground, which forms a parallel resonant structure with the inductor to ground of the input matching network, thereby reducing the insertion loss of the limiting circuit branch.

[0011] Furthermore, the signal output end of the limiter chip circuit is connected to the signal input end of the low noise amplifier chip circuit, and a joint simulation optimization is performed according to actual indicator requirements to determine specific parameters.

[0012] Furthermore, the signal output end of the limiter chip circuit is connected to the signal input end of the noise amplifier chip circuit by gold wire bonding.

[0013] Furthermore, the input matching network comprises a first capacitor C1, a first inductor L1, a second capacitor C2, a first bias resistor R1, and a second bias resistor R2;

[0014] One end of the first capacitor C1 is connected to the first limiter circuit branch, and the other end thereof is connected to the second limiter circuit branch;

[0015] One end of the first inductor L is connected to the first capacitor C1, and the other end is connected to the second capacitor C2, the first bias resistor R1 and the second bias resistor R2, and the second capacitor C2 is grounded;

[0016] One end of the first bias resistor R1 is connected to the second bias resistor R2, and the other end is grounded; the second bias resistor R2 is connected to a power supply.

[0017] Furthermore, the first limiting circuit branch is designed to be a single diode or multiple diodes connected in series according to actual needs.

[0018] Furthermore, the second limiting circuit branch is designed to be a single diode or multiple diodes connected in series according to actual needs.

[0019] Furthermore, the low noise amplifier circuit is designed as a single-stage or multi-stage amplifier circuit according to actual needs.

[0020] Furthermore, the DC power supply terminals of the limiter chip circuit and the low noise amplifier chip circuit are connected via gold wire bonding.

[0021] Beneficial effects: Compared with the prior art, the significant technical effects of the present invention are as follows:

[0022] By transferring the input matching network of the low noise amplifier chip circuit to the limiter chip circuit, a parallel resonant structure is formed with the diode of the limiter circuit branch, which effectively reduces the insertion loss of the limiter.

[0023] By jointly optimizing the limiter chip circuit and the low noise amplifier chip circuit, the degradation of the noise index of the low noise amplifier caused by the limiter is effectively reduced, and the noise index performance of the traditional two-chip limiting low noise amplifier circuit design is improved.

[0024] The technical solution of the present invention is applicable to most two-chip limiting low noise amplifier chip designs, and is not limited by transistor types and the number of low noise amplifier stages. The structural topology design principle of the present invention is clear and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of the present invention;

[0026] Figure 2 It is a schematic diagram of a parallel resonant structure in which the diodes of the input matching network and the limiter circuit branches in the present invention are equivalent;

[0027] Figure 3 It is a schematic diagram of a two-chip limiting low noise amplifier circuit chip based on a traditional method in the prior art;

[0028] Figure 4 A comparison chart of circuit layout noise index simulation results of the present invention and the prior art;

[0029] Figure 5 A comparison diagram of the simulation results of the reflection coefficient at the input end of the circuit layout of the present invention and the prior art;

[0030] Figure 6 A comparison chart of the actual noise index measurement results of the circuit chip of the present invention and the prior art;

[0031] Figure 7 The figure is a comparison chart of the measured results of the reflection coefficient at the input end of the circuit chip of the present invention and the prior art. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is described in detail below in conjunction with specific implementation methods and the accompanying drawings of the specification.

[0033] like Figure 1As shown, the two-chip limiting low-noise amplifier circuit based on the new topological fusion structure of the present invention includes a limiter chip circuit with a new topological fusion structure and a low-noise amplifier chip circuit with a new topological fusion structure that are connected to each other. The limiter chip circuit includes a first limiting circuit branch, an input matching network, and a second limiting circuit branch that are sequentially connected from the input end to the output end, wherein the first limiting circuit branch and the second limiting circuit branch are used to limit the amplitude of the input signal, and the input matching network is responsible for achieving impedance matching between the overall circuit and the input end. The low-noise amplifier chip circuit includes a low-noise amplifier circuit and an output matching network that are sequentially connected from the input end to the output end, wherein the low-noise amplifier circuit is used to amplify the input signal, and the output matching network is responsible for achieving impedance matching between the overall circuit and the output end.

[0034] The signal output end of the limiter chip circuit is connected to the signal input end of the low noise amplifier chip circuit, and joint simulation optimization is performed according to actual indicator requirements to determine specific parameters.

[0035] In this embodiment, the signal output end of the limiter chip circuit is connected to the signal input end of the noise amplifier chip circuit through gold wire bonding.

[0036] In this embodiment, the DC power supply terminals of the limiter chip circuit and the low noise amplifier chip circuit are connected by gold wire bonding, and only one DC power supply is needed for power supply.

[0037] In this embodiment, the input matching network includes a first capacitor C1, a first inductor L1, a second capacitor C2, a first bias resistor R1, and a second bias resistor R2. One end of the first capacitor C1 is connected to the first limiter circuit branch, and the other end thereof is connected to the second limiter circuit branch; one end of the first inductor L is connected to the first capacitor C1, and the other end is connected to the second capacitor C2, the first bias resistor R1, and the second bias resistor R2, and the second capacitor C2 is grounded; one end of the first bias resistor R1 is connected to the second bias resistor R2, and the other end is grounded; the second bias resistor R2 is connected to the power supply.

[0038] The first limiter circuit branch is designed as a single or multiple diodes in series according to actual needs. The second limiter circuit branch is designed as a single or multiple diodes in series according to actual needs. The low noise amplifier circuit is designed as a single-stage or multi-stage amplifier circuit according to actual needs.

[0039] In one embodiment, the insertion loss of the limiter chip circuit is reduced by optimizing the input matching network. Specifically:

[0040] Place the limiter chip circuit and the low-noise amplifier chip circuit in the same schematic diagram, connect the signal output end of the former circuit with the signal circuit input end of the latter, perform joint simulation optimization according to actual indicator requirements, and determine specific parameters.

[0041] When the RF small signal is working, the diodes of the first limiting circuit branch and the second limiting circuit branch are not turned on, which are equivalent to capacitance to ground, which forms a parallel resonant structure with the inductance to ground of the input matching network, thereby reducing the insertion loss of the limiting circuit branch.

[0042] The design principle of the present invention is as follows: the input matching network in the low noise amplifier chip circuit is transferred to the limiter chip circuit to realize a new topological fusion structure. When the RF small signal is working, the diodes of the first limiter circuit branch and the second limiter circuit branch are not turned on, which can be equivalent to a capacitor to ground, and the capacitor and the inductor to ground of the input matching network can form a parallel resonant structure, such as Figure 2 As shown, the insertion loss of the limiting circuit branches is reduced. The input matching network also participates in the overall circuit noise matching in the limiter chip. The noise index performance obtained by the joint simulation optimization of the two-chip limiting low-noise amplifier circuit with a new topology fusion structure is better than that of the traditional two-chip circuit separately simulated and optimized.

[0043] like Figure 1 and Figure 3 As shown, the technical solution of the present invention transfers the input matching network in the traditional low-noise amplifier chip circuit to the limiter chip for integration. The limiter chip circuit is a limiter chip circuit with a new topological fusion structure, and has an input matching network that the traditional limiter does not have. The low-noise amplifier chip circuit is a low-noise amplifier chip circuit with a new topological fusion structure, which does not have the front-stage input matching network in the traditional design, and only includes a low-noise amplifier circuit and an output matching network. The present invention proposes a new topological structure for a two-piece limiting low-noise amplifier circuit. In this regard, the input matching network cannot be directly transferred to the low-noise amplifier chip circuit, which will cause network mismatch. If transfer is required, the network structure needs to be re-optimized in combination with the fusion design method. This solution places the limiter chip circuit and the low-noise amplifier chip circuit in the same schematic diagram, connects the signal output end of the former circuit with the input end of the latter signal circuit, and performs joint simulation optimization according to actual indicator requirements to determine specific parameters.

[0044] like Figure 4 As shown, it can be seen that the noise index of the new topology fusion design is reduced by 0.2dB compared with the traditional method.

[0045] like Figure 5 As shown, it can be seen that the reflection coefficient at the input end of the two-chip limiting low-noise amplifier circuit designed with the new topology fusion is significantly reduced compared with the traditional method. It can be inferred that the limiter chip based on the new topology fusion design has lower insertion loss.

[0046] like Figure 6 As shown, it can be seen that the measured noise index of the new topology fusion design is about 0.2dB lower than that of the traditional method, which is consistent with the simulation;

[0047] like Figure 7 As shown, it can be seen that the input end reflection coefficient measured by the new topology fusion design is significantly lower than that of the traditional method, which is consistent with the simulation;

[0048] The technical solution of the present invention effectively reduces the influence of the limiter on the noise figure of the low noise amplifier, and improves the noise figure performance of the traditional two-chip limiting low noise amplifier circuit design.

Claims

1. A two-chip limiting low noise amplifier circuit based on a new topology fusion structure, characterized in that: It includes a limiter chip circuit with a new topological fusion structure and a low-noise amplifier chip circuit with a new topological fusion structure that are interconnected; The limiter chip circuit comprises a first limiter circuit branch, an input matching network and a second limiter circuit branch connected in sequence from the input end to the output end, wherein the first limiter circuit branch and the second limiter circuit branch are used to limit the amplitude of the input signal, and the input matching network is used to achieve impedance matching between the overall circuit and the input end; The low noise amplifier chip circuit includes a low noise amplifier circuit and an output matching network connected in sequence from the input end to the output end, wherein the low noise amplifier circuit is used to amplify the input signal, and the output matching network is used to achieve impedance matching between the overall circuit and the output end.

2. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The insertion loss of the limiter chip circuit is reduced by optimizing the input matching network.

3. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 2, characterized in that: When the RF small signal is working, the diodes of the first limiting circuit branch and the second limiting circuit branch are not turned on, which are equivalent to capacitance to ground, and form a parallel resonant structure with the inductance to ground of the input matching network.

4. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The signal output end of the limiter chip circuit is connected to the signal input end of the low noise amplifier chip circuit, and joint simulation optimization is performed according to actual indicator requirements to determine specific parameters.

5. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 4, characterized in that: The signal output end of the limiter chip circuit is connected to the signal input end of the noise amplifier chip circuit through gold wire bonding.

6. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The input matching network comprises a first capacitor C1, a first inductor L1, a second capacitor C2, a first bias resistor R1, and a second bias resistor R2; One end of the first capacitor C1 is connected to the first limiter circuit branch, and the other end thereof is connected to the second limiter circuit branch; One end of the first inductor L is connected to the first capacitor C1, and the other end is connected to the second capacitor C2, the first bias resistor R1 and the second bias resistor R2, and the second capacitor C2 is grounded; One end of the first bias resistor R1 is connected to the second bias resistor R2, and the other end is grounded; the second bias resistor R2 is connected to a power supply.

7. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The first limiting circuit branch is designed to be a single diode or multiple diodes connected in series according to actual needs.

8. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The second limiting circuit branch is designed to be a single diode or multiple diodes connected in series according to actual needs.

9. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The low noise amplifier circuit is designed as a single-stage or multi-stage amplifier circuit according to actual needs.

10. The two-chip limiting low noise amplifier circuit based on the new topology fusion structure according to claim 1, characterized in that: The DC power supply terminals of the limiter chip circuit and the low noise amplifier chip circuit are connected via gold wire bonding.

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