An input buffer whose quiescent operating point is not affected by external factors

Abstract

The present invention belongs to the field of integrated circuits, and provides an input buffer whose static operating point is not affected by external factors, comprising: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier; the output terminals of the first operational amplifier and the second operational amplifier are respectively connected to the positive input terminal and the negative input terminal of the second operational amplifier; the positive input terminals of the first operational amplifier and the second operational amplifier are clamped at a preset voltage value. The present invention clamps the input voltage difference of the third operational amplifier at a preset voltage value through the connection mode of the first operational amplifier, the second operational amplifier, and the third operational amplifier, thereby realizing isolation from external input influences and ensuring the stability of the static operating point.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to an input buffer whose static operating point is not affected by external factors. Background Art

[0002] At present, the differential interface methods mainly include LVDS standard, LVPEC standard and CML standard, and these standards mainly have AC coupling mode and DC coupling mode in application. Figure 1 As shown, in the AC coupling mode, the DC is isolated between the signal input and the interface input by capacitive coupling, so the static operating point between the signal input and the interface input is not affected and can work stably.

[0003] However, in DC coupling mode, since the signal and interface input are directly linked, the static operating point, that is, the DC operating point, affects each other. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide an input buffer whose static operating point is not affected by external factors. By connecting the first operational amplifier, the second operational amplifier and the third operational amplifier, the input voltage difference of the third operational amplifier is clamped to a preset voltage value, thereby achieving isolation from external input influences and ensuring the stability of the static operating point.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] An input buffer whose static operating point is not affected by external factors comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier and a third operational amplifier;

[0007] The positive phase input terminal of the first operational amplifier, the positive phase input terminal of the second operational amplifier and the external preset VCM terminal are connected to each other; the second end of the first resistor, the first end of the second resistor and the first end of the first capacitor are connected to each other; the second end of the fifth resistor, the first end of the sixth resistor and the first end of the second capacitor are connected to each other; the second end of the second resistor, the second end of the first capacitor, the first end of the third resistor, the output terminal of the first operational amplifier and the positive phase input terminal of the third operational amplifier are connected to each other at point B; the second end of the sixth resistor, the second end of the second capacitor, the first end of the fourth resistor, the output terminal of the second operational amplifier and the inverting input terminal of the third operational amplifier are connected to each other at point C; the second end of the third resistor, the second end of the fourth resistor, the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are connected to each other at point A; the first end of the first resistor is connected to the positive phase terminal of the input signal; the first end of the fifth resistor is connected to the inverting terminal of the input signal;

[0008] The VCM terminal is used to clamp the non-inverting input terminals of the first operational amplifier and the second operational amplifier to a preset voltage value.

[0009] Preferably, the structures of the first operational amplifier and the second operational amplifier are both cascade folded operational amplifier structures.

[0010] Preferably, the preset voltage value of the VCM terminal is 0.65V.

[0011] Preferably, the resistance values ​​of the first resistor and the fifth resistor are both 106Ω; the resistance values ​​of the second resistor and the sixth resistor are both 10kΩ; and the resistance values ​​of the third resistor and the fourth resistor are both 130kΩ.

[0012] Preferably, the charge capacity of the first capacitor and the second capacitor are both 1.9 pF.

[0013] The present invention discloses the following technical effects:

[0014] The present invention provides an input buffer whose static operating point is not affected by external factors. The voltage difference at the input end of the third operational amplifier is clamped at a preset voltage value by connecting the first operational amplifier, the second operational amplifier and the third operational amplifier, thereby solving the defect that the traditional DC coupling mode circuit is affected by external input interference, and achieving isolation from external input influences and stable maintenance of the static operating point. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 A diagram of existing circuit types provided for embodiments of the present invention;

[0017] Figure 2 An improved input buffer circuit diagram provided by an embodiment of the present invention;

[0018] Figure 3 A detailed circuit design diagram provided for an embodiment of the present invention, Figure 3 (a) is the circuit design diagram of the first op amp and the second op amp. Figure 3 (b) is the circuit design diagram of the third operational amplifier;

[0019] Description of reference numerals:

[0020] R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, R6-sixth resistor, R7-seventh resistor, R8-eighth resistor, R9-ninth resistor, R10-tenth resistor, C1-first capacitor, C2-second capacitor, A1-first op amp, A2-second op amp, A3-third op amp, N1-first nmos tube, N2-second nmos tube, N3-third nmos tube, N4-fourth nmos tube, N5-fifth nmos tube, N6-sixth nmos tube, N7-seventh nmos tube, N8-eighth nmos tube, N9-ninth nmos tube, N10-tenth nmos tube, N11-eleventh nmos tube, N12-twelfth nmos tube, N13-thirteenth nmos tube s tube, N14-the fourteenth nmos tube, N15-the fifteenth nmos tube, N16-the sixteenth nmos tube, N17-the seventeenth nmos tube, N18-the eighteenth nmos tube, N19-the nineteenth nmos tube, N20-the twentieth nmos tube, N21-the twenty-first nmos tube, N22-the twenty-second nmos tube, P1-the first pmos tube, P2-the second pmos tube, P3-the third pmos tube, P4-the fourth pmos tube, P5-the fifth pmos tube, P6-the sixth pmos tube, P7-the seventh pmos tube, P8-the eighth pmos tube, P9-the ninth pmos tube, P10-the tenth pmos tube, P11-the eleventh pmos tube, P12-the twelfth pmos tube, inv3-inverter. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The purpose of the present invention is to provide an input buffer whose static operating point is not affected by external factors. By connecting the first operational amplifier, the second operational amplifier and the third operational amplifier, the voltage difference at the input end of the third operational amplifier is clamped at a preset voltage value, thereby isolating the external input influence and ensuring the stability of the static operating point.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Figure 2 The improved input buffer circuit diagram provided by the embodiment of the present invention is as follows: Figure 2As shown, the present invention provides an input buffer whose static operating point is not affected by external factors, including: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a first operational amplifier A1, a second operational amplifier A2 and a third operational amplifier A3;

[0025] The positive phase input terminal of the first operational amplifier A1, the positive phase input terminal of the second operational amplifier A2, and the external preset VCM terminal are connected to each other; the second end of the first resistor R1, the first end of the second resistor R2, and the first end of the first capacitor C1 are connected to each other; the second end of the fifth resistor R5, the first end of the sixth resistor R6, and the first end of the second capacitor C2 are connected to each other; the second end of the second resistor R2, the second end of the first capacitor C1, the first end of the third resistor R3, the output terminal of the first operational amplifier A1, and the positive phase input terminal of the third operational amplifier A3 are connected to each other at B Point; the second end of the sixth resistor R6, the second end of the second capacitor C2, the first end of the fourth resistor R4, the output end of the second operational amplifier A2 and the inverting input end of the third operational amplifier A3 are connected to each other at point C; the second end of the third resistor R3, the second end of the fourth resistor R4, the inverting input end of the first operational amplifier A1 and the inverting input end of the second operational amplifier A2 are connected to each other at point A; the first end of the first resistor R1 is connected to the positive phase end of the input signal (in+); the first end of the fifth resistor R5 is connected to the inverting end of the input signal (in-);

[0026] The VCM terminal is used to clamp the non-inverting input terminals of the first operational amplifier A1 and the second operational amplifier A2 at a preset voltage value.

[0027] Specifically, the structures of the first operational amplifier A1 and the second operational amplifier A2 are both cascade operational amplifier structures.

[0028] Preferably, the preset voltage value of the VCM terminal is 0.65V.

[0029] Optionally, the resistance values ​​of the first resistor R1 and the fifth resistor R2 are both 106Ω; the resistance values ​​of the second resistor R2 and the sixth resistor R6 are both 10kΩ; and the resistance values ​​of the third resistor R3 and the fourth resistor R4 are both 130kΩ.

[0030] Specifically, the charge capacity of the first capacitor C1 and the second capacitor C2 are both 1.9 pF.

[0031] Preferably, the common mode at point B is controlled by the output of the first op amp, and VCM locks the common mode voltage value at point B through the first op amp A1 and the third resistor R3. The common mode at point C is controlled by the output of the second op amp A2, and VCM locks the common mode voltage value at point C through the second op amp A2 and the fourth resistor R4. Points B and C are the input terminals of the third op amp A3, and the common mode value of the input terminal of the third op amp A3 is locked by VCM. The in+ common mode value is isolated from the common mode value at point B through the first resistor R1 and the second resistor R2, and the in+ common mode value does not affect point B. The in- common mode value is isolated from the common mode value at point C through the fifth resistor R5 and the sixth resistor R6, and the in- common mode value does not affect point C. Therefore, the in+ differential mode signal is applied to the third op amp input terminal point B through the first resistor R1 and the second resistor R2, and the in- differential mode signal is applied to the third op amp A3 input terminal point C through the fifth resistor R5 and the sixth resistor R6. The third op amp A3 amplifies the differential mode signals at points B and C to the output (Y) of the third op amp A3, while the in+ / in- common mode signal cannot affect the third op amp A3 input terminals points B and C.

[0032] Specifically, the common mode point of input point B / C is controlled by introducing op amp A1 / A2 in the loop. Since B / C node is directly controlled by op amp A1 / A2 output, it is not controlled by the common mode DC point of input node in+ / in-. It can input common mode point independently. The potential of B / C node is VCM=0.65V, which ensures the stability of common mode potential of A3 input terminal. In normal operation, in+ / in- input differential signal, according to the input of different standard differential signals such as LVDS / LVPEC / CML, these differential signal common mode levels will be different, but because op amp A1 / A2 and R3 / R4 form common mode feedback, node B / C will be controlled at VCM common mode level. The differential input common mode level and the common mode level VCM of B / C point are isolated by isolation resistor R1R2 / R5R6, and capacitor C1 / C2 is responsible for providing a faster path for differential signal. The B / C nodes are also the inputs of buffer A3. Since the common-mode voltage of the B / C nodes is stable at VCM, the input of buffer A3 only needs to amplify the differential-mode signal. The specific function of A3 is to amplify the differential-mode input signal into a single-ended output CMOS level signal.

[0033] Furthermore, the dual-ended output op amp is used to implement the function of the A1 / A2 op amp. Here, the cascade folded op amp structure is used to implement it, which can obtain considerable gain and low power consumption area to achieve the required bias. In this example, the role of the two op amps A1 / A2 is realized by using a pair of differential inputs and a pair of differential outputs, without the need to use two op amps for implementation. The B / C node is the drain output of the differential op amp A1 / A2, which directly controls the differential input of the op amp A3, so that the differential input of A3 will no longer be affected by the DC operating point of the input signal in+ / in-, ensuring that the DC operating point of the input of A3 is stable and reliable. The common-mode signal of the input common node B / C of A3 is only controlled by its own VCM=0.65, and has nothing to do with the external signal in+ / in-.

[0034] refer to Figure 3 (a) and Figure 3(b), IB is the input current to provide current bias for the entire invention, the positive end of the ninth resistor R9 is connected to the common node VBN1, the negative end of the ninth resistor R9 is connected to the common node VBN2, the drain of the first nmos tube N1 is connected to the negative end of the ninth resistor R9 to form a common node VBN2, the gate of the first nmos tube N1 is connected to the positive end of the ninth resistor R9 to form a common node VBN1, and the source of the first nmos tube N1 is connected to the drain of the second nmos tube N2 to form a common node e. The gate end of the second nmos tube N2 is connected to the negative end of the ninth resistor R9 to form a common node VBN2, and the source end of the second nmos tube N2 is connected to GND. The drain of the third nmos tube N3 is connected to the negative end of the tenth resistor R10 to form a common node VBP2, the gate of the third nmos tube N3 is connected to the positive end of the ninth resistor R9 to form a common node VBN1, and the source end of the third nmos tube N3 is connected to the drain end of the fourth nmos tube N4 to form a common node f. The gate of the fourth nmos tube N4 is connected to the negative end of the ninth resistor R9 to form a common node VBN2, and the source end of the nmos tube is connected to GND. The drain of the second pmos tube P2 is connected to the positive end of the tenth resistor R10 to form a common node VBP1, the gate of the second pmos tube P2 is connected to the negative end of the tenth resistor R10 to form a common node VBP2, and the source of the second pmos tube P2 is connected to the drain of the first pmos tube P1 to form a common node h. The gate of the first pmos tube P1 is connected to the positive end of the tenth resistor R10 to form a common node VBP1, and the source of the first pmos tube P1 is connected to VDD. The drain of the sixth nmos tube N6 is connected to the source of the fifth nmos tube N5 to form a common node g, the gate of the sixth nmos tube N6 is connected to the negative end of the ninth resistor R9 to form a common node VBN2, and the source of the sixth nmos tube N6 is connected to GND. The drain of the fifth nmos tube N5 is connected to the source of the seventh nmos tube N7 to form a common node d, and the gate of the fifth nmos tube N5 is connected to the positive end of the ninth resistor R9 to form a common node VBN1. The drain of the seventh nmos tube N7 is connected to the drain of the third pmos tube P3 to form a common node i, and the gate of the seventh nmos tube N7 is connected to the negative end of R3 to form a common node A. The drain of the eighth nmos tube N8 is connected to the drain of the fifth pmos tube P5 to form a common node p, the gate of the eighth nmos tube N8 is connected to VCM, and the source of the eighth nmos tube N8 is connected to the drain of the fifth nmos tube N5 to form a common node d. The source of the third pmos tube P3 is connected to VDD, and the gate of the third pmos tube P3 is connected to the positive end of the tenth resistor R10. The source of the fifth pmos tube P5 is connected to VDD, and the gate of the fifth pmos tube P5 is connected to the positive end of the tenth resistor R10. The source of the fourth pmos tube P4 is connected to the drain of the seventh nmos tube N7 to form a common node i, the gate of the fourth pmos tube P4 is connected to the negative end of the tenth resistor R10 to form a common node VBP2, and the drain of the fourth pmos tube P4 is connected to the drain of the ninth nmos tube N9 to form a common node j.The source of the sixth pmos tube P6 is connected to the drain of the eighth nmos tube N8 to form a common node p, the gate of the sixth pmos tube P6 is connected to the negative end of the tenth resistor R10 to form a common node VBP2, and the drain of the sixth pmos tube P6 is connected to the drain of the tenth nmos tube N10 to form a common node k. The gate of the ninth nmos tube N9 is connected to the drain of the fourth pmos tube P4 to form a common node j, and the source of the ninth nmos tube N9 is connected to GND. The gate of the tenth nmos tube N10 is connected to the drain of the fourth pmos tube P4 to form a common node j, and the source of the tenth nmos tube N10 is connected to GND. The source of the seventh pmos tube P7 is connected to VDD, the gate of the seventh pmos tube P7 is connected to the positive end of the tenth resistor R10 to form a common node VBP1, and the drain of the seventh pmos tube P7 is connected to the source of the eighth pmos tube P8 to form a common node q. The gate of the eighth pmos tube P8 is connected to the negative end of the tenth resistor R10 to form a common node VBP2, and the drain of the eighth pmos tube P8 is connected to the drain of the eleventh nmos tube N11 to form a common node B. The gate of the eleventh nmos transistor N11 is connected to the positive end of the ninth resistor R9 to form a common node VBN1, the source of the eleventh nmos transistor N11 is connected to the drain of the twelfth nmos transistor N12 to form a common node m. The gate of the twelfth nmos transistor N12 is connected to the drain of the tenth nmos transistor N10 to form a common node k, and the source of the twelfth nmos transistor N12 is connected to GND.

[0035] Specifically, the source of the ninth pmos tube P9 is connected to VDD, the gate of the ninth pmos tube P9 is connected to the positive end of the tenth resistor R10 to form a common node VBP1, and the drain of the ninth pmos tube P9 is connected to the source of the tenth pmos tube P10 to form a common node r. The gate of the tenth pmos tube P10 is connected to the negative end of the tenth resistor R10 to form a common node VBP2, and the drain of the tenth pmos tube P10 is connected to the drain of the thirteenth nmos tube N13 to form a common node C. The gate of the thirteenth nmos tube N13 is connected to the positive end of the ninth resistor R9 to form a common node VBN1, and the source of the thirteenth nmos tube N13 is connected to the drain of the fourteenth nmos tube N14 to form a common node n. The gate of the fourteenth nmos tube N14 is connected to the drain of the tenth nmos tube N10 to form a common node k, and the source of the fourteenth nmos tube N14 is connected to GND.

[0036] Further, the negative end of R6 is connected to the drain end of N13 to form a common node C, the positive end of R6 is connected to the negative end of R5 to form a common node in1-, the positive end of R5 is connected to in-, the positive end of C2 is connected to the positive end of R6 to form a common node in1-, and the negative end of C2 is connected to the drain end of N13 to form a common node C.

[0037] Preferably, R2 is connected to the drain end of N11 to form a common node B, R2 negative end is connected to R1 positive end to form a common node in2+, R1 negative end is connected to in+, C1 negative end is connected to R1 positive end to form a common node in2+, and C1 positive end is connected to N11 drain end to form a common node B.

[0038] Preferably, the positive end of R3 is connected to the drain of the eleventh nmos tube N11 to form a common node B, and the positive end of R4 is connected to the drain of the thirteenth nmos tube N13 to form a common node C.

[0039] Specifically, the drain end of the seventeenth nmos tube N17 is connected to the negative end of the seventh resistor R7 to form a common node v, the positive end of the seventh resistor R7 is connected to VDD, the gate end of the seventeenth nmos tube N17 is connected to the drain end of the thirteenth nmos tube N13 to form a common node C, and the source end of the seventeenth nmos tube N17 is connected to the drain end of the fifteenth nmos tube N15 to form a common node s.

[0040] Furthermore, the drain end of the eighth nmos tube N18 is connected to the negative end of the eighth resistor R8 to form a common node w, the positive end of the eighth resistor R8 is connected to VDD, the gate end of the eighth nmos tube N18 is connected to the drain of the eleventh nmos tube N11 to form a common node B, and the source end of the eighth nmos tube N18 is connected to the drain end of the fifteenth nmos tube N15 to form a common node s.

[0041] Specifically, the gate of the fifteenth nmos tube N15 is connected to the positive end of the ninth resistor R9 to form a common node VBN1, and the source end of the fifteenth nmos tube N15 is connected to the drain end of the sixteenth nmos tube N16 to form a common node t. The gate of the sixteenth nmos tube N16 is connected to the negative end of the ninth resistor R9 to form a common node VBN2, and the source end of the sixteenth nmos tube N16 is connected to GND.

[0042] Further, the drain of the twenty-first nmos tube N21 is connected to the drain of the eleventh nmos tube P11 to form a common node x, the source of the twenty-first nmos tube N21 is connected to the drain of the nineteenth nmos tube N19 to form a common node L, and the gate of the twenty-first nmos tube N21 is connected to the drain of the eighth nmos tube N18 to form a common node w.

[0043] Preferably, the source of the eleventh pmos transistor P11 is connected to VDD, and the gate of the eleventh pmos transistor P11 is connected to the drain of the twenty-first nmos transistor N21 to form a common node x.

[0044] Specifically, the drain of the twenty-second nmos tube N22 is connected to the drain of the first nmos tube P12 to form a common node z, the source of the twenty-second nmos tube N22 is connected to the drain of the nineteenth nmos tube N19 to form a common node L, and the gate of the twenty-second nmos tube N22 is connected to the drain of the seventeenth nmos tube N17 to form a common node v.

[0045] Further, the source of the first pmos transistor P12 is connected to VDD, and the gate of the first pmos transistor P12 is connected to the drain of the twenty-first nmos transistor N21 to form a common node x.

[0046] Specifically, the gate of the nineteenth nmos tube N19 is connected to the positive end of the ninth resistor R9 to form a common node VBN1, and the source end of the nineteenth nmos tube N19 is connected to the drain end of the twentieth nmos tube N20 to form a common node u. The gate of the twentieth nmos tube N20 is connected to the negative end of the ninth resistor R9 to form a common node VBN2, and the source end of the twentieth nmos tube N20 is connected to GND.

[0047] Preferably, the input end of the inverter inv3 is connected to the drain end of the twenty-second nmos tube N22, and the output end of the inverter inv3 is connected to Y.

[0048] The beneficial effects of the present invention are as follows:

[0049] The present invention clamps the input voltage difference of the third operational amplifier to a preset voltage value through the connection mode of the first operational amplifier, the second operational amplifier and the third operational amplifier, thereby realizing isolation from the influence of external input and ensuring the stability of the static operating point.

[0050] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0051] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An input buffer whose static operating point is not affected by external factors, characterized in that: include: A first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier; The positive phase input terminal of the first operational amplifier, the positive phase input terminal of the second operational amplifier and the external preset VCM terminal are connected to each other; the second end of the first resistor, the first end of the second resistor and the first end of the first capacitor are connected to each other; the second end of the fifth resistor, the first end of the sixth resistor and the first end of the second capacitor are connected to each other; the second end of the second resistor, the second end of the first capacitor, the first end of the third resistor, the output terminal of the first operational amplifier and the positive phase input terminal of the third operational amplifier are connected to each other at point B; the second end of the sixth resistor, the second end of the second capacitor, the first end of the fourth resistor, the output terminal of the second operational amplifier and the inverting input terminal of the third operational amplifier are connected to each other at point C; the second end of the third resistor, the second end of the fourth resistor, the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are connected to each other at point A; the first end of the first resistor is connected to the positive phase terminal of the input signal; the first end of the fifth resistor is connected to the inverting terminal of the input signal; The VCM terminal is used to clamp the non-inverting input terminals of the first operational amplifier and the second operational amplifier to a preset voltage value.

2. The input buffer with a static operating point not affected by external factors according to claim 1, characterized in that: The structures of the first operational amplifier and the second operational amplifier are both cascade folded operational amplifier structures.

3. The input buffer with a static operating point not affected by external factors according to claim 1, characterized in that: The preset voltage value of the VCM terminal is 0.65V.

4. The input buffer with a static operating point not affected by external factors according to claim 1, characterized in that: The resistance values ​​of the first resistor and the fifth resistor are both 106Ω; the resistance values ​​of the second resistor and the sixth resistor are both 10kΩ; and the resistance values ​​of the third resistor and the fourth resistor are both 130kΩ.

5. The input buffer with a static operating point not affected by external factors according to claim 1, characterized in that: The charge capacity of the first capacitor and the second capacitor are both 1.9 pF.

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