Receiver and method with fast sampling phase and frequency acquisition

Abstract

The invention relates to a receiver and a method with fast sampling phase and frequency acquisition. Fast sampling phase and frequency acquisition is suitable for incorporating various high bandwidth receivers and receiving methods. An illustrative integrated circuit receiver or "deserializer" design has: a clock circuit that provides a sampling clock; an analog-to-digital converter sampling the received signal according to a sampling clock to provide a received signal sample; and a clock recovery circuit. The clock recovery circuit comprises a phase and frequency acquisition module used for determining and correcting an initial frequency offset and an initial phase offset of a sampling clock; and a feedback circuit for minimizing a timing error of the sampling clock after the initial frequency offset and the initial phase offset have been corrected.

Description

Background Art

[0001] Most integrated circuit devices have become so complex that it is impractical for electronic device designers to design integrated circuit devices from scratch. Instead, electronic device designers rely on predefined modular units of integrated circuit layout design, arranging and joining them as needed to achieve the various functions of the desired device. Each modular unit has a defined interface and behavior that has been verified by its creator. Although it may take a lot of time and investment to create each modular unit, the availability of modular units for reuse and further development greatly reduces product cycle time and achieves better products. Predefined units can be organized hierarchically, where a given unit contains one or more lower-level units and is in turn contained in a higher-level unit. Many organizations have such predefined modular unit libraries for sale or licensing, including, for example, embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, etc. Predefined modular units are also called cells, blocks, cores, and macros, which have different meanings and variations ("intellectual property (IP) cores", "soft macros"), but are often used interchangeably.

[0002] Modular cells can be expressed in different ways, for example, in the form of a hardware description language (HDL) file, or as a fully routed design that can be directly printed to create a range of manufacturing process masks. Fully routed design files are often process specific, which means that additional design work is usually required to migrate the modular cells to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to implement, but they are process independent, which means that different manufacturers can apply their preferred automatic synthesis, placement, and routing processes to implement the cells using a wide range of manufacturing processes. Due to their higher-level representation, HDL cells can be more amenable to modification and the use of variable design parameters, while fully routed cells can provide better predictability in terms of area requirements, reliability, and performance. Although there are no fixed rules, digital module designs are more commonly specified in HDL form, while analog and mixed-signal cells are more commonly specified as lower-level physical descriptions.

[0003] A serializer-deserializer (SerDes) core is often required for device designs that employ modern data communication standards, which continue to evolve toward higher symbol rates and greater number of bits per channel symbol due to the ongoing demand for lower latency and higher transmission rates. Channel symbols are attenuated and dispersed as they propagate, resulting in inter-symbol interference (ISI) at the receiving end of the channel. For a given channel bandwidth, this ISI worsens at higher symbol rates and larger symbol constellations. When attempting to detect channel symbols, the receiver must cope with this ISI in addition to the channel noise that contaminates the received signal. The public literature discloses many equalization and demodulation techniques for recovering digital data from a degraded received signal even in the presence of ISI.

[0004] One technique used to evaluate channels and equalization techniques is an "eye diagram," which represents all possible paths that a signal may follow within a given symbol interval, typically via the superposition of many symbol intervals. Typically, the optimal sampling instant is near the midpoint of the symbol interval, in the hope that a gap can be found between signal paths representing different symbol values. When such a gap exists, a comparator can be used to detect the transmitted symbol by comparing the equalized signal value to a decision threshold at the center of the gap. The reliability of such a decision depends on the amount of noise relative to the distance between the decision threshold and the edge of the gap. When sampling occurs at the optimal point in each symbol interval, the error rate is minimized. Likewise, the public literature discloses a number of timing recovery techniques that can be used in conjunction with various equalization and modulation techniques to determine the sampling frequency and optimal sampling phase.

[0005] A popular timing recovery technique is a clock data recovery (CDR) loop that operates on digitized samples of the received signal, the equalized signal, and / or the symbol decisions to measure the timing error and is combined with a feedback loop to minimize the timing error. Examples of timing error estimators include, for example, bang-bang or proportional phase detectors. A suitable timing error estimator is proposed in co-owned U.S. Patent 10,447,509, "Precompensator-based quantization for clock recovery." Other suitable timing error estimators can be found in the open literature, including, for example, Mueller, "Timing Recovery in Digital Synchronous Data Receivers," IEEE Journal of Communications, Vol. 24, No. 5, May 1976, and Musa, "High-speed Baud-Rate Clock Recovery," University of Toronto thesis, 2008.

[0006] While the CDR loop approach has many advantages, including accuracy and ease of implementation, inherent loop delays (from a variety of sources, including analog-to-digital conversion, timing error estimation, and filtering) require limited loop bandwidth to ensure loop stability. In recent 56Gbd SerDes module designs, the CDR loop bandwidth is limited to approximately 10MHz, which means that the CDR loop typically requires hundreds of nanoseconds from startup to reach steady-state tracking. (At 56Gbd, this translates to more than 10,000 symbols.) In some contexts, any link connection delay of more than a few nanoseconds is unacceptable. Summary of the invention

[0007] Thus, various receivers and reception methods incorporating fast sampling phase and frequency acquisition are disclosed herein. An illustrative integrated circuit receiver or "deserializer" design has: a clock circuit that provides a sampling clock; an analog-to-digital converter that samples a received signal according to the sampling clock to provide received signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module for determining and correcting an initial frequency offset and an initial phase offset of the sampling clock; and a feedback circuit for minimizing the timing error of the sampling clock after the initial frequency offset and the initial phase offset have been corrected.

[0008] An illustrative method includes sampling a received signal in response to a sampling clock to provide received signal samples, the sampling clock having an initial frequency; obtaining a sampling clock phase estimate from each of a plurality of received signal sample pairs; differentiating the sampling clock phase estimates to determine an initial frequency offset; and correcting a source of the sampling clock to compensate for the initial frequency offset.

[0009] The above-mentioned receiver and method can be further embodied as a semiconductor IP core residing on a non-transitory information storage medium, which uses, for example, a hardware description language to represent a schematic diagram, or uses, for example, GDSII or OASIS language to represent a semiconductor manufacturing process mask pattern.

[0010] Each of the foregoing embodiments may be implemented individually or in combination, and may be implemented with any one or more of the following features in any suitable combination: 1. The analog-to-digital converter is one of a set of analog-to-digital converters that samples a received signal in response to an interleaved version of a sampling clock to provide a set of parallel received signal samples. 2. The integrated circuit includes an equalizer that converts the received signal samples into equalized signal samples. 3. The phase and frequency acquisition module uses the received signal samples or the equalized signal samples to derive an initial frequency offset and an initial phase offset. 4. The phase and frequency acquisition module uses a ratio of a pair of equalized signal samples during a preamble period to estimate the sampling clock phase. 5. The sampling clock phase estimates are each calculated as the arc tangent of one of the ratios. 6. The phase and frequency acquisition module estimates the frequency offset based on one or more differences between the sampling clock phase estimates. 7. The clock recovery circuit includes a phase-locked loop having an initial frequency division ratio, and the phase and frequency acquisition module is configured to correct the initial frequency offset by adjusting the initial frequency division ratio. 8. The clock recovery circuit includes a phase interpolator having an initial phase setting, and the phase and frequency acquisition module is configured to correct the initial phase offset by adjusting the initial phase setting. 9. The method includes: combining at least some of the sampling clock phase estimates to obtain the initial phase offset; and correcting the source of the sampling clock to compensate for the initial phase offset. 10. The method includes: after correcting the source of the sampling clock to compensate for the initial frequency offset and the initial phase offset, enabling the clock recovery loop to minimize the timing error. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a perspective view of an illustrative active Ethernet cable ("AEC").

[0012] Figure 2 is a block diagram of an illustrative AEC.

[0013] Figure 3is a block diagram of an illustrative digital communications receiver.

[0014] Figure 4 is a block diagram of an illustrative decision feedback equalizer ("DFE").

[0015] Figure 5 is a block diagram of an illustrative parallelized DFE.

[0016] Figure 6 is a diagram of illustrative staggered clock signals.

[0017] Figure 7 is a flow chart of an illustrative phase and frequency acquisition method. DETAILED DESCRIPTION

[0018] Although specific embodiments are presented in the drawings and the following description, it should be kept in mind that they do not limit the present disclosure. Instead, they provide a basis for one of ordinary skill in the art to identify alternatives, equivalents, and modifications that are within the scope of the claims.

[0019] High bandwidth receivers or "deserializers" are used in many contexts ranging from intra-chip communications to long distance wireless, wired, and fiber optic communications. To provide a specific example, Figure 1 An illustrative active Ethernet cable ("AEC") is shown, which can be used to provide a high-bandwidth communication link between devices in a routing network, such as those used in data centers, server farms, and interconnect exchanges. The routing network can be part of or can include, for example, the Internet, a wide area network, a local area network, or a storage area network. The linked device can be a computer, a switch, a router, etc. The illustrative cable includes a first connector 100 and a second connector 101 connected via an electrical conductor 106 in the line. The electrical conductor 106 can be arranged in pairs, such as with a twinax conductor. (Twinax conductors can be compared to coaxial conductors, but have two inner conductors instead of one). The inner conductors can be driven with differential signals, and their shared shielding can be operated to reduce crosstalk with other twinax conductors in the cable. Depending on the performance criteria, it is also possible to implement other paired conductors or single-ended conductors.

[0020] According to the Ethernet standard, each conductor pair can provide unidirectional transmission of differential signals. In order to achieve robust performance over more extended cable lengths, each connector 100, 101 may include a powered transceiver that performs clock data recovery ("CDR") combined with demodulation and remodulation of the data stream moving in each direction. Such powered transceivers are also referred to as data recovery and remodulation ("DRR") devices. Connectors 100, 101 can be pluggable modules that comply with any of the pluggable module standards (e.g., SFP, SFP-DD, QSFP, QSFP-DD, OSFP). In at least one contemplated embodiment, cable connectors 100, 101 are four small form factor pluggable ("QSFP") transceiver modules that can exchange 800GAUI-8 data streams with a host at a nominal baud rate of 56Gbd in each of eight channels using PAM4 signaling.

[0021] Figure 2 is a block diagram of an illustrative AEC. Connector 100 includes a plug 200 adapted to fit a standard-compliant Ethernet port in a first host device to receive an electrical input signal carrying a data stream from the host device and provide an electrical output signal carrying a data stream to the host device. Similarly, connector 101 includes a plug 201 adapted to fit an Ethernet port of a second host device. Connector 100 includes a first DRR device 202 for performing CDR, demodulation, and remodulation on data streams entering and leaving the cable at connector 100, and connector 101 includes a second DRR device 204 for performing CDR, demodulation, and remodulation on data streams entering and leaving the cable at connector 101. The DRR devices 202, 204 can be integrated circuits mounted on a printed circuit board and connected to edge connector contacts via circuit board traces. Electrical conductors 106 and shields can be soldered to corresponding pads on the printed circuit board that are electrically connected to the DRR devices.

[0022] In at least some contemplated embodiments, the printed circuit boards also each support a microcontroller unit ("MCU") 206. Each DRR device 202, 204 is coupled via a first two-wire bus to a corresponding MCU device 206 that configures the operation of the DRR device. At power-on, the MCU device 206 loads equalization parameters and / or other operating parameters from a flash memory 207 into a configuration register 208 of the DRR device. A host device can access the MCU device 206 via a second two-wire bus that operates according to an I2C bus protocol and / or a faster MDIO protocol. With such access to the MCU device 206, the host device can adjust the operating parameters of the cable and monitor the performance of the cable.

[0023] Each DRR device 202, 204 includes a transmitter and receiver set 220 for communicating with a host device and a transmitter and receiver set 222 for transmitting and receiving via a conductor pair along the length of the cable. The cable-oriented transceiver 222 preferably uses differential PAM4 transmission and reception at 56Gbd in each direction of each channel. The illustrated host-oriented transceiver 220 supports eight channels LN0-LN7 for bidirectional communication with the host device, each bidirectional channel is formed by two unidirectional connections using differential PAM4 signaling at 56Gbd, such as can be implemented using 800GBASE-KR8. The DRR device includes a memory 224 for providing a first-in-first-out (FIFO) buffer between the transmitter and receiver sets 220, 222. The embedded controller 228 coordinates the operation of the transmitter and receiver by, for example, setting initial equalization parameters and ensuring that the training phase is completed across all channels and links before enabling the transmitter and receiver to enter the data transmission phase. Embedded controller 228 employs set of registers 208 to receive commands and parameter values ​​and to provide responses that potentially include status information and performance data.

[0024] Figure 3 is a first illustrative digital receiver that may be used as part of transceiver set 220, 222. The digital receiver includes an analog-to-digital converter ("ADC") 304 that samples an analog received signal 302 at sampling times corresponding to transitions in a sampling clock signal 305, thereby providing samples of the digital received signal to a filter ("feed-forward equalizer" or FFE) 306, which converts the digital received signal samples into equalized signal samples with reduced inter-symbol interference. A slicer 307 compares the equalized signal samples to an appropriate decision threshold to determine which symbol was transmitted in each symbol interval. The resulting demodulated symbol stream 308 may be processed according to a relevant communication protocol to recover relevant information from the data stream (e.g., using frame alignment, deinterleaving, error correction, and descrambling operations).

[0025] The illustrative receiver includes clock recovery circuitry to generate a suitable sampling clock signal 305. Figure 3In , the clock recovery circuit includes a phase and frequency acquisition module 309 and a feedback loop starting with a timing error estimator 310. The timing error estimator 310 can use any suitable timing error estimation technique, for example, the formula in Mueller-Müller, "Timing Recovery in Digital Synchronous Data Receivers" (IEEE Journal of Communications, Vol. 24, No. 5, May 1976). The timing loop filter 312 filters the estimated timing error signal to obtain a timing control signal for the phase interpolator 320. In Figure 3 In the embodiment of the present invention, the timing loop filter 312 is a second-order proportional integral (PI) filter having an adder 314 that receives a proportion (ie, a constant coefficient k) of the timing error signal along the first path. P The scaled) component of the timing error signal along the second path is received by integrating (i.e., scaling by a constant factor k) I The received components are summed and provided to a second integrator 318 which integrates the sum to provide a timing control signal to a phase interpolator 320.

[0026] Phase interpolator 320 also receives a clock signal from a phase locked loop (PLL) 322. The timing control signal causes phase interpolator 320 to generate a sampling signal by adjusting the phase of the clock signal in a manner that minimizes an expected value of the timing error. In other words, the timing control signal compensates for both the frequency offset and the phase error of the PLL output signal relative to the analog data signal 302, thereby aligning the sampling clock 305 with the phase of the data symbols in the analog received signal.

[0027] The clock signal generated by PLL 322 is a multiplied version of the reference clock signal from reference oscillator 324 or other clock source. Voltage controlled oscillator ("VCO") 326 supplies the clock signal to both phase interpolator 320 and counter 328, which divides the frequency of the clock signal by a constant or variable modulus N that provides a specified division ratio. The counter supplies the divided clock signal to phase frequency detector ("PFD") 330. PFD 330 can use a charge pump ("CP") as part of determining which input (i.e., the divided clock signal or the reference clock signal) has an earlier or more frequent transition than the other. Low pass filter 332 filters the output of PFD 330 to provide a control voltage to VCO 326. The filter coefficients are selected so that the divided clock becomes phase aligned with the reference oscillator.

[0028] It should be noted that for at least some intended uses, the reference clock used by the receiver will typically drift relative to the reference clock used by the transmitter, and may differ by hundreds of ppm. Figure 3 In the disclosed embodiment, the resulting frequency offset between the clock signal output of the PLL and the analog data signal may be corrected by adjusting the modulus N of the counter 328 and / or by appropriately setting the integrator 316 to provide continuous phase rotation in the phase interpolator 320. Other feedback loop implementations are available in the public literature and are also suitable for use in the disclosed embodiments.

[0029] The inherent loop delay of the feedback loop is stabilized by appropriate design of the timing loop filter to limit the response bandwidth, but this limitation may result in undesirable delays in achieving minimum timing error. The phase and frequency acquisition module 309 solves this problem by estimating the initial frequency offset and phase offset of the sampling clock signal 305 during the preamble stage, in which the transmitter sends doublets of symbols alternating between symbols, such as +1, +1, -1, -1, +1, +1, -1, -1, ... Preferably, the transmitter uses the maximum amplitude symbol for the preamble, so that for PAM4, the preamble would be a sequence of +3, +3, -3, -3 repetitions. As further explained below, the phase and frequency acquisition module 309 enables the initial frequency offset and initial phase offset to be determined and corrected in less than about 200 symbols, thereby shortening the normal convergence time of the feedback loop by several orders of magnitude. The phase and frequency acquisition module 309 can perform this determination based on received signal samples or, alternatively, based on equalized signal samples. The equalized signal samples can be Figure 3 The outputs of the FFE filter 306 are shown in FIG. , or they may be Figure 4-Figure 5 The input of the limiter 307 shown in the decision feedback equalizer.

[0030] Figure 4 An illustrative implementation of a receiver based on a decision feedback equalizer is shown. Prior to sampling, the analog channel signal 302 is filtered by a continuous time linear equalizer ("CTLE") 440 to attenuate out-of-band noise and optionally provide some spectral shaping to improve the response to high frequency components of the received signal. Figure 3 The receiver may also include similar analog filters.) ADC 304 is provided to digitize the received signal, and FFE filter 306 performs further equalization to further shape the overall channel response of the system and minimize the impact of leading ISI on the current symbol. As part of the shaping of the overall channel response, FFE filter 306 may also be designed to shorten the channel response of the filtered signal while minimizing any accompanying noise enhancement.

[0031] Adder 442 subtracts an optional feedback signal from the output of FFE 306 to minimize the effect of tail ISI on the current symbol, thereby generating an equalized signal coupled to decision element ("slicer") 307. Decision element 307 includes one or more comparators that compare the equalized signal with a corresponding decision threshold to determine which constellation symbol the value of the signal most closely corresponds to for each symbol interval. The input of slicer 307 may also be referred to as a "combined signal" in this article.

[0032] Thus, decision element 307 generates a sequence of symbol decisions 308. In certain contemplated embodiments, the signal constellation is a bipolar (non-return-to-zero) constellation representing -1 and +1, requiring the use of only one comparator with a decision threshold of zero. In certain other contemplated embodiments, the signal constellation is PAM4 (-3, -1, +1, +3), requiring the use of three comparators with decision thresholds of -2, 0, and +2, respectively. (For generality, the units used to express the symbols and thresholds are omitted, but may be assumed to be volts for purposes of explanation. In practice, a scaling factor will be employed.) The comparator outputs may be collectively a thermometer-coded digital representation of the output symbol decisions, e.g., where 000 represents -3, 100 represents -1, 110 represents +1, and 111 represents +3. Alternatively, the comparator outputs may be converted to a binary or Gray-coded representation.

[0033] Feedback filter ("FBF") 444 uses a series of delay elements (e.g., latches, flip-flops, or registers) that store the most recent output symbol decisions to derive the feedback signal. Each stored symbol is associated with a corresponding filter coefficient f i are multiplied, and these products are combined to obtain the feedback signal.

[0034] The DFE based receiver also includes a clock recovery circuit having a phase and frequency acquisition module 309 and a feedback loop starting with a timing error estimator 310. In addition, we note here that the receivers each also include a filter coefficient adaptation unit, but such considerations are addressed in the literature and are well known to those skilled in the art. However, we note here that at least some contemplated embodiments include one or more additional comparators in the decision element 307 to be used to compare the equalized or combined signal with one or more of the symbol values, thereby providing an error signal that can be used for timing recovery and / or coefficient adaptation.

[0035] As symbol rates increase into the gigahertz range, it becomes increasingly difficult for the individual receiver components to perform their required operations completely within each symbol interval, at which point it becomes advantageous to parallelize their operations. Parallelization generally involves the use of multiple components that share the workload by taking turns and thereby providing each of the individual components with more time to complete its operations. Such parallel components are driven by interleaved versions of a clock signal, such as Figure 6 The four-fold parallelization employs a set of four clock signals, each having a frequency of one-quarter the symbol rate, such that each symbol interval contains only one upward transition in the set of interleaved clock signals. Although four-fold parallelization is used for discussion purposes herein, the actual degree of parallelization may be higher, for example, 8x, 16x, 32x, or 64x. Furthermore, the degree of parallelization is not limited to powers of 2.

[0036] Figure 5 An illustrative receiver with a parallelized equalizer implementation (including an optional feedback filter for DFE) is shown. Figure 4 , CTLE 440 filters the channel signal to provide a received signal, which is provided in parallel to a set of analog-to-digital converters (ADC0-ADC3). Each of the ADC elements is provided with a Figure 6 The clock signals have different phases, causing the ADC elements to take turns sampling and digitizing the received signals, so that at any given time, only one of the ADC element outputs is transitioning.

[0037] An array of FFEs (FFE0 to FFE3), each forming a weighted sum of the ADC element outputs. The weighted sum employs filter coefficients that are cyclically shifted relative to each other. FFE0 operates on held signals from ADC3 (elements operating before CLK0), ADC0 (elements responsive to CLK0), and ADC1 (elements operating after CLK0) such that during the assertion of CLK2, the weighted sum produced by FFE0 is summed with FFE 306 ( Figure 4 ) corresponds to the output of FFE 306. FFE1 operates on the hold signals from ADC0 (element operated before CLK1), ADC1 (element responsive to CLK1), and ADC2 (element operated after CLK1) so that during the assertion of CLK3, the weighted sum corresponds to the output of FFE 306. And the operation of the remaining FFEs in the array follows the same pattern with associated phase shifts. In practice, the number of filter taps can be smaller, or the number of elements in the array can be larger, in order to provide a longer effective output window.

[0038] and Figure 4 Like a receiver, an adder can combine the output of each FFE with a feedback signal to provide an equalized signal to the corresponding decision element. Figure 5 An array of decision elements (limiter 0 to limiter 3) is shown, each operating on an equalized signal derived from a corresponding FFE output. Figure 4 Like the decision elements of the , the illustrated decision elements use comparators to determine which symbol the equalized signal most likely represents. Decisions are made when the corresponding FFE output is valid (e.g., limiter 0 operates when CLK2 is asserted, limiter 1 operates when CLK3 is asserted, etc.). Preferably, decisions are provided in parallel on the output bus to enable a lower clock rate to be used for subsequent operations.

[0039] An array of feedback filters (FBF0 to FBF3) operates on previous symbol decisions to provide feedback signals for the adder. As with the FFE, the input to the FBF is cyclically shifted and is only used when the input corresponds to FBF 444 ( Figure 4 ) content, consistent with the time window of the corresponding FFE. In practice, the number of feedback filter taps can be less than that shown, or the number of array elements can be larger, in order to provide a longer valid output window.

[0040] and Figure 4 Like the decision making element, Figure 5 The decision elements in may each employ additional comparators to provide timing recovery information, coefficient training information, and / or pre-calculation to expand one or more taps of the feedback filter. Figure 5 In an embodiment of the invention, the digital timing circuit is also parallelized, wherein the phase and frequency acquisition module 509 operates on the received signal samples during the training preamble to determine and correct the initial phase and frequency offset similar to module 309, and the timing error estimator 510 accepts the codeword decision and the equalized signal in parallel to determine the timing error estimate that will be produced by the estimator 310. The timing loop filter 512 generates the timing control signal that will be produced by the filter 312, and the phase interpolator 520 operates similarly to the phase interpolator 320 to convert the PLL clock signal into a set of interleaved clock signals with evenly spaced phases and codeword aligned transitions. A set of delay lines (DL0-DL3) is provided for fine-tuning the individual clock phases relative to each other as needed to, for example, compensate for different propagation delays of the various ADC elements.

[0041] exist Figure 5, the phase and frequency acquisition module 509 is shown as inhibiting the operation of the timing error estimator 510 (and correspondingly the feedback loop) during the initial acquisition, but such inhibition is optional in view of the limited loop bandwidth. Once the module 509 has determined the initial phase and frequency offset, it can adjust the PLL 322 and the phase interpolator 520 to compensate for the initial offset before enabling the timing error estimator (and correspondingly enabling the feedback loop). Alternatively or additionally, the phase and frequency acquisition module 509 can adjust the contents of the integrator in the loop filter 512 to compensate for the initial offset.

[0042] Figure 7 An illustrative method that can be implemented by the phase and frequency acquisition module mentioned above is shown, but some derivations may be helpful in understanding the method, so it is described first. The acquisition can be performed when the transmitter sends a preamble pattern consisting of alternating binary elements (also called a 2T pattern, for example, a repetition of the sequence [-3,-3,+3,+3]). On the receiving side, the received signal samples (provided by the analog-to-digital converter) or optionally the equalized signal samples output by the FFE filter or DFE adder will resemble a sine wave: Where A is the 2T frequency modulation amplitude, f b is the baud rate on the transmit side, 1 / T is the ADC sampling frequency, k is the ADC sample index, and is the initial sampling phase. The formula can be rewritten as: Where T b =1 / f b , and the ADC sampling period T = T b +ΔT. Then, (2) can be rewritten as: Where Δ=ΔT / T b .

[0043] From (3), we get: Formulas (3) and (4) can be combined: Based on this formula, we can estimate the current ADC sampling phase as:

[0044] The sampling frequency acquisition is done as follows. Let p k 、p k+1 , ... are the unfolded phase sequences in (6). Expanding (4) and (5), we obtain the following: Where D is an integer of the sampling interval. According to (7), we have: where f s =1 / T is the ADC sampling frequency. From (8) we can estimate the normalized frequency offset Δf as: Averaging can be used to improve the estimate, either by averaging the estimated rate of change in the unwrapped phase sequence, or by averaging the estimated normalized frequency offsets over a given interval.

[0045] After the frequency offset has been corrected, or in the case where the ADC sampling frequency can be assumed to be close to the transmit baud rate (e.g., within a few hundred parts per million), the ADC sampling phase will be relatively constant and can be calculated by calculating the phase estimate p over a given interval. k Averaging to estimate the average phase 均 The target sampling phase at the input of the decision element is π / 4. If we use the received signal samples to derive the phase estimate, it is desirable to account for any phase shift that may be introduced by the FFE filter. Denoting the frequency response of the FFE at frequency f as F(f), let the FFE filter be b / 4) is expressed as Then the target sampling phase of the ADC is And it can be predetermined for a given set of filter coefficients. Sampling phase offset becomes The phase and frequency acquisition module can use this sampling phase offset to quickly correct the sampling phase, for example, by adjusting the settings of a phase interpolator to compensate.

[0046] The above derivation assumes that the transmitter uses a 2T preamble pattern. Another popular preamble pattern that can be used by the transmitter is the Nyquist pattern (a sequence of alternating polarity symbols, such as -3, +3, -3, +3, ...). In this case, the received signal sinusoidal wave can be expressed as

[0047] Assume that each ADC sampling cycle generates M samples and the ADC sampling phase remains unchanged within one cycle. Let x nM+i is the i-th sample of the n-th ADC sampling cycle. In the n-th ADC sampling cycle, we sample the ADC input signal as And in the n+1th ADC sampling cycle, we get According to (15) and (16), we have make Make P n,i+D -P n,i =DπΔ (20) Then, the normalized frequency shift Δf is given as The estimated normalized frequency offset may be improved by averaging the estimated values ​​over a given interval.

[0048] After the frequency offset is corrected, or in the case where the ADC sampling frequency can be assumed to be close to the transmit baud rate (e.g., within a few hundred parts per million), the ADC sampling phase will be relatively constant and can be calculated by comparing the phase estimate p from equation (18) over a given interval n,i Take the average to estimate to get the average phase For sampling phase acquisition, the target sampling phase should be such that the Nyquist frequency f b / 2, which is equivalent to sampling at the peak of the frequency tone. The target sampling phase is taken as Sampling Phase Offset becomes If the acquisition phase and frequency offset is performed using equalized samples instead of received signal samples, the phase shift of the FFE filter is already accounted for, and in equations 10 and 22,

[0049] Now back to Figure 7 The phase and frequency acquisition module may be used during link startup when the remote transmitter is expected to transmit a preamble. In block 702, the module optionally disables the feedback loop by, for example, disabling a timing error detector. In block 704, the module Figure 3 and Figure 4 Obtaining (one or more) received signal samples one at a time as provided, or as Figure 5The received signal samples (one or more) are obtained in batches as provided. The sampling clock used to obtain the samples has an initial phase and frequency, which may be offset from the transmit baud rate and the target sampling phase.

[0050] In box 706, the module obtains additional (one or more) received signal samples, combines them with the previous (one or more) received signal samples to obtain a sampling phase estimate. In box 708, the module obtains more (one or more) received signal samples to obtain an updated sampling phase estimate. The module derives the estimated frequency offset from the trend of the sampling phase estimate. In box 710, more (one or more) received signal samples are obtained to provide an updated sampling phase estimate and a new frequency offset estimate, which can be combined with the previous estimate (e.g., by averaging) to improve the reliability of the frequency offset estimate. In box 712, the module determines whether the estimate is sufficiently reliable by, for example, determining whether enough estimates have been averaged together. Boxes 710 and 712 can be repeated until sufficient reliability is achieved.

[0051] In block 714, the module uses the estimated frequency offset to adjust the frequency of the sampling clock. Such adjustment may take the form of adjusting the control voltage of a voltage controlled oscillator, adjusting a phase locked loop frequency divider, and / or adjusting an accumulator value in a clock recovery feedback loop. In each case, the adjustment is readily derived from the estimated frequency offset.

[0052] In block 716, the module obtains (one or more) received signal samples and estimates the sampling phase using a sampling clock with an adjusted frequency. In block 718, the module determines whether the phase estimate is sufficiently reliable, for example, whether enough estimates have been averaged together. Blocks 716 and 718 can be repeated until sufficient reliability is achieved. In block 720, the module uses the estimated phase to calculate the phase offset and adjust the sampling clock phase to compensate for the phase offset. Such adjustments can take the form of adjusting the sampling clock delay, adjusting the phase interpolator setting, and / or adjusting the accumulator value in the clock recovery feedback loop. In each case, the adjustment is easily derived from the estimated phase offset.

[0053] In block 722, the module enables the clock recovery feedback loop, for example by enabling a timing error calculator. Thereafter, the clock recovery feedback loop operates in the usual manner to minimize the timing error, and the receiver can continue to train the equalizer coefficients (if necessary). Figure 7 The operations in have been shown and described in a sequential manner, but these operations may be reordered and / or performed simultaneously. For example, phase offset estimation may be performed before frequency offset estimation or simultaneously with frequency offset estimation.

[0054] Simulations are performed to verify the performance of the proposed fast sampling phase and frequency acquisition. A PAM4 2T mode [-3,-3,+3,+3] at 52.125Gbd is transmitted through a channel with 13dB loss at the Nyquist frequency. The ADC digitizes the received signal with 7-bit resolution. For sampling phase acquisition, 64 PAM4 symbols are used for phase offset estimation. The average phase estimation error magnitude is less than 0.014 channel symbol interval (UI), and most of them are below 0.010UI. For sampling frequency acquisition, 128 PAM4 symbols are used to estimate the frequency offset. For an initial 100ppm frequency offset, the frequency estimation error has an RMS value of 18.58ppm, and for an initial 200ppm frequency offset, the frequency estimation error has an RMS value of 19.27ppm. In these experiments, the phase and frequency acquisition module requires less than 200 channel symbols (less than 2.3 nanoseconds) to provide reasonably good sampling phase and frequency matching.

[0055] The phase and frequency acquisition module can be implemented as a dedicated integrated circuit system. The inverse tangent calculation of the phase estimate can be implemented using an iterative calculation circuit that implements the coordinate rotation digital computer (CORDIC) technology or by using a non-iterative polynomial approximation technique. Alternatively, the method can be implemented as firmware programming for a microcontroller or a programmable digital signal processor.

[0056] It is contemplated that the disclosed phase and frequency acquisition modules may be incorporated into SerDes cores for use by integrated circuit designers and manufacturers to create devices for a wide range of applications that may benefit from cost, complexity, and power efficient high bandwidth communications. Numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the disclosed principles are applicable to PAM, QAM, and PSK modulations, and to larger signal constellations including 8-PSK, 16-PAM, and the like. It is intended that the claims be interpreted as covering all such alternatives, equivalents, and modifications as are included within the scope of the appended claims.

[0057] The above integrated circuits are typically created by patterning layers on a semiconductor substrate using masks during the integrated circuit manufacturing process. Mask patterns can be generated using commercially available software that is used to convert semiconductor IP cores (typically expressed using a hardware description language such as Verilog) into semiconductor process masks. The circuits can be sub-units of more complex integrated circuit devices whose designs are built from modular components in a design database residing on a non-transitory information storage medium. Once the circuit is fully designed, the software can convert the integrated circuit into a semiconductor mask pattern also stored on a non-transitory information storage medium and transmitted to various processing units on a suitable assembly line of the integrated circuit manufacturer.

Claims

1. A receiver, comprising an integrated circuit, the integrated circuit having: an analog-to-digital converter that samples the received signal according to a sampling clock to provide a sampled received signal; as well as A clock recovery circuit, the clock recovery circuit comprising: A phase and frequency acquisition module, used to determine and correct an initial frequency offset and an initial phase offset of the sampling clock; as well as A feedback loop is provided for minimizing a timing error of the sampling clock after the initial frequency offset and the initial phase offset have been corrected.

2. The receiver of claim 1, wherein: The analog-to-digital converter is one of a set of analog-to-digital converters that samples the received signal in response to an interleaved version of the sampling clock to provide a set of parallel sampled received signals.

3. The receiver of claim 1, wherein: The integrated circuit includes an equalizer that converts the sampled received signal into an equalized signal, and wherein the phase and frequency acquisition module uses the equalized signal to derive the initial frequency offset and the initial phase offset.

4. The receiver of claim 3, wherein: The phase and frequency acquisition module estimates a sampling clock phase using ratios of pairs of signal samples received during a preamble period.

5. The receiver of claim 4, wherein: The sampling clock phase estimates are each calculated as the arc tangent of one of the ratios.

6. The receiver of claim 4, wherein: The phase and frequency acquisition module estimates a frequency offset based on one or more differences between the sampling clock phase estimates.

7. The receiver of claim 1, wherein: The clock recovery circuit further includes a phase-locked loop having an initial frequency division ratio, and the phase and frequency acquisition module is configured to correct the initial frequency offset by adjusting the initial frequency division ratio.

8. The receiver of claim 1, wherein: The clock recovery circuit also includes a phase interpolator having an initial phase setting, and the phase and frequency acquisition module is configured to correct the initial phase offset by adjusting the initial phase setting.

9. A method comprising: sampling a received signal in response to a sampling clock to provide received signal samples, the sampling clock having an initial frequency; obtaining a sampling clock phase estimate from each of a plurality of received signal sample pairs; differentiating the sampling clock phase estimate to determine an initial frequency offset; as well as A source of the sampling clock is corrected to compensate for the initial frequency offset.

10. The method of claim 9, further comprising: combining at least some of the sampling clock phase estimates to obtain an initial phase offset; as well as A source of the sampling clock is corrected to compensate for the initial phase offset.

11. The method of claim 10, further comprising: After correcting the source of the sampling clock to compensate for the initial frequency offset and the initial phase offset, a clock recovery loop is enabled to minimize timing errors.

12. The method of claim 9, wherein: Obtaining the sampling clock phase estimate includes equalizing each received signal sample in the pair of received signal samples.

13. The method of claim 9, wherein: Obtaining the sampling clock phase estimate is performed during a preamble period.

14. The method of claim 13, wherein: Each sampling clock phase estimate is the arctangent of the ratio between the received signal samples or between equalized versions of the received signal samples.

15. A non-transitory information storage medium having a semiconductor intellectual property core for generating a circuit system, the circuit system comprising: a clock circuit configured to provide a sampling clock; an analog-to-digital converter configured to sample the received signal according to the sampling clock to provide a sampled received signal; as well as A clock recovery circuit, the clock recovery circuit comprising: A phase and frequency acquisition module, configured to determine and correct an initial frequency offset and an initial phase offset of the sampling clock; as well as A feedback loop is configured to minimize a timing error of the sampling clock after the initial frequency offset and the initial phase offset have been corrected.

16. The non-transitory information storage medium of claim 15, wherein: The analog-to-digital converter is one of a set of analog-to-digital converters configured to sample the received signal in response to an interleaved version of the sampling clock to provide a set of parallel sampled received signals.

17. The non-transitory information storage medium of claim 15, wherein: The circuit system includes an equalizer configured to convert the sampled received signal into an equalized signal, and wherein the phase and frequency acquisition module is configured to derive the initial frequency offset and the initial phase offset using the equalized signal.

18. The non-transitory information storage medium of claim 17, wherein: The phase and frequency acquisition module is configured to estimate the sampling clock phase as an arc tangent of a ratio between equalized signal samples during a preamble period.

19. The non-transitory information storage medium of claim 18, wherein: The phase and frequency acquisition module is configured to estimate the initial frequency offset based on a difference between the sampling clock phase estimates.

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