Image visual data processing system and method based on FPGA

Abstract

The invention relates to the technical field of image visual data processing, in particular to an image visual data processing system and method based on an FPGA. The processing method comprises the following steps: acquiring image data acquired by a front-end camera, preprocessing the image data, and outputting preprocessed data; a buffer rack is arranged to cache the preprocessed data; verifying a link connection state, and executing a transmission operation; performing target identification and tracking processing on the data, and outputting a processing result; the processing system comprises an image data acquisition module, a data buffer module, a link verification module and a data processing module, data is cached firstly, data transmission is directly carried out after the link connection state is verified, and the overall data processing efficiency can be improved while it is guaranteed that the link is transmitted in the connection state.

Description

Technical Field

[0001] The present invention relates to the technical field of image vision data processing, and in particular to an image vision data processing system and method based on FPGA. Background Art

[0002] With the continuous development of image processing systems that are becoming more precise, faster, and more integrated, the requirements for data processing speed are getting higher and higher, and the constraints on volume, power consumption, and upgrade capabilities are becoming more and more stringent. Image processing systems that simply use DSP (digital signal processor) or ASIC (application-specific integrated circuit) are difficult to meet the above requirements. A large number of practices have proved that the parallel processing capabilities and pipeline operations of FPGA can significantly improve the speed of image processing.

[0003] In the existing image vision data processing, FPGA is used to process the data. In order to prevent transmission interruption, data collection is required after the link is connected during the transmission process.

[0004] However, in the above method, data collection is performed only after the link is connected, and verification is required before collection, which results in low data processing efficiency. Summary of the invention

[0005] The purpose of the present invention is to provide an image vision data processing system and method based on FPGA, aiming to solve the technical problem in the prior art that data collection is performed only after waiting for a link connection, and collection is performed after verification, resulting in low data processing efficiency.

[0006] To achieve the above object, the present invention adopts an image vision data processing method based on FPGA, comprising the following steps:

[0007] Obtain image data collected by the front-end camera, pre-process the image data, and output the pre-processed data;

[0008] Set up a buffer rack to cache preprocessed data;

[0009] Verify link connection status and perform transmission operations;

[0010] Perform target recognition and tracking processing on the data and output the processing results.

[0011] Among them, in the step of obtaining image data collected by the front-end camera, preprocessing the image data, and outputting the preprocessed data:

[0012] Connect the camera and FPGA system to obtain image data;

[0013] The image data is processed in sequence including denoising, image enhancement, color correction and format conversion.

[0014] Among them, after the steps of performing denoising, image enhancement, color correction, and format conversion on the image data in sequence:

[0015] Assigning a first identifier and a second identifier to the image data; wherein the first identifier is the real time, and the second identifier is the position coordinate;

[0016] The image data, the first identifier and the second identifier are integrated to output pre-processed data.

[0017] Among them, in the step of setting up a buffer rack to cache the pre-processed data:

[0018] Build a buffer rack to receive pre-processed data;

[0019] Obtaining the second identification content, and classifying the pre-processed data according to the position coordinates;

[0020] The first identification content is obtained, and each type of data is sorted according to the real time.

[0021] Among them, in the step of verifying the link connection status and performing the transmission operation:

[0022] If the link is connected, the transmission channel is divided and the pre-processed data is transmitted according to the location coordinates.

[0023] Among them, in the step of verifying the link connection status and performing the transmission operation:

[0024] If the link is not connected, stop transmission and continuously trigger link verification requests.

[0025] Among them, in the step of performing target recognition and tracking processing on the data and outputting the processing results:

[0026] Extract target features from known target data and store them in the database;

[0027] Extract specific features from the data, compare the specific features with the target features, and output the tracking target;

[0028] Obtain the position and speed information of the tracking target in the current frame, use the motion model to predict the position of the tracking target in the next frame, and obtain the movement trajectory;

[0029] Output trajectory, position, and velocity information.

[0030] The present invention also provides an image vision data processing system based on FPGA, comprising an image data acquisition module, a data buffer module, a link verification module and a data processing module; wherein:

[0031] The image data acquisition module is used to acquire image data collected by the front-end camera, pre-process the image data, and output the pre-processed data;

[0032] The data buffer module is used to set up a buffer rack to cache the pre-processed data;

[0033] The link verification module is used to verify the link connection status and perform the transmission operation;

[0034] The data processing module is used to perform target recognition and tracking processing on the data and output the processing results.

[0035] The present invention provides an FPGA-based image vision data processing system and method, which respectively uses the image data acquisition module, the data buffer module, the link verification module and the data processing module to perform the following steps: acquiring image data collected by a front-end camera, preprocessing the image data, and outputting the preprocessed data; setting up a buffer rack to cache the preprocessed data; verifying the link connection status and performing a transmission operation; performing target recognition and tracking processing on the data and outputting the processing results; first caching the data, and directly transmitting the data after verifying the link connection status, thereby ensuring that the link is transmitted in a connected state while improving the overall data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a flow chart of the steps of the image vision data processing method based on FPGA of the present invention.

[0038] Figure 2 It is a step flow chart of S100 of the present invention.

[0039] Figure 3 It is a step flow chart of S200 of the present invention.

[0040] Figure 4 It is a step flow chart of S400 of the present invention.

[0041] Figure 5 It is a structural principle diagram of the image vision data processing system based on FPGA of the present invention.

[0042] Figure 6 It is a structural principle diagram of the electronic equipment of the present invention.

[0043] 501 - image data acquisition module, 502 - data buffer module, 503 - link verification module, 504 - data processing module. DETAILED DESCRIPTION

[0044] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0045] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0046] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0047] See also Figure 1 to Figure 4 The present invention provides an image visual data processing method based on FPGA, comprising the following steps:

[0048] S100: Acquire image data collected by a front-end camera, pre-process the image data, and output the pre-processed data;

[0049] In this embodiment, the image data collected by the front-end camera is first obtained, the image data is pre-processed, and the pre-processed data is output. The specific process is as follows:

[0050] S101: Connect the camera and FPGA system to obtain image data;

[0051] S102: performing denoising, image enhancement, color correction, and format conversion processing on the image data in sequence;

[0052] S103: assigning a first identifier and a second identifier to the image data; wherein the first identifier is the real time, and the second identifier is the position coordinate;

[0053] S104: Integrate the image data, the first identifier and the second identifier, and output pre-processed data.

[0054] In the above process, the camera and FPGA system are first connected to obtain image data. Then, the image data is subjected to denoising, image enhancement, color correction, and format conversion in turn to improve the quality of subsequent data processing. Then, the image data is given a first identifier and a second identifier; the first identifier is the real time, and the second identifier is the position coordinate. Then, the image data, the first identifier, and the second identifier are integrated to output the preprocessed data.

[0055] S200: Setting up a buffer rack to cache preprocessed data;

[0056] In this embodiment, after the image data is preprocessed, a buffer rack is set up to cache the preprocessed data. The specific process is as follows:

[0057] S201: Building a buffer rack and receiving pre-processed data;

[0058] S202: Acquire the second identification content and classify the pre-processed data according to the position coordinates;

[0059] S203: Obtain the first identification content, and sort each type of data according to the real time.

[0060] In the above process, a buffer rack is first constructed to receive pre-processed data and cache the pre-processed data. Then the second identification content is obtained and the pre-processed data is classified according to the position coordinates. Then the first identification content is obtained and each type of data is sorted according to the real time.

[0061] S300: verifying the link connection status and performing a transmission operation;

[0062] In this embodiment, if the link is connected, the transmission channel is divided and the pre-processed data is transmitted according to the location coordinates; if the link is not connected, the transmission is stopped and the link verification request is continuously triggered.

[0063] S400: Perform target recognition and tracking processing on the data and output the processing results.

[0064] In this embodiment, after receiving the data, target recognition and tracking processing are performed on the data, and the processing results are output. The specific process is:

[0065] S401: extracting target features from known target data and storing them in a database;

[0066] S402: extracting specific features from the data, comparing the specific features with the target features, and outputting the tracking target;

[0067] S403: Obtaining the position and speed information of the tracking target in the current frame, predicting the position of the tracking target in the next frame using the motion model, and obtaining the moving trajectory;

[0068] S404: Output trajectory, position, and speed information.

[0069] In the above process, the target features are first extracted from the known target data and stored in the database. Then, specific features are extracted from the data, compared with the target features, and the tracked target is output. Then, the position and speed information of the tracked target in the current frame are obtained, and the position of the tracked target in the next frame is predicted using the motion model, and the movement trajectory is obtained. Finally, the trajectory, position, and speed information are output.

[0070] Corresponding to the aforementioned embodiment of the image vision data processing method based on FPGA, the present application also provides an embodiment of an image vision data processing system based on FPGA.

[0071] Figure 5 FIG. 1 is a block diagram of an image visual data processing system based on FPGA according to an exemplary embodiment. Figure 5 The system may include: an image data acquisition module 501, a data buffer module 502, a link verification module 503 and a data processing module 504; wherein:

[0072] The image data acquisition module 501 is used to acquire image data collected by the front-end camera, pre-process the image data, and output the pre-processed data;

[0073] The data buffer module 502 is used to set up a buffer rack to cache the pre-processed data;

[0074] The link verification module 503 is used to verify the link connection status and perform the transmission operation;

[0075] The data processing module 504 is used to perform target recognition and tracking processing on the data and output the processing results.

[0076] In this embodiment, the image data acquisition module 501 acquires the image data collected by the front-end camera, pre-processes the image data, and outputs the pre-processed data. The data buffer module 502 sets up a buffer rack to cache the pre-processed data. The link verification module 503 verifies the link connection status and performs a transmission operation. The data processing module 504 performs target recognition and tracking processing on the data and outputs the processing results. The data is first cached, and the data is directly transmitted after the link connection status is verified, so as to ensure that the link is transmitted in the connected state while improving the efficiency of the overall data processing.

[0077] Regarding the system in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0078] For the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application. A person of ordinary skill in the art can understand and implement it without creative work.

[0079] Accordingly, the present application also provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the above-mentioned FPGA-based image visual data processing method. Figure 6 As shown in FIG. 1 , a hardware structure diagram of an FPGA-based image visual data processing system provided by an embodiment of the present invention is provided for any device with data processing capability, except Figure 6 In addition to the processor, memory and network interface shown, any device with data processing capability in which the apparatus in the embodiment is located may also include other hardware, generally based on the actual functions of the device with data processing capability, which will not be described in detail.

[0080] Correspondingly, the present application also provides a computer-readable storage medium on which computer instructions are stored, and when the instructions are executed by the processor, the image vision data processing method based on FPGA as described above is implemented. The computer-readable storage medium can be an internal storage unit of any device with data processing capabilities described in any of the aforementioned embodiments, such as a hard disk or a memory. The computer-readable storage medium can also be an external storage device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), an SD card, a flash card (Flash Card), etc. equipped on the device. Furthermore, the computer-readable storage medium can also include both an internal storage unit of any device with data processing capabilities and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by any device with data processing capabilities, and can also be used to temporarily store data that has been output or is to be output.

[0081] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0082] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. An image visual data processing method based on FPGA, characterized in that: The steps include: Obtain image data collected by the front-end camera, pre-process the image data, and output the pre-processed data; Set up a buffer rack to cache preprocessed data; Verify link connection status and perform transmission operations; Perform target recognition and tracking processing on the data and output the processing results.

2. The FPGA-based image visual data processing method according to claim 1, characterized in that: In the step of obtaining the image data collected by the front-end camera, preprocessing the image data, and outputting the preprocessed data: Connect the camera and FPGA system to obtain image data; The image data is processed in sequence including denoising, image enhancement, color correction and format conversion.

3. The FPGA-based image visual data processing method according to claim 2, characterized in that: After the image data is processed in sequence by denoising, image enhancement, color correction, and format conversion: Assigning a first identifier and a second identifier to the image data; wherein the first identifier is the real time, and the second identifier is the position coordinate; The image data, the first identifier and the second identifier are integrated to output pre-processed data.

4. The FPGA-based image visual data processing method according to claim 3, characterized in that: In the step of setting up a buffer rack to cache preprocessed data: Build a buffer rack to receive pre-processed data; Obtaining the second identification content, and classifying the pre-processed data according to the position coordinates; The first identification content is obtained, and each type of data is sorted according to the real time.

5. The FPGA-based image visual data processing method according to claim 4, characterized in that: In the steps of verifying the link connection status and performing the transmission operation: If the link is connected, the transmission channel is divided and the pre-processed data is transmitted according to the location coordinates.

6. The FPGA-based image visual data processing method according to claim 5, characterized in that: In the steps of verifying the link connection status and performing the transmission operation: If the link is not connected, stop transmission and continuously trigger link verification requests.

7. The FPGA-based image visual data processing method according to claim 6, characterized in that: In the step of target recognition and tracking of data and outputting processing results: Extract target features from known target data and store them in the database; Extract specific features from the data, compare the specific features with the target features, and output the tracking target; Obtain the position and speed information of the tracking target in the current frame, use the motion model to predict the position of the tracking target in the next frame, and obtain the movement trajectory; Output trajectory, position, and velocity information.

8. An FPGA-based image vision data processing system, applied to the FPGA-based image vision data processing method according to claim 1, characterized in that: It includes an image data acquisition module, a data buffer module, a link verification module and a data processing module; wherein: The image data acquisition module is used to acquire image data collected by the front-end camera, pre-process the image data, and output the pre-processed data; The data buffer module is used to set up a buffer rack to cache the pre-processed data; The link verification module is used to verify the link connection status and perform the transmission operation; The data processing module is used to perform target recognition and tracking processing on the data and output the processing results.

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