Semiconductor device and electronic apparatus

Abstract

The invention provides a semiconductor device and an electronic apparatus. The semiconductor device includes: a test signal generation circuit that modulates a test signal to generate a fifth modulated signal and a sixth modulated signal; a first amplifier circuit that outputs a third amplified signal and a fourth amplified signal, which are obtained by amplifying the fifth modulated signal and the sixth modulated signal, to a first output terminal and a second output terminal; a second amplifier circuit that outputs a seventh amplified signal and an eighth amplified signal, which are obtained by amplifying the fifth modulated signal and the sixth modulated signal, to a third output terminal and a fourth output terminal; a first peak frequency detection circuit that detects a first peak frequency by measuring a potential difference between the first output terminal and the second output terminal; a second peak frequency detection circuit that detects a second peak frequency by measuring a potential difference between the third output terminal and the fourth output terminal; and a determination circuit that determines whether or not the difference between the first peak frequency and the second peak frequency is within a predetermined reference frequency difference range.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic device. Background Art

[0002] Patent document 1 describes a speaker failure notification device in which a control unit measures impedance that changes with structural changes in a speaker, determines whether the measured impedance is within a predetermined range, and notifies the speaker of a failure if the impedance is determined to be outside the range.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-199854

[0004] In the speaker failure notification device described in Patent Document 1, it is determined whether the measured impedance is within a predetermined range. Therefore, if the impedance of the speaker changes due to temperature changes, there is a possibility that the speaker failure cannot be accurately determined. Summary of the invention

[0005] One embodiment of the semiconductor device of the present invention comprises: a first output terminal connected to a first terminal of a first sound reproducing device; a second output terminal connected to a second terminal of the first sound reproducing device; a third output terminal connected to the first terminal of a second sound reproducing device; a fourth output terminal connected to the second terminal of the second sound reproducing device; a first modulation circuit that modulates a signal based on a first sound source signal in a first operation mode and outputs a first modulation signal and a second modulation signal; and a second modulation circuit that modulates a signal based on a second sound source signal in the first operation mode and outputs a first modulation signal and a second modulation signal. a test signal generating circuit which modulates the test signal whose frequency is changed in a preset frequency band in a second operation mode to generate a fifth modulation signal and a sixth modulation signal; a first amplifier circuit which, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulation signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulation signal to the second output terminal, and outputs a third amplified signal obtained by amplifying the fifth modulation signal to the first output terminal in the second operation mode. , and outputs a fourth amplified signal obtained by amplifying the sixth modulated signal to the second output terminal; a second amplifier circuit, which outputs a fifth amplified signal obtained by amplifying the third modulated signal to the third output terminal in the first operation mode, and outputs a sixth amplified signal obtained by amplifying the fourth modulated signal to the fourth output terminal, and outputs a seventh amplified signal obtained by amplifying the fifth modulated signal to the third output terminal in the second operation mode, and outputs an eighth amplified signal obtained by amplifying the sixth modulated signal to the fourth output terminal; a first peak frequency detection circuit, The circuit comprises a circuit for measuring the potential difference between the first output terminal and the second output terminal in the second operation mode, and detecting the frequency of the test signal at which the impedance of the first sound reproduction device becomes a peak, namely, a first peak frequency; a second peak frequency detection circuit, which measures the potential difference between the third output terminal and the fourth output terminal in the second operation mode, and detects the frequency of the test signal at which the impedance of the second sound reproduction device becomes a peak, namely, a second peak frequency; and a determination circuit, which determines whether the difference between the first peak frequency and the second peak frequency is included in a specified reference frequency difference range.

[0006] One aspect of the electronic device of the present invention includes one aspect of the semiconductor device, the first sound reproducing device, and the second sound reproducing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a diagram showing a structural example of a semiconductor device according to this embodiment.

[0008] Figure 2This is a diagram showing an example of pulse width modulation for generating the modulation signal DOP.

[0009] Figure 3 FIG. 1 is a diagram showing an example of pulse width modulation for generating the modulation signal DON.

[0010] Figure 4 This is a diagram showing an example of the difference between the modulation signal DOP and the modulation signal DON.

[0011] Figure 5 This is a diagram showing an example of the relationship between the state of a speaker and the impedance characteristics.

[0012] Figure 6 This is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and its peripheral circuits.

[0013] Figure 7 This is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and its peripheral circuits.

[0014] Figure 8 A diagram showing a configuration example of a differential low-pass filter.

[0015] Fig. 9 This is a diagram showing an example of the relationship between a test signal, a peak frequency, and a peak voltage.

[0016] Fig.10 It is a graph showing the temperature dependence of peak impedance and peak frequency.

[0017] Fig.11 This is a diagram showing the temperature dependency of the waveform of the output voltage of the differential low-pass filter.

[0018] Fig.12 This is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode.

[0019] Fig.13 FIG. 1 is a diagram showing another example of pulse width modulation for generating the modulation signal DON.

[0020] Fig.14 This is a diagram showing another example of the difference between the modulation signal DOP and the modulation signal DON.

[0021] Fig.15 This is a functional block diagram of the electronic device according to this embodiment.

[0022] Fig.16 This is a diagram showing a configuration example of a warning device as an example of an electronic device.

[0023] Description of symbols

[0024] 1: semiconductor device; 2: micro control unit; 3, 3a, 3-1 to 3-m: sound reproduction device; 10: communication interface circuit; 20: memory; 21-1 to 21-n: sound source data; 30, 30a: modulation circuit; 31, 31a: digital filter; 32, 32a: Σ-Δ modulation circuit; 33, 33a: pulse width modulation circuit; 41, 41a: switch; 42, 42a: switch; 50, 50a: amplifier circuit; 51P, 51Pa, 51N, 51Na: class D amplifier; 60: test signal generation circuit; 61: determination circuit; 62: memory; 70, 70a: peak frequency detection circuit; 71: differential low-pass filter; 72: A / D conversion circuit ; 73: Peak time measurement circuit; 81, 81a: Switch; 82, 82a: Switch; 91: Output terminal; 92: Output terminal; 93: Output terminal; 94: Output terminal; 100: Sound source reproduction circuit; 110: Inspection circuit; 201-1~201-n: Inverter circuit; 202-1~202-n: Inverter circuit; 211: Operational amplifier; 212, 213, 214: Resistor; 215: Capacitor; 216: Resistor; 217: Capacitor; 218: Resistor; 219: Capacitor; 300: Electronic device; 300A: Warning device; 310: Processing unit; 320: Operation unit; 330: Storage unit; 340: Display unit; 400: Vehicle. DETAILED DESCRIPTION

[0025] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the structures described below are necessarily essential components of the present invention.

[0026] 1. Semiconductor devices

[0027] 1-1. Implementation Method

[0028] 1-1-1.Structure of semiconductor device

[0029] Figure 1 FIG. 1 is a diagram showing a structural example of a semiconductor device according to this embodiment. Figure 1 As shown, the semiconductor device 1 of this embodiment includes a communication interface circuit 10, a memory 20, switches 81, 81a, 82, 82a, a sound source reproduction circuit 100, and a test circuit 110. The semiconductor device 1 is connected to the sound reproduction device 3, 3a. The semiconductor device 1 may be a semiconductor integrated circuit device of one chip, may be composed of semiconductor integrated circuit devices of multiple chips, and may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0030] The semiconductor device 1 has two operation modes, a normal operation mode and a test mode. The normal operation mode is an operation mode in which the sound reproduction device 3, 3a reproduces sound. The test mode is an operation mode in which the state of the sound reproduction device 3, 3a is determined.

[0031] The memory 20 stores n sound source data 21-1 to 21-n. n is an integer greater than 1. The memory 20 may be, for example, a flash memory. The sound source data 21-1 to 21-n may be, for example, pulse code modulated sound data or adaptive differential pulse code modulated sound data. The sound source data 21-1 to 21-n may be, for example, data that is the basis of various sounds such as sounds obtained by imitating human speech, mechanical warning sounds, and effect sounds.

[0032] The communication interface circuit 10 is a circuit for data communication with the micro control unit 2. The communication interface circuit 10 may be, for example, an SPI interface circuit or an I2C interface circuit. SPI is the abbreviation of Serial Peripheral Interface, and I2C is the abbreviation of Inter-Integrated Circuit.

[0033] The communication interface circuit 10 receives various commands sent from the micro control unit 2, and generates various control signals corresponding to the received commands. For example, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the normal operation mode or the inspection mode, it generates a control signal for switching the connection of the switches 41, 41a, 42, 42a, 81, 81a, 82, 82a according to the operation mode. In addition, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3 to reproduce the sound source data 21-i, it reads the sound source data 21-i from the memory 20 and inputs it to the sound source reproduction circuit 100 as the sound source signal DI1, and instructs the sound source reproduction circuit 100 to reproduce by the sound reproduction device 3. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. In addition, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3a to reproduce the sound source data 21-j, the communication interface circuit 10 reads the sound source data 21-j from the memory 20 and inputs it to the sound source reproduction circuit 100 as the sound source signal DI2, and instructs the sound source reproduction circuit 100 to reproduce by the sound reproduction device 3a. The sound source data 21-j is any one of the sound source data 21-1 to 21-n stored in the memory 20. In addition, for example, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i or the sound source data 21-j being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100 to stop the reproduction. In addition, for example, when the communication interface circuit 10 receives various setting commands related to the sound source reproduction, the communication interface circuit 100 performs various settings on the sound source reproduction circuit 100.

[0034] In this embodiment, the sound source signals DI1 and DI2 input to the sound source reproduction circuit 100 are pulse code modulated signals. When the sound source data 21-1 to 21-n are compressed sound data or sound data subjected to adaptive differential pulse code modulation, the sound source data 21-i and 21-j to be reproduced are converted into the sound source signals DI1 and DI2 as pulse code modulated signals respectively by a decoder (not shown).

[0035] The sound source reproduction circuit 100 converts the sound source signal DI1 into amplified signals DOXP and DOXN as sound signals, and outputs them to the sound reproduction device 3. Thus, the sound corresponding to the amplified signals DOXP and DOXN is output from the sound reproduction device 3. In addition, the sound source reproduction circuit 100 converts the sound source signal DI2 into amplified signals DOXPa and DOXNa as sound signals, and outputs them to the sound reproduction device 3a. Thus, the sound corresponding to the amplified signals DOXPa and DOXNa is output from the sound reproduction device 3a. For example, the sound reproduction devices 3 and 3a may be a speaker or a buzzer. In addition, the sound output from the sound reproduction devices 3 and 3a may be, for example, a sound obtained by imitating the sound of a person speaking, or various sounds such as a mechanical warning sound and an effect sound.

[0036] like Figure 1 As shown, in this embodiment, the sound source reproduction circuit 100 includes a modulation circuit 30 , switches 41 and 42 , and an amplifier circuit 50 .

[0037] The modulation circuit 30 receives the sound source signal DI1 as input, modulates the signal based on the sound source signal DI1, and outputs the modulation signals DOP and DON. The signal based on the sound source signal DI1 can be the sound source signal DI1 itself, or can be a signal after some processing is performed on the sound source signal DI1. In this embodiment, the modulation circuit 30 includes a digital filter 31, a Σ-Δ modulation circuit 32, and a pulse width modulation circuit 33.

[0038] The digital filter 31 is a low-pass filter that inputs the sound source signal DI1 and outputs a signal DF that reduces the high-frequency noise contained in the sound source signal DI1. The Σ-Δ modulation circuit 32 inputs the signal DF from the digital filter 31, oversamples the signal DF at a sampling ratio of n times to perform Σ-Δ modulation, thereby outputting a Σ-Δ modulated signal DS with noise biased toward the high-frequency band. n is an integer greater than 2. Therefore, when the sampling frequency of the sound source signal DI1 is fs, the sampling frequency of the signal DF output from the digital filter 31 is fs, and the sampling frequency of the Σ-Δ modulated signal DS is n×fs. The digital filter 31 functions as an anti-aliasing filter that reduces the high-frequency noise that is folded back into the signal band due to oversampling of the Σ-Δ modulation circuit 32.

[0039] The pulse width modulation circuit 33 performs pulse width modulation on the Σ-Δ modulation signal DS and outputs modulation signals DOP and DON. The modulation signals DOP and DON are 1-bit digital signals. When the sampling frequency of the Σ-Δ modulation signal DS is n×fs, the sampling frequency of the modulation signals DOP and DON is n×m×fs. Here, when the number of bits of the Σ-Δ modulation signal DS is M, m=2 M .

[0040] In this way, the modulation circuit 30 performs Σ-Δ modulation on the signal obtained by digitally filtering the sound source signal DI1 , and further performs pulse width modulation to output the modulation signals DOP and DON.

[0041] The pulse width modulation for generating the modulation signal DOP and the pulse width modulation for generating the modulation signal DON are different in manner. Figure 2 is a diagram showing an example of pulse width modulation for generating a modulation signal DOP. Figure 3 FIG. 1 is a diagram showing an example of pulse width modulation for generating the modulation signal DON. Figure 2 and Figure 3 This is an example of a case where the number of bits M of the Σ-Δ modulation signal DS is 4. Figure 2 and Figure 3 In the embodiment, the Σ-Δ modulation signal DS is updated with a period T as a cycle, and the modulation signals DOP and DON are high or low in each of the 16 intervals T1 to T16 obtained by dividing the period T. That is, the length of the period T is 1 / (n×fs), and the length of each of the intervals T1 to T16 is 1 / (n×m×fs).

[0042] like Figure 2 As shown, the modulation signal DOP is a Σ-Δ modulation signal DS, and the larger the value is, the longer the high level time is. For example, when the Σ-Δ modulation signal DS is "-7" in decimal, that is, "1001" in binary, one interval T1 of the modulation signal DOP is high, and 15 intervals T2 to T16 are low. In addition, for example, when the Σ-Δ modulation signal DS is "0" in decimal, that is, "0000" in binary, the modulation signal DOP is high in 8 intervals T1 to T8, and is low in 8 intervals T9 to T16. In addition, for example, when the Σ-Δ modulation signal DS is "7" in decimal, that is, "0111" in binary, the modulation signal DOP is high in 15 intervals T1 to T15, and is low in one interval T16.

[0043] like Figure 3 As shown, the modulation signal DON is a Σ-Δ modulation signal DS, and the time of high level is shorter as the value is larger. For example, when the Σ-Δ modulation signal DS is "-7" in decimal, that is, "1001" in binary, 15 intervals T1 to T15 of the modulation signal DON are high level, and one interval T16 is low level. In addition, for example, when the Σ-Δ modulation signal DS is "0" in decimal, that is, "0000" in binary, 8 intervals T1 to T8 of the modulation signal DON are high level, and 8 intervals T9 to T16 are low level. In addition, for example, when the Σ-Δ modulation signal DS is "7" in decimal, that is, "0111" in binary, one interval T1 of the modulation signal DON is high level, and 15 intervals T2 to T16 are low level.

[0044] Therefore, for example, when the Σ-Δ modulation signal DS is decimal "-7", "0", "7", the difference between the modulation signal DOP and the modulation signal DON is as follows: Figure 4 shown.

[0045] Back to Figure 1 As described above, the switch 41 outputs one of the modulation signal DOP and the modulation signal TP to the class D amplifier 51P of the amplifier circuit 50 according to the control signal output from the communication interface circuit 10. Specifically, the switch 41 outputs the modulation signal DOP to the class D amplifier 51P when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulation signal TP to the class D amplifier 51P when the operation mode of the semiconductor device 1 is the inspection mode.

[0046] In addition, the switch 42 outputs one of the modulation signal DON and the modulation signal TN to the class D amplifier 51N of the amplifier circuit 50 according to the control signal output from the communication interface circuit 10. Specifically, the switch 42 outputs the modulation signal DON to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulation signal TN to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the inspection mode.

[0047] The amplifier circuit 50 receives the modulation signals DOP and DON as input in the normal operation mode, and outputs the amplified signals DOXP and DOXN obtained by amplifying the modulation signals DOP and DON to the output terminals 91 and 92 of the semiconductor device 1. In addition, the amplifier circuit 50 receives the modulation signals TP and TN as input in the inspection mode, and outputs the amplified signals DOXP and DOXN obtained by amplifying the modulation signals TP and TN to the output terminals 91 and 92 of the semiconductor device 1.

[0048] In the present embodiment, the amplifier circuit 50 includes two class D amplifiers 51P and 51N. The class D amplifier 51P outputs an amplified signal DOXP after amplifying the modulation signal DOP to an output terminal 91 in the normal operation mode, and outputs an amplified signal DOXP after amplifying the modulation signal TP to an output terminal 91 in the test mode. The class D amplifier 51N outputs an amplified signal DOXN after amplifying the modulation signal DON to an output terminal 92 in the normal operation mode, and outputs an amplified signal DOXN after amplifying the modulation signal TN to an output terminal 92 in the test mode. The output terminal 91 is connected to the terminal P1 of the sound reproduction device 3, and the output terminal 92 is connected to the terminal P2 of the sound reproduction device 3. And the sound reproduction device 3 reproduces a sound of a magnitude corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN. It is preferable that the sound reproduction device 3 outputs a desired sound indicated by the sound source reproduction command in the normal operation mode, and outputs a small sound that is difficult for human ears to hear in the test mode. That is, it is preferable that the volume reproduced by the sound reproduction device 3 in the inspection mode is smaller than the minimum value of the volume reproduced by the sound reproduction device 3 in the normal operation mode. In other words, it is preferable that the voltage difference between the amplified signal DOXP and the amplified signal DOXN in the inspection mode is smaller than the voltage difference between the amplified signal DOXP and the amplified signal DOXN when the minimum sound is output from the sound reproduction device 3 in the normal operation mode. This makes it difficult for the user to realize that the semiconductor device 1 is operating in the inspection mode.

[0049] like Figure 1 As shown, the sound source reproduction circuit 100 further includes a modulation circuit 30a, switches 41a and 42a, and an amplifier circuit 50a.

[0050] The modulation circuit 30a receives the sound source signal DI2 as input, modulates the signal based on the sound source signal DI2, and outputs the modulation signals DOPa and DONa. The signal based on the sound source signal DI2 may be the sound source signal DI2 itself, or may be a signal obtained by performing some processing on the sound source signal DI2. In the present embodiment, the modulation circuit 30a includes a digital filter 31a, a Σ-Δ modulation circuit 32a, and a pulse width modulation circuit 33a.

[0051] The digital filter 31a is a low-pass filter that receives the sound source signal DI2 and outputs a signal DFa that reduces the high-frequency noise contained in the sound source signal DI2. The Σ-Δ modulation circuit 32a receives the signal DFa from the digital filter 31a, oversamples the signal DFa at a sampling ratio of n times to perform Σ-Δ modulation, and outputs a Σ-Δ modulated signal DSa with noise biased toward the high-frequency band. n is an integer greater than 2. Therefore, when the sampling frequency of the sound source signal DI2 is fs, the sampling frequency of the signal DFa output from the digital filter 31a is fs, and the sampling frequency of the Σ-Δ modulated signal DSa is n×fs. The digital filter 31a functions as an anti-aliasing filter that reduces the high-frequency noise that is folded back into the signal band due to oversampling of the Σ-Δ modulation circuit 32a.

[0052] The pulse width modulation circuit 33a performs pulse width modulation on the Σ-Δ modulation signal DSa and outputs modulation signals DOPa and DONa. The modulation signals DOPa and DONa are 1-bit digital signals. When the sampling frequency of the Σ-Δ modulation signal DSa is n×fs, the sampling frequency of the modulation signals DOPa and DONa is n×m×fs. Here, when the number of bits of the Σ-Δ modulation signal DSa is M, m=2 M .

[0053] In this way, the modulation circuit 30a performs Σ-Δ modulation on the signal obtained by digitally filtering the sound source signal DI2, and further performs pulse width modulation to output the modulation signals DOPa and DONa.

[0054] The pulse width modulation method for generating the modulation signals DOPa and DONa respectively Figure 2 to Figure 4 The pulse width modulation methods for generating the modulation signals DOP and DON are the same, so the description thereof is omitted.

[0055] The switch 41a outputs one of the modulation signal DOPa and the modulation signal TP to the class D amplifier 51Pa of the amplifier circuit 50a according to the control signal output from the communication interface circuit 10. Specifically, the switch 41a outputs the modulation signal DOPa to the class D amplifier 51Pa when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulation signal TP to the class D amplifier 51Pa when the operation mode of the semiconductor device 1 is the inspection mode.

[0056] In addition, the switch 42a outputs one of the modulation signal DONa and the modulation signal TN to the class D amplifier 51Na of the amplifier circuit 50a according to the control signal output from the communication interface circuit 10. Specifically, the switch 42a outputs the modulation signal DONa to the class D amplifier 51Na when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulation signal TN to the class D amplifier 51Na when the operation mode of the semiconductor device 1 is the inspection mode.

[0057] The amplifier circuit 50a receives the modulation signals DOPa and DONa as input in the normal operation mode, and outputs the amplified signals DOXPa and DOXNa after amplifying the modulation signals DOPa and DONa to the output terminals 93 and 94 of the semiconductor device 1. In addition, the amplifier circuit 50a receives the modulation signals TP and TN as input in the inspection mode, and outputs the amplified signals DOXPa and DOXNa after amplifying the modulation signals TP and TN to the output terminals 93 and 94 of the semiconductor device 1.

[0058] In the present embodiment, the amplifier circuit 50a includes two class D amplifiers 51Pa and 51Na. The class D amplifier 51Pa outputs an amplified signal DOXPa obtained by amplifying the modulation signal DOPa to an output terminal 93 in the normal operation mode, and outputs an amplified signal DOXPa obtained by amplifying the modulation signal TP to an output terminal 93 in the inspection mode. The class D amplifier 51Na outputs an amplified signal DOXNa obtained by amplifying the modulation signal DONa to an output terminal 94 in the normal operation mode, and outputs an amplified signal DOXNa obtained by amplifying the modulation signal TN to an output terminal 94 in the inspection mode. The output terminal 93 is connected to the terminal P1a of the sound reproduction device 3a, and the output terminal 94 is connected to the terminal P2a of the sound reproduction device 3a. The sound reproduction device 3a reproduces a sound of a magnitude corresponding to the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa. It is preferred that the sound reproduction device 3a outputs a desired sound indicated by the sound source reproduction command in the normal operation mode, and outputs a tiny sound that is difficult for human ears to hear in the inspection mode. That is, it is preferable that the volume reproduced by the sound reproduction device 3a in the inspection mode is smaller than the minimum value of the volume reproduced by the sound reproduction device 3a in the normal operation mode. In other words, it is preferable that the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa in the inspection mode is smaller than the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa when the minimum sound is output from the sound reproduction device 3a in the normal operation mode. This makes it difficult for the user to realize that the semiconductor device 1 is operating in the inspection mode.

[0059] The inspection circuit 110 is a circuit that inspects the sound reproducing device 3 .

[0060] Figure 5 3 is a diagram showing an example of the relationship between the state of a speaker and the impedance characteristics as an example of the sound reproduction device 3, 3a. Figure 5 In the figure, the horizontal axis is the frequency of the input signal of the speaker, and the vertical axis is the impedance value of the speaker. G1 is an example of the impedance characteristics of the speaker when it is normal. The frequency of the input signal at which the impedance of the speaker becomes a peak, that is, the peak frequency, varies depending on the type of speaker, but when the speaker is normal, it is at least included in the frequency band above 20Hz, the lower limit of the human audible range, and below 3kHz, the frequency used in the buzzer warning sound. G2 is an example of the impedance characteristics of the speaker when the magnet is broken and falls off. If the magnet of the speaker falls off, it becomes only a coil, so as it becomes a high-frequency band, the impedance value slowly rises and the peak frequency disappears. G3 is an example of the impedance characteristics of the speaker when the conical paper is broken. When the conical paper, which serves as the vibration surface of the speaker, is broken, no bass will appear, and the peak frequency will shift to the high-frequency band side.

[0061] Thus, the peak frequency changes depending on the state of the speaker. Therefore, in the present embodiment, in the test mode, the test circuit 110 detects the peak frequency f1 of the sound reproduction device 3, 3a. peak 、f2 peak , based on the detected peak frequency f1 peak 、f2 peak For example, if the sound reproduction devices 3 and 3a are the same type of speakers, if the sound reproduction devices 3 and 3a are normal, the peak frequency f1 peak 、f2 peak are basically consistent with each other, but if a failure occurs in either of the sound reproduction devices 3 and 3a, the peak frequency f1 peak 、f2 peak The difference between them becomes larger, so they do not match, so the inspection circuit 110 can determine the status of the sound reproduction devices 3 and 3a.

[0062] In this embodiment, the inspection circuit 110 includes a test signal generation circuit 60, a determination circuit 61, a memory 62, and peak frequency detection circuits 70, 70a. The test signal generation circuit 60, the determination circuit 61, and the peak frequency detection circuits 70, 70a operate in the inspection mode and stop in the normal operation mode.

[0063] The test signal generating circuit 60 modulates the test signal whose frequency is changed in a preset frequency band to generate modulation signals TP and TN. The frequency band in which the test signal generating circuit 60 changes the frequency of the test signal can be arbitrarily set by the microcontroller unit 2, for example, it can be a frequency band of 10 Hz or more and 3 kHz or less. In the present embodiment, the test signal generating circuit 60 performs pulse width modulation on the test signal to generate modulation signals TP and TN. The pulse width modulation method of the test signal generating circuit 60 is the same as the pulse width modulation method of the pulse width modulation circuits 33 and 33a.

[0064] The peak frequency detection circuit 70 measures the potential difference between the output terminal 91 and the output terminal 92, and detects the peak frequency f1 which is the frequency of the test signal at which the impedance of the sound reproduction device 3 reaches a peak value. peak In addition, the peak frequency detection circuit 70 also detects the peak voltage v1 peak , the peak voltage v1 peak It is a voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal is the peak frequency. As described later, the peak frequency f1 peak , peak voltage v1 peak Changes according to the temperature of the sound-reproducing device 3 .

[0065] The peak frequency detection circuit 70a measures the potential difference between the output terminal 93 and the output terminal 94, and detects the peak frequency f2 which is the frequency of the test signal at which the impedance of the sound reproduction device 3a reaches a peak value. peak In addition, the peak frequency detection circuit 70a also detects the peak voltage v2 peak , the peak voltage v2 peak It is the voltage obtained by amplifying the potential difference between the output terminal 93 and the output terminal 94 when the frequency of the test signal is the peak frequency. As described later, the peak frequency f2 peak , peak voltage v2 peak It changes according to the temperature of the sound-reproducing device 3a.

[0066] The determination circuit 61 determines the peak frequency f1 detected by the peak frequency detection circuit 70. peak The peak frequency f2 detected by the peak frequency detection circuit 70a peak The reference frequency difference range is a frequency range determined based on the difference in peak frequencies of the sound reproduction devices 3 and 3a, the temperature characteristics of the peak frequencies, etc. In addition, the determination circuit 61 further determines whether the peak voltage v1 detected by the peak frequency detection circuit 70 is within the specified reference frequency difference range. peak The peak voltage v2 detected by the peak frequency detection circuit 70a peakThe reference voltage difference range is a voltage range determined based on the difference in peak impedance of the sound reproduction devices 3 and 3a, the temperature characteristics of the peak impedance, etc. In addition, in this embodiment, the determination circuit 61 determines whether the peak frequency f1 is within a predetermined reference voltage difference range. peak With peak frequency f2 peak The result of the determination of whether the difference is included in the reference frequency difference range, the peak voltage v1 peak With the peak voltage v2 peak The state of the sound reproduction device 3, 3a, such as whether the sound reproduction device 3, 3a has a fault, is determined based on the determination result of whether the difference is included in the reference voltage difference range. In addition, the details of the processing of the determination circuit 61 will be described later.

[0067] The memory 62 includes a non-volatile memory (not shown), and constants α and β are stored in the non-volatile memory. The constant α is a constant for determining the aforementioned reference frequency difference range in consideration of characteristic deviations, temperature differences, etc. between the sound reproduction devices 3 and 3a, and β is a constant for determining the aforementioned reference voltage difference range in consideration of characteristic deviations, temperature differences, etc. between the sound reproduction devices 3 and 3a. In addition, the memory 62 includes a non-volatile memory (not shown) for storing various temporarily generated data.

[0068] The switch 81 switches whether to electrically connect or disconnect the output terminal 91 of the semiconductor device 1 and the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. Specifically, the switch 81 electrically disconnects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode.

[0069] Similarly, the switch 82 switches whether to electrically connect or disconnect the output terminal 92 of the semiconductor device 1 and the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. Specifically, the switch 82 electrically disconnects the output terminal 92 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 92 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode.

[0070] Thus, the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91 and 92 by switches 81 and 82 in the normal operation mode, and is electrically connected to the output terminals 91 and 92 in the inspection mode, and measures the potential difference between the output terminals 91 and 92 to detect the peak frequency f1. peak And the peak voltage v1 peak .

[0071] The switch 81a switches whether to electrically connect or disconnect the output terminal 93 of the semiconductor device 1 and the peak frequency detection circuit 70a according to the control signal output from the communication interface circuit 10. Specifically, the switch 81a electrically disconnects the output terminal 93 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 93 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the inspection mode.

[0072] Similarly, the switch 82a switches whether to electrically connect or disconnect the output terminal 94 of the semiconductor device 1 and the peak frequency detection circuit 70a according to the control signal output from the communication interface circuit 10. Specifically, the switch 82a electrically disconnects the output terminal 94 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 94 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the inspection mode.

[0073] In this way, the peak frequency detection circuit 70a is electrically disconnected from the output terminals 93 and 94 through the switches 81a and 82a in the normal operation mode, and is electrically connected to the output terminals 93 and 94 in the inspection mode, and measures the potential difference between the output terminals 93 and 94 to detect the peak frequency f2. peak And the peak voltage v2 peak .

[0074] When receiving a command to read the information of the determination result of the determination circuit 61 from the micro control unit 2, the communication interface circuit 10 obtains the information of the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 can recognize the state of the sound reproduction device 3, 3a based on the information of the determination result and perform various processes corresponding to the state of the sound reproduction device 3, 3a.

[0075] 1-1-2. Status determination of sound reproduction device

[0076] Figure 6 and Figure 7 1 is a diagram showing a configuration example of class D amplifiers 51P and 51N, a peak frequency detection circuit 70, and peripheral circuits thereof. Figure 6 Indicates the structure in normal operation mode. Figure 7 Represents a structure in inspection mode.

[0077] like Figure 6 as well as Figure 7As shown, the class D amplifier 51P has a plurality of inverter circuits 201-1 to 201-n, and the class D amplifier 51N has a plurality of inverter circuits 202-1 to 202-n. n is an integer greater than 2, and can be, for example, about 10 to 100. The inverter circuits 201-1 to 201-n are respectively composed of a pair of PMOS transistors and an NMOS transistor, and the node where the drain of the PMOS transistor is connected to the drain of the NMOS transistor, i.e., the output terminal, is connected to the output terminal 91. Similarly, the inverter circuits 202-1 to 202-n are respectively composed of a pair of PMOS transistors and an NMOS transistor, and the node where the drain of the PMOS transistor is connected to the drain of the NMOS transistor, i.e., the output terminal, is connected to the output terminal 92.

[0078] like Figure 6 As shown, in the normal operation mode, the modulation signal DOP is input to each input terminal of the inverter circuits 201-1 to 201-n of the class D amplifier 51P via the switch 41, and the modulation signal DON is input to each input terminal of the inverter circuits 202-1 to 202-n of the class D amplifier 51N via the switch 42. That is, in the normal operation mode, the inverter circuits 201-1 to 201-n of the class D amplifier 51P are connected in parallel between the modulation circuit 30 and the output terminal 91 of the semiconductor device 1, and the inverter circuits 202-1 to 202-n of the class D amplifier 51N are connected in parallel between the modulation circuit 30 and the output terminal 92 of the semiconductor device 1. As a result, the on-resistance R1 of the class D amplifier 51P is increased. onP The on-resistance R1 of the class D amplifier 51N is 1 / n of the on-resistance of the inverter circuit 201-1. onN This becomes 1 / n of the on-resistance of the inverter circuit 202 - 1 .

[0079] Then, the amplifier circuit 50 outputs the amplified signal DOXP obtained by amplifying the modulation signal DOP to the output terminal 91, and outputs the amplified signal DOXN obtained by amplifying the modulation signal DON to the output terminal 92. The output terminals 91 and 92 are connected to the terminals P1 and P2 of the sound reproduction device 3, respectively. The impedance R1 between the terminals P1 and P2 is sp For example, the on-resistance R1 of the class D amplifier 51P is 4Ω to 128Ω. onP and the on-resistance R1 of the class D amplifier 51N onN is the impedance R1 of the sound reproduction device 3 sp About 1 / 10 to 1 / 100 of the original.

[0080] In addition, if Figure 6 As shown, in the normal operation mode, the switches 81 and 82 are non-conductive, and the peak frequency detection circuit 70 and the output terminals 91 and 92 of the semiconductor device 1 are electrically disconnected.

[0081] On the other hand, Figure 7 As shown, in the test mode, the modulation signal TP is input to each input terminal of a part of the inverter circuits 201-1 to 201-n of the class D amplifier 51P via the switch 41, and each output terminal of another part of the inverter circuits of the inverter circuits 201-1 to 201-n becomes high impedance. For example, in the test mode, the modulation signal TP is input to the input terminal of the inverter circuit 201-1, and each output terminal of the inverter circuits 201-2 to 201-n becomes high impedance. Similarly, the modulation signal TN is input to each input terminal of a part of the inverter circuits 202-1 to 202-n of the class D amplifier 51N via the switch 42, and each output terminal of another part of the inverter circuits of the inverter circuits 202-1 to 202-n becomes high impedance. For example, in the test mode, the modulation signal TN is input to the input terminal of the inverter circuit 202-1, and the output terminals of the inverter circuits 202-2 to 202-n become high impedance. Therefore, for example, the on-resistance R1 of the class D amplifier 51P is onP and the on-resistance R1 of the class D amplifier 51N onN With impedance R1 sp About the same.

[0082] In addition, if Figure 7 As shown, in the inspection mode, the switches 81 and 82 are turned on, and the peak frequency detection circuit 70 is electrically connected to the output terminals 91 and 92 of the semiconductor device 1 .

[0083] The peak frequency detection circuit 70 includes a differential low-pass filter 71 , an A / D conversion circuit 72 , and a peak time measurement circuit 73 .

[0084] The differential low-pass filter 71 receives the voltage of the output terminal 91 and the voltage of the output terminal 92 via the switch 81 and the switch 82 in the inspection mode. That is, the differential low-pass filter 71 receives the amplified signals DOXP and DOXN, reduces the noise components of the high frequency band superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference between the amplified signals DOXP and DOXN. The cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the test signal generating circuit 60 changes the frequency of the test signal. For example, when the test signal generating circuit 60 changes the frequency of the test signal in a frequency band above 10 Hz and below 3 kHz, the cutoff frequency of the differential low-pass filter 71 is higher than 3 kHz. Since the cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, the frequency components contained in the frequency band are not attenuated by the differential low-pass filter 71.

[0085] Figure 8 71 is a diagram showing a configuration example of a differential low-pass filter. Figure 8 As shown, the differential low-pass filter 71 includes an operational amplifier 211 , five resistors 212 , 213 , 214 , 216 , 218 , and three capacitors 215 , 217 , 219 .

[0086] In the inspection mode, the amplified signal DOXP output to the output terminal 91 of the semiconductor device 1 is input to one end of the resistor 212. In addition, the amplified signal DOXN output to the output terminal 92 of the semiconductor device 1 is input to one end of the resistor 213. The other end of the resistor 212, one end of the resistor 214, and one end of the capacitor 215 are connected to the non-inverting input terminal of the operational amplifier 211. The other end of the resistor 213, one end of the resistor 216, one end of the capacitor 217, one end of the resistor 218, and one end of the capacitor 219 are connected to the inverting input terminal of the operational amplifier 211.

[0087] The other end of the resistor 214 and the other end of the capacitor 215 are connected to the output terminal of the operational amplifier 211. The other end of the resistor 216 and the other end of the capacitor 217 are grounded, and the other end of the resistor 218 and the other end of the capacitor 219 are supplied with a power supply voltage.

[0088] The differential low-pass filter 71 configured in this way reduces the high-frequency noise component superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference of the amplified signals DOXP and DOXN, that is, the potential difference between the output terminal 91 and the output terminal 92, from the output terminal of the operational amplifier 211. When the power supply voltage is VDD and the ground voltage is 0V, when the potential difference between the output terminal 91 and the output terminal 92, which reduces the high-frequency noise component, is positive, the voltage V' is higher than VDD×1 / 2, and when the potential difference between the output terminal 91 and the output terminal 92, which reduces the high-frequency noise component, is negative, the voltage V' is lower than VDD×1 / 2.

[0089] Furthermore, the amplitude voltage V'(pp) of the voltage V' and the impedance R1 of the sound reproduction device 3 sp , the on-resistance R1 of the class D amplifier 51P onP and the on-resistance R1 of the class D amplifier 51N onN There is a relationship as shown in formula (1). According to formula (1), the impedance R1 sp The larger the voltage V', the greater the amplitude, so the impedance R1 sp When it reaches the peak value, the amplitude of the voltage V' is maximum.

[0090]

[0091] return Figure 7As described above, the A / D conversion circuit 72 converts the output voltage V' of the differential low-pass filter 71 into an m-bit digital signal and outputs it as an m-bit data DT. m is an integer greater than 2. The integer m is set to an appropriate value according to the requirements of the detection accuracy of the peak frequency, the size of the peak frequency detection circuit 70, etc.

[0092] The peak time measurement circuit 73 measures the peak time, which is the time when the potential difference between the output terminal 91 and the output terminal 92 becomes the maximum, based on the data DT, which is the output signal of the A / D conversion circuit 72. Specifically, the peak time measurement circuit 73 measures the time when the data DT becomes the maximum as the peak time. In addition, the peak time measurement circuit 73 measures the output voltage V' of the differential low-pass filter 71 at the peak time as the peak voltage. Specifically, the peak time measurement circuit 73 measures the maximum value of the data DT as the peak voltage.

[0093] As described above, when the impedance R1 of the sound reproduction device 3 sp When the impedance R1 of the sound reproduction device 3 is at its maximum sp When the impedance R1 is at its peak value, the amplitude of the voltage V' is maximum. sp The peak impedance R1 peak When the potential difference between the output terminal 91 and the output terminal 92 is the largest. Since the frequency of the test signal changes sequentially at a predetermined timing, the impedance R1 of the sound reproduction device 3 is uniquely determined based on the peak time measured by the peak time measurement circuit 73. sp The peak impedance R1 peak Thus, the peak frequency detection circuit 70 detects the peak frequency by measuring the peak time, which is the time when the potential difference between the output terminal 91 and the output terminal 92 is the largest, in the inspection mode. In addition, the peak frequency detection circuit 70 also detects the peak voltage, which is the voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal is the peak frequency, in the inspection mode.

[0094] Fig. 9 It represents the test signal in the inspection mode and the peak frequency f1 peak And the peak voltage v1 peak A diagram showing an example of the relationship between . Fig. 9 In the example of FIG. 1 , the test signal generating circuit 60 continuously changes the frequency of the test signal in a frequency band of 10 Hz to 3 kHz while maintaining the amplitude of the test signal at a constant voltage V1. When the sound reproduction device 3 is normal, the peak frequency f1 of the test signal is peak , the output voltage V' of the differential low-pass filter 71 becomes the peak voltage v1 peakOn the other hand, when a failure occurs in the sound reproduction device 3, although not shown in the figure, the peak frequency f1 peak , peak voltage v1 peak In addition, if Fig. 9 As shown, when a disconnection occurs between the semiconductor device 1 and the sound reproduction device 3, the output voltage V' of the differential low-pass filter 71 is fixed to the power supply voltage. peak The predetermined voltage which is higher than the power supply voltage of the differential low-pass filter 71 is V err When the output voltage V' of the differential low-pass filter 71 is greater than the voltage V err High, that is, the data DT ratio and voltage V err When the corresponding digital value is large, it can be determined as a disconnection fault.

[0095] like Fig.10 As shown, the peak impedance R1 peak , peak frequency f1 peak The higher the temperature of the sound reproduction device 3, the higher the impedance R1 sp The larger the impedance R1, the lower the temperature of the sound reproduction device 3. sp For example, if the temperature range for ensuring the operation of the sound reproduction device 3 is -40°C to 80°C, the peak impedance R1 at a high temperature of 80°C is peak _ High Greater than the peak impedance R1 at room temperature such as 25°C peak _ Nor In addition, the peak impedance R1 at low temperatures such as -40°C peak _ Low Peak impedance R1 at room temperature, such as 25°C peak _ Nor .like Fig.10 As shown, the higher the temperature of the sound reproduction device 3 is, the higher the peak frequency f1 is. peak The lower the temperature of the sound reproduction device 3, the lower the peak frequency f1 peak Therefore, the peak frequency f1 at high temperatures such as 80°C peak _ High Peak frequency f1 at room temperature, such as lower than 25°C peak _ Nor In addition, the peak frequency f1 at low temperatures such as -40°C peak _ Low Higher than the peak frequency f1 at normal temperature such as 25°C peak _ Nor .

[0096] Peak impedance R1 peak , peak frequency f1peak Varies with temperature, so Fig.11 As shown, the waveform of the output voltage V' of the differential low-pass filter 71 also changes according to the temperature.

[0097] In addition, the structures of the class D amplifiers 51Pa, 51Na, the peak frequency detection circuit 70a and its peripheral circuits are similar to those of Figure 6 as well as Figure 7 That is, the peak frequency detection circuit 70a includes a differential low-pass filter 71, an A / D conversion circuit 72, and a peak time measurement circuit 73, similarly to the peak frequency detection circuit 70. In addition, the structure of the differential low-pass filter 71 included in the peak frequency detection circuit 70a is similar to that of the peak frequency detection circuit 70. Figure 8 In addition, the test signal in the inspection mode is similar to the peak frequency f2. peak and peak voltage v2 peak The relationship with Fig. 9 The peak impedance R2 of the sound reproduction device 3a is the same as that of the sound reproduction device 3a, so the illustration and description thereof are omitted. peak , peak frequency f2 peak The temperature dependence of Fig.10 In addition, the temperature dependence of the waveform of the output voltage V' of the differential low-pass filter 71 included in the peak frequency detection circuit 70a is similar to Fig.11 The same, therefore, the illustration and description are omitted.

[0098] Here, when both the sound reproduction devices 3 and 3a are normal, the peak frequency f1 peak 、f2 peak Therefore, when the temperature of the sound reproduction devices 3 and 3a changes in the same manner, the peak frequency f1 peak , peak frequency f2 peak Therefore, the determination circuit 61 determines that the peak frequency f1 detected by the peak frequency detection circuit 70 is peak The peak frequency f2 detected by the peak frequency detection circuit 70a peak The difference is contained in the specified reference frequency difference range.

[0099] Similarly, when both the sound reproduction devices 3 and 3a are normal, the peak impedance R1 peak , R2 peak Therefore, when the temperature of the sound reproduction devices 3 and 3a changes in the same manner, the peak impedance R1 peak With peak impedance R2 peak Therefore, the determination circuit 61 determines that the peak voltage v1 detected by the peak frequency detection circuit 70 ispeak The peak voltage v2 detected by the peak frequency detection circuit 70a peak Whether the difference is contained in the specified reference voltage difference range.

[0100] 1-1-3. Processing of inspection mode

[0101] In this embodiment, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the inspection mode from the micro control unit 2, the operation mode of the semiconductor device 1 is switched to the inspection mode. Alternatively, when the power supply voltage starts to be supplied to the semiconductor device 1, the operation mode of the semiconductor device 1 is automatically switched to the inspection mode. Furthermore, the inspection circuit 110 performs a predetermined process in the inspection mode.

[0102] Fig.12 This is a flowchart showing an example of the processing procedure of the inspection circuit 110 in the inspection mode.

[0103] First, in step S1, the determination circuit 61 sets constants α and β. The constant α is a constant for determining the aforementioned reference frequency difference range in consideration of characteristic variations, temperature differences, etc. of the sound reproduction devices 3 and 3a, and β is a constant for determining the aforementioned reference voltage difference range in consideration of characteristic variations, temperature differences, etc. of the sound reproduction devices 3 and 3a. As described above, the constants α and β are stored in the nonvolatile memory of the memory 62, and the determination circuit 61 reads the constants α and β from the nonvolatile memory and sets them in a predetermined internal register.

[0104] Next, in step S2, the test signal generation circuit 60 starts to output a test signal obtained by sweeping the frequency. In step S3, the determination circuit 61 obtains the peak frequency f1. peak , peak voltage v1 peak In step S4, the determination circuit 61 obtains the peak frequency f2 peak , peak voltage v2 peak .

[0105] Next, in step S5, the determination circuit 61 determines whether the peak voltage v1 obtained in steps S3 and S4 is peak 、v2 peak Are they both higher than the voltage V err When the peak voltage v1 peak 、v2 peak Both are higher than the voltage V err When , in step S6 , the determination circuit 61 determines that both the sound reproduction devices 3 and 3 a have failed, and ends the processing in the inspection mode.

[0106] On the other hand, at the peak voltage v1 peak 、v2peak Any one of the voltages V err In the following case, in step S7, the determination circuit 61 determines that the peak voltage v1 peak Is it higher than the voltage V err At the peak voltage v1 peak Higher than the voltage V err In the case of the above, in step S8, the determination circuit 61 determines that a failure has occurred in the sound reproduction device 3, and the processing in the inspection mode ends.

[0107] On the other hand, when the peak voltage v1 peak is the voltage V err When the peak voltage v2 is less than 2, in step S9, the determination circuit 61 determines that the peak voltage v2 peak Is it higher than the voltage V err When the peak voltage v2 peak Higher than the voltage V err , in step S10, the determination circuit 61 determines that a failure has occurred in the sound reproduction device 3a, and ends the processing in the inspection mode.

[0108] On the other hand, at the peak voltage v2 peak is the voltage V err In the following case, in step S11, the determination circuit 61 determines whether the peak frequency f1 obtained in step S3 is peak The peak frequency f2 obtained in step S4 peak Is the difference within the range higher than -α and lower than +α, that is, the reference frequency difference range? peak With peak frequency f2 peak When the difference is not included in the reference frequency difference range, in step S13, the determination circuit 61 determines that there is a possibility of failure in either the sound reproduction device 3 or 3a, and ends the processing in the inspection mode.

[0109] On the other hand, at the peak frequency f1 peak With peak frequency f2 peak If the difference is within the reference frequency difference range, in step S12, the determination circuit 61 determines that the peak voltage v1 obtained in step S3 is peak The peak voltage v2 obtained in step S4 peak Is the difference within the range higher than -β and lower than +β, that is, the reference voltage difference range? peak With the peak voltage v2 peak If the difference between the peak voltage v1 and the peak voltage v2 is not within the reference voltage difference range, in step S13, the determination circuit 61 determines that either the sound reproduction device 3 or 3a may be faulty, and ends the processing in the inspection mode. peakand peak voltage v2 peak When the difference is included in the reference voltage difference range, in step S14, the determination circuit 61 determines that both the sound reproduction devices 3 and 3a are normal, and ends the processing in the inspection mode.

[0110] Furthermore, the sound reproduction device 3 is an example of a “first sound reproduction device”, the terminal P1 of the sound reproduction device 3 is an example of a “first terminal of the first sound reproduction device”, and the terminal P2 of the sound reproduction device 3 is an example of a “second terminal of the first sound reproduction device”. Furthermore, the sound reproduction device 3a is an example of a “second sound reproduction device”, the terminal P1a of the sound reproduction device 3a is an example of a “first terminal of the second sound reproduction device”, and the terminal P2a of the sound reproduction device 3a is an example of a “second terminal of the second sound reproduction device”. Furthermore, the output terminal 91 of the semiconductor device 1 is an example of a “first output terminal”, and the output terminal 92 of the semiconductor device 1 is an example of a “second output terminal”. Furthermore, the output terminal 93 of the semiconductor device 1 is an example of a “third output terminal”, and the output terminal 94 of the semiconductor device 1 is an example of a “fourth output terminal”. Furthermore, the sound source signal DI1 is an example of a “first sound source signal”, and the sound source signal DI2 is an example of a “second sound source signal”. In addition, the modulation circuit 30 is an example of the “first modulation circuit”, the modulation signal DOP is an example of the “first modulation signal”, and the modulation signal DON is an example of the “second modulation signal”. In addition, the modulation circuit 30a is an example of the “second modulation circuit”, the modulation signal DOPa is an example of the “third modulation signal”, and the modulation signal DONa is an example of the “fourth modulation signal”. In addition, the modulation signal TP is an example of the “fifth modulation signal”, and the modulation signal TN is an example of the “sixth modulation signal”. In addition, the amplifier circuit 50 is an example of the “first amplifier circuit”, the amplified signal DOXP obtained by amplifying the modulation signal DOP is an example of the “first amplified signal”, the amplified signal DOXN obtained by amplifying the modulation signal DON is an example of the “second amplified signal”, the amplified signal DOXP obtained by amplifying the modulation signal TP is an example of the “third amplified signal”, and the amplified signal DOXN obtained by amplifying the modulation signal TN is an example of the “fourth amplified signal”. In addition, the amplifier circuit 50a is an example of the “second amplifier circuit”, the amplified signal DOXPa after the modulation signal DOPa is amplified is an example of the “fifth amplified signal”, the amplified signal DOXNa after the modulation signal DONa is amplified is an example of the “sixth amplified signal”, the amplified signal DOXPa after the modulation signal TP is amplified is an example of the “seventh amplified signal”, and the amplified signal DOXNa after the modulation signal TN is amplified is an example of the “eighth amplified signal”. In addition, the peak frequency detection circuit 70 is an example of the “first peak frequency detection circuit”, and the peak frequency f1 peak This is an example of the "1st peak frequency", the peak voltage v1peak is an example of a "first peak voltage". In addition, the peak frequency detection circuit 70a is an example of a "second peak frequency detection circuit", and the peak frequency f2 peak This is an example of the "second peak frequency", the peak voltage v2 peak It is an example of the “second peak voltage”. In addition, the differential low-pass filter 71, the A / D conversion circuit 72, and the peak time measurement circuit 73 included in the peak frequency detection circuit 70 are examples of the “first differential low-pass filter”, the “first A / D conversion circuit”, and the “first peak time measurement circuit”, respectively. In addition, the differential low-pass filter 71, the A / D conversion circuit 72, and the peak time measurement circuit 73 included in the peak frequency detection circuit 70a are examples of the “second differential low-pass filter”, the “second A / D conversion circuit”, and the “second peak time measurement circuit”, respectively. In addition, the normal operation mode is an example of the “first operation mode”, and the inspection mode is an example of the “second operation mode”.

[0111] The semiconductor device 1 of the present embodiment is configured to enable two sound-reproducing devices 3 and 3 a to output sound, but may be configured to enable three or more sound-reproducing devices to output sound.

[0112] 1-1-4. Effects

[0113] As described above, according to the semiconductor device 1 of the present embodiment, in the normal operation mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN after respectively amplifying the modulation signals DOP and DON based on the sound source signal DI1 to the output terminals 91 and 92, thereby enabling the sound reproduction device 3 to reproduce the sound. In addition, in the normal operation mode, the amplifier circuit 50a outputs the amplified signals DOXPa and DOXNa after respectively amplifying the modulation signals DOPa and DONa based on the sound source signal DI2 to the output terminals 93 and 94, thereby enabling the sound reproduction device 3a to reproduce the sound. On the other hand, in the inspection mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN after respectively amplifying the modulation signals TP and TN based on the test signal to the output terminals 91 and 92, thereby enabling the peak frequency detection circuit 70 to measure the potential difference between the output terminal 91 and the output terminal 92, and detect the peak frequency f1 at which the impedance of the sound reproduction device 3 reaches a peak. peak In the inspection mode, the amplifier circuit 50a outputs the amplified signals DOXPa and DOXNa, which are respectively amplified by the modulation signals TP and TN based on the test signal, to the output terminals 93 and 94, thereby the peak frequency detection circuit 70a measures the potential difference between the output terminal 93 and the output terminal 94, and can detect the peak frequency f2 at which the impedance of the sound reproduction device 3a reaches a peak value. peakWhen the temperatures of the sound reproduction devices 3 and 3a change in the same manner, the peak frequency f1 peak 、f2 peak The difference between them is almost constant regardless of temperature. As a result, if both the sound reproduction devices 3 and 3a are normal, even if the peak frequency f1 peak 、f2 peak The difference between them is also within the specified reference frequency difference range. Therefore, the determination circuit 61 determines that the peak frequency f1 peak With peak frequency f2 peak For example, if the difference is not within the reference frequency difference range, it can be determined that either of the sound reproduction devices 3 and 3a may have a fault. Therefore, according to the semiconductor device 1 of this embodiment, even if the temperature changes, the accuracy of the fault determination of the sound reproduction devices 3 and 3a can be maintained.

[0114] In the semiconductor device 1 of the present embodiment, the amplifier circuit 50 is used for generating the amplified signals DOXP and DOXN for causing the sound reproducing device 3 to reproduce the sound in the normal operation mode and for generating the peak frequency f1 in the test mode. peak Similarly, the amplifier circuit 50a is used for generating the amplified signals DOXPa and DOXNa for causing the sound reproduction device 3a to reproduce the sound in the normal operation mode and for generating the peak frequency f2 in the inspection mode. peak Therefore, according to the semiconductor device 1 of this embodiment, it is possible to generate a signal necessary for detecting a failure of the sound reproducing device 3 or 3a by a small-scale circuit.

[0115] In the semiconductor device 1 of the present embodiment, when the temperatures of the sound reproducing devices 3 and 3a change in the same manner, the peak voltage v1 peak 、v2 peak The difference between them is almost constant regardless of temperature. As a result, if both the sound reproduction devices 3 and 3a are normal, even if the peak voltage v1 peak 、v2 peak The difference between them is also included in the specified reference voltage difference range. Therefore, the determination circuit 61 determines that the peak voltage v1 peak With the peak voltage v2 peakThe determination circuit 61 determines whether the difference is within a predetermined reference voltage difference range. For example, if the difference is not within the reference voltage difference range, the determination circuit 61 can determine that either of the sound reproduction devices 3 and 3a may have a fault. Therefore, according to the semiconductor device 1 of this embodiment, the possibility of erroneously determining that both the sound reproduction devices 3 and 3a are normal can be reduced when either of the sound reproduction devices 3 and 3a may have a fault.

[0116] According to the semiconductor device 1 of the present embodiment, the impedance R1 of the sound reproduction device 3 is sp When the potential difference between the output terminal 91 and the output terminal 92 reaches a peak value, the peak frequency detection circuit 70 can detect the peak frequency f1 by measuring the time when the potential difference between the output terminal 91 and the output terminal 92 reaches a maximum value. peak Similarly, the impedance R2 of the sound reproduction device 3a sp When the potential difference between the output terminal 93 and the output terminal 94 reaches a peak value, the peak frequency detection circuit 70a can detect the peak frequency f2 by measuring the time when the potential difference between the output terminal 93 and the output terminal 94 reaches a maximum. peak .

[0117] In addition, according to the semiconductor device 1 of the present embodiment, in each peak frequency detection circuit 70, 70a, the differential low-pass filter 71 reduces the noise component of the high-frequency band superimposed on the amplified signals DOXP, DOXN by modulating the test signal, the A / D conversion circuit 72 converts the output voltage of the differential low-pass filter 71 into data DT, and the peak time measurement circuit 73 can easily perform high-precision measurement.

[0118] Furthermore, according to the semiconductor device 1 of the present embodiment, the impedance R1 of the sound reproduction device 3 is sp The impedance R2 of the sound reproduction device 3a is independent of the voltage of the amplified signals DOXP and DOXN. sp Since the peak frequency f1 is not dependent on the voltage of the amplified signals DOXPa and DOXNa, the peak frequency f1 can be detected in the test mode when the sound reproduction device 3 or 3a reproduces a very small sound that is difficult for human ears to hear. peak 、f2 peak And the peak voltage v1 peak 、v2 peak Therefore, according to the semiconductor device 1 of the present embodiment, it is possible to make it difficult for the user to be aware that the semiconductor device 1 is operating in the inspection mode.

[0119] 1-2. Modifications

[0120] In the above embodiment, the peak frequency detection circuit 70 detects the peak frequency f1 peakAnd the peak voltage v1 peak , the peak frequency detection circuit 70a detects the peak frequency f2 peak and peak voltage v2 peak , but the peak frequency detection circuit 70 can also perform peak frequency f1 in time division peak And the peak voltage v1 peak Detection and peak frequency f2 peak and peak voltage v2 peak In this case, the peak frequency detection circuit 70a is not required. For example, in the inspection mode, first, the test signal generation circuit 60 outputs a test signal obtained by scanning the frequency, and the peak frequency detection circuit 70 detects the peak frequency f1. peak And the peak voltage v1 peak Next, the test signal generation circuit 60 outputs the test signal obtained by scanning the frequency again, and the peak frequency detection circuit 70 detects the peak frequency f2 peak and peak voltage v2 peak .

[0121] In the above-mentioned embodiment, the memory 20 storing the sound source data 21-1 to 21-n is built into the semiconductor device 1, but instead of the memory 20, an external memory storing the sound source data 21-1 to 21-n may be connected to the semiconductor device 1, and the semiconductor device 1 reads the sound source data 21-i as the sound source signal DI1 and the sound source data 21-j as the sound source signal DI2 from the external memory. Alternatively, instead of the memory 20, the microcontroller 2 may have a built-in memory storing the sound source data 21-1 to 21-n, and the microcontroller 2 may read the sound source data 21-i and 21-j from the memory and send them to the semiconductor device 1 as the sound source signals DI1 and DI2, respectively.

[0122] In addition, in the above-mentioned embodiment, as the modulation method of the pulse width modulation circuit 33, Figure 2 to Figure 4 For example, the pulse width modulation used to generate the modulation signal DOP can be the same as Figure 2 In the same way, the pulse width modulation for generating the modulation signal DON can be Fig.13 In the manner shown. Fig.13 In the example, the modulation signal DON is Figure 2The signal after the logic level of the modulation signal DOP shown is inverted, the larger the value of the Σ-Δ modulation signal DS is, the shorter the time of the high level is. For example, when the Σ-Δ modulation signal DS is "-7" in decimal, that is, "1001" in binary, one interval T1 of the modulation signal DON is a low level, and 15 intervals T2 to T16 are high levels. In addition, for example, when the Σ-Δ modulation signal DS is "0" in decimal, that is, "0000" in binary, 8 intervals T1 to T8 of the modulation signal DON are low levels, and 8 intervals T9 to T16 are high levels. In addition, for example, when the Σ-Δ modulation signal DS is "7" in decimal, that is, "0111" in binary, 15 intervals T1 to T15 of the modulation signal DON are low levels, and one interval T16 is a high level. Therefore, for example, when the Σ-Δ modulation signal DS is "-7", "0", and "7" in decimal, the difference between the modulation signal DOP and the modulation signal DON is as follows: Fig.14 In addition, the pulse width modulation used to generate the modulation signal DONa can also be Fig.13 The method shown.

[0123] 2. Electronic devices

[0124] Fig.15 1 is a functional block diagram showing an example of the configuration of an electronic device according to this embodiment using the semiconductor device 1 according to this embodiment.

[0125] like Fig.15 As shown, the electronic device 300 of this embodiment includes a semiconductor device 1, m sound reproduction devices 3-1 to 3-m, a processing unit 310, an operation unit 320, a storage unit 330, and a display unit 340. In addition, the electronic device 300 of this embodiment may be configured to omit or change Fig.15 part of the structural elements, or adding other structural elements.

[0126] The processing unit 310 performs control processing of each unit of the electronic device 300 and various data processing. For example, the processing unit 310 sends various commands to the semiconductor device 1 to control the operation of the semiconductor device 1. In addition, the processing unit 310 performs various processing corresponding to the operation signal from the operation unit 320, and performs processing of sending display signals for causing the display unit 340 to display various information. For example, the processing unit 310 may also be the aforementioned micro control unit 2.

[0127] The operation unit 320 is an input device composed of operation keys, push button switches, etc., and outputs an operation signal corresponding to the user's operation to the processing unit 310.

[0128] The storage unit 330 stores programs and data for the processing unit 310 to perform various calculations and control processes. The storage unit 330 is implemented by, for example, a hard disk, a floppy disk, MO, MT, various memories, CD-ROM, DVD-ROM, or the like.

[0129] The display unit 340 is a display device composed of an LCD or the like, and displays various information based on an input display signal. LCD is an abbreviation of Liquid Crystal Display. The display unit 340 may also be provided with a touch panel that functions as the operation unit 320.

[0130] In the normal operation mode, the semiconductor device 1 generates a plurality of sound signals based on various commands sent from the processing unit 310, and outputs the sound signals to the sound reproduction devices 3-1 and 3-2. Therefore, desired sounds are output from the sound reproduction devices 3-1 and 3-2. The sound reproduction device 3-1 corresponds to the above-mentioned sound reproduction device 3, and the sound reproduction device 3-2 corresponds to the above-mentioned sound reproduction device 3a. In addition, in the inspection mode, the semiconductor device 1 outputs the amplified signals DOXP and DOXN based on the test signal to the sound reproduction device 3-1, and outputs the amplified signals DOXPa and DOXNa based on the test signal to the sound reproduction device 3-2. Thus, sounds are output from the sound reproduction devices 3-1 and 3-2, and therefore, it is preferable to output a small sound that is difficult for human ears to hear. That is, it is preferable that the volume reproduced by the sound reproduction devices 3-1 and 3-2 in the inspection mode is smaller than the minimum value of the volume reproduced by the sound reproduction devices 3-1 and 3-2 in the normal operation mode. Thus, it is possible to make it difficult for the user to realize that the semiconductor device 1 is operating in the inspection mode. Furthermore, the semiconductor device 1 may check the sound reproduction devices 3-1 and 3-2, and send the check result to the processing unit 310, and the processing unit 310 may determine whether the sound reproduction devices 3-1 and 3-2 have a fault or a fault mode. When the sound reproduction device 3-1 fails, the processing unit 310 may, for example, cause any of the sound reproduction devices 3-3 to 3-m to reproduce a sound notifying that the sound reproduction device 3-1 has failed, or may switch the output destination of the sound signal from the sound reproduction device 3-1 to any of the sound reproduction devices 3-3 to 3-m. When the sound reproduction device 3-2 fails, the processing unit 310 may, for example, cause any of the sound reproduction devices 3-3 to 3-m to reproduce a sound notifying that the sound reproduction device 3-2 has failed, or may switch the output destination of the sound signal from the sound reproduction device 3-2 to any of the sound reproduction devices 3-3 to 3-m.

[0131] The semiconductor device 1 can generate a signal necessary for detecting a failure of the sound reproducing devices 3 - 1 and 3 - 2 , and thus can realize an electronic device 300 with high reliability.

[0132] As such an electronic device 300, various electronic devices can be considered, for example, warning devices, various household electrical appliances such as rice cookers, IH cooking heaters, vacuum cleaners, washing machines, electronic watches, mobile, laptop, tablet and other personal computers, mobile terminals such as smart phones and mobile phones, digital cameras, inkjet printers and other inkjet ejection devices, routers, switches and other storage area network devices, local area network devices, mobile terminal base station devices, televisions, cameras, video recorders, car navigation devices, real-time clock devices, pagers, electronic notepads, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, anti-theft TV monitors, electronic binoculars, POS terminals, electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasonic diagnostic devices, electronic endoscopes and other medical equipment, fish finders, various measuring equipment, measuring instruments for vehicles, aircraft, ships, etc., flight simulators, head-mounted displays, motion search, motion tracking, motion controllers, pedestrian autonomous navigation devices, etc.

[0133] Fig.16 3 is a diagram showing a configuration example of a warning device 300A as an example of an electronic device 300. Fig.16 In, with Fig.15 The same components are denoted by the same reference numerals. Fig.16 The warning device 300A shown is mounted on a vehicle 400. The sound reproducing devices 3-1 to 3-3 are speakers, and the sound reproducing devices 3-4 and 3-5 are buzzers.

[0134] The processing unit 310 sends various sound reproduction commands to the semiconductor device 1 based on signals from various sensors (not shown). The various sounds include, for example, sounds imitating human voices for notifying abnormalities of the brakes, engine oil, power steering, brake override system, etc., driving with half doors, wobbling driving, driving with the parking brake not released, not wearing seat belts, approach of the vehicle ahead, etc., warning sounds, and effect sounds for notifying turn signals, danger, reversing, etc.

[0135] The semiconductor device 1 generates a plurality of sound signals based on a part of a plurality of sound source data corresponding to various sounds based on a command from the processing unit 310, and outputs the plurality of sound signals to the sound reproduction devices 3-1 and 3-2. In addition, the semiconductor device 1 may check the sound reproduction devices 3-1 and 3-2, and send the check result to the processing unit 310, and the processing unit 310 may determine whether the sound reproduction devices 3-1 and 3-2 have a fault or a fault mode. When a fault occurs in the sound reproduction device 3-1, the processing unit 310 may, for example, cause any one of the sound reproduction devices 3-3 to 3-5 to reproduce a sound notifying that the sound reproduction device 3-1 has a fault, or may switch the output destination of the sound signal from the sound reproduction device 3-1 to any one of the sound reproduction devices 3-3 to 3-5. In addition, when a failure occurs in the sound reproduction device 3-2, the processing unit 310 can, for example, cause any one of the sound reproduction devices 3-3 to 3-5 to reproduce a sound notifying that the sound reproduction device 3-2 has failed, or can switch the output destination of the sound signal from the sound reproduction device 3-2 to any one of the sound reproduction devices 3-3 to 3-5.

[0136] The semiconductor device 1 can generate a signal necessary for detecting a failure of the sound reproducing devices 3 - 1 , 3 - 2 , and thus can realize a highly reliable warning device 300A.

[0137] The present invention is not limited to the present embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0138] The above-mentioned embodiment and modification examples are examples, and the present invention is not limited thereto. For example, each embodiment and each modification example may be appropriately combined.

[0139] The present invention includes structures that are substantially the same as the structures described in the embodiments, such as structures with the same functions, methods and results, or structures with the same purposes and effects. In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that play the same role and effect as the structures described in the embodiments, or structures that can achieve the same purpose. In addition, the present invention includes structures that add known technology to the structures described in the embodiments.

[0140] The following contents are derived from the above-mentioned embodiments and modifications.

[0141] One embodiment of a semiconductor device comprises: a first output terminal connected to a first terminal of a first sound reproduction device; a second output terminal connected to a second terminal of the first sound reproduction device; a third output terminal connected to the first terminal of a second sound reproduction device; a fourth output terminal connected to the second terminal of the second sound reproduction device; a first modulation circuit that modulates a signal based on a first sound source signal in a first operation mode and outputs a first modulation signal and a second modulation signal; and a second modulation circuit that modulates a signal based on a second sound source signal in the first operation mode. a test signal generating circuit which modulates a test signal whose frequency varies in a preset frequency band in a second operation mode to generate a fifth modulation signal and a sixth modulation signal; a first amplifier circuit which outputs a first amplified signal obtained by amplifying the first modulation signal to the first output terminal in the first operation mode, and outputs a second amplified signal obtained by amplifying the second modulation signal to the second output terminal, and outputs a third amplified signal obtained by amplifying the fifth modulation signal to the first output terminal in the second operation mode, and outputs a third amplified signal obtained by amplifying the fifth modulation signal to the first output terminal in the second operation mode, and and outputs a fourth amplified signal obtained by amplifying the sixth modulated signal to the second output terminal; a second amplifier circuit, which in the first operation mode outputs a fifth amplified signal obtained by amplifying the third modulated signal to the third output terminal, and outputs a sixth amplified signal obtained by amplifying the fourth modulated signal to the fourth output terminal, and in the second operation mode outputs a seventh amplified signal obtained by amplifying the fifth modulated signal to the third output terminal, and outputs an eighth amplified signal obtained by amplifying the sixth modulated signal to the fourth output terminal; a first peak frequency detection circuit, which In the second operation mode, the potential difference between the first output terminal and the second output terminal is measured, and the frequency of the test signal at which the impedance of the first sound reproduction device becomes a peak, that is, the first peak frequency, is detected; a second peak frequency detection circuit, which measures the potential difference between the third output terminal and the fourth output terminal in the second operation mode, and detects the frequency of the test signal at which the impedance of the second sound reproduction device becomes a peak, that is, the second peak frequency; and a determination circuit, which determines whether the difference between the first peak frequency and the second peak frequency is included in a specified reference frequency difference range.

[0142] According to the semiconductor device, in the first operation mode, the first amplifier circuit outputs the first amplified signal obtained by amplifying the first modulated signal based on the first sound source signal to the first output terminal, and outputs the second amplified signal obtained by amplifying the second modulated signal based on the first sound source signal to the second output terminal, thereby the first sound reproduction device can reproduce the sound. In addition, in the first operation mode, the second amplifier circuit outputs the fifth amplified signal obtained by amplifying the third modulated signal based on the second sound source signal to the third output terminal, and outputs the sixth amplified signal obtained by amplifying the fourth modulated signal based on the second sound source signal to the fourth output terminal, thereby the second sound reproduction device can reproduce the sound. On the other hand, in the second operation mode, the first amplifier circuit outputs the third amplified signal obtained by amplifying the fifth modulated signal based on the test signal to the first output terminal, and outputs the fourth amplified signal obtained by amplifying the sixth modulated signal based on the test signal to the second output terminal, thereby the first peak frequency detection circuit can measure the potential difference between the first output terminal and the second output terminal, and detect the first peak frequency at which the impedance of the first sound reproduction device reaches a peak value. In addition, in the second operation mode, the second amplifier circuit outputs the seventh amplified signal obtained by amplifying the fifth modulated signal based on the test signal to the third output terminal, and outputs the eighth amplified signal obtained by amplifying the sixth modulated signal based on the test signal to the fourth output terminal, so that the second peak frequency detection circuit can measure the potential difference between the third output terminal and the fourth output terminal, and detect the second peak frequency at which the impedance of the second sound reproduction device reaches a peak. When the temperature of the first sound reproduction device and the temperature of the second sound reproduction device change in the same manner, the first peak frequency and the second peak frequency also change in the same manner, so that the difference between them is substantially constant regardless of the temperature. As a result, if both the first sound reproduction device and the second sound reproduction device are normal, even if the first peak frequency and the second peak frequency change due to the change in temperature, the difference between them is included in the prescribed reference frequency difference range. Therefore, the determination circuit determines whether the difference between the first peak frequency and the second peak frequency is included in the prescribed reference frequency difference range. For example, when the difference is not included in the reference frequency difference range, it can be determined that the first sound reproduction device or the second sound reproduction device may be faulty. Therefore, according to this semiconductor device, even if the temperature changes, the accuracy of the failure determination of the first sound reproducing device and the second sound reproducing device can be maintained.

[0143] Furthermore, in the semiconductor device, the first amplifier circuit is used for generating the first amplified signal and the second amplified signal for causing the first sound reproducing device to reproduce the sound in the first operation mode, and for generating the third amplified signal and the fourth amplified signal required for detecting the first peak frequency in the second operation mode. Similarly, the second amplifier circuit is used for generating the fifth amplified signal and the sixth amplified signal for causing the second sound reproducing device to reproduce the sound in the first operation mode, and for generating the seventh amplified signal and the eighth amplified signal required for detecting the second peak frequency in the second operation mode. Therefore, according to the semiconductor device, it is possible to generate signals required for detecting failures of the first sound reproducing device and the second sound reproducing device by a small-scale circuit.

[0144] In one embodiment of the semiconductor device, the first peak frequency detection circuit may also detect a first peak voltage in the second operation mode, wherein the first peak voltage is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when the frequency of the test signal is the first peak frequency; the second peak frequency detection circuit may also detect a second peak voltage in the second operation mode, wherein the second peak voltage is a voltage obtained by amplifying a potential difference between the third output terminal and the fourth output terminal when the frequency of the test signal is the second peak frequency; and the determination circuit may also determine whether a difference between the first peak voltage and the second peak voltage is included in a specified reference voltage difference range.

[0145] In this semiconductor device, when the temperature of the first sound reproducing device and the temperature of the second sound reproducing device change in the same manner, the first peak voltage and the second peak voltage also change in the same manner, so that the difference between them is substantially constant regardless of the temperature. As a result, if both the first sound reproducing device and the second sound reproducing device are normal, even if the first peak voltage and the second peak voltage change due to the change in temperature, the difference between them is included in the prescribed reference voltage difference range. Therefore, the determination circuit determines whether the difference between the first peak voltage and the second peak voltage is included in the prescribed reference voltage difference range. For example, even if the difference between the first peak frequency and the second peak frequency is included in the prescribed reference frequency difference range, if the difference between the first peak voltage and the second peak voltage is not included in the prescribed reference voltage difference range, it can be determined that the first sound reproducing device or the second sound reproducing device may be faulty. Therefore, according to this semiconductor device, the possibility of erroneously determining that both the first sound reproducing device and the second sound reproducing device are normal when the first sound reproducing device or the second sound reproducing device may be faulty is reduced.

[0146] In one embodiment of the semiconductor device, the first peak frequency detection circuit may detect the first peak frequency by measuring the time when the potential difference between the first output terminal and the second output terminal is the largest in the second operation mode, and the second peak frequency detection circuit may detect the second peak frequency by measuring the time when the potential difference between the third output terminal and the fourth output terminal is the largest in the second operation mode.

[0147] According to the semiconductor device, when the impedance of the first sound reproducing device reaches a peak value, the potential difference between the first output terminal and the second output terminal also reaches a peak value, so the first peak frequency detection circuit can detect the first peak frequency by measuring the time when the potential difference between the first output terminal and the second output terminal reaches a maximum. Similarly, when the impedance of the second sound reproducing device reaches a peak value, the potential difference between the third output terminal and the fourth output terminal also reaches a peak value, so the second peak frequency detection circuit can detect the second peak frequency by measuring the time when the potential difference between the third output terminal and the fourth output terminal reaches a maximum.

[0148] In one embodiment of the semiconductor device, the first peak frequency detection circuit may include: a first differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input; a first A / D conversion circuit to convert the output voltage of the first differential low-pass filter into a digital signal; and a first peak time measurement circuit to measure the time when the potential difference between the first output terminal and the second output terminal is maximum based on the digital signal output from the first A / D conversion circuit, and the second peak frequency detection circuit may include: a second differential low-pass filter to which the voltage of the third output terminal and the voltage of the fourth output terminal are input; a second A / D conversion circuit to convert the output voltage of the second differential low-pass filter into a digital signal; and a second peak time measurement circuit to measure the time when the potential difference between the third output terminal and the fourth output terminal is maximum based on the digital signal output from the second A / D conversion circuit.

[0149] According to the semiconductor device, the first differential low-pass filter reduces the high-frequency noise component superimposed on the fifth amplified signal and the sixth amplified signal by modulating the test signal, and the first A / D conversion circuit converts the output voltage of the first differential low-pass filter into a digital signal, so that the first peak time measurement circuit can easily perform high-precision measurement. Similarly, according to the semiconductor device, the second differential low-pass filter reduces the high-frequency noise component superimposed on the fifth amplified signal and the sixth amplified signal by modulating the test signal, and the second A / D conversion circuit converts the output voltage of the second differential low-pass filter into a digital signal, so that the second peak time measurement circuit can easily perform high-precision measurement.

[0150] In one aspect of the semiconductor device, a cutoff frequency of the first differential low-pass filter and a cutoff frequency of the second differential low-pass filter may be higher than a maximum frequency of the frequency band.

[0151] According to the semiconductor device, since the cutoff frequency of the first differential low-pass filter is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, the frequency components included in the frequency band are not attenuated by the first differential low-pass filter, and the first peak time measurement circuit can perform high-precision measurement. Similarly, according to the semiconductor device, since the cutoff frequency of the second differential low-pass filter is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, the frequency components included in the frequency band are not attenuated by the second differential low-pass filter, and the second peak time measurement circuit can perform high-precision measurement.

[0152] One aspect of an electronic device includes one aspect of the semiconductor device, the first sound reproducing device, and the second sound reproducing device.

[0153] According to this electronic device, since the semiconductor device capable of generating a signal necessary for detecting a failure of the first sound reproducing device and a failure of the second sound reproducing device is provided, reliability can be improved.

[0154] In one embodiment of the electronic device, the volumes reproduced by the first sound reproduction device and the second sound reproduction device in the second operation mode may be smaller than the minimum value of the volumes reproduced by the first sound reproduction device and the second sound reproduction device in the first operation mode.

[0155] According to this electronic device, the sounds outputted from the first sound reproducing device and the second sound reproducing device in the second operation mode are small sounds that are difficult for humans to hear, so that the user can hardly be aware that the semiconductor device is operating in the second operation mode.

Claims

1. A semiconductor device comprising: a first output terminal connected to a first terminal of a first sound reproducing device; a second output terminal connected to the second terminal of the first sound reproducing device; a third output terminal connected to the first terminal of the second sound reproducing device; a fourth output terminal connected to the second terminal of the second sound reproducing device; a first modulation circuit that modulates a signal based on a first sound source signal in a first operation mode and outputs a first modulation signal and a second modulation signal; a second modulation circuit that modulates a signal based on the second sound source signal in the first operation mode and outputs a third modulation signal and a fourth modulation signal; a test signal generating circuit that modulates a test signal whose frequency is varied in a preset frequency band in a second operation mode to generate a fifth modulated signal and a sixth modulated signal; a first amplifier circuit, which in the first operation mode outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and in the second operation mode outputs a third amplified signal obtained by amplifying the fifth modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the sixth modulated signal to the second output terminal; a second amplifier circuit, which in the first operation mode outputs a fifth amplified signal obtained by amplifying the third modulated signal to the third output terminal, and outputs a sixth amplified signal obtained by amplifying the fourth modulated signal to the fourth output terminal, and in the second operation mode outputs a seventh amplified signal obtained by amplifying the fifth modulated signal to the third output terminal, and outputs an eighth amplified signal obtained by amplifying the sixth modulated signal to the fourth output terminal; a first peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a first peak frequency, which is a frequency of the test signal at which the impedance of the first sound reproducing device reaches a peak value; a second peak frequency detection circuit that measures a potential difference between the third output terminal and the fourth output terminal in the second operation mode and detects a second peak frequency, which is a frequency of the test signal at which the impedance of the second sound reproducing device reaches a peak value; as well as The determination circuit determines whether a difference between the first peak frequency and the second peak frequency is included in a predetermined reference frequency difference range.

2. The semiconductor device according to claim 1, wherein The first peak frequency detection circuit further detects a first peak voltage in the second operation mode, wherein the first peak voltage is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when the frequency of the test signal is the first peak frequency. The second peak frequency detection circuit further detects a second peak voltage in the second operation mode, wherein the second peak voltage is a voltage obtained by amplifying a potential difference between the third output terminal and the fourth output terminal when the frequency of the test signal is the second peak frequency. The determination circuit further determines whether a difference between the first peak voltage and the second peak voltage is included in a predetermined reference voltage difference range.

3. The semiconductor device according to claim 1, wherein The first peak frequency detection circuit detects the first peak frequency by measuring a time when a potential difference between the first output terminal and the second output terminal is maximum in the second operation mode. The second peak frequency detection circuit detects the second peak frequency by measuring a time when a potential difference between the third output terminal and the fourth output terminal is maximum in the second operation mode.

4. The semiconductor device according to claim 3, wherein: The first peak frequency detection circuit comprises: a first differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input; a first A / D conversion circuit that converts an output voltage of the first differential low-pass filter into a digital signal; and a first peak time measuring circuit for measuring a time when a potential difference between the first output terminal and the second output terminal is maximum based on the digital signal output from the first A / D conversion circuit; The second peak frequency detection circuit comprises: a second differential low-pass filter to which the voltage of the third output terminal and the voltage of the fourth output terminal are input; a second A / D conversion circuit that converts the output voltage of the second differential low-pass filter into a digital signal; and A second peak time measurement circuit measures a time when a potential difference between the third output terminal and the fourth output terminal is maximum based on the digital signal output from the second A / D conversion circuit.

5. The semiconductor device according to claim 4, wherein: A cutoff frequency of the first differential low-pass filter and a cutoff frequency of the second differential low-pass filter are higher than a maximum frequency of the frequency band.

6. An electronic device comprising: The semiconductor device according to any one of claims 1 to 5; the first sound reproducing device; and The second sound reproducing device.

7. The electronic device according to claim 6, wherein: The volumes reproduced by the first sound reproducing device and the second sound reproducing device in the second operation mode are smaller than the minimum value of the volumes reproduced by the first sound reproducing device and the second sound reproducing device in the first operation mode.

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