Electronic device and manufacturing method thereof

Abstract

An electronic device includes a circuit structure, an electronic component electrically connected to the circuit structure, an antenna unit disposed on the circuit structure, and a shielding layer surrounding the electronic component. The circuit structure may have a first surface and a second surface opposite the first surface. The first surface has a first portion, a second portion and a third portion. The third portion connects the first portion and the second portion. In the normal direction of the electronic device, the third portion is closer to the second surface than the first portion and the second portion to form a recess. The electronic component may be disposed in the recess. The antenna unit can be arranged on the first surface of the circuit structure and is electrically connected with the electronic component through the circuit structure.

Description

Technical Field

[0001] The present invention relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device including a shielding layer and a manufacturing method thereof. Background Art

[0002] With the development of digital technology, electronic devices have been widely used in daily life and are constantly developing towards being light, thin, short and fashionable. Electronic devices may include packaging devices and antenna devices. In order to achieve the purpose of product miniaturization, the antenna package (Antennas in package, AiP) structure can integrate the antenna device with other electronic components or circuits in a packaging device. Summary of the invention

[0003] According to some embodiments of the present disclosure, an electronic device is provided, which includes: a circuit structure, an electronic component electrically connected to the circuit structure, an antenna unit disposed on the circuit structure, and a shielding layer surrounding the electronic component. The circuit structure may have a first surface and a second surface relative to the first surface. The first surface has a first part, a second part and a third part, and the third part connects the first part and the second part. Along the normal direction of the electronic device, the first part and the second part are farther away from the second surface than the third part to form a recess. The electronic component may be disposed in the recess. The antenna unit is disposed correspondingly to at least one of the first part and the second part of the first surface, and is electrically connected to the electronic component through the circuit structure.

[0004] According to some embodiments of the present disclosure, a method for manufacturing an electronic device is provided, which includes the following steps: providing a circuit structure, wherein the circuit structure has a first surface and a second surface relative to the first surface, the first surface has a first part, a second part and a third part, the third part connects the first part and the second part, and along the normal direction of the electronic device, the first part and the second part are farther away from the second surface than the third part to form a recess; arranging an electronic component in the recess of the circuit structure, wherein the electronic component is electrically connected to the circuit structure; forming a shielding material layer on the electronic component and the circuit structure; patterning the shielding material layer to form a shielding layer, wherein the shielding layer surrounds the electronic component; and arranging an antenna unit on the first surface of the circuit structure, wherein the antenna unit is electrically connected to the electronic component through the circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1A is a schematic top view of an electronic device according to an embodiment of the present disclosure;

[0007] Figure 1B According to an embodiment of the present disclosure Figure 1A A schematic cross-sectional view of the electronic device along line AA' is shown;

[0008] Figure 2A is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0009] Figure 2B is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0010] Figure 2C is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0011] Figure 3 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0012] 4A to 4H is a schematic cross-sectional view of an electronic device during manufacture of the electronic device according to an embodiment of the present disclosure; and

[0013] FIG. 5A to FIG. 5D FIG. 4 is a cross-sectional schematic diagram of an electronic device during manufacturing of the electronic device according to another embodiment of the present disclosure.

[0014]

Explanation of symbols

[0015] 10: Circuit structure

[0016] 101: Insulation layer

[0017] 103: first metal circuit layer

[0018] 10S1: First surface

[0019] 10S2: Second surface

[0020] 20: First joint component

[0021] 30,100: Electronic components

[0022] 30S: Side surface

[0023] 30T: Top surface

[0024] 30B: Bottom surface

[0025] 40: Second joint component

[0026] 50: Antenna unit

[0027] 60: Buffer layer

[0028] 70: shielding layer

[0029] 70': shielding material layer

[0030] 701: First sublayer

[0031] 703: Second sublayer

[0032] 703': First material sublayer

[0033] 705: The third sublayer

[0034] 705': Second material sublayer

[0035] 70S,RS,PS: Side

[0036] 80: Protective layer

[0037] 90:Substrate

[0038] 901: Second metal circuit layer

[0039] G1: First gap

[0040] R: Depression

[0041] R1: Part 1

[0042] R2: Part 2

[0043] R3: Part 3

[0044] RB: Bottom

[0045] RST: Top

[0046] RSB:Bottom

[0047] T1: Depth of depression

[0048] T2: Height

[0049] D: Release layer

[0050] D1: First distance

[0051] D2: Second distance

[0052] O1: Opening

[0053] P: Photoresist layer

[0054] PT: Top surface

[0055] PL: Passivation layer

[0056] S301, S302, S303, S304, S305, S306, S307, S308: Steps

[0057] RBL,S1L,S2L:Extension line DETAILED DESCRIPTION

[0058] The following description lists various embodiments of the present invention to introduce the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims. The following will refer to exemplary embodiments of the present disclosure in detail, and examples of exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and description to represent the same or similar parts.

[0059] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not intended to limit the scope of the present disclosure.

[0060] The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. It is understood that if the device in the accompanying drawings is turned upside down, the components described on the "down" side will become components on the "up" side. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these figures should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0061] A structure (or layer, component, substrate) described in the present disclosure is located on / above another structure (or layer, component, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate gap) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may refer to that the certain structure is "directly" on the other structure, or it may refer to that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0062] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct (indirect) contact, wherein there is another structure disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or where both structures are fixed. In addition, the term "electrically connected" includes energy transfer between two structures by means of direct or indirect electrical connection, or energy transfer between two separate structures by means of mutual induction.

[0063] The term "A surrounds B" in the present disclosure means that at least part of B is in A, and in a cross-sectional view, A at least directly or indirectly contacts one side surface of B. The term "A indirectly contacts B" in the present disclosure means that there is an intervening structure between A and B. The term "A directly contacts B" in the present disclosure means that there is no intervening structure between A and B.

[0064] The terms "approximately", "equal to", "equal to" or "same", "substantially" or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range. The term "between a and b" refers to a range that includes all values ​​greater than or equal to a, less than or equal to b, and between a and b.

[0065] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims.

[0066] Certain words are used throughout the present disclosure and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components with different names. This document does not intend to distinguish between components that have the same function but different names.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0068] The electronic device may include a power module, an imaging device, a bonding device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, a packaging device, a splicing device, a touch display, a curved display, or a non-rectangular electronic device (free shape display), but the present disclosure is not limited thereto. The electronic device may, for example, include a liquid crystal, a light emitting diode, fluorescence, phosphorescence, other suitable display media, or any combination thereof, but the present disclosure is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasound, but the present disclosure is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but the present disclosure is not limited thereto.

[0069] The electronic device may be a bendable or flexible electronic device. The shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The process of the electronic device described in the present disclosure may be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, which may be chip first or chip last (RDL first).

[0070] The electronic device of the present disclosure may include an electronic component. The electronic component may include a passive component, an active component, or a combination thereof. Examples of passive components may include capacitors, resistors, inductors, varactors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical system components (MEMS), liquid crystal chips, etc., but the present disclosure is not limited thereto. The diode may include a light emitting diode or a non-light emitting diode. The diode may include a PN junction diode, a PIN diode, or a constant current diode. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (microLED), a quantum dot light emitting diode (quantum dot LED), a fluorescence diode, a phosphor diode, or other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The sensor may include, for example, a capacitive sensor, an optical sensor, an electromagnetic sensor, a fingerprint sensor (FPS), a touch sensor, an antenna, or a stylus, etc., but the present disclosure is not limited thereto. Examples of active components may include a chip (die) or a light emitting diode chip (LED die), which may be a chip made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), sapphire (Sapphire) or a glass substrate, but the present disclosure is not limited thereto. In another embodiment, the above-mentioned chip may include a semiconductor packaging component, such as a ball grid array (BGA) packaging component, a chip size package (CSP) component, a system on package (SoC), a system in package (SiP), an antenna in package (AiP), a flip chip or a 2.5-dimensional / 3-dimensional (2.5D / 3D) semiconductor packaging component, but the present disclosure is not limited to this.In another embodiment, the chip may be any flip chip bonding component, such as an integrated circuit (IC), transistors, thyristor rectifiers, valves, thin film transistors, capacitors, inductors, variable capacitors, filters, resistors, diodes, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but the present disclosure is not limited thereto. In addition, the chip may include, for example, a diode or a semiconductor chip (semiconductor die), but the present disclosure is not limited thereto. The chip may be a known good die (KGD), which may include various electronic components, such as (but not limited to) wires, transistors, circuit boards, etc. Adjacent chips may have different functions from each other, such as integrated circuits, RFICs, D-RAMs, but the present disclosure is not limited thereto.

[0071] It should be understood that according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the depth, thickness, width, or height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the component to be measured, and measure the depth, thickness, width, or height of each component, or the spacing or distance between components.

[0072] One aspect of the present disclosure is to provide an electronic device. Figure 1A is a schematic top view of an electronic device according to an embodiment of the present disclosure. Figure 1B According to an embodiment of the present disclosure, Figure 1A The cross-sectional view of the electronic device shown is taken along line AA'. The "cross-sectional view" herein refers to a view taken along the normal direction (ie, the Z direction) of the electronic device.

[0073] like Figure 1A as well as Figure 1BAs shown, the electronic device of the present disclosure may include a circuit structure 10, an electronic component 30 electrically connected to the circuit structure 10, an antenna unit 50 disposed on the circuit structure 10, and a shielding layer 70 surrounding the electronic component 30. The circuit structure 10 may have a first surface 10S1 and a second surface 10S2 relative to the first surface 10S1. The first surface 10S1 has a first portion R1, a second portion R2, and a third portion R3, and the third portion R3 connects the first portion R1 and the second portion R2. Along the normal direction of the electronic device, the third portion R3 is closer to the second surface 10S2 than the first portion R1 and the second portion R2 to form a recess R. The electronic component 30 electrically connected to the circuit structure 10 may be disposed in the recess R. The antenna unit 50 may be disposed on the first surface 10S1 of the circuit structure 10 and electrically connected to the electronic component 30 through the circuit structure 10. In some embodiments, the electronic device may further include a first bonding component 20 disposed on the second surface 10S2 of the circuit structure 10. The first bonding component 20 is electrically connected to the electronic component 30. The electronic component 30 can be electrically connected to other electronic components and / or electronic devices such as a printed circuit board (PCB) through the first bonding component 20. The electronic device can be electrically connected to other electronic components and / or electronic devices such as a printed circuit board through the first bonding component 20.

[0074] The circuit structure 10 may include at least one insulating layer 101 and at least one first metal wiring layer 103. In some embodiments, the first metal wiring layer 103 may be disposed in the insulating layer 101. Figure 1BAs shown, but the present disclosure is not limited thereto. In some embodiments, at least part of the first metal wiring layer 103 may be disposed on the insulating layer 101. The circuit structure 10 may include a single layer or multiple layers of insulating layers 101 and / or a single layer or multiple layers of first metal wiring layers 103. In an embodiment where the circuit structure 10 includes multiple layers of insulating layers 101 and multiple first metal wiring layers 103, the insulating layers 101 and the first metal wiring layers 103 may be stacked alternately along the normal direction (i.e., the Z direction) of the electronic device, so that the multiple layers of first metal wiring layers 103 may be electrically connected to each other. The first metal wiring layer 103 may include a signal line, an RF feed line, a redistribution line and / or a through hole (via). At least part of the first metal wiring layer 103 may be exposed to the outside, and the electronic components 30 and the antenna unit 50 formed subsequently may be electrically connected to the circuit structure 10 by directly or indirectly contacting the first metal wiring layer 103 exposed to the outside. The signal line may include a power line, a ground line, or other signal lines. The circuit structure 10 may be, for example, a redistribution layer (RDL), which can redistribute the circuits of the electronic device and / or further increase the circuit fan-out area, or different electronic components can be electrically connected to each other through the circuit structure 10. For example, the spacing between two adjacent contact pads of the circuit structure 10 that contacts one end of the electronic component 30 may be less than or equal to the spacing between two adjacent contact pads of the circuit structure 10 that is away from the end of the electronic component 30, so that the circuit structure 10 can adjust the circuit fan-out condition, but is not limited thereto. Furthermore, the circuit structure 10 can be applied to wafer level chip scale package (WLCSP), wafer level package (WLP), panel pevel ​​package (PLP) or other packaging methods, but is not limited thereto.

[0075] The material of the insulating layer 101 may include a silicon substrate, a glass substrate, a nitride, an oxide, a nitride oxide, a perfluoroalkoxyalkane (PFA), a resin, a photosensitive polyimide (PSPI), a polyimide (PI), an Ajinomoto build-up film (ABF), a polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The material of the first metal wiring layer 103 may include a seed layer, a metal, or any combination thereof. In some embodiments, examples of metals may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), tantalum (Ta), ruthenium (Ru), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), other suitable metal materials, alloys, or combinations thereof, but the present disclosure is not limited thereto.

[0076] The circuit structure 10 may have a first surface 10S1 and a second surface 10S2 relative to the first surface 10S1. In detail, the first surface 10S1 has a first portion R1, a second portion R2 and a third portion R3, and the third portion R3 connects the first portion R1 and the second portion R2. Along the normal direction (Z direction) of the electronic device, the first portion R1 and the second portion R2 of the first surface 10S1 are farther away from the second surface 10S2 than the third portion R3, thereby forming a recess R. In other words, the recess R has a bottom RB and a side RS connected to the bottom RB. The bottom RB of the recess R and the side RS connected to the bottom RB correspond to the third portion R3 of the first surface 10S1. The bottom RB of the recess R is located between the first portion R1 and / or the second portion R2 of the first surface 10S1 and the second surface 10S2. Specifically, along the Z direction, the distance between the extension line RBL of the bottom RB of the recess R and the extension line S1L of the first portion R1 and / or the second portion R2 of the first surface 10S1 or the distance between the extension line RBL of the bottom RB of the recess R and the extension line S2L of the second surface 10S2 is smaller than the distance between the extension line S1L of the first portion R1 and / or the second portion R2 of the first surface 10S1 and the extension line S2L of the second surface 10S2. Through the above design, the recess R has a receiving space for accommodating electronic components. The extension line RBL of the bottom RB, the extension line S1L of the first portion R1 and / or the second portion R2 of the first surface 10S1, and the extension line S2L of the second surface 10S2 are perpendicular to the Z direction. The side RS of the recess R is located between the bottom RB and the first surface 10S1 and connects the bottom RB and the first surface 10S1. The recess R may have a recess depth T1 in the Z direction, and the recess depth T1 may be between 0.5 μm and 100 μm. The distance between the bottom RB of the recess R and the first surface 10S1 of the circuit structure 10 may be equal to the recess depth T1. In some embodiments, in a direction perpendicular to the Z direction (e.g., the X direction), the width of the bottom RB of the recess R is less than the width of the top of the recess R. That is, in some embodiments, in the cross-sectional view, the recess R may have an inverted trapezoidal or bowl-shaped shape, but is not limited thereto. Specifically, the recess R is a concave space that can accommodate other components. In this embodiment, the angle θ between the side RS of the recess R and the bottom RB may be between 90° and 160° (90°≤θ≤160°), between 105° and 155°, or between 110° and 145°, but the present disclosure is not limited thereto. The side RS has a top RST and a bottom RSB. The top end RST is located between the side RS and the first surface 10S1 and the bottom end RSB is located between the side RS and the bottom RB.

[0077] In some embodiments, any other desired electronic components 100 may be disposed on the first surface 10S1 of the circuit structure 10, such as Figure 1AAs shown, but the present disclosure is not limited thereto. The electronic component 100 may include a surface mount component (SMD), an integrated circuit chip, a diode, a driving circuit, a compensation circuit, an integrated passive device (IPD), or other suitable components, but the present disclosure is not limited thereto. In some embodiments, the electronic component 100 may further include a carrier, such as a transistor formed on a glass carrier, a chip bonded on an ABF carrier, or other suitable electronic components.

[0078] The electronic component 30 disposed in the recess R may have a top surface 30T, a bottom surface 30B relative to the top surface 30T, and a side surface 30S connecting the top surface 30T and the bottom surface 30B. The top surface 30T may be, for example, a side of the electronic component 30 where no conductive pad (I / O pad) is disposed, and the bottom surface 30B may be, for example, a side of the electronic component 30 where a conductive pad (I / O pad) is disposed. In some embodiments, the electronic component 30 may include a semiconductor chip, and the semiconductor chip may be, for example, a doped silicon chip, silicon carbide (SiC), gallium nitride (GaN) or other suitable semiconductor materials, but is not limited thereto. The electronic component 30 may further include a passivation layer PL. In some embodiments, the passivation layer PL may be deposited on the bottom surface of the semiconductor chip. In some embodiments, the passivation layer PL may be located at the bottom surface 30B. In some embodiments, a portion of the passivation layer PL may be disposed between the bottom surface of the semiconductor chip and the conductive pad (I / O pad). The electronic component 30 has a height T2 in the Z direction. The distance between the top surface 30T and the bottom surface 30B of the electronic component 30 may be equal to the height T2. In some embodiments, the height T2 may be between 5 μm and 200 μm. In some embodiments, the recess depth T1 of the recess R may be greater than or equal to the height T2 of the electronic component 30. In some embodiments, the height T2 of the electronic component 30 may be greater than the recess depth T1 of the recess R, but the present disclosure is not limited thereto. In some embodiments, the height T2 of the electronic component 30 and the recess depth T1 of the recess R meet the following relationship:

[0079] 0.1X height T2≦depression depth T1≦0.5X height T2.

[0080] In some embodiments, in the Z direction, the top surface 30T of the electronic component 30 disposed in the recess R may be higher than the first surface 10S1 of the circuit structure 10. Figure 1B The above configuration can reduce the interference of signals between components, but the present disclosure is not limited thereto.

[0081] The projection of the electronic component 30 on a plane perpendicular to the normal direction of the electronic device (e.g., an XY plane) is located in the projection of the recess R on the plane. In the X direction, the bottom end RSB of the side edge RS is at a first distance D1 from the side surface 30S of the adjacent electronic component 30, such as Figure 1B As shown. In some embodiments, the first distance D1 may be greater than or equal to 10μm (≧10μm) or between 10μm and 20μm. Here, "the side surface 30S of the adjacent electronic component 30" in "the bottom end RSB of the side RS and the side surface 30S of the adjacent electronic component 30" refers to the side surface 30S of the electronic component 30 that is closest to the bottom end RSB of the side RS among the side surfaces 30S of the electronic component 30. At this time, there is no other side surface 30S of the electronic component 30 between the bottom end RSB of the side RS and the side surface 30S of the adjacent electronic component 30. In some embodiments, in the X direction, the width of the electronic component 30 and the first distance D1 may satisfy the following relationship:

[0082] The width of the electronic component 30>the first distance D1≧10 μm.

[0083] By placing the electronic component 30 in the recess R under the above conditions, the risk of the electronic component 30 being bumped or scratched during the placement of the electronic component 30 can be reduced. By placing the electronic component 30 in the recess R, the circuit in the first metal circuit layer 103, such as the length of the RF feed line and the height of the through hole in the Z direction can be shortened to reduce signal loss or deviation or reduce signal transmission delay. In addition, by placing the electronic component 30 in the recess R, the risk of the electronic component 30 being deflected during the manufacture, transportation, or use of the electronic device can also be reduced, thereby improving the reliability of the electronic device.

[0084] In some embodiments, the electronic component 30 may include a surface mount component (SMD), an integrated circuit chip, a diode, a driving circuit, a compensation circuit, an integrated passive device (IPD), a radio frequency integrated circuit (RFIC), or other suitable components, but the present disclosure is not limited thereto. In some embodiments, the electronic component 30 may be a radio frequency integrated circuit (RFIC). For example, the electronic component 30 may be a known good chip including a semiconductor structure, and the electronic component 30 may further include a conductive pad to be bonded to the circuit structure 10, thereby electrically connected. The conductive pad may include copper, tin, aluminum, gallium, or other suitable conductive materials, but is not limited thereto.

[0085] In some embodiments, the electronic device may further include a second bonding element 40 located between the electronic component 30 and the circuit structure 10. The electronic component 30 may be disposed in the recess R of the circuit structure 10 through the second bonding element 40 and electrically connected to the circuit structure 10. In some embodiments, the second bonding element 40 may be located between the bottom surface 30B of the electronic component 30 and the bottom RB of the recess R and electrically connect the electronic component 30 to the first metal wiring layer 103 of the circuit structure 10. The material of the second bonding element 40 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), other suitable metal materials or a combination of the foregoing, but the present disclosure is not limited thereto. According to some embodiments, the copper pillar formed on the conductive pad (I / O pad) of the electronic component 30 and the copper pillar formed on the circuit structure 10 are combined with each other to define the second bonding element 40, and this bonding method may be called copper-copper heterogeneous bonding (Cu-Cu hybrid bonding).

[0086] In some embodiments, the electronic device may further include a buffer layer 60. The buffer layer 60 may be located between the electronic component 30 and the circuit structure 10 and surround the second bonding component 40. The buffer layer 60 may reduce the risk of oxidation of the second bonding component 40 and enhance the mechanical strength between the electronic component 30 and the circuit structure 10. In some embodiments, the material of the buffer layer 60 may include an organic material, but the present disclosure is not limited thereto. Examples of organic materials may include epoxy resins, acrylic resins, or other suitable materials. In some embodiments, the buffer layer 60 may be, for example, an under filler. In some embodiments, the buffer layer 60 may include filling particles to enhance the mechanical strength of the buffer layer 60 and improve the reliability of the electronic device. In some embodiments, the material of the buffer layer 60 may include an inorganic material. For example, in some embodiments, the buffer layer 60 may include silicon oxide, silicon nitride, or a stack of multiple layers of silicon oxide and multiple layers of silicon nitride along the Z direction.

[0087] The antenna unit 50 is disposed on the first surface 10S1 of the circuit structure 10 and is electrically connected to the electronic component 30 through the circuit structure 10. According to some embodiments, the antenna unit 50 may be disposed correspondingly on the first portion R1 of the first surface 10S1, the antenna unit 50 may be disposed correspondingly on the second portion R2 of the first surface 10S1, or the antenna unit 50 may be disposed respectively on the first portion R1 and the second portion R2. When the electronic device has a plurality of antenna units 50, the frequencies of transmitting or receiving radio waves of at least two of the plurality of antenna units 50 may be different, but not limited thereto. The antenna unit 50 may include a loop antenna, a broadband dipole, a monopole antenna, a folded dipole antenna, a microstrip or patch antenna, a planar inverted F antenna (PIFA), an inverted F antenna (IFA), a Vivaldi antenna, a slotted waveguide antenna, a half-wave antenna, a quarter-wave antenna, a stereo antenna, other suitable antennas, or any combination thereof, but the present disclosure is not limited thereto. By disposing the antenna unit 50 on the first surface 10S1 of the circuit structure 10, the heat generated by the electronic component 30 disposed in the recess R can be dissipated more easily, and the heat dissipation effect of the electronic device can be improved. In some embodiments, the heat dissipation effect of the electronic device can be improved by more than 20%, but not limited thereto.

[0088] The shielding layer 70 is formed on the circuit structure 10 and surrounds the electronic component 30. The shielding layer 70 can reduce the risk of radio frequency radiation interference (RFI / EMI) of the electronic component 30 with other signals, thereby improving the signal receiving sensitivity of the antenna unit 50. The shielding layer 70 can directly or indirectly contact the entire side surface 30S of the electronic component 30. In some embodiments, the shielding layer 70 can cover the entire side surface 30S and the entire top surface 30T of the electronic component 30, but the present disclosure is not limited thereto. In some embodiments, the shielding layer 70 can cover the entire side surface 30S of the electronic component 30 and expose at least a portion of the top surface 30T of the electronic component 30. In some embodiments, the shielding layer 70 can cover a portion of the bottom RB of the recess R and the first surface 10S1 of the circuit structure 10. Specifically, in some embodiments, the shielding layer 70 can cover the bottom RB of the recess R that does not overlap with the electronic component 30 in the Z direction and a portion of the first surface 10S1. In some embodiments, the shielding layer 70 may directly or indirectly contact the side surface 30S and the top surface 30T of the electronic component 30, the side RS and the bottom RB of the recess R, and the first surface 10S1 partially connected to the recess R. Figure 1B The projection of the electronic component 30 on a plane perpendicular to the normal direction of the electronic device (e.g., the XY plane) may be located in the projection of the recess R on the plane, and the projection of the recess R on the plane may be located in the projection of the shielding layer 70 on the plane, as shown in FIG. Figure 1AAs shown. According to the above design, on a plane perpendicular to the normal direction of the electronic device (e.g., the XY plane), the projection area of ​​the shielding layer 70 is larger than the projection area of ​​the recess R on the plane. That is to say, the shielding layer 70 may cover part of the bottom RB of the recess R, the side RS of the recess R, and the first portion R1 and / or the second portion R2 of the first surface 10S1 partially connected to the recess R, so as to reduce the risk of radio frequency radiation interference (RFI / EMI) of the electronic component 30 with other signals, thereby improving the signal receiving sensitivity of the antenna unit 50, but not limited to this. In the Z direction, the thickness of the shielding layer 70 on the first surface 10S1 of the circuit structure 10 may be substantially the same as the thickness of the shielding layer 70 on the top surface 30T of the electronic component 30 (the difference does not exceed ±10%). The shielding layer 70 may have a side 70S. In some embodiments, the side 70S may be located on the first portion R1 and / or the second portion R2 of the first surface 10S1 of the circuit structure 10. In this embodiment, in a direction perpendicular to the normal direction of the electronic device (eg, the X direction), the top RST of the side RS and the side 70S of the adjacent shielding layer 70 may be spaced apart by a second distance D2, such as Figure 1A as well as Figure 1B As shown. That is to say, the width of the shielding layer 70 disposed on the first portion R1 and / or the second portion R2 of the first surface 10S1 of the circuit structure 10 can be regarded as the second distance D2. In some embodiments, the second distance D2 may be greater than or equal to 10μm (≧10μm) or between 10μm and 100μm. Here, "the side 70S of the adjacent shielding layer 70" in "the top RST of the side RS and the side 70S of the adjacent shielding layer 70" refers to the side 70S of the shielding layer 70 that is closest to the side RS of the recess R among the side 70S of the shielding layer 70. At this time, there is no other side 70S of the shielding layer 70 between the side RS of the recess R and the side 70S of the adjacent shielding layer 70.

[0089] The shielding layer 70 may include a single-layer structure or a multi-layer structure. In some embodiments, the shielding layer 70 may include a multi-layer structure having a first sub-layer 701, a second sub-layer 703, and a third sub-layer 705, wherein the second sub-layer 703 is located between the first sub-layer 701 and the third sub-layer 705, and the third sub-layer 705 is located between the second sub-layer 703 and the electronic component 30, such as Figure 1BAs shown, but the present disclosure is not limited thereto. In some embodiments, the shielding layer 70 may include a structure of more than three layers. In other embodiments, the shielding layer 70 may include a structure of less than three layers. The first sublayer 701, the second sublayer 703, and the third sublayer 705 may include different materials. In some embodiments, the material of the first sublayer 701 may include a material having excellent oxidation resistance, and the materials of the second sublayer 703 and the third sublayer 705 may include a material having good radio frequency radiation shielding ability. In some embodiments, the material of the first sublayer 701 may include nickel (Ni), the material of the second sublayer 703 may include copper (Cu), and the material of the third sublayer 705 may include titanium (Ti), but the present disclosure is not limited thereto. In some embodiments, in the Z direction. The second sublayer 703 and the third sublayer 705 may have different thicknesses. In some embodiments, the thickness of the second sublayer 703 may be 0.6 μm, and the thickness of the third sublayer 705 may be 0.1 μm, but the present disclosure is not limited thereto.

[0090] The electronic device of the present disclosure having the above structure can have good heat dissipation effect, signal sensitivity, and / or system stability. According to some embodiments, by providing a shielding layer 70 covering the electronic component 30, wherein the width of the shielding layer 70 contacting the first surface 10S1 of the circuit structure 10 is between 10 μm and 30 μm, the electronic device can have good signal sensitivity, or the bonding ability between the shielding layer 70 and the circuit structure 10 can be improved.

[0091] Figure 2A FIG. 1 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. In this embodiment, the shielding layer 70 surrounding the electronic component 30 has an opening O1, and a portion of the top surface 30T of the electronic component 30 can be exposed through the opening O1. Figure 2AAs shown. The shielding layer 70 having the opening O1 can be used together with the electronic component 30 as another antenna unit to receive or transmit a signal of a bandwidth different from that of the antenna unit 50. In an embodiment where the shielding layer 70 includes a first sublayer 701, a second sublayer 703, and a third sublayer 705, the opening O1 is defined by a first opening in the first sublayer 701, a second opening in the second sublayer 703, and a third opening in the third sublayer 705. In some embodiments, in a direction perpendicular to the normal direction of the electronic device (e.g., the X direction), the width of the second opening may be approximately equal to the width of the third opening. In some embodiments, in a direction perpendicular to the normal direction of the electronic device (e.g., the X direction), the width of the second opening and / or the third opening may be greater than the width of the first opening. In this embodiment, a first gap G1 may be provided between the first sublayer 701 and the electronic component 30. Specifically, a first gap G1 may be provided between the bottom surface of the first sublayer 701 and the top surface 30T of the electronic component 30. In some embodiments, the first gap G1 may be between 0.1 μm and 1 μm or between 0.2 μm and 0.8 μm, but the disclosure is not limited thereto.

[0092] In addition to the shielding layer 70 having the opening O1, Figure 2A The structure of the electronic device shown is Figure 1A as well as Figure 1B The structures of the electronic devices shown are substantially the same, and thus will not be described in detail herein.

[0093] Figure 2B is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. In this embodiment, the electronic device of the present disclosure may further include a protective layer 80, which may surround and cover the shielding layer 70 and the electronic component 30, thereby reducing the risk of the electronic component 30 and the shielding layer 70 being affected by moisture and oxygen in the environment. In some embodiments, the protective layer 80 may be in direct or indirect contact with the shielding layer 70 and the electronic component 30, such as Figure 2B As shown, but the present disclosure is not limited thereto. In this embodiment, the projection of the shielding layer 70 on a plane perpendicular to the normal direction of the electronic device (e.g., the XY plane) is located in the projection of the protective layer 80 on the plane, and the projection of the electronic component 30 on the plane is located in the projection of the shielding layer 70 on the plane. In an embodiment in which the shielding layer 70 has an opening O1, the protective layer 80 may be filled in the opening O1 of the shielding layer 70 and in direct contact with the portion of the top surface 30T of the electronic component 30 exposed through the opening O1, but the present disclosure is not limited thereto. The material of the protective layer 80 may include epoxy resin, acrylic resin, other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. According to some embodiments, the dielectric loss of the protective layer 80 is less than or equal to 0.05, that is, Df(@10GHz)≤0.05.

[0094] In addition to further comprising a protective layer 80, Figure 2B The structure of the electronic device shown is Figure 2A The structures of the electronic devices shown are substantially the same, and thus will not be described in detail herein.

[0095] Figure 2C is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. In this embodiment, the electronic device of the present disclosure may further include a substrate 90, which may be located between the circuit structure 10 and the first bonding component 20. The substrate 90 may include a second metal wiring layer 901. The second metal wiring layer 901 may include metal wiring and / or vias. The second metal wiring layer 901 may include a single layer or a multi-layer structure. In an embodiment where the second metal wiring layer 901 includes multiple layers of second metal wiring layers 901, these second metal wiring layers 901 may be electrically connected to each other. The circuit structure 10 and the first bonding component 20 may be electrically connected through the second metal wiring layer 901. The substrate 90 may enhance the support of the electronic device or enhance the design flexibility of the wiring and components in the electronic device. The material of the second metal wiring layer 901 may include a seed layer, a metal, or any combination thereof. In some embodiments, examples of metals may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), other suitable metal materials, or a combination of the foregoing, but the present disclosure is not limited thereto. The substrate 90 may include a silicon substrate, a glass substrate, an ABF substrate, a FR-4 substrate, a ceramic substrate or other suitable substrates, but is not limited thereto. The thickness of the substrate 90 may be greater than the thickness of the circuit structure 10, or the rigidity of the substrate 90 may be greater than the rigidity of the circuit structure 10, so that the substrate 90 can carry more components and improve the mechanical strength of the electronic device, but is not limited thereto.

[0096] In addition to further including a substrate 90 between the circuit structure 10 and the first bonding element 20, Figure 2C The structure of the electronic device shown is Figure 1A and Figure 1B The structures of the electronic devices shown are substantially the same, and thus will not be described in detail herein.

[0097] Another embodiment of the present disclosure provides a method for manufacturing an electronic device. Figure 3 FIG. 1 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 3As shown, the manufacturing method of the electronic device disclosed in the present invention includes: step S301 of providing a circuit structure, wherein the circuit structure has a first surface and a second surface opposite to the first surface, the first surface has a first part, a second part and a third part, and the third part connects the first part and the second part. Along the normal direction of the electronic device, the third part is closer to the second surface than the first part and the second part to form a recess; step S302 of setting an electronic component in the recess of the circuit structure, wherein the electronic component is electrically connected to the circuit structure; step S303 of forming a shielding material layer on the electronic component and the circuit structure, wherein the shielding material layer conformally covers the electronic component and the circuit structure; step S304 of patterning the shielding material layer to form a shielding layer, wherein the shielding layer surrounds the electronic component; and step S305 of setting an antenna unit on the first surface of the circuit structure, wherein the antenna unit is electrically connected to the electronic component through the circuit structure.

[0098] 4A to 4H FIG. 1 is a cross-sectional view of an electronic device during the manufacturing process of the electronic device according to an embodiment of the present disclosure. Figure 3 as well as 4A to 4H A method for manufacturing an electronic device according to an embodiment of the present disclosure is further described.

[0099] Step S301 may include providing the circuit structure 10 on a carrier C having a release layer D disposed thereon, and then forming a recess R in the circuit structure 10, but the disclosure is not limited thereto. In some embodiments, the circuit structure 10 of step S301 may be provided on a substrate. FIG. 4A to FIG. 4G FIG. 1 is an embodiment of a circuit structure 10 provided on a carrier C on which a release layer D is disposed. In some embodiments, the circuit structure 10 can be disposed on the carrier C in a manner such that the second surface 10S2 is located between the first surface 10S1 and the release layer D. Figure 4A As shown. The following is an example in which the circuit structure 10 may include an insulating layer 101 and a first metal wiring layer 103 disposed on or in the insulating layer 101. The first metal wiring layer 103 may include an RF feed line, a redistribution line and / or a through hole (via). According to some embodiments, a release layer D may not be required on the carrier C, that is, the circuit structure 10 may be directly disposed on the carrier C, and thus the carrier C may include, for example, a substrate 90.

[0100] The circuit structure 10 may have a first surface 10S1 and a second surface 10S2 relative to the first surface 10S1. The first surface 10S1 has a first portion R1, a second portion R2 and a third portion R3, and the third portion R3 connects the first portion R1 and the second portion R2. Along the normal direction of the electronic device, the third portion R3 is closer to the second surface 10S2 than the first portion R1 and the second portion R2 to form a recess R. In some embodiments, the recess R may be formed by a plasma etching process, a laser etching process, a chemical etching process, a yellow light process, other suitable patterning processes or any combination thereof, but the present disclosure is not limited thereto. During the process of performing a patterning step on the circuit structure 10 to form the recess R, the patterning step may be performed to expose at least a portion of the first metal wiring layer 103 in the insulating layer 101 to facilitate the subsequent electrical connection step, but the present disclosure is not limited thereto. The recess R may have a bottom RB and a side RS surrounding the bottom. The bottom RB of the recess R may be located between the first portion R1 and / or the second portion R2 of the first surface 10S1 and the second surface 10S2. The side RS of the recess R may be located between the bottom RB and the first portion R1 and / or the second portion R2 of the first surface 10S1 and connect the bottom RB to the first portion R1 and / or the second portion R2 of the first surface 10S1. The side RS has a top RST and a bottom RSB. The top RST is located between the side RS and the first portion R1 and / or the second portion R2 of the first surface 10S1 and the bottom RSB is located between the side RS and the bottom RB. In some embodiments, the distance between the top RST of the side RS and the first metal wiring layer 103 in the circuit structure 10 is greater than or equal to 10 μm (≧10 μm), but the present disclosure is not limited thereto. The recess R may have a recess depth T1 in the Z direction. The distance between the bottom RB of the recess R and the first portion R1 and / or the second portion R2 of the first surface 10S1 of the circuit structure 10 may be equal to the recess depth T1. In some embodiments, in a direction perpendicular to the Z direction (e.g., the X direction), the width of the bottom RB of the recess R may be less than the width of the top of the recess R. That is, in some embodiments, in the cross-sectional view, the recess R has an inverted trapezoidal shape. In this embodiment, the angle between the side RS of the recess R and the bottom RB may be between 90° and 160°, between 105° and 155°, or between 110° and 145°. However, the present disclosure is not limited thereto.

[0101] In step S302, the second bonding component 40 may be disposed on the bottom RB of the recess R and may be disposed between the bottom surface 30B of the electronic component 30 and the bottom RB of the recess R. Methods for forming the second bonding component 40 include ball drop, electroplating, chemical plating, deposition, printing, pressurization and heating, or other suitable methods. The electronic component 30 may be disposed on the bottom RB of the recess R of the circuit structure 10 through the second bonding component 40 and may be electrically connected to the first metal circuit layer 103 of the circuit structure 10 through the second bonding component 40. According to some embodiments, the copper pillars (Cu pillars) formed on the conductive pads of the electronic component 30 and the copper pillars formed on the circuit structure 10 are combined with each other to define the second bonding component 40, and this bonding method may be referred to as Cu-Cu hybrid bonding. In some embodiments, step S302 may further include disposing a buffer layer 60 located between the electronic component 30 and the circuit structure 10 and surrounding the second bonding component 40 to reduce the risk of oxidation of the second bonding component 40 and enhance the mechanical strength between the electronic component 30 and the circuit structure 10, such as Figure 4C In some embodiments, the buffer layer 60 may be omitted.

[0102] The electronic component 30 in step S302 may have a top surface 30T, a bottom surface 30B relative to the top surface 30T, and a side surface 30S connecting the top surface 30T and the bottom surface 30B. In the Z direction, the electronic component 30 may have a height T2. In some embodiments, the height T2 may be between 5 μm and 200 μm. In some embodiments, the recess depth T1 of the recess R may be greater than or equal to the height T2 of the electronic component 30. In some embodiments, the height T2 of the electronic component 30 may be greater than the recess depth T1 of the recess R, but the present disclosure is not limited thereto. In some embodiments, the height T2 of the electronic component 30 and the recess depth T1 of the recess R meet the following relationship:

[0103] 0.1X height T2≦depression depth T1≦0.5X height T2.

[0104] The top surface 30T of the electronic component 30 disposed in the recess R may be higher than the extension line S1L of the first surface 10S1 of the circuit structure 10. That is, along the Z direction, the top surface 30T of the electronic component 30 is located between the extension line S1L of the first surface 10S1 of the circuit structure 10 and the bottom surface 30B. Figure 4C According to some embodiments, the bottom surface 30B of the electronic component 30 may be lower than the first surface 10S1 of the circuit structure 10. That is, along the Z direction, the extension line S1L of the first surface 10S1 of the circuit structure 10 is located between the top surface 30T and the bottom surface 30B of the electronic component 30.

[0105] In step S302, the electronic component 30 may be disposed in the recess R with the side surface 30S and the edge of the bottom RB of the side RS being spaced apart by a first distance D1 in a direction perpendicular to the Z direction (eg, the X direction), such as Figure 4C As shown. In some embodiments, the first distance D1 may be greater than or equal to 10μm (≥10μm) or between 10μm and 100μm. By placing the electronic component 30 in the recess R under the above conditions, the risk of the electronic component 30 being bumped or scratched during the setting of the electronic component 30 can be reduced. By placing the electronic component 30 in the recess R, the length of the RF feed line in the first metal circuit layer 103 and the height of the through hole in the Z direction can be shortened to reduce signal loss or deviation or reduce signal transmission delay. In addition, by placing the electronic component 30 in the recess R, the risk of the electronic component 30 being offset during the manufacture, transportation, or use of the electronic device can also be reduced, thereby improving the reliability of the electronic device.

[0106] In step S303, the shielding material layer 70' may be formed on the electronic component 30 and the circuit structure 10 through an electroplating process, a chemical plating process, a sputtering process, other suitable processes or any combination thereof. Specifically, the shielding material layer 70' may cover and contact the first surface 10S1 of the entire circuit structure 10, the top surface 30T and the side surface 30S of the electronic component 30, the side RS of the recess R, and the bottom RB of the recess R that does not overlap with the electronic component 30 in the Z direction, such as Figure 4D As shown. In some embodiments, the shielding material layer 70' may include a first material sublayer 703' and a second material sublayer 705', wherein the second material sublayer 705' may be located between the first material sublayer 703' and the electronic component 30, but the present disclosure is not limited thereto. The materials of the first material sublayer 703' and the second material sublayer 705' may include materials having good radio frequency radiation shielding capabilities. The first material sublayer 703' and the second material sublayer 705' may include different materials. In some embodiments, the material of the first material sublayer 703' may include copper (Cu), and the material of the second material sublayer 705' may include titanium (Ti), but the present disclosure is not limited thereto. In some embodiments, in the Z direction. The first material sublayer 703' and the second material sublayer 705' may have different thicknesses. In some embodiments, the thickness of the first material sublayer 703' may be 0.6 μm, and the thickness of the second material sublayer 705' may be 0.1 μm, but the present disclosure is not limited thereto.

[0107] In step S304, the shielding material layer 70' formed in step S303 may be patterned to form a shielding layer 70. In some embodiments, step S304 may include a patterning process of patterning the shielding material layer 70' and a shielding layer sublayer forming process of forming a first sublayer 701 on the patterned shielding material layer 70' to form the shielding layer 70.

[0108] The patterning process may include a photoresist forming process, a photoresist patterning process, an etching process, and a photoresist removing process. The photoresist forming process may include forming a photoresist layer P on the shielding material layer 70' using a dry film process and / or a wet film process. In some embodiments, the photoresist layer P and the shielding material layer 70' are conformally formed on the shielding material layer 70' and cover the entire shielding material layer 70' to reduce the impact of subsequent processes on the quality of components under the photoresist layer P, but the present disclosure is not limited thereto. Specifically, the top surface PT of the photoresist layer P corresponding to a portion of the electronic component 30 may protrude from the top surface PT of the photoresist layer P of other portions, such as Figure 4E In some embodiments, the top surface PT of the photoresist layer P of the portion corresponding to the electronic component 30 may be flush with the top surface PT of the photoresist layer P of other portions.

[0109] The photoresist layer P may be patterned by a photoresist patterning process. The photoresist patterning process may include an exposure / development process. In a direction perpendicular to the Z direction (e.g., the X direction), a side edge (not shown) of the patterned photoresist layer P may be a second distance D2 from a top RST of a side edge RS of the recess R. In some embodiments, the second distance D2 is greater than or equal to 10 μm (≧10 μm) or is between 10 μm and 100 μm.

[0110] The etching process and the photoresist removal process may include a wet etching process and / or a dry etching process. The patterned photoresist layer P may be used as a mask in the etching process, and the photoresist removal process may remove the patterned photoresist layer P. The shielding material layer 70' covered by the patterned photoresist layer P may form a patterned shielding material layer 70' after the etching process and the photoresist removal process. In the embodiment where the shielding material layer 70' includes a first material sublayer 703' and a second material sublayer 705', the patterned shielding material layer 70' may include a second sublayer 703 and a third sublayer 705, and the shielding material layer 70' not covered by the patterned photoresist layer P may only have the second material sublayer 705' after the etching process and the photoresist removal process.

[0111] In the shielding layer sub-layer formation process, the first sub-layer 701 can be formed on the patterned shielding material layer 70' through an electroplating process, a chemical plating process, a sputtering process, other suitable processes or any combination thereof to form a shielding layer 70 including the first sub-layer 701, the second sub-layer 703, and the third sub-layer 705. Figure 4FSpecifically, after the etching process and the photoresist removal process, the shielding material layer 70' not covered by the patterned photoresist layer P and the patterned shielding material layer 70' have different materials, and the first sub-layer 701 is selectively formed only on the patterned shielding material layer 70'.

[0112] The shielding layer 70 formed in step S304 may surround the electronic component 30 and fill the recess R of the circuit structure 10. Specifically, the projection of the electronic component 30 and the recess R on a plane perpendicular to the normal direction of the electronic device (e.g., the XY plane) may be located in the projection of the shielding layer 70 on the plane. In this embodiment, in a direction perpendicular to the normal direction of the electronic device (e.g., the X direction), the top RST of the side RS of the recess R and the adjacent side 70S of the shielding layer 70 may be at a second distance D2, such as Figure 4F In some embodiments, the second distance D2 is greater than or equal to 10 μm (≧10 μm) or is between 10 μm and 100 μm.

[0113] The antenna unit 50 is formed on the first surface 10S1 of the circuit structure 10 in step S305 and is electrically connected to the electronic component 30 through the circuit structure 10. The resulting structure is as shown in FIG. Figure 4G The electronic device disclosed in the present invention can be freely Figure 4G The structure shown is obtained after removing the carrier C, but the present disclosure is not limited thereto. In the embodiment where the circuit structure 10 is provided on a substrate in step S301, the electronic device of the present disclosure can be obtained directly after step S305 without removing the substrate under the circuit structure 10. The method of removing the carrier C includes degrading the release layer D by heating or irradiating light, so that the circuit structure 10 or other components can be separated from the carrier C.

[0114] In some embodiments, the manufacturing method of the electronic device of the present disclosure may further include: step S306 of disposing a first bonding component on the second surface of the circuit structure, wherein the first bonding component is electrically connected to the electronic component; and step S307 of forming a protective layer surrounding and covering the shielding layer and the electronic component, such as Figure 3 As shown. However, the present disclosure is not limited thereto. In some embodiments, any one or a combination of steps S306 to S307 may be omitted. In some embodiments, steps S306 to S307 may be performed sequentially, but the present disclosure is not limited thereto. In some embodiments, step S307 may be performed before step S306.

[0115] Step S306 may be performed after step S305. Step S306 may be performed in Figure 4GAfter the carrier C is removed from the structure shown, the first bonding component 20 is set on the second surface 10S2 of the circuit structure 10. In detail, after the carrier C is removed, a portion of the first metal circuit layer 103 can be exposed, and the exposed first metal circuit layer 103 can be regarded as an under-bump metallization (UBM), which can be used to bond with the first bonding component 20. According to some embodiments, when the carrier C does not need to be removed, the carrier C can be regarded as a substrate 90 of the electronic device, and the substrate 90 can be located between the first bonding component 20 and the electronic component 30, and can electrically connect the first bonding component 20 and the electronic component 30. Specifically, the first bonding component 20 and the electronic component 30 can be located on opposite sides of the substrate 90 and electrically connected through the second metal circuit layer 901 in the substrate 90, such as Figure 2C In some embodiments, the substrate 90 may be omitted, and the electronic device without the substrate 90 has the following features: Figure 4H The structure shown.

[0116] Step S307 of forming the protective layer 80 may be performed before or after step S306. As long as the purpose of protecting the electronic component 30 and the shielding layer 70 can be achieved and the signal receiving sensitivity of the antenna unit 50 is not affected, the step S307 of forming the protective layer 80 may include molding, laminating, coating, deposition or other suitable processes. The protective layer 80 may be formed by any suitable process.

[0117] FIG. 5A to FIG. 5D is a cross-sectional schematic diagram of an electronic device during the manufacturing process of an electronic device according to another embodiment of the present disclosure. Steps S301 to S303 in this embodiment are similar to those in reference 4A to 4D Same as described, Figure 5A is Figure 3 The cross-sectional view of the electronic device obtained after step S303 of the method for manufacturing the electronic device shown in FIG. Figure 4D The structures shown are substantially the same, so they will not be described in detail here. Figure 3 as well as FIG. 5A to FIG. 5D Steps S304 to S307 in the method for manufacturing an electronic device according to another embodiment of the present disclosure are further described.

[0118] In step S304, the shielding material layer 70' formed in step S303 may be patterned to form a shielding layer 70 having an opening O1. In some embodiments, step S304 may include a patterning process of patterning the shielding material layer 70' and a shielding layer sublayer forming process of forming a first sublayer 701 on the patterned shielding material layer 70' to form the shielding layer 70 having the opening O1.

[0119] The patterning process may include a photoresist forming process, a photoresist patterning process, an etching process, and a photoresist removing process. The photoresist forming process may include forming a photoresist layer P on the shielding material layer 70' using a dry film process and / or a wet film process. In some embodiments, the photoresist layer P is conformally formed on the shielding material layer 70' and covers the entire shielding material layer 70' to reduce the impact of subsequent processes on the quality of components under the photoresist layer P, but the present disclosure is not limited thereto. Specifically, the top surface PT of the photoresist layer P of a portion corresponding to the electronic component 30 may protrude from the top surface PT of the photoresist layer P of other portions, such as Figure 4E As shown, but the present disclosure is not limited thereto. In some embodiments, the top surface PT of the photoresist layer P of the portion corresponding to the electronic component 30 may be flush with the top surface PT of the photoresist layer P of other portions. The "A is conformally formed on B" referred to in the present disclosure means that A formed on a surface of B has a surface, the surface of A is away from the surface of B, and the surface of A and the surface of B have the same topography.

[0120] The photoresist layer P may be patterned by a photoresist patterning process. The photoresist patterning process may include an exposure / development process. The patterned photoresist layer P may have an opening O2. The opening O2 may expose a portion of the shielding material layer 70' located on the top surface 30T of the electronic component 30, such as Figure 5B As shown. According to some embodiments, each sub-layer of the shielding material layer 70' may be patterned sequentially through multiple patterning processes to form a shielding layer 70 having an opening O1. According to some embodiments, each sub-layer of the shielding material layer 70' may be patterned through a single patterning process to form a shielding layer 70 having an opening O1. In a direction perpendicular to the Z direction (e.g., the X direction), the side PS of the patterned photoresist layer P may be a second distance D2 from the top RST of the side RS of the recess R. In some embodiments, the second distance D2 is greater than or equal to 10μm (≧10μm) or is between 10μm and 100μm.

[0121] The etching process and the photoresist removal process may include a wet etching process and / or a dry etching process. The patterned photoresist layer P may be used as a mask in the etching process, and the photoresist removal process may remove the patterned photoresist layer P. The shielding material layer 70' covered by the patterned photoresist layer P may form a patterned shielding material layer 70' after the etching process and the photoresist removal process. In the embodiment where the shielding material layer 70' includes a first material sublayer 703' and a second material sublayer 705', the patterned shielding material layer 70' may include a second sublayer 703' and a third sublayer 705', and the shielding material layer 70' not covered by the patterned photoresist layer P may only have the second material sublayer 705' after the etching process and the photoresist removal process. In other words, the patterned shielding material layer 70' may include a material layer opening corresponding to the opening O2. The second material sublayer 705' is disposed in the material layer opening.

[0122] In the shielding layer sub-layer formation process, the first sub-layer 701 can be formed on the patterned shielding material layer 70' through an electroplating process, a chemical plating process, a sputtering process, other suitable processes or any combination thereof to form a shielding layer 70 including the first sub-layer 701, the second sub-layer 703, and the third sub-layer 705. Figure 5C As shown, but the present disclosure is not limited thereto. In some embodiments, Figure 5C The first sublayer 701 of the shielding layer 70 shown may have a first gap G1 between it and the electronic component 30. Specifically, the first gap G1 may be between the bottom surface of the first sublayer 701 and the top surface 30T of the electronic component 30. In some embodiments, the first gap G1 may be between 0.1 μm and 0.5 μm, but the present disclosure is not limited thereto.

[0123] The shielding layer 70 formed in step S304 may surround the electronic component 30 and fill the recess R of the circuit structure 10. Specifically, the projection of the electronic component 30 and the recess R on a plane perpendicular to the normal direction of the electronic device (e.g., the XY plane) may be located in the projection of the shielding layer 70 on the plane. In this embodiment, in a direction perpendicular to the normal direction of the electronic device (e.g., the X direction), the top RST of the side RS of the recess R and the adjacent side 70S of the shielding layer 70 may be at a second distance D2, such as Figure 5C In some embodiments, the second distance D2 is greater than or equal to 10 μm (≧10 μm) or is between 10 μm and 100 μm.

[0124] The antenna unit 50 is formed on the first surface 10S1 of the circuit structure 10 in step S305 and is electrically connected to the electronic component 30 through the circuit structure 10. The resulting structure is as shown in FIG. Figure 5D The electronic device disclosed in the present invention can be freely Figure 5DThe structure shown is obtained after removing the carrier C, but the present disclosure is not limited thereto. In the embodiment where the circuit structure 10 is provided on a substrate in step S301 , the electronic device of the present disclosure can be obtained directly after step S305 without removing the substrate under the circuit structure 10 .

[0125] In some embodiments, the manufacturing method of the electronic device of the present disclosure may further include: step S306 of disposing a first bonding component on the second surface of the circuit structure, wherein the first bonding component is electrically connected to the electronic component; and step S307 of forming a protective layer surrounding and covering the shielding layer and the electronic component, such as Figure 3 As shown. However, the present disclosure is not limited thereto. In some embodiments, any one or a combination of steps S306 to S307 may be omitted. In some embodiments, steps S306 to S307 may be performed in sequence, but the present disclosure is not limited thereto. In some embodiments, step S307 may be performed before step S306.

[0126] Step S306 can be performed after step S305. Figure 5D After the carrier C is removed from the structure shown, the first bonding component 20 is set on the second surface 10S2 of the circuit structure 10. In detail, after removing the carrier C, a portion of the first metal circuit layer 103 can be exposed, and the exposed first metal circuit layer 103 can be regarded as an under-bump metallization (UBM), which can be used to bond with the first bonding component 20. According to some embodiments, when the carrier C does not need to be removed, the carrier C can be regarded as a substrate 90 of the electronic device, and the substrate 90 can be located between the first bonding component 20 and the electronic component 30, and can electrically connect the first bonding component 20 and the electronic component 30. Specifically, the first bonding component 20 and the electronic component 30 can be located on opposite sides of the substrate 90 and electrically connected through the second metal circuit layer 901 in the substrate 90, but the present disclosure is not limited thereto. In some embodiments, the substrate 90 can be omitted, and the electronic device without the substrate 90 has the following features: Figure 5D The structure shown.

[0127] Step S307 of forming the protective layer 80 may be performed before step S306 or after step S306. There is no specific limitation on step S307 of forming the protective layer 80 as long as the purpose of protecting the electronic component 30 and the shielding layer 70 can be achieved and the signal receiving sensitivity of the antenna unit 50 is not affected. The protective layer 80 may be formed by any suitable process.

[0128] The electronic device manufactured according to the manufacturing method of the above-mentioned electronic device disclosed in the present invention includes an electronic component disposed in a recess of the circuit structure, and the electronic component can be disposed on the same side of the circuit structure as the antenna unit. The electronic device manufactured according to the manufacturing method of the above-mentioned electronic device disclosed in the present invention can therefore have a better heat dissipation effect and / or reliability. In addition, when the electronic device disclosed in the present invention is used in a device for transmitting or receiving radio waves, the signal reception sensitivity can be improved through the above-mentioned design, so that the electronic device has a stronger efficiency and directivity, but is not limited to this.

[0129] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present disclosure. As long as the same functions can be implemented in the embodiments described herein or the same results can be obtained, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each embodiment can replace, reorganize and mix the features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features between the embodiments can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict. Each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. An electronic device, characterized in that: include: A circuit structure having a first surface and a second surface opposite to the first surface, wherein the first surface has a first portion, a second portion and a third portion, the third portion connecting the first portion and the second portion, wherein along the normal direction of the electronic device, the first portion and the second portion are farther away from the second surface than the third portion to form a recess; An electronic component is disposed in the recess and is electrically connected to the circuit structure; an antenna unit, correspondingly disposed on at least one of the first portion and the second portion of the first surface, and the antenna unit is electrically connected to the electronic component through the circuit structure; and A shielding layer surrounds the electronic component.

2. The electronic device according to claim 1, wherein: The recess has a bottom and a side connected to the bottom. In a cross-sectional view, an angle between the side of the recess and the bottom is between 90° and 160°.

3. The electronic device according to claim 1, wherein: Also includes: A second bonding component is located between the electronic component and the circuit structure, and the electronic component is electrically connected to the circuit structure through the second bonding component; and The buffer layer is located between the electronic component and the circuit structure and surrounds the second bonding component.

4. The electronic device according to claim 1, wherein: The recess has a bottom and a side connected to the bottom. The bottom end of the side of the recess is at a first distance from the side of the adjacent electronic component. The first distance is greater than or equal to 10 μm and less than or equal to 100 μm.

5. The electronic device according to claim 1, wherein: The recess has a bottom and a side connected to the bottom. The top of the side of the recess is at a second distance from the adjacent side of the shielding layer. The second distance is greater than or equal to 10 μm and less than or equal to 100 μm.

6. A method for manufacturing an electronic device, characterized in that: The following steps are involved: A circuit structure is provided, wherein the circuit structure has a first surface and a second surface opposite to the first surface, wherein the first surface has a first portion, a second portion and a third portion, the third portion connects the first portion and the second portion, wherein along the normal direction of the electronic device, the first portion and the second portion are farther away from the second surface than the third portion to form a recess; Disposing an electronic component in the recess of the circuit structure, wherein the electronic component is electrically connected to the circuit structure; forming a shielding material layer on the electronic component and the circuit structure; patterning the shielding material layer to form a shielding layer, wherein the shielding layer surrounds the electronic component; and An antenna unit is disposed on the first surface of the circuit structure, wherein the antenna unit is electrically connected to the electronic component through the circuit structure.

7. The method for manufacturing an electronic device according to claim 6, wherein: The recess has a bottom and a side connected to the bottom. The bottom end of the side of the recess is at a first distance from the side of the adjacent electronic component. The first distance is greater than or equal to 10 μm.

8. The method for manufacturing an electronic device according to claim 6, wherein: The recess has a bottom and a side surrounding the bottom. A top of the side of the recess is at a second distance from a side of the adjacent shielding layer. The second distance is greater than or equal to 10 μm.

9. The method for manufacturing an electronic device according to claim 6, wherein: The method further includes forming a protection layer surrounding and covering the shielding layer and the electronic component.

10. The method for manufacturing an electronic device according to claim 6, wherein: The step of forming the shielding layer includes a shielding layer sub-layer forming process of further forming a first sub-layer on the patterned shielding material layer after patterning the shielding material layer.

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