Semiconductor device, memory system, and electronic apparatus

Abstract

The invention discloses a semiconductor device, a storage system and electronic equipment. The semiconductor device includes a stacked structure; the stacking structure comprises a plurality of stacking parts which are arranged in a stacked mode, and each stacking part comprises a switching layer and a chip arranged on the switching layer; wherein the chips in the stacking parts are electrically connected with the switching layers, and the chips in the adjacent stacking parts are electrically connected through the switching layers. According to the invention, the electrical connection between the chips is more flexible, and more requirements of the semiconductor device can be met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a storage system and an electronic device. Background Art

[0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D non-or) flash memory and 3D NAND (3D non-and) flash memory.

[0003] Among them, 3D NAND memory takes its small size and large capacity as its starting point, and uses a highly integrated design concept of stacking storage units in a three-dimensional mode to produce memory with high storage density per unit area and efficient storage unit performance. It has become the mainstream process for the design and production of emerging memories.

[0004] However, in current memories, due to the single connection method between storage units, more memory requirements cannot be met. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device, a storage system, and an electronic device, which can increase the diversity of connections between stacked parts and meet more requirements of semiconductor devices.

[0006] An embodiment of the present application provides a semiconductor device, comprising:

[0007] A stacking structure, comprising a plurality of stacking parts stacked in layers, wherein the stacking parts include a transfer layer and a chip arranged on the transfer layer;

[0008] The chips in the stacking part are electrically connected to the transfer layer, and the chips in adjacent stacking parts are electrically connected via the transfer layer.

[0009] In some embodiments of the present application, connecting leads are provided in the transfer layer, a first contact structure is provided on a side of the chip close to the transfer layer, and in the stacking portion, the first contact structure is connected to the connecting leads of the transfer layer.

[0010] In some embodiments of the present application, between two adjacent stacking parts, the chip of one stacking part is arranged close to the transfer layer of another stacking part;

[0011] Wherein, a second contact structure is arranged between two adjacent stacking parts, and the second contact structure is connected to the chip and the connecting lead.

[0012] In some embodiments of the present application, in the stacking section, a plurality of the chips are arranged on the transfer layer, and between two adjacent stacking sections, one of the chips in one of the stacking sections is electrically connected to any one of the plurality of chips in the other stacking section.

[0013] In some embodiments of the present application, the connecting lead includes a first lead disposed in the transfer layer and extending along a first direction, and the first direction is parallel to a stacking direction of the plurality of stacking portions.

[0014] In some embodiments of the present application, the connecting lead further includes a second lead disposed in the transfer layer and extending along a second direction, and the second direction intersects with the first direction.

[0015] In some embodiments of the present application, the transfer layer includes a plurality of dielectric sub-layers, and the first lead passes through at least one of the dielectric sub-layers along the first direction, and the second lead is located between adjacent dielectric sub-layers.

[0016] In some embodiments of the present application, the material of the transfer layer includes at least one of a silicon material, a silicon nitride material and a resin material, and the material of the connecting lead includes a conductive metal material.

[0017] In some embodiments of the present application, the semiconductor device further includes an external connection lead, and the external connection lead is connected between two transfer layers in any two of the stacking parts.

[0018] In some embodiments of the present application, the semiconductor device further includes a substrate, the stacking structure is disposed on the substrate, and the external lead is connected between the substrate and the transfer layer of at least one of the stacking parts.

[0019] In some embodiments of the present application, the semiconductor device further comprises a first connector, the first connector being disposed between the substrate and the stacking structure, and the plurality of stacking portions comprising a bottom stacking portion close to a surface of the substrate;

[0020] Wherein, in each of the stacking parts, the transfer layer is located between the chip and the substrate, and the transfer layer in the bottom stacking part is connected to the first connecting member.

[0021] In some embodiments of the present application, the semiconductor device also includes an opposing substrate arranged on a side of the stacking structure away from the substrate, and a second connecting member is arranged in the opposing substrate, and the external lead is connected between the second connecting member and the transfer layer of at least one of the stacking parts.

[0022] In some embodiments of the present application, the chip includes a storage array and / or a peripheral circuit, wherein the peripheral circuit is coupled to the storage array and is used to control the storage array to store data.

[0023] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a storage system, which includes a controller and the semiconductor device, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0024] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides an electronic device, comprising the storage system.

[0025] The embodiments of the present application provide a semiconductor device, a storage system and an electronic device. A stacking part is set in a stacking structure, and the stacking part includes a transfer layer and a chip. The chip is electrically connected to the transfer layer, and the chips in multiple stacking parts can be electrically connected through the transfer layer. This makes the electrical connection between the chips more flexible and can meet more requirements of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0027] Figure 1 A schematic diagram of a structure of a semiconductor device provided in some embodiments;

[0028] Figure 2 A schematic diagram of a structure of a semiconductor device provided for some embodiments of the present application;

[0029] Figure 3 Another structural schematic diagram of a semiconductor device provided for some embodiments of the present application;

[0030] Figure 4 A schematic diagram of a structure of a transfer layer provided for some embodiments of the present application;

[0031] Figure 5 Another structural schematic diagram of a transfer layer provided for some embodiments of the present application;

[0032] Figure 6 A structural schematic diagram of a storage system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0035] Please refer to Figure 1 In some embodiments, the semiconductor device includes a substrate 1 and a plurality of memory cells 2 disposed on the substrate 1 and stacked in a vertical direction, and the plurality of memory cells 2 are directly connected through leads 3. This connection method between single memory cells cannot meet more requirements of the memory, for example, it is not conducive to improving the integration.

[0036] Please refer to Figure 2 Some embodiments of the present application provide a semiconductor device, which includes a stacking structure, wherein the stacking structure includes a plurality of stacking parts 10 stacked in layers, and the stacking part 10 includes a transfer layer 12 and a chip 11 arranged on the transfer layer 12.

[0037] Furthermore, the chips 11 in the stacking part 10 are electrically connected to the transfer layer 12 , and the chips 11 in adjacent stacking parts 10 are electrically connected via the transfer layer 12 .

[0038] In the embodiment of the present application, a stacking part 10 is arranged in the stacking structure, and the stacking part 10 includes a transfer layer 12 and a chip 11, and the chip 11 is electrically connected to the transfer layer 12, and the chips 11 in multiple stacking parts 10 can be electrically connected through the transfer layer 12, so that the electrical connection between the chips 11 is more flexible, which can meet more requirements of semiconductor devices and is conducive to improving the integration of chips in semiconductor devices.

[0039] For details, please refer to Figure 2An embodiment of the present application provides a semiconductor device, which includes a substrate 31 and an opposing substrate 32 that are arranged opposite to each other, and a stacking structure arranged between the substrate 31 and the opposing substrate 32, and the stacking structure is arranged on a side of the substrate 31 close to the opposing substrate 32.

[0040] The stacking structure includes a plurality of stacking parts 10 stacked along a first direction M, the first direction M is perpendicular to the substrate 31, and the stacking direction of the plurality of stacking parts 10 in the first direction M; each stacking part 10 includes a transfer layer 12 and a chip 11 arranged on the transfer layer 12, and in each stacking part 10, the chip 11 is electrically connected to the transfer layer 12, and at the same time, the chips 11 in adjacent stacking parts 10 are also electrically connected through the transfer layer 12; it can be understood that the embodiment of the present application adds a transfer layer 12 in the stacking part 10, and the chips 11 can be electrically connected through the transfer layer 12, relative to Figure 1 In the semiconductor device shown, connection is made directly on the chip 11. In the semiconductor device provided in the embodiment of the present application, the connection method of the stacking part 10 is relatively flexible. The added transfer layer 12 has more ample design space and wiring space, which can increase the number and integration of chips 11 in the stacking part 10 and meet more demands.

[0041] In some embodiments, chip 11 includes a memory array and / or a peripheral circuit, wherein the peripheral circuit is coupled to the memory array and is used to control the memory array to store data.

[0042] Furthermore, a connecting lead 120 is provided in the transfer layer 12. In each stacking part 10, the transfer layer 12 is located between the chip 11 and the substrate 31. A first contact structure 13 is provided on the side of the chip 11 close to the transfer layer 12, and the first contact structure 13 is connected to the connecting lead 120 in the transfer layer 12 to realize the electrical connection function between the chip 11 and the transfer layer 12.

[0043] In some embodiments, the material of the transfer layer 12 includes at least one of a silicon material, a silicon nitride material, and a resin material, and the material of the connecting lead 120 includes a conductive metal material, such as gold, copper, or aluminum.

[0044] In some embodiments, Figure 3 As shown, between two stacking parts 10 adjacent to each other along the first direction M, the chip 11 of one stacking part 10 is arranged close to the transfer layer 12 of the other stacking part 10, and a second contact structure 14 is arranged on the side of the chip 11 in one stacking part 10 close to the transfer layer 12 in the other stacking part 10, and the second contact structure 14 is connected to the chip 11 and the connecting lead 120 in the transfer layer 12, thereby realizing the electrical connection function between the chips 11 in adjacent stacking parts 10.

[0045] In some embodiments, please refer to Figure 2 The semiconductor device also includes an external lead 20, and the external lead 20 is connected between two transfer layers 12 in any two stacking parts 10, and the external lead 20 can also be connected between the transfer layer 12 and the substrate 31 in any stacking part 10, that is, the embodiment of the present application can also realize the electrical connection between the chips 11 in any two stacking parts 10 through the external lead 20, further improving the connection flexibility between multiple stacking parts 10 and the diversity of signal transmission.

[0046] Furthermore, the semiconductor device also includes a first connecting structure 41 arranged between the substrate 31 and the stacking structure, and a second connecting structure 42 is arranged in the opposing substrate 32; wherein, the multiple stacking parts 10 include a bottom stacking part close to the surface of the substrate 31, and the transfer layer 12 in the bottom stacking part is connected to the first connecting structure 41, and the transfer layer 12 in any stacking part 10 can be connected to the second connecting member 42 through an external lead 20.

[0047] It should be noted that a third connection structure 43 is also provided on the side of the substrate 31 away from the stacking structure, and the stacking structure in the semiconductor device can also be connected to an external device through the third connection structure 43 to achieve signal transmission; in other embodiments of the present application, a fourth connection structure (not shown in the figure) can also be provided on the side of the opposing substrate 32 away from the stacking structure, and the stacking structure in the semiconductor device can also be connected to an external device through the fourth connection structure to achieve signal transmission.

[0048] As mentioned above, in some embodiments of the present application, the external lead 20 is connected to the transfer layer 12 in the stacking part 10, and a contact structure such as a pad can be set on the transfer layer 12, and the external lead 20 and the pad on the transfer layer 12 can be connected by wire bonding (Wire Bonding, WB); similarly, the connection between the external lead 20 and the substrate 31 and the opposing substrate 32 can also be connected by wire bonding (Wire Bonding, WB); compared with the high-temperature bonding used in the related art that easily causes the wafer to warp and crack, the embodiments of the present application can not only realize flexible connection between multiple stacking parts 10, but also simplify the connection method and improve the yield rate of the stacking part 10.

[0049] In some embodiments of the present application, each stacking unit 10 includes a plurality of chips 11 ( Figure 2Taking two as an example), that is, in each stacking part 10, multiple chips 11 can be arranged on the same transfer layer 12, so as to increase the number of integrated chips 11 in the semiconductor device and improve the integration of the semiconductor device; it should be noted that between two adjacent stacking parts 10, any chip 11 in one stacking part 10 can be connected to any one of the multiple chips 11 in the other stacking part 10, so as to further improve the connection diversity and flexibility between the multiple chips 11 in the semiconductor device.

[0050] For example Figure 2 In the embodiment, the chip 11 on the left side of the bottom stacking part 10 can be electrically connected to the chip 11 on the right side of the second stacking part 10 , which can be achieved by arranging the connecting leads 120 in the transfer layer 12 .

[0051] In some embodiments, please combine Figure 2 and Figure 4 The connecting lead 120 includes a first lead 1201 extending along the first direction M and arranged in the transfer layer 12, and the chips 11 of two adjacent stacking parts 10 are connected through the connecting lead 120, and the first lead 1201 passes through the transfer layer 12 along the first direction M.

[0052] In some embodiments, please combine Figure 2 and Figure 5 The connecting lead 120 includes a first lead 1201 extending along a first direction M and disposed in the transfer layer 12 , and a second lead 1202 extending along a second direction N and disposed in the transfer layer 12 , and the second direction N intersects with the first direction M.

[0053] Optionally, the second direction N is perpendicular to the first direction M.

[0054] The transfer layer 12 includes a plurality of dielectric sublayers 121 stacked along a first direction M, wherein a first lead 1201 passes through at least one dielectric sublayer 121 along the first direction M, and a second lead 1202 is located between adjacent dielectric sublayers 121, and thus first leads 1201 located at different positions of the transfer layer 12 and staggered along the first direction M can be connected via the second lead 1202.

[0055] It should be noted that the connecting leads may also include auxiliary leads (not shown in the figure) arranged on the opposite side surfaces of the transfer layer 12, and one end of the auxiliary lead is connected to the first lead 1201, and the other end is connected to the chip 11 on the transfer layer 12, so as to realize the function of signal transmission of the chip 11 through the transfer layer 12; in addition, the auxiliary lead can also be connected between the solder pad on the transfer layer 12 and the chip 11, so as to realize the function of signal transmission of the chip 11 through the external connection lead 20 connected to the transfer layer 12.

[0056] As mentioned above, in the embodiment of the present application, a stacking part 10 is arranged in the stacking structure, and the stacking part 10 includes a transfer layer 12 and a chip 11, and the chip 11 is electrically connected to the transfer layer 12, and the chips 11 in multiple stacking parts 10 can be electrically connected through the transfer layer 12, so that the electrical connection between the chips 11 is more flexible, which can meet more requirements of semiconductor devices and is conducive to improving the integration of chips in semiconductor devices.

[0057] In addition, the present application also provides a storage system, please refer to Figure 6 The storage system 50 includes a controller 51 and a semiconductor device 52. The controller 51 is coupled to the semiconductor device 52 and is used to control the semiconductor device 52 to store data. The semiconductor device 52 is a semiconductor device 52 manufactured by the manufacturing method of the semiconductor device 52 described in the above embodiment or the semiconductor device 52 described in the above embodiment.

[0058] It can be understood that the semiconductor device 52 can be a memory or a part of a memory.

[0059] Specifically, the controller 51 may control the semiconductor device 52 through the channel CH, and the semiconductor device 52 may perform an operation based on the control of the controller 51 in response to a request from the host 60. The semiconductor device 52 may receive a command CMD and an address ADDR from the controller 51 through the channel CH and access an area selected from the memory array in response to the address. In other words, the semiconductor device 52 may perform an internal operation corresponding to the command on the area selected by the address.

[0060] In some embodiments, the storage system 50 may be implemented as a storage device including but not limited to a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0061] Specifically, the storage system 50 can be used in terminal products such as computers, televisions, set-top boxes, and vehicles.

[0062] In addition, an embodiment of the present application further provides an electronic device, which includes the storage system described in the above embodiment.

[0063] The electronic device includes the storage system described in the above embodiment. Specifically, the electronic device can be any device that can store data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, etc.

[0064] Some embodiments of the present application provide an electronic device, which has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided by some embodiments of the present application.

[0065] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0066] The semiconductor device, storage system and electronic device provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A stacking structure, comprising a plurality of stacking parts stacked in layers, wherein the stacking parts include a transfer layer and a chip arranged on the transfer layer; The chips in the stacking part are electrically connected to the transfer layer, and the chips in adjacent stacking parts are electrically connected via the transfer layer.

2. The semiconductor device according to claim 1, wherein: The transfer layer is provided with connecting leads, a side of the chip close to the transfer layer is provided with a first contact structure, and in the stacking portion, the first contact structure is connected to the connecting leads of the transfer layer.

3. The semiconductor device according to claim 2, characterized in that Between two adjacent stacking parts, the chip of one stacking part is arranged close to the transfer layer of the other stacking part; Wherein, a second contact structure is arranged between two adjacent stacking parts, and the second contact structure is connected to the chip and the connecting lead.

4. The semiconductor device according to claim 3, characterized in that In the stacking part, a plurality of the chips are arranged on the transfer layer, and between two adjacent stacking parts, one of the chips in one of the stacking parts is electrically connected to any one of the plurality of chips in the other stacking part.

5. The semiconductor device according to claim 3, characterized in that The connecting lead includes a first lead which is arranged in the transfer layer and extends along a first direction, and the first direction is parallel to a stacking direction of the plurality of stacking parts.

6. The semiconductor device according to claim 5, characterized in that The connecting lead also includes a second lead which is arranged in the transfer layer and extends along a second direction, and the second direction intersects with the first direction.

7. The semiconductor device according to claim 6, characterized in that The transfer layer includes a plurality of dielectric sub-layers, and the first lead passes through at least one of the dielectric sub-layers along the first direction, and the second lead is located between adjacent dielectric sub-layers.

8. The semiconductor device according to claim 2, wherein: The material of the transfer layer includes at least one of a silicon material, a silicon nitride material and a resin material, and the material of the connecting lead includes a conductive metal material.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises an external connection lead connected between two transfer layers in any two of the stacking parts.

10. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises a substrate, the stacking structure is arranged on the substrate, and the external connection lead is connected between the substrate and the transfer layer of at least one of the stacking parts.

11. The semiconductor device according to claim 10, characterized in that The semiconductor device further comprises a first connector, the first connector being disposed between the substrate and the stacking structure, the plurality of stacking portions comprising a bottom stacking portion close to the surface of the substrate; Wherein, in each of the stacking parts, the transfer layer is located between the chip and the substrate, and the transfer layer in the bottom stacking part is connected to the first connecting member.

12. The semiconductor device according to claim 10, characterized in that The semiconductor device further comprises an opposing substrate disposed on a side of the stacking structure away from the substrate, and a second connecting member is disposed in the opposing substrate, and the external connecting lead is connected between the second connecting member and the transfer layer of at least one of the stacking parts.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that: The chip includes a memory array and / or a peripheral circuit, wherein the peripheral circuit is coupled to the memory array and is used to control the memory array to store data.

14. A storage system, characterized in that: The storage system comprises a controller and the semiconductor device according to any one of claims 1 to 13, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

15. An electronic device, characterized in that: Includes the storage system as claimed in claim 14.

Images