Semiconductor memory device and electronic system including same

Abstract

A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device includes a cell array structure and a peripheral circuit structure. The unit array structure comprises a first stacking structure, a second stacking structure on the first stacking structure and a third stacking structure on the second stacking structure; each of the first to third stacked structures includes a plurality of word lines. A vertical channel structure extending into the first to third stack structures; and a second cell contact plug extending into the first to third stack structures and connected to the second contact plug at an end of the second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stacked structure and the second stacked structure.

Description

[0001] This patent application claims the priority of Korean Patent Application No. 10-2023-0102332 filed in the Korean Intellectual Property Office on August 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention generally relates to a semiconductor memory device, a method for manufacturing the semiconductor memory device, and an electronic system including the semiconductor memory device, and more specifically, to a semiconductor memory device including a peripheral circuit structure and a cell array structure coupled to each other via a bonding pad (also called a "bonding pad"), a method for manufacturing the semiconductor memory device, and an electronic system including the semiconductor memory device. Background Art

[0003] A semiconductor device capable of storing a large amount of data may be required as part of an electronic system. A higher integration of semiconductor devices may be required to meet consumer demand for large data storage capacity, excellent performance and low price. In the case of two-dimensional or planar semiconductor devices, since their integration can be mainly determined by the area occupied by the unit memory cell, the integration level will be affected by the level of fine pattern forming technology. However, extremely expensive process equipment may be required to improve the pattern fineness, and practical limitations will be set on improving the integration level of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell has recently been proposed. Summary of the invention

[0004] An object of the inventive concept is to provide a three-dimensional semiconductor memory device having improved electrical characteristics and reliability and a method of manufacturing the same.

[0005] An object of the inventive concept is to provide a three-dimensional semiconductor memory device and a method of manufacturing the same capable of simplifying a process.

[0006] Problems to be solved by the inventive concept are not limited to the above-mentioned problems, and the present disclosure may provide other problems for which solutions are not explicitly discussed herein, which may become clear to those skilled in the art from the following description.

[0007] A semiconductor memory device according to some embodiments of the inventive concept may include a cell array structure and a peripheral circuit structure. The cell array structure may include: a first stack structure, a second stack structure on the first stack structure, and a third stack structure on the second stack structure, each of the first stack structure to the third stack structure including a plurality of word lines; a vertical channel structure penetrating (i.e., extending to or passing through) the first stack structure to the third stack structure; and a second cell contact plug extending into the first stack structure to the third stack structure and connected to a second contact pad at an end of a second word line in the second stack structure, and the second cell contact plug may include a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure.

[0008] The semiconductor memory device according to some embodiments of the present invention may include a peripheral circuit structure and a cell array structure on the peripheral circuit structure. The cell array structure may include a semiconductor layer, a first stacking structure on the semiconductor layer, a second stacking structure on the first stacking structure, and a third stacking structure on the second stacking structure, wherein the first stacking structure to the third stacking structure are arranged between the semiconductor layer and the peripheral circuit structure and each includes a plurality of word lines. The cell array structure may also include a vertical channel structure extending into the first stacking structure to the third stacking structure, a first cell contact plug extending into the first stacking structure to the third stacking structure and connected to the first contact pad at the end of the first word line in the first stacking structure, a second cell contact plug extending into the first stacking structure to the third stacking structure and connected to the second contact pad at the end of the second word line in the second stacking structure, and a third cell contact plug extending into the first stacking structure to the third stacking structure and connected to the third contact pad at the end of the third word line in the third stacking structure. The second cell contact plug may include a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stacking structure and the second stacking structure.

[0009] An electronic system according to some embodiments of the inventive concept may include a three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device including: a peripheral circuit structure and a cell array structure disposed on the peripheral circuit structure, the cell array structure including a cell array region and a cell array contact region; and a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad and controlling the three-dimensional semiconductor memory device. The cell array structure may also include: a first stack structure, a second stack structure, and a third stack structure, each including a plurality of word lines; a vertical channel structure penetrating the first stack structure to the third stack structure; and a second cell contact plug penetrating the first stack structure to the third stack structure and penetrating a second contact pad at an end of a second word line disposed in the second stack structure, and the second cell contact plug may include a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements throughout the several views.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0011] Figure 1 is a schematic diagram illustrating an example electronic system including a three-dimensional semiconductor memory device according to one or more embodiments of the inventive concept.

[0012] Figure 2 is a perspective view schematically illustrating an example electronic system including a three-dimensional semiconductor memory device according to one or more embodiments of the inventive concept.

[0013] Figure 3 and Figure 4 are respectively along Figure 2 sectional views taken along line II′ and line II-II′ of FIG. 1 to illustrate a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0014] Figure 5 is a top plan view showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, and is based on Figure 8 Floor plan of LV1.

[0015] Figure 6 is a top plan view showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, and is based on Figure 8 The floor plan of LV2.

[0016] Figure 7is a top plan view showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, and is based on Figure 8 The floor plan of LV3.

[0017] Figure 8 FIG. 2 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 5 A cross-sectional view taken along line II'.

[0018] Fig. 9 yes Figure 8 An enlarged view of a region “ZR” of a three-dimensional semiconductor memory device is shown in FIG.

[0019] Fig.10 yes Figure 8 An enlarged view of region “R” of the three-dimensional semiconductor memory device shown in FIG.

[0020] Fig.11 , Figures 15 to 18 and Figure 23 to Figure 24 It is along Figure 5 A cross-sectional view taken along line II′ of FIG. 1 illustrates an intermediate process in an example method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0021] Figure 12 to Figure 14 yes Fig.11 An enlarged cross-sectional view of area “Q1” in FIG.

[0022] Figures 19 to 22 yes Fig.18 An enlarged cross-sectional view of area “Q2” in FIG. DETAILED DESCRIPTION

[0023] Hereinafter, a semiconductor memory device, a method of manufacturing the same, and an electronic system including the same according to embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a schematic diagram illustrating an example electronic system including a three-dimensional semiconductor memory device according to one or more embodiments of the inventive concept.

[0025] Reference Figure 1, the electronic system 1000 according to some embodiments of the inventive concept may include a semiconductor memory device 1100 and a controller 1200 electrically connected to each other. As may be used herein, the term "connection" (and its variations, or similar terms) is intended to refer to a physical connection and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. The electronic system 1000 may be or may include a storage device including one or more semiconductor memory devices 1100 and / or an electronic device including the storage device. For example, the electronic system 1000 may be or may include at least one of a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, and a communication system in which at least one semiconductor memory device 1100 is provided.

[0026] The three-dimensional semiconductor memory device 1100 may be a nonvolatile memory device, and may be, for example, a three-dimensional NAND flash memory device. The three-dimensional semiconductor memory device 1100 may include a first region 1100F and a second region 1100S on the first region 1100F. However, unlike the example shown in the drawings, the first region 1100F may optionally be disposed on one side of the second region 1100S. The first region 1100F may be, for example, a peripheral circuit region including a decoder 1110, a page buffer 1120, and a logic circuit 1130. The second region 1100S may be a memory cell region including a bit line BL, a common source line CSL, a word line WL, first lines LL1 and LL2, second lines UL1 and UL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0027] In the second region 1100S, each of the memory cell strings CSTR may include first transistors LT1 and LT2 adjacent to the common source line CSL, second transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the first transistors LT1 and LT2 and the second transistors UT1 and UT2. According to an embodiment, the number of the first transistors LT1 and LT2 and the number of the second transistors UT1 and UT2 may be changed differently; furthermore, the number of the first transistors LT1 and LT2 need not be the same as the number of the second transistors UT1 and UT2. The memory cell string CSTR may be positioned between the common source line CSL and the first region 1100F.

[0028] For example, the second transistors UT1 and UT2 may include string selection transistors, and the first transistors LT1 and LT2 may include ground selection transistors. The first lines LL1 and LL2 may be used as gate electrodes of the first transistors LT1 and LT2. The word line WL may be used as a gate electrode of the memory cell transistor MCT, and the second lines UL1 and UL2 may be used as gate electrodes of the second transistors UT1 and UT2.

[0029] The common source line CSL, the first lines LL1 and LL2, the word lines WL, and the second lines UL1 and UL2 may be electrically connected to the decoder 1110 through the first interconnection line 1115 extending between the first region 1100F and the second region 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second interconnection line 1125 extending between the first region 1100F and the second region 1100S.

[0030] In the first region 1100F, the decoder 1110 and the page buffer 1120 may be configured to control a control operation performed on at least one selected memory cell transistor among the memory cell transistors MCT. The decoder 1110 and / or the page buffer 1120 may be at least partially controlled by the logic circuit 1130. The three-dimensional semiconductor memory device 1100 may communicate with the controller 1200 through one or more input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through one or more corresponding input / output interconnection lines 1135 extending between the first region 1100F and the second region 1100S.

[0031] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface (I / F) 1230 . In an embodiment, the electronic system 1000 may include a plurality of three-dimensional semiconductor memory devices 1100 , in which case the controller 1200 may control the plurality of three-dimensional semiconductor memory devices 1100 .

[0032] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. Based on a specific firmware, the processor 1210 may perform operations of controlling the NAND controller 1220 and accessing the three-dimensional semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that may be used to communicate with the three-dimensional semiconductor memory device 1100. The NAND interface 1221 may be used to send and / or receive control commands to control the three-dimensional semiconductor memory device 1100, data to be written to or read from the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100, and the like. The host interface 1230 may be configured to allow communication between the electronic system 1000 and an external host (not explicitly shown). When a control command is provided from the external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0033] Figure 2 is a perspective view schematically illustrating an example electronic system including a three-dimensional semiconductor memory device according to one or more embodiments of the inventive concept.

[0034] Reference Figure 2 , the electronic system 2000 may include a main substrate 2001 and a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 and to each other through an interconnection pattern 2005 that may be provided in the main substrate 2001.

[0035] The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host (not explicitly shown). In the connector 2006, the number and arrangement of the pins may vary according to the type (e.g., protocol) of the communication interface between the electronic system 2000 and the external host. For example, the electronic system 2000 may communicate with the external host according to one or more interfaces such as a universal serial bus (USB), a peripheral component express interconnect (PCI-Express), a serial advanced technology attachment (SATA), a universal flash memory (UFS) M-PHY, etc. In an embodiment, the electronic system 2000 may be driven by power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for separately supplying power provided from an external host to the controller 2002 and the semiconductor package 2003.

[0036] The controller 2002 may control write and / or read operations on the semiconductor package 2003 and may improve the operation speed of the electronic system 2000 .

[0037] The DRAM 2004 may be a buffer memory that reduces technical difficulties caused by a speed difference between the semiconductor package 2003 used as a data storage device and an external host. The DRAM 2004 in the electronic system 2000 may be used as a high-speed cache memory and may provide a storage space in which data may be temporarily stored when a control operation is performed on the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0038] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other on the main substrate 2001. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 disposed on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of the semiconductor chip 2200, respectively, a connection structure 2400 that can electrically connect the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 disposed on the package substrate 2100 to cover the semiconductor chip 2200 and the connection structure 2400. As may be used herein, the term "covering" (and variations thereof, or similar terms) is intended to broadly refer to an element, structure or layer that is on or over another element, structure or layer directly or with one or more other intermediate elements, structures or layers therebetween.

[0039] The package substrate 2100 may be a printed circuit board including an upper pad 2130. Each of the semiconductor chips 2200 may include one or more input / output pads 2210. Each of the input / output pads 2210 may be connected to a Figure 1 The input / output pad 1101 corresponds to the input / output pad 1101. Each of the semiconductor chips 2200 may include a gate stack 3210 and a memory channel structure 3220. Each of the semiconductor chips 2200 may include a three-dimensional semiconductor memory device to be described below.

[0040] The connection structure 2400 may be, for example, a bonding wire provided to electrically connect the input / output pad 2210 to the upper pad 2130. That is, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in the form of a bonding wire, and may be electrically connected to the upper pad 2130 of the package substrate 2100. In some embodiments, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other through a through silicon via (TSV, also referred to as a "through silicon via") rather than through a connection structure 2400 provided in the form of a bonding wire.

[0041] and Figure 2 Unlike the example shown in , the controller 2002 and the semiconductor chip 2200 may be included in a single package rather than separate packages; that is, the controller 2002 may be integrated in one or more semiconductor chips 2200. In an embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate intermediate substrate instead of the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through interconnection lines provided in the intermediate substrate.

[0042] Figure 3 and Figure 4 are respectively along Figure 2 sectional views taken along line II′ and line II-II′ of FIG. 1 to illustrate a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0043] Reference Figure 3 and Figure 4 , semiconductor package 2003 may include a package substrate 2100 , a semiconductor chip 2200 on package substrate 2100 , and a molding layer 2500 covering package substrate 2100 and semiconductor chip 2200 (ie, on or over package substrate 2100 and semiconductor chip 2200 ).

[0044] The package substrate 2100 may include a package substrate main body portion 2120, an upper pad 2130 disposed on the upper surface of the package substrate main body portion 2120 and exposed to the outside of the package substrate main body portion 2120 near the upper surface, a lower pad 2125 disposed on the bottom surface of the package substrate main body portion 2120 or exposed to the outside of the package substrate main body portion 2120 near the bottom surface, and an internal line 2135 disposed in the package substrate main body portion 2120 to electrically connect the upper pad 2130 to the lower pad 2125. The term "exposed" (and its variations, or similar terms) may be used herein to describe the relationship between elements and / or refer to intermediate processes in manufacturing semiconductor devices, but specific elements may not be required to be exposed in the completed device. Similarly, the term "unexposed" may be used to describe the relationship between elements and / or refer to intermediate processes in manufacturing semiconductor devices, but specific elements may not be required to be unexposed in the completed device. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the connection structure 2400 via a conductive connection portion 2800 (e.g., a solder bump, etc.). Figure 2 2005 of the main substrate 2001 of the electronic system 2000 shown in FIG.

[0045] Reference Figure 2 and Figure 3 , the semiconductor chips 2200 may be arranged so that some of their side surfaces are not vertically aligned with each other, or at least a subset of the semiconductor chips 2200 may have side surfaces vertically aligned with each other. The semiconductor chips 2200 may be electrically connected to each other through a connection structure 2400 provided in the form of a bonding wire. Each of the semiconductor chips 2200 may include substantially the same elements.

[0046] Each of the semiconductor chips 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 on the first structure 4100. The second structure 4200 may be connected to the first structure 4100 in a wafer bonding manner.

[0047] The first structure 4100 may include a peripheral circuit interconnection line 4110 and a first bonding pad 4150. The second structure 4200 may include a common source line 4205, a gate stack 4210 disposed between the common source line 4205 and the first structure 4100, a memory channel structure 4220 and a separation structure 4230 disposed to vertically penetrate (i.e., extend to) the gate stack 4210, and word lines WL (e.g., see FIG. 4 ) connected to the memory channel structure 4220 and the gate stack 4210, respectively. Figure 1 ) of the second bonding pad 4250. For example, the second bonding pad 4250 can be electrically connected to the bit line 4240 of the memory channel structure 4220 and the gate interconnection line 4235 ( Figure 4 ) are electrically connected to the memory channel structure 4220 and the word line WL, respectively. The first bonding pad 4150 of the first structure 4100 and the second bonding pad 4250 of the second structure 4200 may contact each other and may be bonded to each other. The bonding portion between the first bonding pad 4150 and the second bonding pad 4250 may be formed of, for example, copper (Cu) or include, for example, copper (Cu).

[0048] Each of the semiconductor chips 2200 may further include an input / output pad 2210 and an input / output interconnection line 4265 under the input / output pad 2210. The input / output interconnection line 4265 may be electrically connected to some of the second bonding pads 4250 and some of the peripheral circuit interconnection lines 4110.

[0049] Figure 5 is a top plan view showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, and based on Figure 8 LV1 shown in . Figure 6 is a top plan view showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, and based on Figure 8 LV2 shown in . Figure 7 is a top plan view showing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, and based on Figure 8 LV3 shown in. Figure 8 It is along Figure 5 A cross-sectional view taken along line II' of FIG. 1 illustrates a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 9 yes Figure 8 0 is an enlarged cross-sectional view of a region “ZR” of a three-dimensional semiconductor memory device shown in FIG. Fig.10 yes Figure 8 0 is an enlarged cross-sectional view of a region “R” of a three-dimensional semiconductor memory device shown in FIG.

[0050] Reference Figures 5 to 10 , the three-dimensional semiconductor memory device according to the inventive concept may include a peripheral circuit structure PS and a cell array structure CS disposed on the peripheral circuit structure PS in a vertical direction (third direction D3) perpendicular to the upper surface of the first substrate 10. The cell array structure CS may be bonded to the peripheral circuit structure PS, and thus the cell capacity per unit area of ​​the three-dimensional semiconductor memory device according to the inventive concept may be increased. In addition, forming the peripheral circuit structure PS and the cell array structure CS separately and combining them (after forming circuit elements / circuit structures therein) may prevent damage to the peripheral transistor PTR due to various heat treatment processes, thereby improving the electrical characteristics and reliability of the semiconductor memory device.

[0051] The peripheral circuit structure PS may include a first substrate 10. The first substrate 10 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The first substrate 10 may have a first conductivity type. As an example, the first conductivity type may be a p-type. The first substrate 10 may have an upper surface parallel to a first direction D1 and a second direction D2 and orthogonal to a third direction D3, the second direction D2 intersecting the first direction D1; the first direction D1 and the second direction D2 may be horizontal directions. For example, the first direction to the third direction D1, D2, and D3 may be directions orthogonal to each other. A device isolation layer 11 may be disposed in the first substrate 10. The device isolation layer 11 may define an active region of the first substrate 10.

[0052] A peripheral transistor PTR, a peripheral contact plug 31, a peripheral circuit line 33 electrically connected to the peripheral transistor PTR through the peripheral contact plug 31, a first bonding pad 35 electrically connected to the peripheral circuit line 33, and a peripheral insulating layer 30 surrounding the peripheral circuit line 33, the peripheral transistor PTR, the first bonding pad 35 and the peripheral contact plug 31 may be disposed on the first substrate 10. As may be used herein, the term "surrounding" (and its variations, or similar terms) is intended to broadly refer to an element, structure or layer extending around, encapsulating, surrounding or encircling another element, structure or layer on all sides, although interruptions or gaps may also exist. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it surrounds. The peripheral transistor PTR may be disposed on the active area of ​​the first substrate 10. The peripheral circuit line 33 may be connected to the first substrate 10. Figure 3 and Figure 4 The peripheral circuit interconnection line 4110 corresponds to the first bonding pad 35. Figure 3 and Figure 4 Corresponding to the first bonding pad 4150 .

[0053] For example, the width of the peripheral contact plug 31 in the first direction D1 and / or the second direction D2 may decrease as the peripheral contact plug 31 extends toward the first substrate 10 in the third direction D3. The peripheral contact plug 31 and the peripheral circuit line 33 may include a conductive material such as metal.

[0054] The peripheral transistor PTR can form, for example, a decoder ( Figure 1 1110 in), page buffer ( Figure 1 1120) and / or logic circuit ( Figure 11130 in). In detail, each of the peripheral transistors PTR may include a peripheral gate insulating layer, a peripheral gate electrode, a peripheral covering pattern, a peripheral gate spacer, and a peripheral source / drain region. The peripheral gate insulating layer may be disposed between the peripheral gate electrode and the first substrate 10. The peripheral covering pattern may be disposed on the peripheral gate electrode. The peripheral gate spacer may cover the sidewalls of the peripheral gate insulating layer, the peripheral gate electrode, and the peripheral covering pattern. The peripheral source / drain region may be disposed inside the first substrate 10, adjacent to both sides of the peripheral gate electrode. The peripheral circuit line 33 and the first bonding pad 35 may be electrically connected to the peripheral transistor PTR through the peripheral contact plug 31. Each of the peripheral transistors PTR may be, for example, an n-channel metal oxide semiconductor (NMOS) transistor or a p-channel metal oxide semiconductor (PMOS) transistor.

[0055] The peripheral insulating layer 30 may be disposed on the first substrate 10. The peripheral insulating layer 30 may cover the peripheral transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33 on the first substrate 10. The peripheral insulating layer 30 may include a plurality of insulating layers having a multilayer structure. For example, the peripheral insulating layer 30 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric material. The peripheral insulating layer 30 may not cover the upper surface of the first bonding pad 35; that is, at least a portion of the corresponding upper surface of the first bonding pad 35 may be exposed by the peripheral insulating layer 30. The upper surface of the peripheral insulating layer 30 may be substantially coplanar with the upper surface of the first bonding pad 35 (in the vertical direction).

[0056] A cell array structure CS including a second bonding pad 45, a bit line BL, a stacked structure ST, and a semiconductor layer 191 may be disposed on the peripheral circuit structure PS. The cell array structure CS may include a cell array region CAR and an extension region (or referred to as a “cell array contact region”) EXR. The extension region EXR may extend horizontally from the cell array region CAR in a direction opposite to the first direction D1 (or in the first direction D1).

[0057] The second bonding pad 45, the bit line BL and the stack structure ST may be connected to Figure 3 and Figure 4 The first bonding pad 4250, the bit line 4240 and the gate stack 4210 correspond to each other. A first interconnection line 43 electrically connected to the second bonding pad 45 through a connection contact plug 41, a second bonding pad 45 contacting the first bonding pad 35 of the peripheral circuit structure PS, and a cell insulation layer 40 surrounding the first interconnection line 43, the connection contact plug 41 and the second bonding pad 45 may be provided.

[0058] In some embodiments, the unit insulating layer 40 may include a plurality of insulating layers having a multilayer structure. For example, the unit insulating layer 40 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric material. For example, the width of the connection contact plug 41 in the first direction D1 and / or the second direction D2 may increase as the connection contact plug 41 extends toward the first substrate 10 in the third direction D3. The connection contact plug 41 and the first interconnect line 43 may include a conductive material such as a metal.

[0059] The unit insulating layer 40 may not cover the lower surface of the second bonding pad 45; that is, the lower surface of the corresponding second bonding pad 45 may be exposed by the unit insulating layer 40. The lower surface of the unit insulating layer 40 may be substantially vertically coplanar with the lower surface of the second bonding pad 45. The lower surface of each of the second bonding pads 45 may be in direct contact with the upper surface of each of the first bonding pads 35. The first bonding pad 35 and the second bonding pad 45 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni) or tin (Sn). As an example, the first bonding pad 35 and the second bonding pad 45 may include copper (Cu). The first bonding pad 35 and the second bonding pad 45 may form an integrated shape without an interface therebetween. It is shown that the first bonding pad 35 and the second bonding pad 45 may be arranged so that their side walls are aligned with each other in the third direction D3, but the inventive concept is not limited thereto. In addition, when viewed in a plan view, the side walls of the first bonding pad 35 and the second bonding pad 45 may be spaced apart from each other.

[0060] The bit lines BL and the second interconnection lines CL contacting the connection contact plugs 41 may be disposed in the cell insulating layer 40. For example, each of the bit lines BL and the second interconnection lines CL may extend in the second direction D2 and be spaced apart from each other in the first direction D1. The bit lines BL and the second interconnection lines CL may include a conductive material such as a metal.

[0061] The stacked structure ST may be disposed on the cell insulating layer 40. The semiconductor layer 191 and the upper insulating layer 192 may be sequentially disposed on the stacked structure ST. The semiconductor layer 191 may be disposed on the cell array region CAR, although not shown, the semiconductor layer 191 may not be disposed on the extension region EXR. The stacked structure ST may include a first stacked structure ST1, a second stacked structure ST2, and a third stacked structure ST3 sequentially disposed between the semiconductor layer 191 and the cell insulating layer 40. In this specification, in order to simplify the explanation, the description is based on three stacked structures, but there may be three or more stacked structures. The stacked structure ST may include a structure in which interlayer insulating layers and conductive patterns are alternately stacked in a third direction D3.

[0062] The first stacked structure ST1 may include interlayer insulating layers 111 and first word lines EL1 that are alternately stacked, the second stacked structure ST2 may include interlayer insulating layers 111 and second word lines EL2 that are alternately stacked, and the third stacked structure ST3 may include interlayer insulating layers 111 and third word lines EL3 that are alternately stacked. The first stacked structure ST1 may be disposed between the second stacked structure ST2 and the semiconductor layer 191. In detail, the uppermost interlayer insulating layer 111 of the second stacked structure ST2 may be in contact with the lowermost interlayer insulating layer 111 of the first stacked structure ST1. Similarly, the second stacked structure ST2 may be disposed between the third stacked structure ST3 and the first stacked structure ST1. In detail, the uppermost interlayer insulating layer 111 of the third stacked structure ST3 may be in contact with the lowermost interlayer insulating layer 111 of the second stacked structure ST2.

[0063] The first to third word lines EL1, EL2, and EL3 may be formed of the same material at the same time. The first to third word lines EL1, EL2, and EL3 may include, for example, at least one material selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, molybdenum, nickel, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and a transition metal (e.g., titanium, tantalum, etc.). The interlayer insulating layer 111 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric material. For example, the interlayer insulating layer 111 may include a high density plasma oxide (HDP oxide) or tetraethyl orthosilicate (TEOS).

[0064] In the extension region EXR, each of the first stacked structure ST1, the second stacked structure ST2, and the third stacked structure ST3 may include an inverted stepped end. The contact pad RP exposed by the opening region VL may be disposed at the stepped end. The first stacked structure ST1 may include a 1a buried insulating layer 131a filling the opening region VL extending into all the first word lines EL1 and a 1b buried insulating layer 131b extending into some of the first word lines EL1. As may be used herein, the term "fill" (and its variations, or similar terms) is intended to broadly refer to completely filling a defined space (e.g., the opening region VL) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have a gap or other space in the entire space. The 1a buried insulating layer 131a may cover the 1a contact pad RP1a of the first word line EL1, and the 1b buried insulating layer 131b may cover the 1b contact pad RP1b of the first word line EL1. The second stacked structure ST2 may include a 2a buried insulating layer 132a filling the opening region VL extending into all the second word lines EL2 and a 2b buried insulating layer 132b extending into some of the second word lines EL2. The 2a buried insulating layer 132a may cover the 2a contact pad RP2a of the second word line EL2, and the 2b buried insulating layer 132b may cover the 2b contact pad RP2b of the second word line EL2. The third stacked structure ST3 may include a 3a buried insulating layer 133a filling the opening region VL extending into all the third word lines EL3 and a 3b buried insulating layer 133b extending into some of the third word lines EL3. The 3a buried insulating layer 133a may cover the 3a contact pad RP3a of the third word line EL3, and the 3b buried insulating layer 133b may cover the 3b contact pad RP3b of the third word line EL3.

[0065] In the cell array region CAR, the vertical channel structure VS may be disposed in the vertical channel hole CH extending into the stack structure ST along the third direction D3. The vertical channel structure VS may be connected to the vertical channel hole CH. Figure 3 and Figure 4 The memory channel structure 4220 corresponds to the memory channel structure 4220. The lower portion of the vertical channel structure VS can be connected to the bit line BL. As an example, the bit line contact plug can be set between the vertical channel structure VS and the bit line BL. The upper portion of the vertical channel structure VS can be connected to the semiconductor layer 191. The semiconductor layer 191 may include a polycrystalline silicon layer. The semiconductor layer 191 may include a common source region of the vertical channel structure VS in the electrically connected stacked structure ST. As an example, the semiconductor layer 191 may include a p-type doped region in a region adjacent to the vertical channel structure VS. The upper insulating layer 192 may include a silicon oxide layer.

[0066] In the extension region EXR, a support structure DV extending into the stack structure ST in the third direction D3 may be provided The support structure DV may include an insulating material such as a silicon oxide layer, but may otherwise have a structure similar to the vertical channel structure VS.

[0067] Although not shown, the width of the vertical channel hole CH in the first direction D1 and / or the second direction D2 may decrease as the distance from the peripheral circuit structure PS increases. The vertical channel hole CH may have a step whose width in the first direction D1 and / or the second direction D2 changes discontinuously at the boundary between the first stacking structure ST1 and the second stacking structure ST2 and at the boundary between the second stacking structure ST2 and the third stacking structure ST3. That is, the vertical channel hole CH is configured to have a step difference so that the first portion extending along the interface between the first stacking structure ST1 and the second stacking structure ST2 is wider than the second portion extending along the interface between the second stacking structure ST2 and the third stacking structure ST3.

[0068] Each of the vertical channel structures VS may include a conductive pad, a data storage pattern, a vertical semiconductor pattern, and a buried insulating pattern sequentially disposed in the vertical channel hole CH adjacent to the cell insulating layer 40. The vertical semiconductor pattern may include, for example, a semiconductor material doped with impurities, an intrinsic semiconductor material in an undoped state, or a polycrystalline semiconductor material. The conductive pad may include, for example, a semiconductor material or a conductive material doped with impurities. The buried insulating pattern may include an insulating material such as a silicon oxide layer. However, the embodiments are not limited to the specific materials mentioned for the vertical semiconductor pattern, the conductive pad, or the buried insulating pattern.

[0069] The data storage pattern may include a blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially stacked on the sidewall of the vertical channel hole CH. A Fowler-Nordheim (FN) tunneling phenomenon that may be caused by a voltage difference between the vertical semiconductor pattern VSP and the first to third word lines EL1, EL2, and EL3 may be used to store or change data in the data storage pattern DSP. For example, the blocking insulating layer and the tunneling insulating layer may include silicon oxide, and the charge storage layer may include silicon nitride or silicon oxynitride.

[0070] Reference Figure 5 , Figure 6 and Figure 7, when viewed in a plan view, a first trench TR1 and a second trench TR2 extending in the first direction D1 and intersecting the stack structure ST may be provided. The first trench TR1 may be provided in the cell array region CAR and the extension region EXR, and the second trench TR2 may be provided in the extension region EXR (although not shown, the second trench TR2 may not be provided in the cell array region CAR). The first separation pattern SP1 and the second separation pattern SP2 may be provided to at least partially fill the inside of each of the first trench TR1 and the second trench TR2. The first separation pattern SP1 and the second separation pattern SP2 may be provided with Figure 3 The first separation pattern SP1 may have a length in the first direction D1 greater than the length in the first direction D1 of the second separation pattern SP2. Sidewalls of the first separation pattern SP1 and the second separation pattern SP2 may contact at least a portion of the first to third word lines EL1, EL2, and EL3 of the stacked structure ST and the interlayer insulating layer 111. The first separation pattern SP1 and the second separation pattern SP2 may include, for example, an oxide such as silicon oxide.

[0071] When a plurality of stack structures ST are provided, the first separation pattern SP1 may be provided between the stack structures ST arranged along the second direction D2. In other words, the stack structures ST may be spaced apart from each other in the second direction D2, and the first separation pattern SP1 may be provided between the stack structures ST.

[0072] The cell contact plug and structures adjacent thereto are described in more detail below.

[0073] like Figures 5 to 8 As shown in , a cell contact plug CP extending into the stack structure ST in the third direction D3 may be provided. As the contact plug CP extends in the third direction D3, the horizontal width or diameter of each of the cell contact plugs CP may be continuously increased. The cell contact plug CP may include a metal material such as tungsten, titanium or tantalum, although the embodiment is not limited thereto. Each of the cell contact plugs CP may be connected to one of the first to third word lines EL1, EL2 and EL3, and other word lines other than the connected word lines may be spaced apart from each other, and an insulating spacer 141 may be provided between the other word lines. As an example, the insulating spacer 141 may include a silicon oxide layer. Each of the cell contact plugs CP may extend into the first stack structure ST1, the second stack structure ST2 and the third stack structure ST3, and be connected to the upper insulating layer 192. Each of the cell contact plugs CP may include a single continuous conductor, and there is no interface between the first stack structure ST1 and the second stack structure ST2 and between the second stack structure ST2 and the third stack structure ST3.

[0074] The cell contact plugs CP may include first cell contact plugs CP1a and CP1b respectively connected to contact pads (or referred to as “first contact pads”) RP1a and RP1b of the first word line EL1, second cell contact plugs CP2a and CP2b respectively connected to contact pads (or referred to as “second contact pads”) RP2a and RP2b of the second word line EL2, and third cell contact plugs CP3a and CP3b respectively connected to contact pads (or referred to as “third contact pads”) RP3a and RP3b of the third word line EL3.

[0075] The second cell contact plugs CP2a and CP2b may include a 2a-th cell contact plug CP2a connected to a 2a-th contact pad RP2a and a 2b-th cell contact plug CP2b connected to a 2b-th contact pad RP2b. Figure 5 and Figure 8 As shown in , the second unit contact plugs CP2a and CP2b may include a first horizontal protrusion LP1, and the diameter of the first horizontal protrusion LP1 in the first direction D1 and / or the second direction D2 discontinuously increases at the connecting portion of the first stack structure ST1 and the second stack structure ST2. That is, each of the second unit contact plugs CP2a and CP2b may be constructed to have a step difference, so that the width of the first horizontal protrusion LP1 extending in the first direction D1 and / or the second direction D2 along the interface between the first stack structure ST1 and the second stack structure ST2 is greater than the width of the corresponding second unit contact plugs CP2a, CP2b outside the interface between the first stack structure ST1 and the second stack structure ST2 in the first direction D1 and / or the second direction D2. In detail, as Fig. 9 and Fig.10 As shown in , the first horizontal protrusion LP1 may be disposed in the lowest interlayer insulating layer 111 of the first stacked structure ST1. The first horizontal protrusion LP1 may be vertically overlapped with the 2b contact pad RP2b or the 2a contact pad RP2a. As may be used herein, the term "overlap" (and its variations, or similar terms) is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., a third direction D3), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first direction D1 and / or the second direction D2). The first horizontal protrusion LP1 may be disposed between the 2b contact pad RP2b and the upper insulating layer 192, or between the 2a contact pad RP2a and the upper insulating layer 192. The first horizontal protrusion LP1 may not be disposed between the second stacked structure ST2 and the third stacked structure ST3. The first horizontal protrusion LP1 may not be disposed between the 2b contact pad RP2b and the second interconnect line CL and between the 2a contact pad RP2a and the second interconnect line CL.

[0076] like Fig.10 As shown in FIG. 1 , the second cell contact plugs CP2a and CP2b may have a first width W1 in the first direction D1 in a region adjacent to the first horizontal protrusion LP1, and the first horizontal protrusion LP1 may have a second width W2 greater than the first width W1 in the first direction D1. For example, the second width W2 may be about 1.2 times to about 3.0 times the first width W1.

[0077] The first horizontal protrusion LP1 may have a ring shape surrounding each of the second cell contact plugs CP2a and CP2b, but is not limited thereto. A thickness t1 of the first horizontal protrusion LP1 in the third direction D3 may be smaller than the second width W2.

[0078] The third cell contact plugs CP3a and CP3b are a 3a-th cell contact plug CP3a connected to a 3a-th contact pad RP3a and a 3b-th cell contact plug CP3b connected to a 3b-th contact pad RP3b. Figure 6 and Fig. 9 As shown in , the third unit contact plugs CP3a and CP3b may include a second horizontal protrusion LP2, and the diameter of the second horizontal protrusion LP2 in the first direction D1 and / or the second direction D2 discontinuously increases at the connection portion of the second stack structure ST2 and the third stack structure ST3. That is, each of the third unit contact plugs CP3a and CP3b may be constructed to have a step difference, so that the width of the second horizontal protrusion LP2 extending in the first direction D1 and / or the second direction D2 along the interface between the second stack structure ST2 and the third stack structure ST3 is greater than the width of the corresponding third unit contact plugs CP3a, CP3b outside the interface between the second stack structure ST2 and the third stack structure ST3 in the first direction D1 and / or the second direction D2. In detail, as Fig. 9 As shown in , the second horizontal protrusion LP2 may be disposed in the lowermost interlayer insulating layer 111 of the second stacked structure ST2. The second horizontal protrusion LP2 may be vertically overlapped with the 3a-th contact pad RP3a or the 3b-th contact pad RP3b. The second horizontal protrusion LP2 may be disposed between the 3b-th contact pad RP3b and the upper insulating layer 192, or between the 3a-th contact pad RP2a and the upper insulating layer 192. The second horizontal protrusion LP2 may not be disposed between the second stacked structure ST2 and the first stacked structure ST1. The second horizontal protrusion LP2 may not be disposed between the 3b-th contact pad RP3b and the second interconnect line CL and between the 3a-th contact pad RP3a and the second interconnect line CL.

[0079] The first cell contact plugs CP1 a and CP1 b connected to the first word line EL1 closest to the upper insulating layer 192 in the first stack structure ST1 may not include a horizontal protrusion.

[0080] like Figures 5 to 7 As shown in , the first cell contact plugs CP1a and CP1b, the second cell contact plugs CP2a and CP2b, and the third cell contact plugs CP3a and CP3b may be sequentially and repeatedly placed in the first direction D1. In the direction opposite to the first direction D1 (i.e., the direction away from the vertical channel structure VS), the third cell contact plugs CP3a and CP3b, the second cell contact plugs CP2a and CP2b, and the first cell contact plugs CP1a and CP1b may be repeatedly arranged multiple times. For example, the 3b-th cell contact plug CP3b, the 2b-th cell contact plug CP2b, the 1b-th cell contact plug CP1b, and the 3a-th cell contact plug CP3a, the 2a-th cell contact plug CP2a, and the 1a-th cell contact plug CP1a may be sequentially arranged in the direction opposite to the first direction D1. The 2b-th cell contact plug CP2b may be disposed between the 3b-th cell contact plug CP3b and the 1b-th cell contact plug CP1b, and the 2a-th cell contact plug CP2a may be disposed between the 3a-th cell contact plug CP3a and the 1a-th cell contact plug CP1a.

[0081] The first horizontal protrusion LP1 and the second horizontal protrusion LP2 may prevent leakage current and short circuit between the contact plug CP and the adjacent word line due to misalignment of the contact hole in the process of forming the contact plug CP (to be described below). The first horizontal protrusion LP1 and the second horizontal protrusion LP2 may not be formed at all interfaces between the stacked structures, but may be formed at the nearest interface between the contact pad RP and the upper insulating layer 192 among the interfaces of the stacked structures. That is, the first horizontal protrusion LP1 and the second horizontal protrusion LP2 may be provided only at the interface of the stacked structure immediately above them, thereby simplifying the process and increasing integration.

[0082] Fig.11 , Figures 15 to 18 as well as Figure 23 to Figure 24 According to one or more embodiments of the invention, Figure 5 A cross-sectional view taken along line II' of FIG. 1 illustrates an intermediate process in an example method of manufacturing a three-dimensional semiconductor memory device. Figure 12 to Figure 14 yes Fig.11 An enlarged cross-sectional view of area “Q1” in FIG. Figures 19 to 22 yes Fig.18 An enlarged cross-sectional view of area “Q2” in FIG.

[0083] Reference Fig.11, a first preliminary stacked structure STp1 may be formed on the second substrate 100. The second substrate 100 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate, but the embodiment is not limited thereto. The second substrate 100 may have a first conductivity type. As an example, the first conductivity type may be a p-type. Before forming the first preliminary stacked structure STp1, a buffer insulating layer and / or an etching stop layer may be formed on the second substrate 100.

[0084] The first preliminary stacked structure STp1 may include interlayer insulating layers 111 and sacrificial layers 121 alternately and repeatedly stacked in the third direction D3 (i.e., vertically). The interlayer insulating layer 111 and the sacrificial layer 121 may be formed of different insulating materials. The sacrificial layer 121 may be formed of a material that can be selectively etched relative to the interlayer insulating layer 111. For example, the sacrificial layer 121 may be formed of silicon nitride, and the interlayer insulating layer 111 may be formed of silicon oxide. Each of the sacrificial layers 121 may have substantially the same cross-sectional thickness. The uppermost layer in the interlayer insulating layer 111 may be thicker than the other layers.

[0085] In the extension region EXR, an opening region VL exposing the upper surface of the sacrificial layer 121 may be formed. As an example, the opening region VL may be formed by forming a mask pattern and trimming the mask pattern via a plurality of etching processes. As a result, the sidewall of the opening region VL (when viewed in a cross-sectional view) may be formed to have a stepped shape defined by the upper surface of the sacrificial layer 121. A plurality of opening regions VL may be provided, and the number of sacrificial layers 121 penetrating the opening region VL (i.e., extending into the opening region VL) may vary depending on the position of the opening region VL. For example, as the distance from the cell array region CAR in the first direction D1 increases, the depth of the opening region VL in the third direction D3 may increase.

[0086] Reference Fig.11 and Fig.12 , a first pad sacrificial pattern 171 may be formed on the upper surface of the sacrificial layer 121 exposed by the opening region VL. A sacrificial layer covering the opening region VL may be formed, and then the sacrificial layer may be removed from the region other than the exposed upper surface of the sacrificial layer 121 to form the first pad sacrificial pattern 171. The first pad sacrificial pattern 171 may be formed of a material that can be selectively etched relative to the interlayer insulating layer 111. For example, the first pad sacrificial pattern 171 may be formed of the same material as that of the sacrificial layer 121, such as silicon nitride. Thereafter, a 1a-th buried insulating layer 131a and a 1b-th buried insulating layer 131b may be formed to fill the opening region VL. The 1a-th buried insulating layer 131a and the 1b-th buried insulating layer 131b may include a silicon oxide layer, but the embodiment is not limited thereto.

[0087] Through holes TH1 to TH6 in the first preliminary stacked structure STp1 extending vertically (i.e., in the third direction D3) into the extension region EXR and vertical channel holes CH in the first preliminary stacked structure STp1 extending vertically into the cell array region CAR may be formed. Through holes TH1 to TH6 and vertical channel holes CH may be simultaneously formed by an anisotropic etching process. Through holes TH1 to TH6 and vertical channel holes CH may expose the second substrate 100. A first through sacrificial pattern SF1 may be formed to fill the through holes TH1 to TH6 and the vertical channel holes CH. The first through sacrificial pattern SF1 may be formed of a material that can be selectively etched with respect to the interlayer insulating layer 111 and the sacrificial layer 121. As an example, the first through sacrificial pattern SF1 may include polysilicon or silicon carbide, but the embodiment is not limited thereto.

[0088] Reference Fig.11 and Fig.13 , a mask pattern 116 may be formed to cover the upper surface of the first preliminary stacked structure STp1 and expose some of the through holes TH1 to TH6. The mask pattern 116 may include a photoresist and / or silicon nitride, but the embodiment is not limited thereto. As an example, the mask pattern 116 may include an opening overlapping the second through hole TH2 and the fifth through hole TH5 in the third direction D3. A recessed area PH may be formed in which an upper portion of the first through sacrificial pattern SF1 exposed by the opening and a portion of the uppermost interlayer insulating layer 111 are removed.

[0089] Reference Fig.11 and Fig.14 , the first extension pattern AP1 may be formed to at least partially fill the recessed area PH. The first extension pattern AP1 may be formed of the same material as the first through sacrificial pattern SF1. Thereafter, the mask pattern 116 may be removed.

[0090] Reference Fig.15, a second preliminary stacked structure STp2 and a third preliminary stacked structure STp3 may be sequentially formed on the first preliminary stacked structure STp1. The second preliminary stacked structure STp2 may be formed by repeating a process similar to that of the first preliminary stacked structure STp1. As a result, a second pad sacrificial pattern 172, a 2a buried insulating layer 132a, and a 2b buried insulating layer 132b may be formed in the opening region VL in the second preliminary stacked structure STp2, and a second through sacrificial pattern SF2 may be formed on each of the first through sacrificial patterns SF1, respectively. A second extension pattern AP2 may be formed on some of the second through sacrificial patterns SF2. Similarly, a third pad sacrificial pattern 173, a 3a buried insulating layer 133a, and a 3b buried insulating layer 133b may be formed in the opening region VL in the third preliminary stacked structure STp3, and a third through sacrificial pattern SF3 may be formed on the second through sacrificial pattern SF2, respectively. An extension pattern may not be formed in the third through sacrificial pattern SF3.

[0091] Reference Fig.16 , after removing the first through sacrificial patterns SF1, SF2, and SF3 in the vertical channel holes CH of the first preliminary stacking structures STp1, STp2, and STp3, a vertical channel structure VS may be formed. Hereinafter, each of the vertical channel holes CH may refer to a hole sequentially extending vertically into the first preliminary stacking structures STp1, STp2, and STp3 or passing through the first preliminary stacking structures STp1, STp2, and STp3. The step of forming the vertical channel structure VS may include forming a data storage pattern and a vertical semiconductor pattern conformally covering an inner sidewall of the vertical channel hole CH, and forming a buried insulating pattern in a space surrounded by the vertical semiconductor pattern.

[0092] Reference Fig.17 , the first through sacrificial pattern to the third through sacrificial pattern SF1, SF2 and SF3 may be removed in the extension region EXR to expose the first through hole TH1 to the sixth through hole TH6. Hereinafter, each of the first through hole TH1 to the sixth through hole TH6 may refer to a hole that sequentially passes through the first preliminary stacking structure to the third preliminary stacking structure STp1, STp2 and STp3 in the third direction D3. When the first to the third sacrificial pattern SF1, SF2 and SF3 are removed, the first extension pattern AP1 and the second extension pattern AP2 may also be removed to form the first gap region GP1 and the second gap region GP2, respectively.

[0093] Reference Fig.18 , Fig.19 and Fig. 20, a portion of the sacrificial layer 121 exposed by the first through holes TH1 to the sixth through holes TH6 may be removed. The sacrificial layer 121 may not be completely removed, and only a portion close to the first through holes TH1 to the sixth through holes TH6 may be horizontally etched. As a result, a first horizontal recessed area EH1 in which the first through holes TH1 to the sixth through holes TH6 are horizontally extended may be formed. The first to third pad sacrificial patterns 171, 172, and 173 may be removed together with the sacrificial layer 121. As a result, a portion of the first horizontal recessed area EH1 may become a second horizontal recessed area EH2 whose cross-sectional thickness in the third direction D3 is further expanded.

[0094] Reference Fig.18 and Fig.21 , an insulating spacer 141 may be formed in the first horizontal recessed area EH1. The insulating spacer 141 may include the same material as the interlayer insulating layer 111, such as a silicon oxide layer. The step of forming the insulating spacer 141 may include forming an insulating layer covering the first horizontal recessed area EH1 and the second horizontal recessed area EH2, and then performing anisotropic etching to remove the remaining insulating layer in the first through hole TH1 to the sixth through hole TH6. The cross-sectional thickness of the second horizontal recessed area EH2 in the third direction D3 may be greater than the cross-sectional thickness of the first horizontal recessed area EH1 in the third direction D3, so when removing the remaining insulating layer, the insulating layer in the second horizontal recessed area EH2 may be removed together.

[0095] After forming the insulating spacer 141, the fourth to sixth pad sacrificial patterns 176, 177, and 178 may be formed in the second horizontal recessed area EH2. The fourth to sixth pad sacrificial patterns 176, 177, and 178 may be formed of a material that can be removed together with the sacrificial layer 121. As an example, the fourth to sixth pad sacrificial patterns 176, 177, and 178 may be formed of silicon nitride. Then, a vertical sacrificial pattern 144 may be formed to fill the first through hole TH1 to the sixth through hole TH6. The vertical sacrificial pattern 144 may be formed of a material that can be etched selectively with respect to the interlayer insulating layer 111 and the sacrificial layer 121. As an example, the vertical sacrificial pattern 144 may include polysilicon or silicon carbide. The vertical sacrificial pattern 144 may fill the first gap area GP1 and the second gap area GP2.

[0096] Reference Figure 5 and Fig.23, first trenches TR1 and second trenches TR2 vertically extending into or through the first preliminary stacked structures STp1, STp2, and STp3 may be formed. The first trenches TR1 and second trenches TR2 may extend from the cell array region CAR to the extension region EXR in the first direction D1. The sacrificial layer 121 may be removed through the first trenches TR1 and second trenches TR2. The sacrificial layer 121 may be removed by, for example, using hydrofluoric acid (HF) and / or phosphoric acid (H 3 PO 4 ) solution to perform a wet etching process to remove the sacrificial layer 121. The fourth to sixth pad sacrificial patterns 176, 177, and 178 may be removed together with the sacrificial layer 121.

[0097] The first to third word lines EL1, EL2, and EL3 may be formed to fill the space from which the sacrificial layer 121 has been removed. The contact pad RP may be formed in the space from which the sacrificial patterns 176, 177, and 178 have been removed. Thus, a stack structure ST including a first stack structure ST1, a second stack structure ST2, and a third stack structure ST3 may be formed. Thereafter, a first separation pattern SP1 and a second separation pattern SP2 may be formed to fill the first trench TR1 and the second trench TR2, respectively.

[0098] Reference Figures 5 to 7 and Fig.24 After removing the vertical sacrificial pattern 144, a cell contact plug CP may be formed to fill the space from which the vertical sacrificial pattern 144 is removed. The cell contact plug CP may be formed of a metal material such as tungsten, titanium, or tantalum, but the embodiment is not limited thereto. A first horizontal protrusion LP1 may be formed in the first gap region GP1, and a second horizontal protrusion LP2 may be formed in the second gap region GP2.

[0099] Refer again Figure 8 , a bit line BL, a second interconnect line CL, a connection contact plug 41, a first interconnect line 43, a second bonding pad 45, and a cell insulation layer 40 covering the bit line BL, the second interconnect line CL, the connection contact plug 41, the first interconnect line 43, and the second bonding pad 45 can be formed on the stacked structure ST. Therefore, the step of forming the cell array structure CS can be completed. Then, the cell array structure CS and the peripheral circuit structure PS can be combined with each other. In detail, the cell array structure CS and the peripheral circuit structure PS can be bonded (for example, using a wafer bonding process) so that the second bonding pad 45 contacts the first bonding pad 35. Afterwards, the second substrate 100 can be removed to expose the upper portion of the vertical channel structure VS and the upper portion of the cell contact plug CP.

[0100] A semiconductor layer 191 may be formed to cover the exposed upper portion of the vertical channel structure VS. The semiconductor layer 191 may not be formed on the cell contact plug CP. An upper insulating layer 192 may be formed over the cell contact plug CP. The upper insulating layer 192 may cover the semiconductor layer 191.

[0101] According to an embodiment of the inventive concept, the contact plug may include a horizontal protrusion to prevent leakage current and short circuit between the contact plug and the adjacent word line. In addition, the horizontal protrusion may be disposed only at the nearest interface between the contact pad and the semiconductor layer among the interfaces of the stacked structure, thereby simplifying the process and increasing the integration.

[0102] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the inventive concept defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept should be considered in all aspects to be illustrative rather than restrictive, and the spirit and scope of the inventive concept are indicated by the appended claims.

Claims

1. A semiconductor memory device, comprising: A cell array structure and a peripheral circuit structure, wherein the cell array structure is arranged on the peripheral circuit structure along a vertical direction, Wherein, the cell array structure includes: a first stack structure, a second stack structure on the first stack structure, and a third stack structure on the second stack structure, each of the first stack structure, the second stack structure, and the third stack structure comprising a plurality of word lines; a vertical channel structure extending into the first stacked structure, the second stacked structure, and the third stacked structure; and a second cell contact plug extending into the first stack structure, the second stack structure, and the third stack structure and connected to a second contact pad at an end of a second word line in the second stack structure, and The second cell contact plug includes a first horizontal protrusion having a horizontal width that discontinuously increases at a connection portion of the first stack structure and the second stack structure.

2. The semiconductor memory device according to claim 1, further comprising: a third cell contact plug extending from the first stack structure to the third stack structure and connected to a third contact pad at an end of a third word line in the third stack structure, The third cell contact plug includes a second horizontal protrusion having a horizontal width that discontinuously increases at a connection portion of the third stack structure and the second stack structure.

3. The semiconductor memory device according to claim 2, wherein: The third cell contact plug does not include a horizontal protrusion at a connection portion of the first stack structure and the second stack structure.

4. The semiconductor memory device according to claim 2, further comprising: a first cell contact plug extending from the first stack structure to the third stack structure and connected to a first contact pad at an end of a first word line in the first stack structure, Wherein, the first unit contact plug does not include a horizontal protrusion.

5. The semiconductor memory device according to claim 4, wherein: The second cell contact plug is between the first cell contact plug and the vertical channel structure, and The third unit contact plug is between the second unit contact plug and the vertical channel structure.

6. The semiconductor memory device according to claim 4, wherein: The third cell contact plug, the second cell contact plug, and the first cell contact plug are repeatedly arranged a plurality of times in a horizontal direction extending away from the vertical channel structure.

7. The semiconductor memory device according to claim 1, wherein: The first horizontal protrusion is spaced apart from the peripheral circuit structure, and the second contact pad is located between the first horizontal protrusion and the peripheral circuit structure.

8. The semiconductor memory device according to claim 1, wherein: The first horizontal protrusion vertically overlaps the second contact pad.

9. The semiconductor memory device according to claim 1, wherein: The second cell contact plug does not include a horizontal protrusion at a connection portion of the second stack structure and the third stack structure.

10. The semiconductor memory device according to claim 1, wherein The second cell contact plug has a first horizontal width in a region adjacent to the first horizontal protrusion, wherein the first horizontal protrusion has a second horizontal width, and The second horizontal width is 1.2 to 3.0 times the first horizontal width.

11. The semiconductor memory device according to claim 10, wherein: The cross-sectional thickness of the first horizontal protrusion is smaller than the second horizontal width.

12. The semiconductor memory device according to claim 1, further comprising: An insulating spacer horizontally separates the second cell contact plug from the first word line of the first stack structure and the third word line of the third stack structure.

13. A semiconductor memory device, comprising: Peripheral circuit structure; as well as Cell array structure, in the peripheral circuit structure, Wherein, the cell array structure includes: Semiconductor layer; an upper insulating layer, disposed on the semiconductor layer; A first stack structure, a second stack structure, and a third stack structure are disposed between the semiconductor layer and the peripheral circuit structure, each of the first stack structure to the third stack structure comprising a plurality of word lines; A vertical channel structure extending from the first stacking structure to the third stacking structure; a first cell contact plug extending from the first stack structure into the third stack structure and connected to a first contact pad at an end of a first word line in the first stack structure; a second cell contact plug extending into the first to third stack structures and connected to a second contact pad at an end of a second word line in the second stack structure; and a third cell contact plug extending from the first stack structure to the third stack structure and connected to a third contact pad at an end of a third word line in the third stack structure, and The second cell contact plug includes a first horizontal protrusion having a horizontal width that discontinuously increases at a connection portion of the first stack structure and the second stack structure.

14. The semiconductor memory device according to claim 13, wherein: The third cell contact plug includes a second horizontal protrusion having a horizontal width that discontinuously increases at a connection portion of the third stack structure and the second stack structure.

15. The semiconductor memory device according to claim 14, wherein: The third cell contact plug does not include a horizontal protrusion at a connection portion of the first stack structure and the second stack structure.

16. The semiconductor memory device according to claim 13, wherein: The first cell contact plug does not include a horizontal protrusion.

17. The semiconductor memory device according to claim 14, wherein: The third cell contact plug, the second cell contact plug, and the first cell contact plug are repeatedly arranged a plurality of times in a horizontal direction extending away from the vertical channel structure.

18. The semiconductor memory device according to claim 13, wherein: The first horizontal protrusion is between the second contact pad and the upper insulating layer.

19. The semiconductor memory device according to claim 13, wherein: The second cell contact plug does not include a horizontal protrusion at a connection portion of the second stack structure and the third stack structure.

20. An electronic system, comprising: A three-dimensional semiconductor memory device comprising a peripheral circuit structure and a cell array structure on the peripheral circuit structure, wherein the cell array structure comprises a cell array region and a cell array contact region; as well as a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad and configured to control the three-dimensional semiconductor memory device, The cell array structure further includes: a first stack structure, a second stack structure on the first stack structure, and a third stack structure on the second stack structure, each of the first to third stack structures comprising a plurality of word lines; A vertical channel structure extending from the first stacking structure to the third stacking structure; and a second cell contact plug extending from the first stack structure to the third stack structure and connected to a second contact pad at an end of a second word line in the second stack structure, and The second cell contact plug includes a first horizontal protrusion having a horizontal width that discontinuously increases at a connection portion of the first stack structure and the second stack structure.

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