Device based on active area driving force redistribution, preparation method and layout structure

Abstract

The invention discloses a device based on active region driving force redistribution, a preparation method and a layout structure. The device structure comprises a substrate layer, a nucleating layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode and a gate electrode. The substrate layer, the nucleating layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top to form an epitaxial substrate; a source electrode active region and a drain electrode active region are formed in the epitaxial substrate; the source electrode and the drain electrode are correspondingly arranged on one side of the source electrode active region and one side of the drain electrode active region; the gate electrode is arranged between the source electrode and the drain electrode; the source electrode active region and the drain electrode active region are asymmetrically distributed on the two sides of the gate electrode. According to the scheme, only a mask plate for ohm and active region isolation two-step photoetching needs to be changed on the basis of a conventional device standard process, no additional working procedure needs to be introduced, the linearity of the device is improved under the condition that the process complexity and the preparation cost are not increased, and compatibility among the yield, stable device performance and high linearity is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a device based on active area driving force redistribution, a preparation method and a layout structure. Background Art

[0002] Thanks to the material characteristics of high electron mobility, high electron saturation velocity and high breakdown field strength, GaN high electron mobility transistor (GaN HEMT) combines the advantages of high operating frequency and high output power. In the field of telecommunication infrastructure above 3GHz, its market share is leading the first-generation semiconductor devices (Si Laterally Diffused Metal Oxide Semiconductor, SiLDMOS) and the second-generation semiconductor devices (GaAs Metal-Semiconductor Field Effect Transistor, GaAs MESFET) year by year. However, compared with Si LDMOS and GaAs MESFET, RF GaN HEMT exposes more serious nonlinear problems, which will have an adverse effect on signal transmission quality and amplification capability under high input power. With the continuous expansion of application frequency bands and the exponential growth of data throughput, modern wireless communication technology has put forward an urgent demand for high data transmission rate and high spectrum utilization efficiency, prompting RF GaN to take measures to solve its nonlinear problems and play a more active role in the current fierce market competition environment.

[0003] At present, the solutions to RF GaN nonlinear problems are mainly from the perspectives of circuits and devices. Circuit-level linearization technologies include power back-off, feedback, digital pre-distortion, and Doherty architecture, which have now developed to a relatively mature level and have been widely used. However, considering the cost, integration, and design complexity issues brought about by circuit-level technologies, research has begun to turn its attention to more basic, device-level solutions.

[0004] Source series resistance (R S ) at high current (I DS ) is considered to be one of the sources of intrinsic nonlinearity at the GaN HEMT device level, and the growth trend of source resistance is further related to the device transconductance (G m ) profile. As the transconductance curve is intuitive and controllable, device-level linearity technology often optimizes the flat transconductance profile, including epitaxial material optimization solutions represented by double heterojunction and polarization doped channel, and device structure optimization solutions represented by field plate, fin-type gate, source injection, etc.

[0005] Among them, the source injection technology forms a heavily doped n ++ The low resistance region reduces the resistance of the source series resistance relative to the drain series resistance, so that the drain bears more of the channel electric field, weakens the dependence of the source series resistance on the drain current, and improves the flatness of the transconductance profile. Fin-type gate technology uses special lithography and etching processes to periodically block the channel below the gate along the gate width direction, forming a three-dimensional control of the top gate and two sidewall gates. By designing the fin width, fin height and array ratio, the proportional relationship between the active area width corresponding to the source resistance and the active area width corresponding to the channel is adjusted. The source resistance corresponding to a single fin-type channel is reduced, which suppresses the trend of the source resistance increasing with the increase of the leakage current, and improves the transconductance linearity of the device. The double heterojunction structure controls the threshold voltage for the upper and lower channels to open by adjusting the degree of coupling between the channels. When the R corresponding to the upper channel S When the nonlinear growth trend appears and the transconductance rolls off, the lower channel is just turned on, and the corresponding R S smaller, and the transconductance rises. At this time, the R S In parallel, the equivalent R S The transconductance is reduced, and the transconductance presents a greatly widened profile after splicing, and the linearity is improved.

[0006] However, the above device-level linearity optimization scheme still has the following disadvantages:

[0007] For the source injection technology, on the one hand, it introduces an additional process in the device preparation process. The injection process requires a reasonable design of the mask and injection dose to control the area and injection depth of the injection region, and the injection process has an outward expansion amount, which is not conducive to the reduction of the lateral size of the device. On the other hand, although the injection of Si reduces the resistance of the source active area and reduces the voltage divider, the scattering of ionized impurities introduced by doping will reduce the mobility of the channel carriers at the source, which is not conducive to the improvement of the device frequency characteristics.

[0008] The implementation of fin-type gate technology requires adding a lithography and etching process on top of the conventional GaN HEMT preparation process. The etching damage caused by the etching process will induce problems related to interface state traps, and the off-state current of the device will also deteriorate. In addition, in order to form the gate control of the sidewall, the FinFET periodically blocks the channel along the gate width, resulting in a decrease in the device's conduction capability. The gate metal on the sidewall also introduces additional parasitic capacitance, which limits the improvement of the device's frequency characteristics.

[0009] For double heterojunction devices, their inherent double-peak characteristics of transconductance provide an inherent advantage for achieving the widening of the transconductance profile. However, the coupling between transconductors often requires the assistance of other technologies, otherwise a valley that is difficult to fill will be formed between the two transconductance peaks, which is not conducive to the improvement of transconductance flatness. In addition, due to the long distance from the lower channel to the gate, double heterojunction devices are more difficult to achieve stable gate control than conventional devices under the same gate length, which is easy to cause problems related to the short channel effect.

[0010] In summary, the improvement of linearity in existing device-level linearization technologies often comes at the expense of manufacturing costs and extended process cycles, and there are generally problems of high process complexity and compromise between linearity and other performance indicators. Summary of the invention

[0011] In order to solve the above problems existing in the prior art, the present invention provides a device, a preparation method and a layout structure based on active area driving force redistribution. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0012] In a first aspect, the present invention proposes a device based on an asymmetric active region, the device comprising: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode and a gate electrode;

[0013] The substrate layer, the nucleation layer, the buffer layer, the channel layer and the barrier layer are stacked in sequence from bottom to top to form an epitaxial substrate;

[0014] A source active region and a drain active region are formed in the epitaxial substrate;

[0015] The source electrode and the drain electrode are respectively arranged on one side of the source active region and one side of the drain active region; the gate electrode is arranged between the source electrode and the drain electrode;

[0016] The source active region and the drain active region are asymmetrically distributed on both sides of the gate electrode to form an asymmetrical active region, thereby realizing the redistribution of the driving capabilities of the source active region and the drain active region of the device.

[0017] In the second aspect, the present invention proposes a device layout structure based on active area driving force redistribution, the layout structure includes a device core area, the device core area includes a source active area, a source electrode, a drain active area, a drain electrode and a gate electrode, the source active area and the drain active area are asymmetrically distributed on both sides of the gate electrode; the device core area adopts the active area design scheme of the device based on active area driving force redistribution provided by the first aspect of the present invention, and leads out a metal PAD through a T-type or U-type interconnection method to realize probe testing.

[0018] In a third aspect, the present invention provides a method for preparing a device based on active area driving force redistribution, which is used to prepare the device based on active area driving force redistribution provided by the first aspect of the present invention, and the preparation method comprises the following steps:

[0019] A nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially prepared on a substrate to form an epitaxial substrate;

[0020] Using a pre-prepared asymmetric ohmic region mask, photolithography a source electrode region and a drain electrode region on the barrier layer, and fabricating a source electrode and a drain electrode;

[0021] Using a pre-prepared asymmetric active region mask, active region isolation is performed on the epitaxial substrate to form an asymmetric source active region and a drain active region;

[0022] forming a dielectric layer on the source electrode, the drain electrode and the barrier layer;

[0023] Photolithography and etching a gate electrode region on the dielectric layer, and manufacturing a gate electrode in the gate electrode region; the gate electrode is located between the source electrode and the drain electrode;

[0024] The dielectric layer above the source electrode and the drain electrode is removed, and a metal interconnection layer is made to complete the device preparation.

[0025] Beneficial effects of the present invention:

[0026] The present invention improves the conduction capability of the source active region relative to the drain active region by designing the source active region and the drain active region into an asymmetric structure and redistributing the driving capability of the source active region and the drain active region of the device, reduces the voltage division at the source end, prevents the electric field in the source active region from reaching the critical level of inducing electron velocity quasi-saturation, curbs the decrease of electron mobility and the increase of source end series resistance, improves the bell-shaped profile of transconductance, and thus improves the linearity of the device. Compared with the existing device-level linearization technology, this solution only needs to change the mask of the two-step lithography of ohm and active region isolation on the basis of the conventional device standard process, without introducing additional processes, and improves the device linearity without increasing the process complexity and preparation cost; and the process cycle is not extended compared with the current mature standard process, achieving compatibility between yield, stable device performance and high linearity.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a device based on active area driving force redistribution provided by an embodiment of the present invention;

[0029] Figure 2It is a schematic diagram of a top view of a device based on active area driving force redistribution provided by an embodiment of the present invention and a conventional device;

[0030] Figure 3 is a comparison diagram of the source terminal series resistance versus drain current variation trend of a device based on active area driving force redistribution provided by an embodiment of the present invention and a conventional device;

[0031] Figure 4 is a comparison diagram of transfer characteristic curves of a device based on active area driving force redistribution provided by an embodiment of the present invention and a conventional device;

[0032] Figure 5 This is a schematic diagram of the layout structure of the currently commonly used RF GaN HEMT T-type interconnect;

[0033] Figure 6 This is a schematic diagram of the layout structure of the currently commonly used RF GaN HEMT U-type interconnect;

[0034] Figure 7 It is a schematic diagram of a first layout structure of a device core area in the RF GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present invention;

[0035] Figure 8 It is a schematic diagram of a second layout structure of a device core area in the RF GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present invention;

[0036] Fig. 9 It is a schematic diagram of a third layout structure of a device core area in the RF GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present invention;

[0037] Fig.10 It is a schematic diagram of a fourth layout structure of a device core area in the RF GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present invention;

[0038] Fig.11 It is a schematic diagram of the fifth layout structure of the device core area in the RF GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present invention;

[0039] Fig.12 It is a schematic diagram of the sixth layout structure of the device core area in the RF GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present invention;

[0040] Fig.13 It is a schematic flow chart of a method for preparing a device based on active area driving force redistribution provided by an embodiment of the present invention;

[0041] Fig.14It is a process flow chart of manufacturing a device based on active area driving force redistribution provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] For GaN HEMT devices, the source series resistance (R S ) at high current (I DS ) is one of the sources of its inherent nonlinearity. This undesirable growth causes the transconductance of the device to roll off under large gate voltages. In RF applications, this will result in the suppression of the signal amplification capability under high input power, resulting in additional signal distortion, making it difficult to meet the application requirements of high linearity. Since the DC transconductance of the device is intuitive and easy to characterize, when the R S When the trend of transconductance roll-off is observed to be alleviated, it can be preliminarily considered that the linearity of the device has been improved.

[0044] Generally speaking, the extrinsic transconductance (G m,ext ) and the source terminal series resistance (R S ) can be expressed by the following formula (1):

[0045] G m,ext =G m,int / (1+R s ·G m,int ) (1);

[0046] In the formula, G m,int is the intrinsic transconductance obtained when the series resistance is neglected.

[0047] According to formula (1), the device extrinsic transconductance (G m,ext ) and the source series resistance (R S ). When the device linearity is not optimized, the source series resistance shows a nonlinear growth trend with the increase of drain current, which makes the transconductance present a non-ideal bell-shaped shape. Although the influence of the source series resistance cannot be completely removed in the actual device preparation process, the bell-shaped profile of the transconductance can be improved by suppressing its nonlinear growth trend.

[0048] Since the resistance of the source and drain active regions of the device is directly related to the current driving capability of the corresponding source and drain, the relative size of the source and drain active region resistance can be changed by redistributing the driving capability of the two, thereby improving the linearity of the device. According to the resistance law, when the resistivity ρ is constant, the resistance of the conductor is proportional to its length L and inversely proportional to the cross-sectional area S, as shown in formula (2):

[0049]

[0050] From the above analysis, it can be seen that the conduction capability of the source and drain terminals can be changed by adjusting the width of the source / drain active region (ie, the cross-sectional area S of the active region resistor) or the length L of the active region (ie, the gate-source / gate-drain spacing).

[0051] Based on this, the present invention proposes a device-level linearity improvement technology based on active area driving force redistribution. Through the design of asymmetric active areas, the driving capabilities of the source active area and the drain active area of ​​the device are redistributed, aiming to improve the conduction capability of the source active area relative to the drain active area, reduce the source end voltage division, suppress the electric field in the source active area from reaching the critical level of inducing electron velocity quasi-saturation, and weaken the dependence of the source end series resistance on the drain current.

[0052] Specifically, the first aspect of the present invention provides a device based on active area driving force redistribution. Figure 1 , Figure 1 1 is a schematic structural diagram of a device based on active area driving force redistribution provided by an embodiment of the present invention, the device comprising: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode S, a drain electrode G and a gate electrode D;

[0053] The substrate layer, the nucleation layer, the buffer layer, the channel layer and the barrier layer are stacked in sequence from bottom to top to form an epitaxial substrate;

[0054] A source active region and a drain active region are formed in the epitaxial substrate;

[0055] The source electrode and the drain electrode are respectively arranged on one side of the source active region and one side of the drain active region; the gate electrode is arranged between the source electrode and the drain electrode;

[0056] The source active region and the drain active region are asymmetrically distributed on both sides of the gate electrode to form an asymmetrical active region, thereby realizing the redistribution of the driving capabilities of the source active region and the drain active region of the device.

[0057] The device based on active area driving force redistribution provided in this embodiment (i.e., asymmetric active area device) is mainly illustrated by RF GaN HEMT device. Regarding the materials of each layer structure of the device, this embodiment is designed as follows: the substrate layer material includes but is not limited to one of silicon carbide (SiC), silicon (Si), sapphire and other materials; the buffer layer material includes but is not limited to one of GaN, aluminum nitride (AlN), aluminum gallium nitride (AlGaN) and other materials; the channel layer material includes but is not limited to one of GaN, indium gallium nitride (InGaN), AlGaN and other materials; the barrier layer material includes but is not limited to one of AlGaN, indium aluminum nitride (InAlN), AlN and other materials; the source electrode and the drain electrode are Ti, Al, Ni, Au metal stack structures from bottom to top; the gate electrode is Ni, Au two-layer metal stack structure from bottom to top. The thickness and other dimensions of each layer structure can be designed according to the existing device structure design, and this embodiment does not make specific restrictions on this.

[0058] Further, according to the above formula (2), the design of the asymmetric active area in this embodiment can be implemented in the following three ways:

[0059] Method 1: The source active region and the drain active region are based on the principle of width redistribution to form an asymmetric active region with unequal widths;

[0060] Method 2: The source active region and the drain active region are based on the length redistribution principle to form an asymmetric active region with unequal lengths;

[0061] Method 3: The source active area and the drain active area are based on the length and width redistribution principle to form an asymmetric active area with unequal length and width.

[0062] Optionally, as a specific implementation form of the first approach, an asymmetric design may be adopted in which the source active region and the drain active region are trapezoidal structures, and the width of the source active region is greater than that of the drain active region.

[0063] Specifically, see Figure 2 , Figure 2 Schematic diagrams of top view structures of a device based on active area driving force redistribution and a conventional device provided by an embodiment of the present invention. The left side (a) is a schematic diagram of the top view structure of a device based on active area driving force redistribution (i.e., an asymmetric active area device), and the right side (b) is a schematic diagram of the top view structure of a conventional device. Figure 2 In the example, the width of the source active region is W. S , length L GS , the width of the drain active area is W D , length L GD It can be seen that the width W of the source active area of ​​the asymmetric active area device on the left is SGreater than the width W of the drain active area D , the width W of the source active area of ​​the conventional device on the right S The width W of the drain active area D equal.

[0064] It should be noted that the current mature GaN RF devices have generally adopted the design of gate electrode biased towards source electrode (i.e. Figure 2 L GD Usually larger than L GS ) to improve the frequency characteristics of the device. The present invention changes the structure of the ohmic electrode and the active area isolation mask on the basis of retaining the gate bias source design.

[0065] Optionally, as a second implementation form of the first method, the source active region and the drain active region are both rectangular structures; the drain electrode is an asymmetric design of an array structure under the periodic blocking of the active region isolation mask, so that the width of the source active region is greater than the width of the drain active region. For this structural design, please refer to the following and Figure 8 For version Figure 2 introduction to understand.

[0066] Further, for the above-mentioned method 2, as a first optional implementation form, this embodiment can adopt the following asymmetric active area design with unequal lengths, that is, the source active area is a rectangular structure, and the drain active area is a bulge-shaped structure with recessed ends and protruding in the middle in the width direction, so as to further increase the difference between the length of the source active area and the length of the drain active area on the basis of the existing design of the gate electrode biased towards the source electrode. For this structural design, please refer to the following and Fig. 9 For version Figure 3 introduction to understand.

[0067] In addition, as a second implementation form of the second method, this embodiment can adopt the following asymmetric active area design with unequal lengths, that is, the source active area is a rectangular structure, and the drain active area is a bowl-shaped structure with protruding ends and a concave middle in the width direction, so as to further increase the difference between the length of the source active area and the length of the drain active area on the basis of the existing design of the gate electrode biased toward the source electrode. For this structural design, please refer to the following and Fig.10 For version Figure 4 introduction to understand.

[0068] Further, for the third method, as a first optional implementation form, this embodiment can adopt the following asymmetric active area design with unequal length and width, that is, the source active area is a rectangular structure, the drain active area is a comb-shaped structure in the width direction, the drain electrode is an array structure, and adjacent arrays are not blocked, so that on the basis of the existing gate electrode biased source electrode design, the width of the source active area is greater than the width of the drain active area, and the difference between the length of the source active area and the length of the drain active area is increased. For this structural design, please refer to the following and Fig.11 For version Figure 5 introduction to understand.

[0069] In addition, as a second implementation form of the third method, this embodiment can adopt the following asymmetric active area design with unequal length and width, that is, the source active area is a rectangular structure, and the drain active area and the drain electrode are aligned and spliced ​​in the width direction. Comb-shaped structure, so that the width of the source active area is greater than the width of the drain active area on the basis of the existing gate electrode biased toward the source electrode design, and the difference between the length of the source active area and the length of the drain active area is increased. For this structural design, please refer to the following and Fig.12 For version Figure 6 introduction to understand.

[0070] It is understandable that in addition to the asymmetric active area structure designs listed above, other forms of asymmetric designs can also be used. For example, a layout design including but not limited to comb-shaped, bowl-shaped, bulge-shaped and other structures can be used on one side of the source active area to improve the driving capability of the source active area relative to the drain active area, weaken the dependence of the source end series resistance on the drain current, and achieve the purpose of improving the linearity of the device.

[0071] In addition, a dielectric layer is also provided on the upper surface of the asymmetric active region device, and the dielectric layer material includes but is not limited to one of silicon nitride (SiN), silicon oxide (SiO2), aluminum oxide (Al2O3) and the like. A metal interconnection layer is also provided on each electrode of the device, and the metal interconnection layer is a two-layer metal stack structure of Ti and Au from bottom to top. The thickness and other dimensions of each layer structure can be designed according to the existing device structure design, and this embodiment does not specifically limit this.

[0072] The performance comparison between the device based on active area driving force redistribution provided by the embodiment of the present invention and the conventional device is as follows: Figure 3 and Figure 4 As shown, Figure 3 is the normalized source terminal series resistance (R) of the device based on active area driving force redistribution and the conventional device. S / R S0 ) with the change trend of drain current, Figure 4The figure is a comparison of the transfer characteristic curves of the device based on active area driving force redistribution and the conventional device. It can be seen that the source end series resistance of the conventional device shows a nonlinear growth trend with the increase of drain current, which makes the device transconductance present a non-ideal bell-shaped shape. After the linearity is optimized by using an asymmetric active area, the nonlinear growth trend of the source end series resistance of the device with the increase of drain current is significantly alleviated, thereby achieving a flatter transconductance profile.

[0073] It can be seen that the present invention improves the conduction capability of the source active region relative to the drain active region by designing the source active region and the drain active region into an asymmetric structure, reduces the voltage division at the source end, and prevents the electric field applied to the source active region from reaching the critical level of inducing electron velocity quasi-saturation, thereby weakening the dependence of the source end series resistance on the drain current, improving the bell-shaped profile of the transconductance, and improving the linearity of the device. When implementing the asymmetric active region scheme, it is only necessary to redesign the photolithography mask for active region isolation and change the photolithography mask of the ohmic region accordingly.

[0074] Compared with the existing device-level linearization technology, this solution only needs to change the two-step lithography mask of ohmic and active area isolation based on the standard process of conventional devices, without introducing additional steps, thus improving the device linearity without increasing the process complexity and preparation cost; and the process cycle is not extended compared with the current mature standard process, thus achieving compatibility between yield, stable device performance and high linearity.

[0075] Based on the same inventive concept, the second aspect of the present invention also provides a device layout structure based on active area driving force redistribution, the layout structure including a device core area, the device core area including a source active area, a source electrode, a drain active area, a drain electrode and a gate electrode, the source active area and the drain active area are asymmetrically distributed on both sides of the gate electrode; wherein, the device core area adopts the active area design scheme of the device based on active area driving force redistribution proposed in the first aspect above, and leads out a metal PAD through a T-type or U-type interconnection method to realize probe testing.

[0076] Specifically, see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the layout structure of the currently commonly used RF GaN HEMT T-type interconnection. Among them, the gate has two fingers, one on the left and one on the right, which are connected to the gate interconnection PAD through the interconnection opening area in the middle. Figure 6This is a schematic diagram of the layout structure of the currently commonly used RF GaN HEMT U-type interconnect. Among them, the gate is two parallel fingers, connected to the gate interconnect PAD through the interconnect opening area on the left. The gate index of this U-type interconnect structure is not limited to two fingers. Two fingers and multiples of two fingers can use this interconnect structure. The source electrode and drain electrode between multiple fingers also need to be connected using an air bridge process.

[0077] The present invention designs different asymmetric active area structures in the device core area in the T-type and U-type interconnection layout structures. It can be understood that the layout design of the device core area of ​​the T-type and U-type interconnection structures is different only in the interconnection form, and the functions implemented are the same. The following is a detailed introduction to the different layout designs of the device core area of ​​the T-type and U-type interconnection structures in combination with the implementation methods of the above three asymmetric structures.

[0078] version Figure 1

[0079] See also Figure 7 , Figure 7 This is a schematic diagram of the first layout structure of the device core area in the RF GaN HEMT T-type and U-type interconnection structures provided by the embodiment of the present invention; wherein the upper figure is a T-type interconnection structure, and the lower figure is a U-type interconnection structure. Figure 7 In the example, the source active region and the drain active region are both trapezoidal in shape, and the width of the source active region is W S Greater than the drain active area width W D , corresponding to the above Figure 1 and Figure 2 The structure shown in Figure (a) is the first implementation form of the above method 1. Compared with the preparation process of conventional GaN HEMT devices, Figure 7 The structure shown requires replacement of the mask for the two-step lithography for ohmic and active area isolation.

[0080] version Figure 2

[0081] See also Figure 8 , Figure 8 This is a schematic diagram of the second layout structure of the device core area in the RF GaN HEMT T-type and U-type interconnection structures provided by the embodiment of the present invention, corresponding to the second implementation form of the above-mentioned method one; wherein the upper figure is a T-type interconnection structure, and the lower figure is a U-type interconnection structure. Figure 8 In the example, the source and drain active regions are both rectangular, and the mask of the drain active region is comb-shaped. The mask of the drain ohmic region is blocked along the gate width to form an array structure, so that the drain electrode also has an array structure. The array-shaped drain electrode is connected to the interconnect metal through the mask of the opening region to complete the current collection. The width of the drain active region corresponding to a single tooth of the mask of the drain ohmic region is Δw. When the number of teeth is n, the total width of the corresponding drain active region is W.D =n×Δw, this design can still ensure W S >W D Understandably, Figure 8 The structure shown requires replacement of the mask for the two-step lithography for ohmic and active area isolation.

[0082] version Figure 3

[0083] See also Fig. 9 , Fig. 9 This is a schematic diagram of the third layout structure of the device core area in the RF GaN HEMT T-type and U-type interconnection structures provided by the embodiment of the present invention, corresponding to the first implementation form of the above-mentioned method 2; wherein the upper figure is a T-type interconnection structure, and the lower figure is a U-type interconnection structure. Fig. 9 In the example, the source active region is a rectangle, and the drain active region is a bulge-like structure with recessed ends and a protruding middle. Fig. 9 The asymmetric structure shown in the figure has the least resistance to conduction current, which flows from the source, through the gate, and then through L GDmin The distance is collected on both sides of the drain, and the way with the greatest resistance to conduction current is to flow from the source, pass through the gate, and flow through L GDmax The distance is collected in the middle of the drain.

[0084] version Figure 4

[0085] See also Fig.10 , Fig.10 This is a schematic diagram of the fourth layout structure of the device core area in the RF GaN HEMT T-type and U-type interconnection structures provided by the embodiment of the present invention, corresponding to the second implementation form of the above-mentioned method 2; wherein the upper figure is a T-type interconnection structure, and the lower figure is a U-type interconnection structure. Fig.10 In the example, the source active region is a rectangle, and the drain active region is a bowl-shaped structure with protruding ends and a concave middle. Fig. 9 The structure, Fig.10 The asymmetric structure shown in the figure has the least resistance to conduction current, which flows from the source, passes through the gate, and flows through L GDmin The distance is collected in the middle of the drain, and the way with the greatest resistance to conduction current is to flow from the source, pass through the gate, and flow through L GDmax The distance is collected by both sides of the drain.

[0086] version Figure 5

[0087] See also Fig.11 , Fig.11This is a fifth layout structure diagram of the device core area in the RF GaN HEMT T-type and U-type interconnection structures provided by the embodiment of the present invention, corresponding to the first implementation form of the above-mentioned method three; wherein the upper figure is a T-type interconnection structure, and the lower figure is a U-type interconnection structure. Fig.11 In the example, the source active region is rectangular, the drain active region is a comb-shaped structure in the width direction, and the drain ohmic region is an array-shaped structure in the width direction. Adjacent arrays are not blocked and still have the ability to conduct current. Specifically, for Fig.11 The asymmetric structure shown in the figure has the least resistance to conduction current, which flows from the source, through the gate, and then through L GDmin The distance is collected by the drain, and the way with the greatest resistance to conduction current is to flow from the source, pass through the gate, and flow through L GDmax The distance between the source and drain ends is 100 meters, and the other end is collected by the side of the arrayed ohmic electrode. In contrast, the source ohmic region is continuous and complete, with a stronger current driving capability, thus forming an unequal conduction capability between the source and drain ends.

[0088] version Figure 6

[0089] See also Fig.12 , Fig.12 This is a sixth layout structure diagram of the device core area in the RF GaN HEMT T-type and U-type interconnection structures provided by the embodiment of the present invention, corresponding to the second implementation form of the above-mentioned method three; wherein the upper figure is a T-type interconnection structure, and the lower figure is a U-type interconnection structure. Fig.12 In the embodiment, the source active region is rectangular, and the drain active region and the drain end ohmic electrode are aligned and spliced ​​in a comb-like structure along the gate width direction. Fig.12 The asymmetric structure shown in the figure has three possible current conduction modes, which can be divided into three types according to the resistance encountered during the conduction process from small to large: one is to flow from the source, pass through the gate, and flow through L GDmin After a distance of L, it is collected by the drain. Secondly, it flows out from the source, passes through the gate, and flows through a distance of L GDmin <L<L GDmax Then it is collected on the side of the comb-shaped ohmic electrode, and then flows out from the source, passes through the gate, and flows through L GDmax In contrast, the source ohmic region has only one way to conduct current with the least resistance, and has a stronger ability to drive current, thus forming an unequal conduction capability between the source and drain ends.

[0090] The above six layouts can be summarized as follows: Figure 1 and 2 Both control the inequality of the conduction capabilities of the source and drain ends by adjusting the width of the active region, that is, the cross-sectional area S of the resistor in formula (2); Figure 3 and4 The inequality of the conduction capabilities of the source and drain ends is controlled by adjusting the length of the active region, that is, the length L of the resistor in formula (2); Figure 5 and 6 At the same time, the width and length of the drain active region, that is, the cross-sectional area S and length L of the resistor in formula (2) are changed to control the inequality of the conduction capabilities of the source and drain ends.

[0091] It is understandable that the interconnection structure based on the asymmetric active region provided by the present invention is not limited to one of the T-shaped and U-shaped structures, and can be adaptively changed according to actual conditions.

[0092] The third aspect of the present invention also provides a method for preparing a device based on active area driving force redistribution. Fig.13 , Fig.13 1 is a flow chart of a method for preparing a device based on active area driving force redistribution provided by an embodiment of the present invention. The preparation method mainly comprises the following steps:

[0093] Step 1: Prepare a nucleation layer, a buffer layer, a channel layer and a barrier layer in sequence on a substrate to form an epitaxial substrate.

[0094] It is understandable that after obtaining the epitaxial substrate, it is necessary to form a pattern with a certain depth and easy to identify on the surface of the epitaxial substrate as an alignment mark for subsequent steps; it can be an etched alignment mark or a metal alignment mark, etc.

[0095] Step 2: Based on the alignment mark, use the pre-prepared ohmic area mask to photolithography the source electrode area and the drain electrode area on the barrier layer, and make the source electrode and the drain electrode.

[0096] Among them, the source electrode and the drain electrode are a bottom-up Ti, Al, Ni, and Au metal stack structure. An annealing process is required to sink the source electrode and the drain electrode into the buffer layer and are located at the two ends of the buffer layer respectively.

[0097] It should be noted here that, since the present invention has an asymmetric design for the active area of ​​the device, the shapes of the source electrode and the drain electrode also need to be changed accordingly, so it is necessary to prepare an ohmic area mask of a corresponding shape according to the actual shape of the active area in advance. It can be understood that after this step is completed, the width of the source active area and the current driving capacity of the drain active area on both sides of the gate are not equal.

[0098] Step 3: Using the pre-prepared asymmetric active area mask, isolate the active area on the epitaxial substrate to form an asymmetric source active area and a drain active area.

[0099] The asymmetric active area mask can be prepared by referring to the structural design of the second aspect of the present invention or the layout design of the second aspect. Based on the prepared asymmetric active area mask, the active area of ​​the epitaxial substrate is isolated by etching or ion implantation to prevent electrical connection between devices.

[0100] Step 4: forming a dielectric layer on the source electrode, the drain electrode and the barrier layer.

[0101] Step 5: photolithography and etching a gate electrode region on the dielectric layer, and manufacturing a gate electrode in the gate electrode region; the gate electrode is located between the source electrode and the drain electrode.

[0102] Among them, the gate electrode is a two-layer metal stack structure of Ni and Au from bottom to top.

[0103] Step 6: remove the dielectric layer above the source electrode and the drain electrode, and make a metal interconnection layer to complete the device preparation.

[0104] It can be seen that in the process of preparing the device proposed in the present invention, only the mask of the two-step lithography of ohmic and active area isolation is changed, no additional process is introduced, and the process cycle is not extended compared with the current mature standard process.

[0105] Combine the following Fig.14 The preparation process flow chart shown in the figure is used to introduce the preparation method provided by the present invention in detail. It should be noted that: Fig.14 The photolithography masks used in the steps marked with an "*" are different from the masks used in the conventional device manufacturing process.

[0106] S1. Prepare epitaxial substrate, such as Fig.14 As shown in Figure (a).

[0107] Specifically, the epitaxial substrate can be grown using a metal organic chemical vapor deposition (MOCVD) system, with triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, and ammonia (NH 3 ) as the N source, and the carrier gas was high-purity hydrogen (H 2 ). The epitaxial substrate includes a substrate layer, a nucleation layer, a buffer layer, a channel layer and a barrier layer from bottom to top.

[0108] S2. Make alignment marks on the epitaxial substrate, such as Fig.14 As shown in Figure (b).

[0109] First, an alignment mark pattern is photolithographically formed on the epitaxial substrate as follows:

[0110] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0111] (b) Apply photoresist (EPI621) on the sample, with a spinning speed of 3000 rad / min, a spinning time of 40 sec, and a thickness of more than 800 nm. Then, bake the sample on a hot plate at 90°C for 1 min.

[0112] (c) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 280 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0113] (d) placing the exposed sample in a developer (EPD1000) to remove the photoresist in the alignment mark area for 75 seconds, and then rinsing with ultrapure water and drying with nitrogen gas;

[0114] (e) Harden the film before pattern etching, and bake the sample on a hot plate at 100°C for 1 min;

[0115] Then, the ICP etching process is used, and the reaction gas is Cl 2 and BCl 3 , Cl 2 =8sccm, BCl 3 =20sccm, pressure =5mT, upper electrode power =50W, lower electrode power =15W, and an alignment mark pattern with a depth greater than 400nm needs to be etched on the epitaxial substrate.

[0116] Finally, the sample after the alignment mark etching is cleaned to remove the residual photoresist on the surface.

[0117] S3, making ohmic contacts of source electrode and drain electrode on the epitaxial substrate, such as Fig.14 As shown in Figure (c).

[0118] First, the source electrode region and the drain electrode region are photolithographically formed on the barrier layer as follows:

[0119] (a) Place the epitaxial substrate on a hot plate at 200°C and bake for 5 min;

[0120] (b) coating the stripping glue (PMGI SF6) on the barrier layer, with a spinning speed of 2000 rad / min, a spinning time of 40 sec, and a thickness of 0.35 μm. The sample was then baked on a hot plate at 200 °C for 5 min.

[0121] (c) coating photoresist (EPI621) on the stripping glue, with a spinning speed of 5000 rad / min, a spinning time of 30 sec, and a spinning thickness of 0.77 μm. The sample was then baked on a hot plate at 90° C. for 1 min.

[0122] (d) placing the sample after the coating and spinning of the glue into a photolithography machine for exposure, using the ohmic region mask designed by the present invention, with an exposure time of 230 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0123] (e) placing the substrate in a developer (EPD1000) to remove the photoresist and the stripping adhesive for 45 seconds, and then rinsing the substrate with ultrapure water and drying it with nitrogen to obtain the source electrode region and the drain electrode region defined in the present invention.

[0124] Then, the source electrode and the drain electrode are evaporated on the barrier layer in the source electrode and the drain electrode ohmic region and on the photoresist outside the source and drain ohmic region as follows:

[0125] (a) The sample with active electrode and drain electrode photolithography pattern was placed in a plasma stripper for bottom film treatment at a power of 200 W. 2 =100sccm, processing time 5min;

[0126] (b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, metal is evaporated on the barrier layer in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form the source electrode and the drain electrode. The metal is sequentially as follows from bottom to top:

[0127] (c) The sample after metal evaporation is stripped to remove the metal, photoresist and stripping glue outside the source electrode and drain electrode, and then the sample is rinsed with ultrapure water and blown dry with nitrogen.

[0128] Finally, the sample after metal evaporation and stripping was placed in a rapid thermal annealing furnace for annealing, so that the metal on the surface of the barrier layer in the area where the source electrode and the drain electrode were located could sink to the channel layer, thereby forming a good ohmic contact between the electrode and the heterojunction channel. The annealing atmosphere was N 2 , annealing temperature is 840℃, and annealing time is 60s.

[0129] S4, using etching to isolate the active area on the epitaxial substrate, such as Fig.14 As shown in Figure (d).

[0130] First, the position of the active area is determined by photolithography on the barrier layer as follows:

[0131] (a) Place the epitaxial substrate on a hot plate at 200°C and bake for 5 min;

[0132] (b) Apply photoresist (EPI621) on the surface of the epitaxial substrate, with a spinning speed of 3000 rad / min, a spinning time of 30 sec, and a thickness of more than 800 nm. Then, bake the sample on a hot plate at 90°C for 1 min.

[0133] (c) placing the sample after the coating and spinning of the glue into a photolithography machine for exposure, using the active area isolation mask designed by the present invention, with an exposure time of 230 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0134] (d) placing the photoresist in a developer (EPD1000) for 75 seconds to remove the photoresist, and then rinsing with ultrapure water and drying with nitrogen to obtain the active area defined in the present invention;

[0135] (e) Before etching, the film was hardened and the sample was baked on a hot plate at 100°C for 1 min.

[0136] Then, using the ICP process, the sample surface outside the active area is etched down to remove a portion with a thickness of about 120nm, ensuring that the area outside the active area on the epitaxial substrate has no current conduction capability. The etching reaction gas is Cl 2 and BCl 3 , Cl 2 =8sccm, BCl 3 =20sccm, pressure =5mT, upper electrode power =50W, lower electrode power =15W.

[0137] Finally, the etched samples are cleaned to remove the residual photoresist on the surface.

[0138] It is understandable that the active area isolation in step S4 can also be achieved by ion implantation. The detailed implementation process can be referred to the existing related technology, and this embodiment will not be described in detail here.

[0139] S5. On the surface of the epitaxial wafer on which the source electrode and the drain electrode are prepared, a dielectric layer is grown by a plasma enhanced chemical vapor deposition process, such as Fig.14 As shown in Figure (e).

[0140] First, the surface of the sample after the source electrode and drain electrode are made is cleaned as follows:

[0141] (a) Place the sample in an acetone solution and ultrasonically clean it for 5 min;

[0142] (b) Place the sample in a stripping solution at 60°C and heat it in a water bath for 15 min;

[0143] (c) placing the sample in acetone solution and isopropanol solution for ultrasonic cleaning for 3 min;

[0144] (d) Rinse the sample with ultrapure water and blow dry with nitrogen.

[0145] Then, a passivation layer with a thickness of 120 nm is grown on the source electrode, drain electrode and barrier layer of the active region by PECVD process. Taking SiN as an example, the process conditions for its growth are: SiN (2% SiH 4 / N 2 )=200sccm,NH 3 =2sccm, N 2 =0sccm, He=200sccm, pressure=600mT, temperature=250℃, power=22W, deposition time=25min.

[0146] S6, photolithography a gate groove region on the passivation layer, and etching the passivation layer in the gate groove region using an inductively coupled plasma (ICP) process, such as Fig.14 As shown in Figure (f).

[0147] First, the gate groove area is photolithographically formed on the passivation layer as follows:

[0148] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0149] (b) coating and spinning of electron beam photoresist, with a spinning speed of 3500 rad / min, a spinning time of 40 sec, a layer thickness of 450 nm, and baking the sample on a hot plate at 150° C. for 1 min;

[0150] (c) placing the sample in an electron beam lithography machine to expose the photoresist in the gate groove area;

[0151] (d) placing the exposed sample into a developer to remove the photoresist in the gate groove area, and drying it with nitrogen after the development;

[0152] (e) Before etching the gate groove, the film was hardened and the sample was baked on a hot plate at 130°C for 1 min.

[0153] Then, the passivation layer in the gate groove area is removed by ICP etching process, and the etching conditions are: CF 4 =60sccm, O 2 = 2 sccm, pressure = 5 mT, upper electrode power = 100 W, lower electrode power = 25 W. The etching depth is equal to the thickness of the SiN layer.

[0154] Finally, the sample after the gate groove etching is cleaned to remove the residual photoresist on the surface.

[0155] S7, photolithography the gate electrode region, and use electron beam evaporation process to make the gate electrode, such as Fig.14As shown in Figure (g).

[0156] First, the gate electrode region is photolithographically formed on the barrier layer as follows:

[0157] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0158] (b) coating the stripping glue (PMGI SF6) on the passivation layer, with a spinning speed of 1000 rad / min, a spinning time of 40 sec, and a thickness of 0.5 μm, and then baking the sample on a hot plate at 200° C. for 5 min;

[0159] (c) coating photoresist (EPI621) on the stripping glue, with a spinning speed of 5000 rad / min, a spinning time of 30 sec, and a spinning thickness of 0.77 μm. The sample was then baked on a hot plate at 90° C. for 1 min.

[0160] (d) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 280 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0161] (e) The film is placed in a developer (EPD1000) to remove the photoresist and stripping adhesive for 60 seconds, and then rinsed with ultrapure water and dried with nitrogen.

[0162] Then, the gate electrode is evaporated on the barrier layer in the gate electrode region and on the photoresist outside the gate electrode region as follows:

[0163] (a) Place the sample with the gate electrode photolithography pattern into a plasma stripper for bottom film treatment at a power of 200 W. 2 =100sccm, processing time 5min;

[0164] (b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, the gate metal is evaporated on the barrier layer in the gate electrode area and the photoresist outside the gate electrode area. The gate metal is sequentially from bottom to top.

[0165] (c) Stripping the sample after gate metal evaporation to remove the gate metal, photoresist and stripping glue outside the gate electrode area, rinse the sample with ultrapure water and blow dry with nitrogen to form a gate electrode.

[0166] S8, photolithography a metal interconnect opening area on the passivation layer, and etching away the passivation layer of the interconnect opening area using an ICP process, such as Fig.14 As shown in Figure (h).

[0167] First, the metal interconnect opening area is photolithographically formed on the passivation layer as follows:

[0168] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0169] (b) Apply photoresist (EPI621) on the sample at a spinning speed of 3000 rad / min for 30 seconds, and then bake the sample on a hot plate at 90°C for 1 minute;

[0170] (c) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 280 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0171] (d) placing the exposed sample in a developer (EPD1000) to remove the photoresist in the interconnect opening area for 75 seconds, and then rinsing with ultrapure water and drying with nitrogen gas;

[0172] (e) Before etching the metal interconnect opening area, the film was hardened and the sample was baked on a hot plate at 100°C for 1 min.

[0173] Then, the ICP etching process is used, and the reaction gas is CF 4 and O 2 , C.F. 4 =60sccm, O 2 =2sccm, pressure =5mT, upper electrode power =100W, lower electrode power =25W, remove the passivation layer in the interconnect opening area.

[0174] Finally, the sample after etching of the interconnect opening area is cleaned to remove the residual photoresist on the surface.

[0175] S9, photolithography the metal interconnection layer region on the source electrode and the drain electrode in the metal interconnection opening region and the passivation layer that has not been etched, and use an electron beam evaporation process to form a metal interconnection layer, such as Fig.14 As shown in Figure (i).

[0176] First, a metal interconnection layer is photolithographically formed on the source electrode and the drain electrode in the metal interconnection opening area and the passivation layer that is not etched by the opening, as follows:

[0177] (a) Place the sample with metal interconnect hole etching on a hot plate at 200°C for 5 min.

[0178] (b) coating the stripping glue (PMGI SF6) on the barrier layer, with a spinning speed of 2000 rad / min, a spinning time of 40 sec, and a thickness of 0.35 μm. The sample was then baked on a hot plate at 200 °C for 5 min.

[0179] (c) coating photoresist (EPI621) on the stripping glue, with a spinning speed of 5000 rad / min, a spinning time of 30 sec, and a spinning thickness of 0.77 μm. The sample was then baked on a hot plate at 90° C. for 1 min.

[0180] (d) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 270 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0181] (e) The photoresist and stripping glue in the metal interconnection area are removed in a developer (EPD1000) for 60 seconds, and then the film is rinsed with ultrapure water and dried with nitrogen gas.

[0182] Then, a metal interconnect layer is evaporated on the electrode and the passivation layer in the metal interconnect area and the photoresist outside the metal interconnect area as follows:

[0183] (a) The sample with metal interconnection area is placed in a plasma stripper for bottom film treatment, with a power of 200 W. 2 =100sccm, processing time 5min;

[0184] (b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After the Torr, the interconnection metal is evaporated on the electrode and passivation layer in the metal interconnection area and the photoresist outside the metal interconnection area to form a metal interconnection layer. The metal interconnection layer is sequentially formed from bottom to top. To extract the electrode;

[0185] (c) The sample after interconnect metal evaporation is stripped to remove the metal, photoresist and stripping glue outside the metal interconnect area layer, and the sample is rinsed with ultrapure water and blown dry with nitrogen.

[0186] At this point, the preparation of the asymmetric active region device is completed.

[0187] In summary, the device with asymmetric active region provided by the present invention has the following beneficial effects:

[0188] First, it can improve the nonlinearity of GaN HEMT; second, compared with the previously reported device-level linearization technology, only the lithography mask for isolating the ohmic and active areas is changed on the basis of the conventional process, which has low process complexity and short process cycle; finally, since only the mask in the standard process is changed, it provides a larger design margin and process window for improving other device performance (such as operating frequency and output power).

[0189] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0190] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0191] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0192] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A device based on active area driving force redistribution, characterized in that: The device comprises: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode and a gate electrode; The substrate layer, the nucleation layer, the buffer layer, the channel layer and the barrier layer are stacked in sequence from bottom to top to form an epitaxial substrate; A source active region and a drain active region are formed in the epitaxial substrate; The source electrode and the drain electrode are respectively arranged on one side of the source active region and one side of the drain active region; the gate electrode is arranged between the source electrode and the drain electrode; The source active region and the drain active region are asymmetrically distributed on both sides of the gate electrode to form an asymmetrical active region, thereby realizing the redistribution of the driving capabilities of the source active region and the drain active region of the device.

2. The device based on active area driving force redistribution according to claim 1, characterized in that: The source active region and the drain active region form asymmetric active regions with unequal widths based on the principle of width redistribution; Alternatively, the source active region and the drain active region form asymmetric active regions with unequal lengths based on a length redistribution principle; Alternatively, the source active region and the drain active region form asymmetric active regions with unequal lengths and widths based on the length and width redistribution principle.

3. The device based on active area driving force redistribution according to claim 2, characterized in that: The source active region and the drain active region are both trapezoidal structures, and the width of the source active region is greater than the width of the drain active region.

4. The device based on active area driving force redistribution according to claim 2, characterized in that: The source active region and the drain active region are both rectangular structures; the drain electrode is in an array structure under the periodic blocking of the active region isolation mask, so that the width of the source active region is greater than the width of the drain active region.

5. The device based on active area driving force redistribution according to claim 2, characterized in that: The source active region is a rectangular structure, and the drain active region is a bulge-like structure with concave ends and protruding in the middle in the width direction, so as to increase the difference between the length of the source active region and the length of the drain active region.

6. The device based on active area driving force redistribution according to claim 2, characterized in that: The source active region is a rectangular structure, and the drain active region is a bowl-shaped structure with protruding ends and a recessed middle in the width direction, so as to increase the difference between the length of the source active region and the length of the drain active region.

7. The device based on active area driving force redistribution according to claim 2, characterized in that: The source active region is a rectangular structure, the drain active region is a comb-shaped structure in the width direction, the drain electrode is an array-shaped structure, and adjacent arrays are not blocked, so that the width of the source active region is greater than the width of the drain active region, and the difference between the length of the source active region and the length of the drain active region is increased.

8. The device based on active area driving force redistribution according to claim 2, characterized in that: The source active region is a rectangular structure, and the drain active region and the drain electrode are aligned and spliced ​​in a comb-like structure in the width direction, so that the width of the source active region is greater than the width of the drain active region, and the difference between the length of the source active region and the length of the drain active region is increased.

9. A device layout structure based on active area driving force redistribution, characterized in that: The layout structure includes a device core area, and the device core area includes a source active area, a source electrode, a drain active area, a drain electrode and a gate electrode, and the source active area and the drain active area are asymmetrically distributed on both sides of the gate electrode; the device core area adopts the active area design scheme of the device based on active area driving force redistribution as described in any one of claims 1 to 8, and leads out a metal PAD through a T-shaped or U-shaped interconnection method to realize probe testing.

10. A method for preparing a device based on active area driving force redistribution, used for preparing the device based on active area driving force redistribution according to any one of claims 1 to 8, characterized in that: The preparation method comprises the following steps: A nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially prepared on a substrate to form an epitaxial substrate; Using a pre-prepared asymmetric ohmic region mask, photolithography a source electrode region and a drain electrode region on the barrier layer, and fabricating a source electrode and a drain electrode; Using a pre-prepared asymmetric active area mask, active area isolation is performed on the epitaxial substrate to form an asymmetric source active area and a drain active area; forming a dielectric layer on the source electrode, the drain electrode and the barrier layer; Photolithography and etching a gate electrode region on the dielectric layer, and manufacturing a gate electrode in the gate electrode region; the gate electrode is located between the source electrode and the drain electrode; The dielectric layer above the source electrode and the drain electrode is removed, and a metal interconnection layer is formed, thereby completing the device preparation.

Images