Silicon carbide epitaxial wafer, preparation method, silicon carbide device and electronic equipment

Abstract

The embodiment of the invention provides a silicon carbide epitaxial wafer, a preparation method, a silicon carbide device and electronic equipment, relates to the technical field of semiconductors, and is used for improving the performance of the silicon carbide epitaxial wafer. The silicon carbide epitaxial wafer comprises a substrate, a buffer layer and a drift layer, the buffer layer is arranged on one side of the substrate and doped with nitrogen impurities and isoelectronic impurities; the doping concentration of nitrogen impurities in the buffer layer is the first doping concentration. The drift layer is arranged on one side, far away from the substrate, of the buffer layer and is doped with nitrogen impurities; the doping concentration of the nitrogen impurity in the drift layer is a second doping concentration, and the second doping concentration is smaller than the second doping concentration; the difference value of the lattice constants of the buffer layer and the drift layer at the contact interface is smaller than a reference value, the reference value is the difference value of the lattice constants between the two reference epitaxial layers, the two reference epitaxial layers are silicon carbide epitaxial layers doped with nitrogen impurities, and the doping concentrations of the nitrogen impurities are the first doping concentration and the second doping concentration respectively. The silicon carbide epitaxial wafer can be used for preparing a silicon carbide device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide epitaxial wafer, a preparation method, a silicon carbide device and an electronic device. Background Art

[0002] Silicon carbide (SiC) has many excellent physical properties such as large bandgap, high carrier saturation migration velocity, high thermal conductivity and high critical breakdown field strength, making it a semiconductor material with broad application prospects in the fields of high-temperature, high-power and high-frequency electronic power devices. Silicon carbide devices refer to semiconductor devices that use silicon carbide as semiconductor materials. Silicon carbide devices have the advantages of high input impedance, high switching speed stability, and low on-resistance, and are suitable for high-power and high-frequency applications.

[0003] Silicon carbide devices are usually prepared on silicon carbide epitaxial wafers, which have become the basis for preparing most silicon carbide devices, and the performance of silicon carbide epitaxial wafers has also become a key factor affecting the performance of silicon carbide devices. In a silicon carbide epitaxial wafer provided in the related art, it includes a substrate and an epitaxial layer, and the epitaxial layer is arranged on one side of the substrate, including a buffer layer and a drift layer stacked along the thickness direction of the substrate.

[0004] However, the silicon carbide epitaxial wafer provided by the related art is prone to extended defects between the buffer layer and the drift layer, which affects the performance of the silicon carbide epitaxial wafer. Summary of the invention

[0005] The embodiments of the present application provide a silicon carbide epitaxial wafer, a preparation method, a silicon carbide device and an electronic device, which are used to improve the problem in the related art that the silicon carbide epitaxial wafer is prone to extended defects between the buffer layer and the drift layer, which affects the performance of the silicon carbide epitaxial wafer.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a silicon carbide epitaxial wafer, which includes a substrate, a buffer layer and a drift layer; wherein the buffer layer is arranged on one side of the substrate and is doped with nitrogen impurities and isoelectronic impurities; the doping concentration of the nitrogen impurities in the buffer layer is a first doping concentration.

[0008] The drift layer is arranged on a side of the buffer layer away from the substrate and is doped with nitrogen impurities; the doping concentration of the nitrogen impurities in the drift layer is a second doping concentration, and the second doping concentration is less than the second doping concentration;

[0009] The difference in lattice constants between the buffer layer and the drift layer at the contact interface is less than a reference value, and the reference value is the difference in lattice constants between two reference epitaxial layers. Both reference epitaxial layers are silicon carbide epitaxial layers doped with nitrogen impurities, and the doping concentrations of the nitrogen impurities are respectively a first doping concentration and a second doping concentration.

[0010] In the silicon carbide epitaxial wafer provided in the embodiment of the present application, the buffer layer is doped with isoelectronic impurities on the basis of being doped with nitrogen impurities. The isoelectronic impurities can compensate for the lattice contraction of the buffer layer caused by nitrogen doping, so that the lattice constant of the buffer layer becomes larger; and by controlling the doping of isoelectronic impurities, the difference in lattice constants between the buffer layer and the drift layer at the contact interface can be reduced compared with the related art under the condition of the same nitrogen doping concentration, thereby reducing the lattice mismatch stress between the buffer layer and the drift layer at the contact interface. The reduction of lattice mismatch stress can effectively inhibit the slip of base plane dislocation (Baselplane dislocation, abbreviated BPD) at the contact interface between the buffer layer and the drift layer, thereby reducing the generation of half loop array (Half Loop Array, abbreviated HLA) dislocations, thereby achieving the purpose of improving the performance of silicon carbide epitaxial wafers and improving the performance of silicon carbide devices prepared using the silicon carbide epitaxial wafers.

[0011] In addition, isoelectronic impurities are doped in the buffer layer of the silicon carbide epitaxial wafer, without the need to introduce additional insertion layers, thereby avoiding increasing the thickness of the silicon carbide epitaxial wafer. Moreover, the doping of isoelectronic impurities can be achieved during the process of silicon carbide epitaxy, thereby avoiding the impact on the output efficiency of the epitaxial process. At the same time, the doping of isoelectronic impurities does not require the introduction of changes in other epitaxial process parameters, thereby avoiding the impact on epitaxial process regulation, especially defect density control.

[0012] In some embodiments, the doping concentration of isoelectronic impurities in the buffer layer is a third doping concentration; the third doping concentration increases continuously in the buffer layer in a direction away from the substrate. The isoelectronic impurities are doped in the buffer layer with the third doping concentration designed as described above, so that the isoelectronic impurities can gradually compensate for the lattice contraction caused by nitrogen doping in the buffer layer, thereby gradually increasing the lattice constant of the buffer layer in a direction away from the substrate, and realizing a gradual change in the lattice constant of the buffer layer. With such a design, on the basis of ensuring that the difference in lattice constants between the buffer layer and the drift layer at the contact interface meets the requirements, on the one hand, the film quality of the buffer layer can be ensured by gradually increasing the isoelectronic impurity doping; on the other hand, the difference in lattice constants between the substrate and the buffer layer can be taken into account, thereby improving the contact quality between the substrate and the buffer layer; thereby being beneficial to improving the performance of silicon carbide epitaxial wafers and the performance of silicon carbide devices prepared using the silicon carbide epitaxial wafers.

[0013] In addition, the design of continuously increasing the third doping concentration can be achieved by changing the flow rate of the doping source gas flow without introducing changes in other epitaxial process parameters, thereby avoiding the impact on epitaxial process regulation, especially defect density control.

[0014] In some embodiments, the third doping concentration increases continuously in the buffer layer in a linear, parabolic or exponential manner in a direction away from the substrate. The third doping concentration designed in the above increasing manner in the buffer layer is relatively easy to achieve, thereby helping to reduce the difficulty of manufacturing silicon carbide epitaxial wafers.

[0015] In some embodiments, the doping concentration of isoelectronic impurities in the buffer layer is a third doping concentration; in the direction away from the substrate, the third doping concentration increases in a step-by-step manner in the buffer layer. In the silicon carbide epitaxial wafer using the above design, the lattice constant of the buffer layer increases in a step-by-step manner in the direction away from the substrate. With such a design, on the basis of ensuring that the difference in lattice constants between the buffer layer and the drift layer at the contact interface meets the requirements, on the one hand, the film quality of the buffer layer can be ensured by gradually increasing the doping of isoelectronic impurities; on the other hand, the difference in lattice constants between the substrate and the buffer layer can be taken into account to improve the contact quality between the substrate and the buffer layer; thereby, it is beneficial to improve the performance of silicon carbide epitaxial wafers and the performance of silicon carbide devices prepared using the silicon carbide epitaxial wafers. In addition, it is beneficial to make different parts of the buffer layer in steps according to the step-by-step growth law, thereby reducing the difficulty of making the buffer layer.

[0016] In some embodiments, the variation range of the third doping concentration in the buffer layer is within an optional concentration range, and the optional concentration range is [0,1×10 20 cm -3 ]. This design can flexibly select the appropriate doping concentration of isoelectronic impurities while ensuring that the slip of BPD at the contact interface between the buffer layer and the drift layer can be effectively suppressed and the generation of HLA dislocations can be reduced. It can also be adapted to silicon carbide epitaxial wafers with different parameters, with good adaptability and a wide range of applications.

[0017] In some embodiments, the maximum value of the third doping concentration in the buffer layer is equal to the first doping concentration. With such a design, on the basis of ensuring that the slip of BPD at the contact interface between the buffer layer and the drift layer can be effectively suppressed and the generation of HLA dislocations can be reduced, the uniformity of nitrogen impurities and isoelectronic impurities doped simultaneously in the buffer layer can be improved at the contact interface between the buffer layer and the drift layer, which is beneficial to improving the interface quality of the contact interface between the buffer layer and the drift layer, thereby facilitating the improvement of the performance of the silicon carbide epitaxial wafer and the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0018] In some embodiments, the doping concentration of the isoelectronic impurities in the buffer layer is a third doping concentration; the third doping concentration is a constant value in the buffer layer. Such a design can reduce the process difficulty when doping with isoelectronic impurities, which is conducive to improving the output efficiency of silicon carbide epitaxial wafers.

[0019] In some embodiments, the third doping concentration is any value in an optional concentration range, and the optional concentration range is [0,1×10 20 cm -3 ]. This design can flexibly select the appropriate doping concentration of isoelectronic impurities while ensuring that the slip of BPD at the contact interface between the buffer layer and the drift layer can be effectively suppressed and the generation of HLA dislocations can be reduced. It can also be adapted to silicon carbide epitaxial wafers with different parameters, with good adaptability and a wide range of applications.

[0020] In some embodiments, the third doping concentration is equal to the first doping concentration. With such a design, the uniformity of nitrogen impurities and isoelectronic impurities doped in the buffer layer can be improved while ensuring that the slip of BPD at the contact interface between the buffer layer and the drift layer can be effectively suppressed and the generation of HLA dislocations can be reduced, which is beneficial to improving the performance of silicon carbide epitaxial wafers and the performance of silicon carbide devices prepared using the silicon carbide epitaxial wafers.

[0021] In some embodiments, the difference in lattice constants between the buffer layer and the drift layer at the contact interface is zero. With such a design, the difference in lattice constants between the buffer layer and the drift layer at the contact interface can be made zero, thereby avoiding the generation of lattice mismatch stress between the buffer layer and the drift layer at the contact interface, and thus effectively avoiding the slip of BPD at the contact interface between the buffer layer and the drift layer, avoiding the generation of HLA dislocations, and achieving the purpose of improving the performance of silicon carbide epitaxial wafers and the performance of silicon carbide devices prepared using the silicon carbide epitaxial wafers.

[0022] In some embodiments, the isoelectronic impurities include at least one of germanium, tin and lead. In the silicon carbide epitaxial wafer provided in the embodiments of the present application, the isoelectronic impurities have a variety of options, so that the appropriate isoelectronic impurities can be flexibly selected according to the actual application scenario, and the applicability is good, which can meet the requirements of different application scenarios.

[0023] In a second aspect, the present application also provides a method for preparing a silicon carbide epitaxial wafer, the method comprising:

[0024] A growth gas source, a nitrogen doping gas source and an isoelectronic doping gas source are introduced into a reaction chamber where a substrate is placed, and a buffer layer is formed on one side of the substrate;

[0025] After the buffer layer is formed, the introduction of the isoelectronic doping gas source is stopped;

[0026] A drift layer is formed on a side of the buffer layer away from the substrate.

[0027] In the silicon carbide epitaxial wafer prepared by the above preparation method, the buffer layer is doped with isoelectronic impurities on the basis of being doped with nitrogen impurities. The isoelectronic impurities can compensate for the lattice shrinkage of the buffer layer caused by nitrogen doping, and by controlling the doping of isoelectronic impurities, the difference in lattice constants between the buffer layer and the drift layer at the contact interface can be reduced compared with the related art under the condition of the same nitrogen doping concentration, thereby reducing the lattice mismatch stress between the buffer layer and the drift layer at the contact interface. The reduction of lattice mismatch stress can effectively inhibit the slip of BPD at the contact interface between the buffer layer and the drift layer, thereby reducing the generation of HLA dislocations, achieving the purpose of improving the performance of the silicon carbide epitaxial wafer and improving the performance of the silicon carbide device prepared by using the silicon carbide epitaxial wafer.

[0028] In addition, isoelectronic impurities are doped in the buffer layer 4 of the silicon carbide epitaxial wafer without introducing an additional insertion layer, thereby avoiding increasing the thickness of the silicon carbide epitaxial wafer. Moreover, the doping of isoelectronic impurities can be achieved during the process of silicon carbide epitaxy, thereby avoiding the impact on the output efficiency of the epitaxial process. At the same time, the doping of isoelectronic impurities does not require the introduction of changes in other epitaxial process parameters, thereby avoiding the impact on the epitaxial process regulation, especially the defect density control.

[0029] In some embodiments, a growth gas source, a nitrogen doping gas source, and an isoelectronic doping gas source are introduced into a reaction chamber where a substrate is placed, and a buffer layer is formed on one side of the substrate; comprising:

[0030] During the manufacturing process of the buffer layer, the flow rate of the isoelectronic doping gas source is controlled to remain unchanged, increase continuously or increase in steps.

[0031] The preparation method provided in the embodiment of the present application can prepare silicon carbide epitaxial wafers with different isoelectronic impurity doping designs by adjusting the isoelectronic doping gas source flow rate, without introducing changes in other epitaxial process parameters, thereby avoiding the impact on epitaxial process regulation, especially defect density control.

[0032] In a third aspect, an embodiment of the present application also provides a silicon carbide device, which includes a silicon carbide epitaxial wafer as described in any one of the embodiments of the first aspect, and a semiconductor structure arranged on the silicon carbide epitaxial wafer.

[0033] In a fourth aspect, an embodiment of the present application also provides an electronic device, which includes a circuit board, and a silicon carbide device as described in the embodiment of the third aspect, which is arranged on the circuit board.

[0034] The technical effects that can be achieved by the silicon carbide devices and electronic devices provided in the embodiments of the present application are the same as the technical effects that can be achieved by the silicon carbide epitaxial wafers in any of the above embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a silicon carbide epitaxial wafer provided for related technology;

[0036] Figure 2 for Figure 1 Schematic diagram of the change of lattice constant in silicon carbide epitaxial wafer;

[0037] Figure 3 A schematic diagram of the structure of another silicon carbide epitaxial wafer provided for related technology;

[0038] Figure 4 for Figure 3 Schematic diagram of the change of lattice constant in silicon carbide epitaxial wafer;

[0039] Figure 5 A schematic diagram of the structure of a silicon carbide epitaxial wafer provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the change of lattice constant in a silicon carbide epitaxial wafer provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of the change of lattice constant in another silicon carbide epitaxial wafer provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram of the change of lattice constant in another silicon carbide epitaxial wafer provided in an embodiment of the present application;

[0043] Fig. 9 A flow chart of a method for preparing a silicon carbide epitaxial wafer provided in an embodiment of the present application;

[0044] Fig.10 A schematic diagram of the structure of a silicon carbide device provided in an embodiment of the present application;

[0045] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] Silicon carbide (SiC) has many excellent physical properties such as large bandgap, high carrier saturation migration velocity, high thermal conductivity and high critical breakdown field strength, making it a semiconductor material with broad application prospects in the fields of high-temperature, high-power and high-frequency electronic power devices. Silicon carbide devices refer to semiconductor devices that use silicon carbide as semiconductor materials. Silicon carbide devices have the advantages of high input impedance, high switching speed stability, and low on-resistance, and are suitable for high-power and high-frequency applications.

[0047] Silicon carbide devices are usually prepared on silicon carbide epitaxial wafers 10. Silicon carbide epitaxial wafers 10 have become the basis for preparing most silicon carbide devices, and the performance of silicon carbide epitaxial wafers 10 has also become a key factor affecting the performance of silicon carbide devices.

[0048] Figure 1 A schematic diagram of the structure of a silicon carbide epitaxial wafer 10 provided in the related art, such as Figure 1 As shown, the silicon carbide epitaxial wafer 10 includes a substrate 1 and an epitaxial layer 2, wherein the substrate 1 is a base including silicon carbide, such as a silicon carbide single crystal. The epitaxial layer 2 is arranged on one side of the substrate 1 and is formed by adopting a silicon carbide epitaxial growth process on the surface of the substrate 1. The epitaxial layer 2 includes a buffer layer 4 and a drift layer 3 stacked along the thickness direction of the substrate 1, wherein the buffer layer 4 is close to the substrate 1 relative to the drift layer 3, and the drift layer 3 is arranged on the side of the buffer layer 4 away from the substrate 1.

[0049] In the above-mentioned silicon carbide epitaxial wafer 10, the substrate 1, the buffer layer 4 and the drift layer 3 are all doped with nitrogen impurities, and the doping concentrations of nitrogen doping in the substrate 1, the buffer layer 4 and the drift layer 3 are different, the doping concentration in the substrate 1 is the largest, the doping concentration in the drift layer 3 is the smallest, and the doping concentration in the buffer layer 4 is between the doping concentrations in the substrate 1 and the drift layer 3.

[0050] As described above, the substrate 1 in the silicon carbide epitaxial wafer 10 is a base including silicon carbide, on which there are a large number of basal plane dislocations (BPDs), which may extend to the epitaxial layer 2 (e.g. Figure 1 The BPDs on the substrate 1 are spontaneously transformed into threading edge dislocations (TEDs) during epitaxial growth, and the effects of TEDs on the performance of the silicon carbide epitaxial wafer 10 are much smaller. However, some BPDs in the substrate 1 still extend into the epitaxial layer 2.

[0051] like Figure 2As shown, since the nitrogen atoms doped in silicon carbide tend to replace the lattice sites of carbon (C) atoms (doping competition principle), lattice contraction will occur, making the lattice constant (Lattice Constant) smaller; and the higher the doping concentration of nitrogen impurities, the smaller the lattice constant of silicon carbide after doping. Therefore, due to the different doping concentrations of nitrogen impurities in the substrate 1, the buffer layer 4 and the drift layer 3, the lattice constants of the substrate 1, the buffer layer 4 and the drift layer 3 are different. The difference in lattice constants between the buffer layer 4 and the drift layer 3 will cause lattice mismatch stress at the contact interface between the buffer layer 4 and the drift layer 3. This lattice mismatch stress will cause the BPD to slip at the contact interface. When the BPD slips at the contact interface between the buffer layer 4 and the drift layer 3, interface dislocation fragments will be left on the slip path, eventually forming a half loop array (Half Loop Array, abbreviated HLA) dislocation.

[0052] HLA dislocations may affect the performance of the silicon carbide epitaxial wafer 10, and the performance of the silicon carbide device manufactured using the silicon carbide epitaxial wafer 10. For example, HLA dislocations in the silicon carbide epitaxial wafer 10 may expand into stacking faults (SF) under high current pressure, thereby forming extended dislocations; in the silicon carbide device manufactured using the silicon carbide epitaxial wafer 10, the extended dislocations may cause bipolar degradation of the silicon carbide device, thereby affecting the performance of the silicon carbide device.

[0053] In addition, when preparing some silicon carbide devices with a higher withstand voltage design level, the withstand voltage requirements of the silicon carbide epitaxial wafer 10 will be further increased, so that the nitrogen impurity doping concentration of the drift layer 3 in the silicon carbide epitaxial wafer 10 will be further reduced. The further reduction of the doping concentration of nitrogen impurities in the drift layer 3 will cause the difference in the nitrogen impurity doping concentration between the drift layer 3 and the buffer layer 4 to further increase, thereby causing the lattice constant difference between the buffer layer 4 and the drift layer 3 at the contact interface to further increase, and the lattice mismatch stress between the buffer layer 4 and the drift layer 3 at the contact interface to further increase. Due to the further increase in lattice mismatch stress, the probability of BPD slipping at the contact interface between the drift layer 3 and the buffer layer 4 to produce HLA dislocations is further increased; ultimately, the adverse effects on the performance of the silicon carbide epitaxial layer 2 are aggravated, and the adverse effects on the performance of the silicon carbide device prepared using the silicon carbide epitaxial layer 2 are aggravated.

[0054] In order to improve the above problems, another silicon carbide epitaxial wafer 10 is also provided in the related art, such as Figure 3As shown, the silicon carbide epitaxial wafer 10 introduces a transition layer 5 between the buffer layer 4 and the drift layer 3. The transition layer 5 is also doped with nitrogen impurities, and the doping concentration of the nitrogen impurities in the transition layer 5 is designed to be gradual. In the process of the transition layer 5 extending from the buffer layer 4 to the drift layer 3, the doping concentration of the nitrogen impurities gradually changes from large to small, and gradually transitions from the buffer layer 4 to the drift layer 3.

[0055] like Figure 4 As shown, the silicon carbide epitaxial wafer 10 can realize a gradual transition of the lattice constant between the buffer layer 4 and the drift layer 3 by adopting the transition layer 5 designed as described above, thereby suppressing the slip of the BPD at the contact interface between the buffer layer 4 and the drift layer 3, and further reducing the generation of HLA dislocations. The reduction of HLA dislocations helps to improve the performance of the silicon carbide epitaxial wafer 10, and improve the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0056] However, while the above solution suppresses BPD slip and reduces HLA dislocation generation, it also has some defects. On the one hand, the setting of the transition layer 5 makes the epitaxial layer 2 of the silicon carbide epitaxial wafer 10 Figure 1 The two parts of Figure 3 The three parts in the structure of the epitaxial layer 2 will become complicated, and the thickness of the epitaxial layer 2 will increase; at the same time, the thickness of the silicon carbide epitaxial wafer 10 will also increase.

[0057] On the other hand, the transition layer 5 is prepared by the silicon carbide epitaxial process. The added transition layer 5 will increase the process time required for preparing the epitaxial layer 2, affecting the efficiency of epitaxial output. On the other hand, the change of nitrogen impurity doping concentration needs to be achieved by coordinating the epitaxial C / Si (carbon / silicon) ratio and the nitrogen source flow rate, and the fine control of the C / Si ratio during the epitaxial process will increase the difficulty of controlling epitaxial defects.

[0058] Based on this, the embodiments of the present application provide a silicon carbide epitaxial wafer 10, a preparation method, a silicon carbide device and an electronic device; for improving the above-mentioned problems.

[0059] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0060] In the following, in the embodiments of the present application, the terms "first", "second", etc. are only used for convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "plurality" means two or more.

[0061] In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to being defined relative to the positions of the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative description and clarification, and may change accordingly according to the changes in the positions of the components in the drawings.

[0062] In the embodiments of the present application, unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0063] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0064] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0065] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0066] In the embodiments of the present application, exemplary embodiments are described with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams as idealized exemplary drawings. In the drawings, the thickness of the layers and regions is magnified for clarity. Therefore, it is conceivable that the shape changes relative to the drawings are caused by, for example, manufacturing technology and / or tolerances. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as a rectangle will generally have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0067] The present application embodiment provides a silicon carbide epitaxial wafer 10, such as Figure 5 As shown, the silicon carbide epitaxial wafer 10 includes a substrate 1 and an epitaxial layer 2; wherein the substrate 1 is a base made of silicon carbide as a semiconductor material, for example, the substrate 1 can be a silicon carbide single crystal. Nitrogen impurities are doped in the substrate 1, and the doping of the nitrogen impurities is N-type doping. By doping nitrogen impurities, additional electrons can be provided to the silicon carbide, so that the electrons in the silicon carbide are majority carriers, so as to improve the conductivity of the silicon carbide. In order to make the substrate 1 have a lower resistivity, the doping concentration of nitrogen doping is usually high. For example, the doping concentration of nitrogen impurities in the substrate 1 can be 1×10 19 cm -3 .

[0068] The substrate 1 is a plate-like structure, including a first surface and a second surface arranged opposite to each other in the thickness direction. Figure 5 Taking the shown orientation as an example, the thickness direction of the substrate 1 is the longitudinal direction, the first surface is located above the second surface, the first surface is the upper surface of the substrate 1, and the second surface is the lower surface of the substrate 1.

[0069] The epitaxial layer 2 is arranged on one side of the substrate 1 and is formed on the first surface of the substrate 1 by a silicon carbide epitaxial process. The epitaxial layer 2 includes a buffer layer 4 and a drift layer 3 stacked in the thickness direction of the substrate 1. The buffer layer 4 is closer to the substrate 1 relative to the drift layer 3, and the buffer layer 4 is arranged on the first surface of the substrate 1. The buffer layer 4 is also doped with nitrogen impurities, and the doping concentration of the nitrogen impurities is less than the doping concentration of the nitrogen impurities in the substrate 1. For example, the doping concentration of the nitrogen impurities in the substrate 1 is 1×10 19 cm -3 In the case of 18 cm -3 .

[0070] By providing the buffer layer 4, on the one hand, the surface damage of the substrate 1 can be repaired, and the surface defects of the substrate 1 can be blocked to reduce the defect density of the epitaxial layer 2. On the other hand, the provision of the buffer layer 4 is also beneficial to the preparation of the drift layer 3 and to the control of the doping concentration of nitrogen impurities in the drift layer 3.

[0071] Please continue to refer to Figure 5 , the drift layer 3 is arranged on the side of the buffer layer 4 away from the substrate 1, and the drift layer 3 is also doped with nitrogen impurities, and the doping concentration of the nitrogen doping is lower than the doping concentration of the nitrogen doping in the buffer layer 4. For example, the doping concentration of the nitrogen impurities in the buffer layer 4 is 1×10 18 cm -3 In the case of , the doping concentration of nitrogen impurities in the drift layer 3 can be 1×10 16 cm -3 The drift layer 3 can be used as a high-voltage resistant region capable of withstanding high voltage, so that the silicon carbide epitaxial wafer 10 can be used to prepare silicon carbide devices with higher voltage resistance requirements.

[0072] In the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the buffer layer 4 is also doped with isoelectronic impurities, and the doping of isoelectronic impurities belongs to isoelectronic doping, which refers to isoelectric doping that only plays a role in changing the lattice constant of the semiconductor material and does not affect the carrier density in the semiconductor material. The selection of isoelectronic impurities is related to the semiconductor material. For silicon carbide, isoelectronic impurities can be selected from elements of the same group IV as carbon (C). For example, isoelectronic impurities can be selected from at least one of germanium (Ge), tin (Sn) and lead (Pb).

[0073] According to the above description, the nitrogen impurities doped in silicon carbide will shrink the lattice, thereby reducing the lattice constant; and the higher the doping concentration of nitrogen impurities in silicon carbide, the smaller the lattice constant.

[0074] In the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the buffer layer 4 is doped with isoelectronic impurities in addition to being doped with nitrogen impurities. Isoelectronic impurities can compensate for the lattice contraction of silicon carbide caused by nitrogen doping, thereby increasing the lattice constant of silicon carbide doped with nitrogen impurities. Moreover, the higher the doping concentration of isoelectronic impurities, the larger the lattice constant.

[0075] For the sake of ease of description, in this article, the doping concentration of nitrogen impurities in the buffer layer 4 is defined as the first doping concentration, the doping concentration of nitrogen impurities in the drift layer 3 is defined as the second doping concentration, and the doping concentration of isoelectronic impurities in the buffer layer 4 is defined as the third doping concentration; at the contact interface between the buffer layer 4 and the drift layer 3, the lattice constant of the buffer layer 4 is defined as the first lattice constant, and the lattice constant of the drift layer 3 is defined as the second lattice constant.

[0076] Based on the above description, it can be known that when the first doping concentration and the second doping concentration are determined, by adjusting the doping concentration of the isoelectronic impurities in the buffer layer 4, that is, the third doping concentration, the first lattice constant can be adjusted, that is, the difference between the first lattice constant and the second lattice constant can be adjusted. It should be noted that the effect of isoelectronic doping on the lattice constant is also related to the isoelectronic impurities. When the third doping concentration is the same, different isoelectronic impurities have certain differences in the adjustment of the lattice constant; therefore, when adjusting the first lattice constant, a suitable third doping concentration should be selected based on the isoelectronic impurities.

[0077] In the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the difference between the first lattice constant and the second lattice constant is less than the reference value, where the reference value is the lattice constant difference between two reference epitaxial layers 2, both of which are silicon carbide epitaxial layers 2 doped with nitrogen impurities, and the doping concentrations of the nitrogen impurities are the first doping concentration and the second doping concentration, respectively. In other words, the reference value can be understood as the difference in lattice constants between the buffer layer 4 and the drift layer 3 at the contact section when the buffer layer 4 is only doped with nitrogen impurities but not with isoelectronic impurities. It can also be understood that, in the case of Figure 1 In the related art shown, the nitrogen impurity doping concentration in the buffer layer 4 is a first doping concentration, and the doping concentration in the drift layer 3 is a second doping concentration. In this case, the difference in lattice constants between the buffer layer 4 and the drift layer 3 at the contact cross section.

[0078] Therefore, when the difference between the first lattice constant and the second lattice constant is less than the reference value, it can be considered that compared with the related art, the difference in lattice constant between the buffer layer 4 and the drift layer 3 in the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application is reduced.

[0079] It can be seen that in the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the buffer layer 4 is doped with isoelectronic impurities on the basis of being doped with nitrogen impurities. The isoelectronic impurities can compensate for the lattice contraction of the buffer layer 4 caused by nitrogen doping, and by controlling the doping of isoelectronic impurities, the difference in lattice constants between the buffer layer 4 and the drift layer 3 at the contact interface can be reduced compared with the related art under the condition of the same nitrogen doping concentration, thereby reducing the lattice mismatch stress between the buffer layer 4 and the drift layer 3 at the contact interface. The reduction of the lattice mismatch stress can effectively inhibit the slip of the BPD at the contact interface between the buffer layer 4 and the drift layer 3, thereby reducing the generation of HLA dislocations, and achieving the purpose of improving the performance of the silicon carbide epitaxial wafer 10 and improving the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0080] In addition, isoelectronic impurities are doped in the buffer layer 4 of the silicon carbide epitaxial wafer 10, and no additional insertion layer is required, thereby avoiding increasing the thickness of the silicon carbide epitaxial wafer 10. Moreover, the doping of isoelectronic impurities can be achieved during the process of silicon carbide epitaxy, thereby avoiding the impact on the output efficiency of the epitaxial process. At the same time, the doping of isoelectronic impurities does not require the introduction of changes in other epitaxial process parameters, thereby avoiding the impact on the epitaxial process control, especially the defect density control.

[0081] In some embodiments, the difference between the first lattice constant and the second lattice constant is zero; the difference being zero can be achieved by adjusting the difference of isoelectronic impurities, that is, selecting appropriate isoelectronic impurities and the third doping concentration. With such a design, the difference in lattice constants between the buffer layer 4 and the drift layer 3 at the contact interface can be made zero, thereby avoiding the generation of lattice mismatch stress between the buffer layer 4 and the drift layer 3 at the contact interface, and thus effectively avoiding the slip of BPD at the contact interface between the buffer layer 4 and the drift layer 3, avoiding the generation of HLA dislocations, and achieving the purpose of improving the performance of the silicon carbide epitaxial wafer 10 and improving the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0082] In the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the third doping concentration in the buffer layer 4 can be a constant value, that is, the third doping concentration is equal at different positions in the buffer layer 4. Using a uniform third doping concentration in the buffer layer 4 can reduce the process difficulty when isoelectronic impurity doping, which is conducive to improving the output efficiency of the silicon carbide epitaxial wafer 10. Figure 6 As shown, in the silicon carbide epitaxial wafer 10 adopting the above design, the lattice constant of the buffer layer 4 is a constant value.

[0083] In some embodiments, the third doping concentration can be any value in an optional concentration range, wherein the optional concentration range is 0 cm -3 to 1×10 20 cm -3 ; Exemplarily, the third doping concentration may be 0cm -3 , 1×10 4 cm -3 , 1×10 8 cm -3 , 1×10 12 cm -3 , 1×10 16 cm -3 or 1×10 20 cm -3 Such a design can flexibly select a suitable doping concentration of isoelectronic impurities while ensuring that the slip of BPD at the contact interface between the buffer layer 4 and the drift layer 3 can be effectively suppressed and the generation of HLA dislocations can be reduced. It can also be adapted to silicon carbide epitaxial wafers 10 with different parameters, and has a wide range of applications.

[0084] In some embodiments, the third doping concentration is equal to the first doping concentration. For example, when the first doping concentration is 1×10 18 cm -3 In the case of 18 cm -3 Such a design can improve the uniformity of nitrogen impurities and isoelectronic impurities doped simultaneously in the buffer layer 4 while ensuring that the slip of BPD at the contact interface between the buffer layer 4 and the drift layer 3 can be effectively suppressed and the generation of HLA dislocations can be reduced, which is beneficial to improving the performance of the silicon carbide epitaxial wafer 10 and the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0085] In the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the third doping concentration may be a non-constant value, that is, the third doping concentration may be different at different positions in the buffer layer 4 .

[0086] In some embodiments, the third doping concentration increases continuously in the buffer layer 4 in a direction away from the substrate 1 , and the rule of continuous increase here can be arbitrary; illustratively, the third doping concentration can increase in the buffer layer 4 in a linear, linear or parabolic form.

[0087] like Figure 7 As shown, in the silicon carbide epitaxial wafer 10 provided in the embodiment of the present application, the isoelectronic impurities are doped in the buffer layer 4 using the third doping concentration designed as described above, so that the isoelectronic impurities can gradually compensate for the lattice contraction caused by nitrogen doping in the buffer layer 4, so that the lattice constant of the buffer layer 4 gradually increases in the direction away from the substrate 1, and the lattice constant of the buffer layer 4 is gradually changed. In addition, the lattice constant of the buffer layer 4 at the position in contact with the drift layer 3, that is, the first lattice constant, is the maximum value of the lattice constant in the buffer layer 4. The lattice constant of the buffer layer 4 at the position in contact with the substrate 1 is the minimum value of the lattice constant in the buffer layer 4.

[0088] With such a design, on the basis of ensuring that the difference between the first lattice constant and the second lattice constant meets the requirements, on the one hand, the film quality of the buffer layer 4 can be ensured by gradually increasing the isoelectronic impurity doping; on the other hand, the difference in the lattice constant between the substrate 1 and the buffer layer 4 can be taken into account, thereby improving the contact quality between the substrate 1 and the buffer layer 4; thereby, it is beneficial to improve the performance of the silicon carbide epitaxial wafer 10, as well as the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0089] In addition, the design of continuously increasing the third doping concentration can be achieved by changing the flow rate of the doping source gas flow without introducing changes in other epitaxial process parameters, thereby avoiding the impact on epitaxial process regulation, especially defect density control.

[0090] In some embodiments, the third doping concentration increases in a stepwise manner in the buffer layer 4 in a direction away from the substrate 1. Figure 8 As shown, in the silicon carbide epitaxial wafer 10 using the above design, the lattice constant of the buffer layer 4 increases in a step-by-step manner in the direction away from the substrate 1. With such a design, on the basis of ensuring that the difference between the first lattice constant and the second lattice constant meets the requirements, on the one hand, the film quality of the buffer layer 4 can be ensured by gradually increasing the isoelectronic impurity doping; on the other hand, the difference in the lattice constant between the substrate 1 and the buffer layer 4 can be taken into account, and the contact quality between the substrate 1 and the buffer layer 4 can be improved; thus, it is beneficial to improve the performance of the silicon carbide epitaxial wafer 10 and the performance of the silicon carbide device prepared using the silicon carbide epitaxial wafer 10.

[0091] In addition, it is helpful to manufacture different parts of the buffer layer 4 step by step according to a step-by-step growth rule, which is helpful to reduce the difficulty of manufacturing the buffer layer 4 .

[0092] In some embodiments, the variation interval of the third doping concentration is within an optional concentration range, wherein the optional concentration range is [0 cm -3 ,1×10 20 cm -3 ], illustratively, the variation range of the third doping concentration may be [0cm -3 ,1×10 20 cm -3 ],[0cm -3 ,1×10 18 cm -3 ], [1×10 10 cm -3 ,1×10 20 cm -3 ], [1×10 5 cm -3 ,1×10 15 cm -3 ] or [1×10 8 cm -3 ,1×10 18 cm -3 ] etc. With such a design, on the basis of ensuring that the slip of BPD at the contact interface between the buffer layer 4 and the drift layer 3 can be effectively suppressed and the generation of HLA dislocations can be reduced, the appropriate doping concentration of isoelectronic impurities can be flexibly selected, and the silicon carbide epitaxial wafer 10 with different parameters can be adapted, and the application range is wide.

[0093] In some embodiments, the maximum value of the third doping concentration in the buffer layer 4 is equal to the first doping concentration. For example, when the first doping concentration is 1×10 18 cm -3In the case of 18 cm -3 Such a design can effectively suppress the slip of BPD at the contact interface between the buffer layer 4 and the drift layer 3 and reduce the generation of HLA dislocations. At the contact interface between the buffer layer 4 and the drift layer 3, the uniformity of nitrogen impurities and isoelectronic impurities doped simultaneously in the buffer layer 4 can be improved, which is beneficial to improving the interface quality of the contact interface between the buffer layer 4 and the drift layer 3, thereby facilitating the improvement of the performance of the silicon carbide epitaxial wafer 10 and the performance of the silicon carbide device prepared by using the silicon carbide epitaxial wafer 10.

[0094] The present application embodiment also provides a method for preparing a silicon carbide epitaxial wafer 10, such as Fig. 9 As shown, the preparation method 20 may include:

[0095] Step S100 : introducing a growth gas source, a nitrogen doping gas source and an isoelectronic doping gas source into a reaction chamber where the substrate 1 is placed, and forming a buffer layer 4 on one side of the substrate 1 .

[0096] In step S100 , the substrate 1 may be a silicon carbide substrate that has been doped, and the doped substrate 1 contains nitrogen impurities with a designed doping concentration.

[0097] The growth gas source is used to form a silicon carbide epitaxial layer 2 on the surface of the substrate 1 through an epitaxial growth process. The growth gas source includes a silicon source and a carbon source. The silicon source is one or more of silane, trichlorosilane, dichlorosilane and methylsilane, and the carbon source is one or more of methane, ethylene and propane.

[0098] In the process of preparing the silicon carbide epitaxial wafer 10, a buffer layer 4 is firstly made on one side of the substrate 1. The nitrogen doping gas source is used to dope the buffer layer 4 with nitrogen impurities, and nitrogen (N2) can be selected; by controlling the flow rate of the nitrogen gas, the doping concentration of the nitrogen impurities in the buffer layer 4 can be adjusted.

[0099] The isoelectronic doping gas source is used to achieve isoelectronic doping of the buffer layer 4. By controlling the flow rate of the isoelectronic doping gas source, the doping concentration of the isoelectronic impurities in the buffer layer 4 can be adjusted. Exemplarily, the isoelectronic impurity can be germanium, and the isoelectronic doping gas source can be one or more of germane, methylgermanium trichloride, dichlorohydrogengermanium and germanium chloride.

[0100] It can be known from the above description that the doping concentration of the isoelectronic impurities in the buffer layer 4, i.e., the third doping concentration, can be a constant value or a non-constant value. For the design in which the third doping concentration is a constant value, the control strategy for the flow rate of the isoelectronic doping gas source in step S100 is: during the formation of the buffer layer 4, the flow rate of the isoelectronic doping gas source is controlled to remain unchanged.

[0101] For designs where the third doping concentration is a non-constant value, the control strategy for the isoelectronic doping gas source flow rate in step S100 is: during the formation of the buffer layer 4, the flow rate of the isoelectronic doping gas source is controlled to vary according to the variation of the third doping concentration.

[0102] Exemplarily, when the third doping concentration increases continuously in the buffer layer 4 in the direction away from the substrate 1, the control strategy for the flow rate of the isoelectronic doping gas source in step S100 is: during the formation of the buffer layer 4, the flow rate of the isoelectronic doping gas source is controlled to increase continuously. The law of the continuous increase of the flow rate can also refer to the law of the increase of the third doping concentration in the buffer layer 4, for example, the third doping concentration can increase in the buffer layer 4 in a linear, linear or parabolic form. When controlling the flow rate of the isoelectronic doping gas source to increase continuously, the flow rate can be controlled to increase in a linear, linear or parabolic form.

[0103] As another example, when the third doping concentration increases in a step-by-step manner in the buffer layer 4 in the direction away from the substrate 1, the control strategy for the isoelectronic doping gas source flow in step S100 is: during the formation of the buffer layer 4, the flow of the isoelectronic doping gas source is controlled to increase in a step-by-step manner.

[0104] Step S200: After the buffer layer 4 is formed, the introduction of the isoelectronic doping gas source is stopped.

[0105] By controlling the epitaxial process, the growth thickness of the buffer layer 4 can be adjusted, and the preparation of the buffer layer 4 is completed after the buffer layer 4 grows to a specified thickness. After the preparation of the buffer layer 4 is completed, the introduction of the isoelectronic doping gas source is stopped to prepare for the preparation of the drift layer 3.

[0106] Step S300 : forming a drift layer 3 on a side of the buffer layer 4 away from the substrate 1 .

[0107] After the buffer layer 4 is formed, the growth gas source and the nitrogen doping gas source are adjusted to form the drift layer 3 on the side of the buffer layer 4 away from the substrate 1. Since the doping concentrations of nitrogen impurities in the buffer layer 4 and the drift layer 3 are different, when forming the drift layer 3, the doping concentration of nitrogen impurities in the drift layer 3 can be controlled by adjusting the flow rate of the nitrogen doping gas source.

[0108] By controlling the epitaxial process, the growth thickness of the drift layer 3 can be adjusted, and the preparation of the drift layer 3 is completed after the drift layer 3 grows to a specified thickness. After the preparation of the drift layer 3 is completed, the preparation of the silicon carbide epitaxial layer 2 is completed.

[0109] In the silicon carbide epitaxial wafer 10 prepared by the above preparation method, the buffer layer 4 is doped with isoelectronic impurities on the basis of being doped with nitrogen impurities. The isoelectronic impurities can compensate for the lattice shrinkage of the buffer layer 4 caused by nitrogen doping, and by controlling the doping of isoelectronic impurities, the difference in lattice constants between the buffer layer 4 and the drift layer 3 at the contact interface can be reduced compared with the related art under the condition of the same nitrogen doping concentration, thereby reducing the lattice mismatch stress between the buffer layer 4 and the drift layer 3 at the contact interface. The reduction of the lattice mismatch stress can effectively inhibit the slip of the BPD at the contact interface between the buffer layer 4 and the drift layer 3, thereby reducing the generation of HLA dislocations, and achieving the purpose of improving the performance of the silicon carbide epitaxial wafer 10 and improving the performance of the silicon carbide device prepared by using the silicon carbide epitaxial wafer 10.

[0110] In addition, isoelectronic impurities are doped in the buffer layer 4 of the silicon carbide epitaxial wafer 10, and no additional insertion layer is required, thereby avoiding increasing the thickness of the silicon carbide epitaxial wafer 10. Moreover, the doping of isoelectronic impurities can be achieved during the process of silicon carbide epitaxy, thereby avoiding the impact on the output efficiency of the epitaxial process. At the same time, the doping of isoelectronic impurities does not require the introduction of changes in other epitaxial process parameters, thereby avoiding the impact on the epitaxial process control, especially the defect density control.

[0111] Based on the above description, it can also be seen that the preparation method provided in the embodiment of the present application can prepare silicon carbide epitaxial wafers 10 with different isoelectronic impurity doping designs by adjusting the isoelectronic doping gas source flow rate, and there is no need to introduce changes in other epitaxial process parameters, thereby avoiding the impact on epitaxial process regulation, especially defect density control.

[0112] The present application also provides a silicon carbide device, such as Fig.10 As shown, the silicon carbide device 30 includes the silicon carbide epitaxial wafer 10 described in the above embodiment, and a semiconductor structure 31 manufactured on the silicon carbide epitaxial wafer 10 .

[0113] The silicon carbide device 30 provided in the embodiment of the present application can be an electronic power device including a Schottky Barrier Diode (SBD), an Insulated Gate Bipolar Transistor (IGBT), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, also referred to as MOS tube), a Junction Field-Effect Transistor (JFET) and a Bipolar Junction Transistor (BJT), etc.

[0114] The technical effect that can be achieved by the silicon carbide device 30 provided in the embodiment of the present application is the same as the technical effect that can be achieved by the silicon carbide epitaxial wafer 10 of any of the above embodiments, and will not be repeated here.

[0115] The present application also provides an electronic device, such as Fig.11 As shown, the electronic device 40 includes a printed circuit board 41 (printed circuit board, reduced PCB) and the silicon carbide device 30 as described in the above embodiment, wherein the silicon carbide device 30 is arranged on the circuit board 41 .

[0116] In some embodiments, the electronic device 40 may be a power conversion device, such as a power adapter, an energy storage device, a switching power supply, a DC / DC converter, a photovoltaic power generation device, an electric drive system, and the like.

[0117] In some embodiments, the electronic device 40 may also be other devices with a power conversion device, such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Among them, consumer electronic products are such as mobile phones, tablet computers (pad), laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products are such as smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products are such as ATM machines, self-service terminals, etc.

[0118] The embodiment of the present application does not impose any special limitation on the specific form of the electronic device 40 .

[0119] The technical effect that can be achieved by the electronic device 40 provided in the embodiment of the present application is the same as the technical effect that can be achieved by the silicon carbide epitaxial wafer 10 in any of the above embodiments, and will not be repeated here.

[0120] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A silicon carbide epitaxial wafer, characterized in that: include: substrate; a buffer layer, the buffer layer being disposed on one side of the substrate and doped with nitrogen impurities and isoelectronic impurities; the doping concentration of the nitrogen impurities in the buffer layer being a first doping concentration; and a drift layer, the drift layer being arranged on a side of the buffer layer away from the substrate and doped with nitrogen impurities; a doping concentration of the nitrogen impurities in the drift layer being a second doping concentration, and the second doping concentration being less than the second doping concentration; Among them, the difference in lattice constants between the buffer layer and the drift layer at the contact interface is less than a reference value, and the reference value is the lattice constant difference between two reference epitaxial layers. The two reference epitaxial layers are both silicon carbide epitaxial layers doped with nitrogen impurities, and the doping concentrations of the nitrogen impurities are respectively a first doping concentration and a second doping concentration.

2. The silicon carbide epitaxial wafer according to claim 1, characterized in that: The doping concentration of the medium electron impurities in the buffer layer is a third doping concentration; The third doping concentration continuously increases in the buffer layer in a direction away from the substrate.

3. The silicon carbide epitaxial wafer according to claim 2, characterized in that: In a direction away from the substrate, the third doping concentration increases continuously in the buffer layer in a linear, parabolic or exponential form.

4. The silicon carbide epitaxial wafer according to claim 1, characterized in that: The doping concentration of the medium electron impurities in the buffer layer is a third doping concentration; Along the direction away from the substrate, the third doping concentration increases in the buffer layer in a step-by-step manner.

5. The silicon carbide epitaxial wafer according to any one of claims 2 to 4, characterized in that: The variation interval of the third doping concentration in the buffer layer is within an optional concentration interval, and the optional concentration interval is [0,1×10 20 cm -3 ].

6. The silicon carbide epitaxial wafer according to any one of claims 2 to 5, characterized in that: A maximum value of the third doping concentration in the buffer layer is equal to the first doping concentration.

7. The silicon carbide epitaxial wafer according to claim 1, characterized in that: The doping concentration of medium electron impurities in the buffer layer is a third doping concentration; and the third doping concentration is a constant value in the buffer layer.

8. The silicon carbide epitaxial wafer according to claim 7, characterized in that: The third doping concentration is any value in an optional concentration range, and the optional concentration range is [0,1×10 20 cm -3 ].

9. The silicon carbide epitaxial wafer according to claim 7 or 8, characterized in that: The third doping concentration is equal to the first doping concentration.

10. The silicon carbide epitaxial wafer according to claim 1, characterized in that: The difference in lattice constants between the buffer layer and the drift layer at a contact interface is zero.

11. The silicon carbide epitaxial wafer according to any one of claims 1 to 10, characterized in that: The isoelectronic impurities include at least one of germanium, tin and lead.

12. A method for preparing a silicon carbide epitaxial wafer, characterized in that: include: A growth gas source, a nitrogen doping gas source and an isoelectronic doping gas source are introduced into a reaction chamber where a substrate is placed, and a buffer layer is formed on one side of the substrate; After the buffer layer is formed, the introduction of the isoelectronic doping gas source is stopped; A drift layer is formed on a side of the buffer layer away from the substrate.

13. The preparation method according to claim 12, characterized in that: The method of introducing a growth gas source, a nitrogen doping gas source and an isoelectronic doping gas source into a reaction chamber where a substrate is placed, and forming a buffer layer on one side of the substrate comprises: During the manufacturing process of the buffer layer, the flow rate of the isoelectronic doping gas source is controlled to remain unchanged, increase continuously or increase in steps.

14. A silicon carbide device, characterized in that: include: The silicon carbide epitaxial wafer according to any one of claims 1 to 11, and A semiconductor structure is arranged on the silicon carbide epitaxial wafer.

15. An electronic device, characterized in that: include: Circuit boards, and The silicon carbide device according to claim 14 is disposed on the circuit board.

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