Electrode structure of semiconductor quantum chip and testing method

Abstract

The application discloses an electrode structure and a testing method of a semiconductor quantum chip. The electrode structure of the semiconductor quantum chip comprises a source electrode and a drain electrode located on opposite sides of a substrate, and a plurality of gate electrodes. The gate electrodes comprise: a first gate electrode for applying a first direct current voltage signal to form a two-dimensional electron gas under the first gate electrode; a second gate electrode for applying a second direct current voltage signal to adjust the charge density of the two-dimensional electron gas in a channel under the second gate electrode to form an induced quantum dot; and a third gate electrode located between the first gate electrode and the second gate electrode for applying a radio frequency signal to read the state of the induced quantum dot. The first gate electrode and the third gate electrode have overlapping end portions in the vertical direction of the substrate, and an insulating medium layer is formed between the overlapping end portions. The application avoids the leakage of a measurement signal along the electrode structure of the semiconductor quantum chip, and improves the measurement compatibility of the semiconductor quantum chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computers, in particular to an electrode structure of a semiconductor quantum chip and a testing method. BACKGROUND

[0002] Silicon-based spin qubits have been considered as the quantum physical system that is expected to realize large-scale general quantum computers in the future due to their advantages such as long coherence time, nanoscale structure size, all-electrical manipulation of solid-state physical system, and good compatibility with traditional CMOS fabrication process.

[0003] The spin state information of silicon-based spin qubits is indirectly read by using the charge-spin conversion mechanism and the change of the charge state in the adjacent single-electron transistor. There are two mainstream measurement schemes in the current international: (1) traditional transport measurement, which uses transport current to detect the weak resistance signal change in the single-electron transistor; (2) radio frequency reflection reading technology, which introduces an "impedance transformer" circuit between the single-electron transistor and the measurement reading link, thereby constructing an impedance matching network that can feedback the conductance state change in the single-electron transistor in real time.

[0004] The integration time required by the traditional transport measurement direct current resistance is millisecond level, in addition, the measurement bandwidth is limited to the order of ~10 kHz due to the restriction of the RC circuit composed of the direct current measurement line and the single-electron transistor, the reading speed is relatively slow as a whole, and it will also be affected by the low-frequency 1 / f noise on the measurement system link. The initialization and control waveform scale of silicon-based spin qubits is nanosecond or microsecond level, and the traditional transport measurement greatly limits the efficient readout of quantum bits. The radio frequency reflection reading technology uses a radio frequency signal source as an input carrier signal, modulates the impedance or conductance change of the single-electron transistor through the resonant circuit of the impedance matching network, and realizes the effective readout of the signal through the low-noise amplifier signal amplification and room temperature signal demodulation. The radio frequency reflection reading technology is far less intuitive and accurate than the traditional transport measurement in evaluating the initial working state of the quantum dot in the quantum chip.

[0005] Therefore, in actual testing, the combination of the above two measurement methods is often required, and from the perspective of quantum chip structure design, how to realize the compatibility of the two is a bottleneck problem that has been difficult to solve for a long time. SUMMARY

[0006] The application provides an electrode structure of a semiconductor quantum chip and a testing method, which are used for solving the problem that the electrode structure of the semiconductor quantum chip in the prior art cannot realize the compatibility of two measurement methods of traditional transport measurement and radio frequency reflection reading measurement of quantum dots, avoiding the leakage of radio frequency signals along the electrode structure of the semiconductor quantum chip, and improving the measurement compatibility of the semiconductor quantum chip.

[0007] The first aspect of the application provides an electrode structure of a semiconductor quantum chip, which comprises a source electrode and a drain electrode located on opposite sides of a substrate, and a plurality of gate electrodes, wherein the gate electrodes comprise:

[0008] a first gate electrode for applying a first direct current voltage signal to form a two-dimensional electron gas in a channel below the first gate electrode;

[0009] a second gate electrode for applying a second direct current voltage signal to adjust the charge density of the two-dimensional electron gas in a channel below the second gate electrode to form an induced quantum dot;

[0010] a third gate electrode located between the first gate electrode and the second gate electrode for applying a radio frequency signal to read the state of the induced quantum dot;

[0011] wherein the first gate electrode and the third gate electrode extend in opposite directions to form a first extension and a second extension, and in the vertical extension direction, the end of the first extension and the end of the second extension overlap, and an insulating medium layer is formed between the overlapping ends.

[0012] The electrode structure of the semiconductor quantum chip as described above, preferably, the first gate electrode extends in the direction of the third gate electrode on the substrate to form the first extension, and the third gate electrode extends in the direction of the first gate electrode on the substrate to form the second extension.

[0013] wherein the first extension is above the second extension.

[0014] The electrode structure of the semiconductor quantum chip as described above, preferably, the first gate electrode extends in the direction of the third gate electrode on the substrate to form the first extension, and the third gate electrode extends in the direction of the first gate electrode on the substrate to form the second extension.

[0015] wherein the first extension is below the second extension.

[0016] The electrode structure of the semiconductor quantum chip as described above, preferably, the first gate electrode and the third gate electrode each comprise a pad on the substrate and a signal transmission line connected to one end of the pad, and the other end of the signal transmission line extends to the induced quantum dot region.

[0017] The overlapping end is located on the signal transmission line close to one end of the induced quantum dot region.

[0018] The electrode structure of the semiconductor quantum chip as described above, preferably, an area of the overlapping end is not less than 10 square nanometers and not more than 100 square nanometers.

[0019] The electrode structure of the semiconductor quantum chip as described above, preferably, a resistance of the overlapping end is not less than 10 mega ohms when a first direct current voltage signal applied on the first gate is zero.

[0020] The electrode structure of the semiconductor quantum chip as described above, preferably, an impedance of the third gate is less than an impedance of the induced quantum dot.

[0021] The electrode structure of the semiconductor quantum chip as described above, preferably, the third gate is further used to apply a third direct current voltage signal to make a channel under the third gate form the two-dimensional electron gas.

[0022] The second aspect of the present application provides a testing method of a semiconductor quantum chip, the semiconductor quantum chip comprising the electrode structure of the semiconductor quantum chip of any one of the above, the method comprising:

[0023] applying the third direct current voltage signal through the third gate to make a channel under the third gate form a two-dimensional electron gas;

[0024] applying the first direct current voltage signal through the first gate to make a channel under the first gate form a two-dimensional electron gas;

[0025] applying the second direct current voltage signal through the second gate to adjust a charge density of the two-dimensional electron gas in the channel to form an induced quantum dot;

[0026] applying an excitation signal through the drain to form a transport current in the channel and transmit to the induced quantum dot;

[0027] measuring a current output by the source to obtain a state of the induced quantum dot.

[0028] The third aspect of the present application provides a testing method of a semiconductor quantum chip, the semiconductor quantum chip comprising the electrode structure of the semiconductor quantum chip of any one of the above, the method comprising:

[0029] turning off a signal source electrically connected with the drain and the first gate;

[0030] applying the second direct current voltage signal through the second gate to adjust a charge density of the two-dimensional electron gas in the channel to form an induced quantum dot;

[0031] The third direct current voltage signal is applied through the third gate to form a two-dimensional electron gas under the third gate;

[0032] The state of the sensing quantum dot is read by applying a radio frequency signal through the third gate. Compared with the prior art, after the electrode is split into the first gate and the third gate, the sensing quantum dot can be read by not only applying an excitation signal through the drain to realize the traditional transport measurement mode, at this time, the excitation signal applied on the drain is a voltage signal, and the two-dimensional electron gas under the first gate and the third gate is used to introduce electrons into the sensing quantum dot region to form a transport current for reading; but also by applying a radio frequency signal through the third gate to read the sensing quantum dot, at this time, the voltage signals of the drain and the first gate are zero, and the electrode is suspended. The overlapping end portions separated by the insulating medium layer are formed between the first gate and the third gate, so that the first gate and the third gate present a high resistance state, and the radio frequency signal cannot leak from the first gate. No matter which reading mode is used, signal leakage does not occur, and the compatibility of the traditional transport measurement and the radio frequency reflection reading technology is realized.

[0033] The test method of the semiconductor quantum chip provided by the application adopts the electrode structure of the semiconductor quantum chip, and therefore has the same beneficial effects, which will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 It is a structural schematic diagram of a gate of a semiconductor quantum chip in the prior art;

[0035] Figure 2 It is a structural schematic diagram of a gate of a semiconductor quantum chip provided by an embodiment of the application;

[0036] Figure 3 It is a structural schematic diagram of an overlapping end portion provided by an embodiment of the application;

[0037] Figure 4 It is another structural schematic diagram of an overlapping end portion provided by an embodiment of the application;

[0038] Figure 5 It is a position schematic diagram of an overlapping end portion on a substrate provided by an embodiment of the application;

[0039] Figure 6 It is a flowchart of a test method of a semiconductor quantum chip provided by an embodiment of the application;

[0040] Figure 7 It is another flowchart of a test method of a semiconductor quantum chip provided by an embodiment of the application.

[0041] In the drawing marks:

[0042] 1 - substrate, 2 - gate, 3 - ohmic electrode, 4 - gate, 5 - two-dimensional electron gas;

[0043] 11 - induced quantum dot region, 21 - first gate, 22 - third gate, 23 - overlapping end, 31 - drain, 32 - source, 41 - second gate;

[0044] 212 - pad, 213 - signal transmission line, 231 - first extension, 232 - second extension, 233 - insulating dielectric layer. DETAILED DESCRIPTION

[0045] In order to make the technical personnel in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should fall within the scope of protection of the present application. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as a limitation on the present application.

[0046] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "left", "right" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0047] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0048] As shown in the drawings Figure 1The reading schematic of the prior art gated silicon-based spin quantum bit is shown, 1 is a semiconductor quantum chip substrate, electrodes 2 and 4 are both gates, electrode 31 represents a drain, electrode 32 represents a source, and 5 represents a two-dimensional electron gas. Specifically, electrode 2 can be used to apply a direct current voltage signal to form a two-dimensional electron gas in the channel, and can also be used to apply a radio frequency signal to read the charge state of quantum dot Q1; electrode 4 is used to apply a direct current voltage signal to form a quantum dot Q1 for reading. In addition, the ion implantation region is formed below the drain 31 and the source 32, which can be used to apply a direct current voltage signal, the charge flows from the drain 31 into the ion implantation region, and then flows into the sensing quantum dot through the two-dimensional electron gas, and then is output by the source 32, forming a transport current signal to test the sensing quantum dot Q1.

[0049] In addition, in the figure, R1 is the equivalent resistance of the ion implantation region, R2 is the equivalent resistance of the two-dimensional electron gas, and C2 is the equivalent parasitic capacitance of the two-dimensional electron gas. Among them, R1, R2 and C2 are equivalent resistance and capacitance, which are used to characterize the impedance characteristics in the radio frequency signal transmission link.

[0050] The reading of quantum dot Q1 can adopt a conventional transport measurement technology, that is, a direct current voltage signal is applied to electrode 4 to form a sensing quantum dot below it; a direct current voltage signal is applied to electrode 2 to form a two-dimensional electron gas in the channel, and an excitation signal is applied to the drain 31, and the measurement of the sensing quantum dot is realized by measuring the change of the current output by the source 32.

[0051] The reading of quantum dot Q1 can also adopt a radio frequency reflection reading technology, that is, a direct current voltage signal is applied to electrode 4 to form a sensing quantum dot below it; a direct current voltage signal is applied to electrode 2 to form a two-dimensional electron gas in the channel below electrode 2, and a radio frequency signal is applied to electrode 2 at the same time to read the state of the sensing quantum dot.

[0052] It can be imagined that when the conventional transport measurement technology is performed, the channel of the single electron transistor needs to be opened to form a transport current; then the radio frequency reflection reading is performed, and when the radio frequency signal is applied to the drain 31, the radio frequency signal will leak along the transport channel. There is an urgent need for a semiconductor quantum chip structure that can realize the compatibility of conventional transport measurement and radio frequency reflection reading.

[0053] Based on this, combined with the accompanying drawings Figure 2 and the accompanying drawings Figure 3As shown, this application proposes an electrode structure for a semiconductor quantum chip, including a drain 31 and a source 32 located on opposite sides of a substrate, and a plurality of gates located between the drain 31 and the source 32. The gates include: a first gate 21 for applying a first DC voltage signal to form a two-dimensional electron gas in a channel below the first gate 21; a second gate 41 for applying a second DC voltage signal to adjust the charge density of the two-dimensional electron gas in the channel below the second gate 41 to form an inductive quantum dot; and a third gate 22 located between the first gate 21 and the second gate 41 for applying a radio frequency signal to read the state of the inductive quantum dot. The first gate 21 and the third gate 22 extend in opposite directions to form a first extension 231 and a second extension 232. In the vertical extension direction, the ends of the first extension 231 and the second extension 232 overlap, and an insulating dielectric layer 233 is formed between the overlapping ends 23.

[0054] In this embodiment, the appendix Figure 1 The electrode 2, used to form a two-dimensional electron gas 5 within the channel and to apply radio frequency signals, is divided into a first gate 21 and a third gate 22. Specifically, the first gate 21 is used to apply a first DC voltage signal to form a two-dimensional electron gas 5 in the channel below the first gate 21. The third gate 22 is located between the first gate 21 and the second gate 41 and is used to apply radio frequency signals to read the state of the sensed quantum dot. The first gate 21 and the third gate 22 are respectively used to apply different types of signals to form the two-dimensional electron gas 5 within the channel and to read the sensed quantum dot.

[0055] In this embodiment, the drain 31 and source 32 are located on opposite sides of the substrate, and the first gate 21, the second gate 41, and the third gate 22 are located between the drain 31 and the source 32. Since the second gate 41 is used to apply a voltage signal to form an inductive quantum dot, it is located on the substrate... Figure 2 The diagram illustrates a combined gate structure. Additionally, [the diagram is attached]. Figure 1 and attached Figure 2 The gate structure shown in the example is only for reading one sensing quantum dot; when more sensing quantum dots are integrated on the semiconductor quantum chip and need to be read, the gate structure needs to be set accordingly, which will not be described in detail in this embodiment.

[0056] Combined with appendix Figure 2As shown, when the conventional transport measurement method is adopted, the second DC voltage signal applied on the second gate 41 forms the induced quantum dot under the channel; the first DC voltage signal applied on the first gate 21 forms the two-dimensional electron gas in the channel under it, and the excitation signal is applied on the drain 31, and the measurement of the induced quantum dot is realized by measuring the change of the current output by the source 32. At this time, the excitation signal applied on the drain 31 is a voltage signal, which cannot be leaked through the equivalent capacitance C2 channel of the two-dimensional electron gas under the first gate 21 and the third gate 22.

[0057] In combination with the accompanying drawings Figure 3 As shown, when the radio frequency reflection reading technology is adopted, the first gate 21 and the third gate 22 extend in opposite directions on the substrate 1 to form the first extension 231 and the second extension 232, the end of the first extension 231 and the end of the second extension 232 have overlapping ends 23 in the vertical direction of the extension, and the insulating medium layer 233 is formed between the overlapping ends 23, so that the first gate 21 and the third gate 22 are in a high resistance state, and short circuit connection is avoided. When the radio frequency signal is applied on the third gate 22 to read the induced quantum dot, the radio frequency signal cannot be leaked from the first gate 21; in addition, the resistance value between the third gate 22 and the drain 31 is much larger than the resistance value between the third gate 22 and the first gate 21, and the radio frequency signal cannot be leaked along the path of the drain 31, so as to ensure that the radio frequency signal can be transmitted to the induced quantum dot in whole, and dissipation is formed in the quantum dot area to realize the measurement of the induced quantum dot, and the measurement sensitivity and accuracy are improved.

[0058] Continue to show in the accompanying drawings Figure 2 As shown, the overlapping ends 23 arranged between the first gate 21 and the third gate 22 can ensure the continuity of the two-dimensional electron gas in the channel under the first gate 21 and the third gate 22, so that the electrons can be moved from the drain 31 to the source 32 to ensure the circulation of the transport current.

[0059] In addition, in combination with the accompanying drawings Figure 1 and the accompanying drawings Figure 2 As shown, when the conventional transport measurement is adopted, the output channel of the signal source can be electrically connected to the drain 31 of the semiconductor quantum chip to provide the excitation signal, and the measurement device is electrically connected to the source 32 of the semiconductor quantum chip to measure the output current signal. When the radio frequency reflection reading is adopted, the output channel of the microwave source is electrically connected to the third gate 22 of the semiconductor quantum chip to provide the radio frequency signal, and in addition, the reflection signal representing the state of the induced quantum dot is also output to the measurement device through the third gate 22; at this time, one port of the coupler can be electrically connected to the third gate 22, and the other port of the coupler is respectively electrically connected to the microwave source and the measurement device.

[0060] In summary, when the counter electrode 2 is split into the first gate 21 and the third gate 22, the induced quantum dot can be read by not only the traditional transport measurement mode through the excitation signal applied to the drain 31, but also the RF signal applied to the third gate 22, and no signal leakage occurs in either reading mode, realizing the compatibility of the traditional transport measurement and the RF reflection reading technology.

[0061] As shown in the accompanying drawings, Figure 3 As an embodiment of the present application, the first gate 21 extends in the direction of the third gate 22 on the substrate 1 to form the first extension 231, and the third gate 22 extends in the direction of the first gate 21 on the substrate 1 to form the second extension 232; wherein the first extension 231 is above the second extension 232.

[0062] As shown in the accompanying drawings, Figure 4 As another embodiment of the present application, the first gate 21 extends in the direction of the third gate 22 on the substrate 1 to form the first extension 231, and the third gate 22 extends in the direction of the first gate 21 on the substrate 1 to form the second extension 232; wherein the first extension 231 is below the second extension 232.

[0063] When the first gate 21 and the third gate 22 are prepared on the substrate 1, the first extension 231 and the second extension 232 have an overlapping end 23, wherein the lower extension is prepared first, then the insulating medium layer 233 is formed on the surface of the lower extension, and finally the upper extension is formed on the surface of the insulating medium layer 233. The continuous two-dimensional electron gas is ensured by the overlapping end 23 to realize the circulation of the channel transport current; and the high impedance between the first gate 21 and the third gate 22 is realized by the insulating medium layer 233 to block the leakage of the RF signal.

[0064] As shown in the accompanying drawings, Figure 5 The first gate and the third gate each include a pad 212 on the substrate and a signal transmission line 213 connected to the pad at one end, and the other end of the signal transmission line 213 extends to the induced quantum dot region 11; the overlapping end 23 is located on the signal transmission line 213 close to one end of the induced quantum dot region.

[0065] The accompanying drawings, Figure 5In the figure, 1 represents the substrate, 31 represents the drain, 32 represents the source, 11 represents the sensing quantum dot region, which is generally the central region of the substrate 1; 212 represents the pad, and 213 represents the signal transmission line connected to the pad. The first gate and the third gate both include the pad 212 and the signal transmission line 213 connected to the pad 212, and the other end of the signal transmission line 213 is connected to the sensing quantum dot region 11. In addition, the pad of the second gate is also connected to the central region of the substrate 1 through a signal transmission line 213, which is used to form the sensing quantum dot in the central region.

[0066] In the figure, the overlapping end 23 in the semiconductor quantum chip is located on the signal transmission line 213 close to the sensing quantum dot region 11; the radio frequency signal is applied to the pad 212 of the third gate 22, and is transmitted to the sensing quantum dot region 11 in the center of the substrate 1 through the signal transmission line 213. By setting the high-resistance overlapping end 23 close to the sensing quantum dot region 11, the leakage of the radio frequency signal can be maximized. Figure 5 It can be imagined that if the overlapping end 23 is set close to the pad 212, the radio frequency signal will be transmitted along one end of the signal transmission line 213 in the central region of the substrate 1 to the pad 212. Even if it is blocked by the high-resistance overlapping end 23 close to the pad 212, it will be dissipated when transmitted on the signal transmission line 213, so that the accuracy of the radio frequency signal transmitted to the sensing quantum dot region 11 is low, which affects the measurement effect of the sensing quantum dot.

[0067] It should be noted that the semiconductor quantum chip

[0068] In the schematic diagram of the semiconductor quantum chip, the schematic pad 212 is generally formed around the periphery of the substrate 1, which is used for electrical connection with the signal source or test circuit. In addition, the drain 31 and the source 32 also have corresponding pads, and the size of the pad is usually in microns; the sensing quantum dot region 11 is generally in the central region of the substrate 1, and the pad 212 around the periphery of the substrate 1 is usually introduced to the vicinity of the sensing quantum dot region 11 through a nanoscale signal transmission line 213. Figure 5

[0069] ​In the embodiment of the present application, the area of the overlapping end portion 23 is not less than 10 square nanometers, and the area of the overlapping end portion 23 is not more than 100 square nanometers. The overlapping end portion 23 is used to realize the communication of the two-dimensional electron gas in the channel below the first gate 21 and the two-dimensional electron gas in the channel below the third gate 22. When the first direct current voltage signal and the third direct current voltage signal need to be respectively applied to the first gate 21 and the third gate 22, the two-dimensional electron gas can be formed in the channel below the overlapping end portion 23. The size of the overlapping end portion 23 is not easy to set too large. When the size of the overlapping end portion 23 is too large, the risk of leakage of the radio frequency signal is increased. In addition, the size of the overlapping end portion 23 is not easy to set too small. When the size is too small, the two-dimensional electron gas cannot be formed below the overlapping end portion, so that the two-dimensional electron gas in the channel below the first gate 21 and the third gate 22 is discontinuous, and the transport current cannot be formed. The area of not less than 10 square nanometers and not more than 100 square nanometers used in the embodiment is verified by tests. On the one hand, the structure is easy to prepare on the substrate. On the other hand, the high impedance can be ensured.

[0070] Specifically, when the first direct current voltage signal applied to the first gate is zero, the resistance of the overlapping end portion is not less than 10 megaohms. The resistance value of 10 megaohms is very large, and the radio frequency signal cannot pass through. Compared with the open circuit, the radio frequency signal cannot leak along the overlapping end portion to the first gate.

[0071] In addition, when the third gate is formed on the substrate, the impedance of the third gate is less than the impedance of the induced quantum dot. When the radio frequency signal is transmitted, the greater the impedance in the transmission path, the greater the dissipation of the radio frequency signal. The impedance of the third gate is limited to ensure that the radio frequency signal applied by the third gate can be transmitted to the induced quantum dot for measurement as much as possible.

[0072] In the embodiment, the third gate is not only used to apply the radio frequency signal for reading the induced quantum dot, but also used to apply the third direct current voltage signal to form the two-dimensional electron gas in the channel below the third gate. The two-dimensional electron gas in the channel below the third gate is in communication with the two-dimensional electron in the channel below the first gate, so that the electrons can move from the drain to the source to ensure the flow of the transport current. Then, the radio frequency signal tests the induced quantum dot through the transport current.

[0073] As shown in the accompanying drawings, Figure 6 Based on the same application concept, the embodiment of the present application also provides a test method of a semiconductor quantum chip, which includes the electrode structure of any one of the above semiconductor quantum chips, and the method includes the following steps:

[0074] Step S10: A third direct current voltage signal is applied through the third gate to form a two-dimensional electron gas in the channel below the third gate.

[0075] Step S11: applying a first direct current voltage signal through the first gate to form a two-dimensional electron gas in the channel under the first gate.

[0076] Step S12: applying the second direct current voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induced quantum dot.

[0077] Step S13: applying an excitation signal through the drain to form a transport current in the channel and transmit to the induced quantum dot.

[0078] Step S14: measuring the current output by the source to obtain the state of the induced quantum dot.

[0079] By applying a first direct current voltage signal and a third direct current voltage signal through the first gate and the third gate respectively, a continuous two-dimensional electron gas is formed in the channel under the first gate and the third gate; a second direct current voltage signal is applied to the second gate to form an induced quantum dot; finally, an excitation signal is applied to the drain, wherein the excitation signal is generally a voltage signal, and the voltage signal causes the electrons in the channel to move from the drain to the source to form a transport current. The state of the induced quantum dot will cause a change in the transport current, and the state of the induced quantum dot can be obtained by testing the current output by the source.

[0080] The electrodes of the semiconductor chip to be tested adopt the electrode structure in the embodiments of the present application, and the semiconductor quantum chip for the electrode structure adopts a conventional transport measurement method, without the need to apply a radio frequency signal to the third gate to complete the test of the induced quantum dot.

[0081] As shown in the accompanying drawings, Figure 7 Based on the same application concept, the embodiments of the present application also provide another test method for a semiconductor quantum chip, which includes any of the electrode structures of the semiconductor quantum chip described above, and the method includes the following steps:

[0082] Step S20: turning off the voltage signals output to the drain and the first gate.

[0083] Step S21: applying the second direct current voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induced quantum dot.

[0084] Step S22: applying a third direct current voltage signal through the third gate to form a two-dimensional electron gas in the channel under the third gate.

[0085] Step S23: applying a radio frequency signal through the third gate to read the state of the induced quantum dot.

[0086] The electrode of the semiconductor chip to be tested adopts the electrode structure in the embodiment of the application, and when the semiconductor quantum chip for the electrode structure is read by radio frequency reflection, no voltage signal needs to be applied on the drain and the first gate, a second direct current voltage signal is applied on the second gate to form an induced quantum dot, and a third direct current voltage signal is applied on the third gate to ensure that a two-dimensional electron gas is formed at the corresponding position below, so that the applied radio frequency signal can be transmitted to the induced quantum dot.

[0087] The electrode structure of the semiconductor quantum chip in the embodiment can be used to read the induced quantum dot by applying an excitation signal on the drain to realize the traditional transport measurement mode, or can be used to read the induced quantum dot by applying a radio frequency signal on the third gate, and no matter which reading mode is used, signal leakage does not occur, and the compatibility of the traditional transport measurement and the radio frequency reflection reading technology is realized.

[0088] In the description of the specification, the description of the terms "some embodiments" or "examples" means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the specification.

[0089] The above is only the preferred embodiment of the application, and does not limit the application in any way. Any person skilled in the art can make any form of equivalent replacement, modification or change to the technical solutions and technical contents disclosed in the application without departing from the scope of the technical solutions of the application, and such changes still belong to the protection scope of the application.

Claims

1. An electrode structure of a semiconductor quantum chip, characterized by, The semiconductor quantum chip includes an electrode structure as claimed in any one of claims 1-7, and the method comprises: a first gate for applying a first direct current voltage signal to form a two-dimensional electron gas under the first gate; a second gate for applying a second direct current voltage signal to adjust the charge density of the two-dimensional electron gas in the channel under the second gate to form an induced quantum dot; a third gate between the first gate and the second gate for applying a radio frequency signal to read the state of the induced quantum dot; wherein the first gate extends in a direction towards the third gate on the substrate to form a first extension, and the third gate extends in a direction towards the first gate on the substrate to form a second extension, and the end of the first extension and the end of the second extension overlap in the vertical extension direction, and an insulating medium layer is formed between the overlapping ends; the first gate and the third gate each include a pad on the substrate and a signal transmission line connected to the pad at one end, and the other end of the signal transmission line extends to the region where the induced quantum dot is located; and the overlapping ends are located at one end of the signal transmission line close to the region where the induced quantum dot is located.

2. The electrode structure of a semiconductor quantum chip according to claim 1, wherein The first extension is above the second extension.

3. The electrode structure of a semiconductor quantum chip according to claim 1, wherein The first gate extends in a direction towards the third gate on the substrate to form the first extension, and the third gate extends in a direction towards the first gate on the substrate to form the second extension; wherein the first extension is below the second extension.

4. The electrode structure of a semiconductor quantum chip according to claim 1, wherein The area of the overlapping ends is not less than 10 square nanometers and not more than 100 square nanometers.

5. The electrode structure of a semiconductor quantum chip according to claim 1, wherein When the first direct current voltage signal applied to the first gate is zero, the resistance of the overlapping ends is not less than 10 megaohms.

6. The electrode structure of a semiconductor quantum chip as claimed in claim 1, wherein The impedance of the third gate is less than the impedance of the induced quantum dot.

7. The electrode structure of a semiconductor quantum chip as claimed in claim 1, wherein The third gate is also used to apply a third direct current voltage signal to form the two-dimensional electron gas under the third gate.

8. A method of testing a semiconductor quantum chip, characterized by, The semiconductor quantum chip includes an electrode structure as claimed in any one of claims 1-7, and the method comprises: applying a third direct current voltage signal through the third gate to form a two-dimensional electron gas under the third gate; applying the first direct current voltage signal through the first gate to form a two-dimensional electron gas under the first gate; applying the second direct current voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induced quantum dot; applying an excitation signal through the drain to form a transport current in the channel and transmit to the induced quantum dot; measuring the current output by the source to obtain the state of the induced quantum dot.

9. A method of testing a semiconductor quantum chip, characterized by, The semiconductor quantum chip includes an electrode structure as claimed in any one of claims 1-7, and the method comprises: turning off the signal source electrically connected to the drain and the first gate; applying the second direct current voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induced quantum dot; A third direct current voltage signal is applied through the third gate to form a two-dimensional electron gas in a channel under the third gate; A radio frequency signal is applied through the third gate to read the state of the sensing quantum dot.

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