Manufacturing method of semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps: forming a zeroth interlayer dielectric layer around a dummy gate structure by using a first CMP (Chemical Mechanical Polishing) process, and etching a laminated layer formed by the dummy gate structure and a contact etching stop layer, so that the top surface of a dummy gate is exposed and a height difference is formed between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer; then a second CMP process is carried out to reduce the height difference and enable the dummy gate to reach the target thickness, when the second CMP process is carried out, the grinding amount of the zeroth interlayer dielectric layer is larger than that of the dummy gate, and when grinding is finished, the generation risk of the dished defect falls on the dummy gate, so that the thickness of the dummy gate reaches the target thickness. The dished defect on the dummy gate can be removed along with the removal of the dummy gate, so that the risk that obvious dished defects are formed on the surface of the zeroth interlayer dielectric layer is reduced, the risk that the metal gate material remains on the top surface of the zeroth interlayer dielectric layer is reduced, and the process reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] Traditional MOS transistors (metal-oxide-semiconductor field-effect transistors) mostly use doped polysilicon as the gate material. However, the boron penetration effect caused by the dopant boron can lead to reduced device performance, and the polysilicon gate is more prone to depletion, which increases the equivalent gate dielectric layer thickness and reduces the gate capacitance, thereby weakening the device driving capability. Currently, a MOS transistor manufacturing process using a metal gate instead of a polysilicon gate has been developed. The process usually uses a gate last process, in which a dummy gate is made of polysilicon on a substrate and a gate sidewall and a source and drain region are formed. Then, a dielectric material covering the dummy gate and the substrate is formed. Then, a CMP (chemical mechanical polishing) process is performed to expose the top surface of the dummy gate. The remaining dielectric material is located around the dummy gate to form a zeroth interlayer dielectric layer (ILD0). Thereafter, the dummy gate is removed, and a metal gate material is deposited in the formed gate trench and on the zeroth interlayer dielectric layer. The CMP process is performed again to expose the top surface of the zeroth interlayer dielectric layer. The remaining metal gate material located in the gate trench is the metal gate.

[0003] However, in the above process, after the previous CMP treatment, a dishing defect often forms on the top surface of the zero-th interlayer dielectric layer. Severe dishing defects will cause metal gate material to remain on the top surface of the zero-th interlayer dielectric layer after the next CMP treatment. As the process node decreases, the residual metal gate material on the dishing defect has a greater impact on the reliability of subsequent processes, thereby reducing the yield of semiconductor devices. Summary of the invention

[0004] In order to improve the existing gate-last process, avoid the formation of a dish-shaped defect on the top surface of the zero-th interlayer dielectric layer where metal gate material is easily left, and improve process reliability, the present invention provides a method for manufacturing a semiconductor device.

[0005] The method for manufacturing a semiconductor device provided by the present invention comprises:

[0006] Forming at least one dummy gate structure on the substrate, wherein the dummy gate structure includes a dummy gate and sidewalls covering two sides of the dummy gate;

[0007] Conformally forming a contact etch stop layer on the dummy gate structure and the substrate surface;

[0008] Covering the contact etching stop layer with a dielectric material, wherein a top surface of the dielectric material is higher than a top surface of the dummy gate structure;

[0009] Performing a first CMP process to use the contact etching stop layer covering the top of the dummy gate structure as a grinding stop layer, and the remaining dielectric material is located around the dummy gate structure to form a zeroth interlayer dielectric layer;

[0010] Etching the stacked layer formed by the dummy gate structure and the contact etching stop layer to expose the top surface of the dummy gate and form a height difference between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer;

[0011] Performing a second CMP process to reduce the height difference and make the dummy gate reach a target thickness;

[0012] removing the dummy gate and forming a gate groove in the region of the dummy gate; and

[0013] A metal gate is formed in the gate groove.

[0014] Optionally, forming the metal gate in the gate groove includes:

[0015] Conformally forming a work function metal layer on the inner surface of the gate groove and the top surface of the zeroth interlayer dielectric layer;

[0016] forming a metal electrode layer, the metal electrode layer filling the gate groove and covering the top surface of the zeroth interlayer dielectric layer; and

[0017] A third CMP process is performed to expose the top surface of the zeroth interlayer dielectric layer, and the remaining work function metal layer and the metal electrode layer are located in the gate groove to form the metal gate.

[0018] Optionally, the dielectric material covering the contact etch stop layer includes a first dielectric layer stacked on a surface of the contact etch stop layer and a second dielectric layer stacked on a surface of the first dielectric layer, wherein the hardness of the second dielectric layer is greater than that of the first dielectric layer.

[0019] Optionally, the first dielectric layer is a first silicon oxide layer formed by a HARP process, and the second dielectric layer is a second silicon oxide layer formed by a HDP process.

[0020] Optionally, before etching the stack formed by the dummy gate structure and the contact etching stop layer, the top surface of the dummy gate is lower than the top surface of the surrounding zeroth interlayer dielectric layer.

[0021] Optionally, after forming the zeroth interlayer dielectric layer around the dummy gate structure, the manufacturing method includes:

[0022] measuring a first height of a top surface of the zeroth interlayer dielectric layer relative to a top surface of the substrate, and measuring a second height of a top surface of the stack relative to a top surface of the substrate; and

[0023] The thickness of the stack to be etched is obtained according to the first height, the second height and the height difference to be formed, so as to set parameters for etching the stack according to the thickness of the stack to be etched.

[0024] Optionally, a thickness of the stack to be etched away is equal to (H2-(H1-H3)), wherein H1 represents the first height, H2 represents the second height, and H3 represents the height difference.

[0025] Optionally, both the contact etching stop layer and the dummy gate have etching selectivity with the zeroth interlayer dielectric layer, and maskless etching is used to etch the stacked layer consisting of the dummy gate structure and the contact etching stop layer.

[0026] Optionally, when performing the second CMP process, the dummy gate is used as a grinding stop layer.

[0027] Optionally, the height difference between the top surface of the stack and the zeroth interlayer dielectric layer is greater than or equal to and less than or equal to

[0028] In the method for manufacturing a semiconductor device provided by the present invention, after a first CMP process is performed to form a zero-th interlayer dielectric layer around the dummy gate structure, the stack formed by the dummy gate structure and the contact etching stop layer is etched to expose the top surface of the dummy gate, and a height difference is formed between the top surface of the dummy gate and the top surface of the zero-th interlayer dielectric layer. Then, a second CMP process is performed to reduce the height difference and make the dummy gate reach a target thickness. When the second CMP process is performed, the amount of grinding of the zero-th interlayer dielectric layer is larger than that of the dummy gate, so when the grinding is completed, the risk of generating a dishing defect falls on the The dummy gate is formed on the surface of the zero-th interlayer dielectric layer, and the risk of obvious dish-shaped defects forming on the surface of the zero-th interlayer dielectric layer is reduced, so the flatness of the dummy gate and the zero-th interlayer dielectric layer can be improved; and, since the dummy gate will be removed, the dish-shaped defects appearing on the dummy gate will be removed together. Compared with the prior art, it is equivalent to transferring the risk of dish-shaped defects from the zero-th interlayer dielectric layer of the prior art to the dummy gate in the present invention. As the influence of the second CMP process on the relatively low-positioned dummy gate is removed, not only the risk of residual metal gate material on the top surface of the zero-th interlayer dielectric layer is reduced, but also the process reliability is improved.

[0029] In addition, when the zero-th interlayer dielectric layer is formed around the dummy gate structure, a dielectric material is covered on the contact etch stop layer, and the dielectric material is ground using the first CMP process, so that the contact etch stop layer covering the top of the dummy gate structure is used as a grinding stop layer, and after the first CMP process is completed, the contact etch stop layer covering the top of the dummy gate structure is exposed. A dielectric material with a higher hardness can be used as the top layer of the dielectric material to be ground in the first CMP process, and when the first CMP process is performed, the problem of the dielectric material being ground too fast and the formation of a dish-shaped defect on the top surface of the zero-th interlayer dielectric layer can be improved.

[0030] Different from the prior art which uses only one CMP process to expose the dummy gate, the manufacturing method of the semiconductor device provided by the present invention uses two CMP processes to expose the dummy gate, wherein a first CMP process is used to form a zeroth interlayer dielectric layer around the dummy gate structure, and then the stack consisting of the dummy gate structure and the contact etching stop layer is etched to form a height difference between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer, and then a second CMP process is performed. When the second CMP process is performed, since the previous etching of the stack bears a part of the consumption of the stack, the grinding time can be shortened to avoid scratch defects caused by long-term grinding. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1A to 1FThe invention is a cross-sectional schematic diagram of a manufacturing method of a semiconductor device during the manufacturing process.

[0032] Figure 2 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0033] 3A to 3H It is a cross-sectional schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention during the manufacturing process. DETAILED DESCRIPTION

[0034] The following is a further detailed description of the method for manufacturing a semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the accompanying drawings is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0035] Figures 1A to 1F The present invention is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device during the manufacturing process. Figures 1A to 1F A method for manufacturing a semiconductor device is introduced, wherein a dummy gate is first formed on a substrate, and then the dummy gate is replaced by a metal gate. The method specifically includes the following steps:

[0036] like Figure 1A As shown, a dummy gate structure using a polysilicon gate is formed on a substrate 100, the dummy gate structure includes a dummy gate DG, and a contact etch stop layer 110 (CESL) is formed along the dummy gate structure and the surface of the substrate 100;

[0037] like Figure 1B As shown, a dielectric material is covered on the dummy gate structure and the surrounding substrate 100;

[0038] like Figure 1C As shown, a CMP process is performed to expose the top surface of the dummy gate DG and reach a target thickness, and the remaining dielectric material is used as the zeroth interlayer dielectric layer ILD0;

[0039] like Figure 1DAs shown, the dummy gate DG in the dummy gate structure is removed, and a gate trench GT (gate trench) is formed at the position where the dummy gate DG was originally set;

[0040] like Figure 1E As shown, a metal material is deposited in the gate groove GT and on the zeroth interlayer dielectric layer ILD0;

[0041] like Figure 1F As shown, the CMP process is performed again to expose the top surface of the zeroth interlayer dielectric layer ILD0, and the remaining metal material in the gate groove GT serves as the metal gate MG.

[0042] In the above process, Figure 1C and Figure 1D As shown, after the previous CMP process, a more obvious dishing defect 10 (dishing) is formed on the top surface of the zeroth interlayer dielectric layer ILD0. After the metal material is deposited, the metal material at the bottom of the dishing defect 10 is thicker; Figure 1F As shown, after the subsequent CMP process, while ensuring the thickness and surface quality of the metal gate MG formed in the gate groove GT, the metal material at the bottom of the dish-shaped defect 10 is difficult to be removed completely and forms a metal residue 11, which affects the reliability of subsequent processes. For example, it is easy to cause a short circuit in the metal interconnection line subsequently formed on the zeroth interlayer dielectric layer ILD0 and increase signal interference, which will reduce the yield of the semiconductor device.

[0043] Compared to Figures 1A to 1F In the process shown, the method for manufacturing a semiconductor device according to an embodiment of the present invention is used. Before the previous CMP process is performed, a height difference is made between the top surface of the dielectric material and the top surface of the dummy gate. When the previous CMP process is performed to remove excess dielectric material and to make the dummy gate reach a target thickness, although there is a difference in the grinding speed of the dielectric material and the dummy gate, due to the high dielectric material, the process of reducing the height difference is not easy to form a dish-shaped defect on the surface of the zeroth interlayer dielectric layer ILD0 formed. Moreover, since the dummy gate will be removed later, the influence of this CMP process on the dummy gate with a lower height is eliminated. From the overall effect, the method for manufacturing a semiconductor device according to the embodiment of the present invention can reduce the risk of forming a dish-shaped defect that is easy to cause residual metal gate material on the top surface of the zeroth interlayer dielectric layer ILD0, thereby improving process reliability.

[0044] The following combination Figure 2 and 3A to 3H A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail.

[0045] Reference Figure 2 and Figure 3AFirst, step S1 is performed to form at least one dummy gate structure on a substrate 100 , wherein the dummy gate structure includes a dummy gate DG and sidewalls 102 covering both sides of the dummy gate DG.

[0046] The substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates known to those skilled in the art for carrying semiconductor devices.

[0047] At least one of the dummy gate structures formed on the substrate 100 is used to form at least one MOS transistor, which may include an NMOS transistor and / or a PMOS transistor. Each of the dummy gate structures may include a gate dielectric layer 101 formed on the surface of the substrate 100, a dummy gate DG stacked on the gate dielectric layer 101, and a sidewall 102 covering the sides of the gate dielectric layer 101 and the dummy gate DG. The gate dielectric layer 101 may be a single layer or a multilayer. For example, in one embodiment, the gate dielectric layer 101 includes a silicon oxide layer and a high dielectric constant layer stacked on the silicon oxide layer. In addition, the dummy gate structure may further include an etching stopper layer (e.g., titanium nitride) between the gate dielectric layer 101 and the dummy gate DG. When the dummy gate DG is subsequently removed, the etching stopper layer may protect the gate dielectric layer 101. The thickness of the dummy gate DG is, for example, about

[0048] The sidewall spacers 102 covering both sides of the dummy gate DG may be a single-layer structure or a multi-layer structure, and the sidewall spacers 102 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] Since there is a height difference between the dummy gate structure and the surface of the substrate 100 , there is a gap around the dummy gate structure, and the gap is subsequently filled with a dielectric material.

[0050] It should be noted that the present embodiment focuses on how to avoid the problem of forming a dish-shaped defect that is easy to leave residual metal material on the top surface of the zero-th interlayer dielectric layer. Those skilled in the art can understand that it is not necessary to describe the detailed entire process of manufacturing a semiconductor device in the specification, and the accompanying drawings only show several dummy gate structures as examples in the form of schematic diagrams. Before step S2, the following process steps (not shown) may also be completed but are not limited to: forming an isolation channel (such as shallow trench isolation, STI) and an ion implantation region in the substrate 100, forming an LDD region in the substrate 100 at the end of the dummy gate DG and below the sidewall 102, and forming a source region and a drain region in the substrate 100 on both sides of the dummy gate structure, etc.

[0051] Reference Figure 2 and Figure 3A , perform step S2 to conformally form a contact etch stop layer 110 (CESL) on the dummy gate structure and the surface of the substrate 100. The contact etch stop layer 110 can serve as a stop layer for a subsequent CMP process and a protective layer for the substrate 100. The contact etch stop layer 110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. As an example, in this embodiment, the contact etch stop layer 110 is made of silicon nitride.

[0052] Next, refer to Figure 2 , executing step S3, forming a zeroth interlayer dielectric layer around the dummy gate structure.

[0053] In order to form the zeroth interlayer dielectric layer around the dummy gate structure, a dielectric material may be first covered on the contact etch stop layer 110 so that the surface of the dielectric material is higher than the top surface of the dummy gate structure, and then a CMP process (referred to as the first CMP process) is performed to use the contact etch stop layer 110 covering the top of the dummy gate structure as a grinding stop layer, and the remaining dielectric material is located around the dummy gate structure to form the zeroth interlayer dielectric layer (ILD0).

[0054] Considering Figures 1A to 1F The problem of the process shown in FIG. 1 is that the flatness of the top surface of the zeroth interlayer dielectric layer ILD0 obtained after the CMP process should be improved as much as possible to avoid the formation of serious dishing defects. To this end, in step S3 of the present embodiment, referring to FIG. Figure 3B , first deposit a first dielectric layer 121 to fill the gap around the dummy gate structure. To ensure the filling quality, the hardness of the first dielectric layer 121 can be relatively small. Then deposit a second dielectric layer 122 with relatively high hardness, so that the second dielectric layer 122 is used as the top layer of the dielectric material to be polished in the subsequent CMP process, so as to reduce the polishing speed of the CMP process for the stack of the first dielectric layer 121 and the second dielectric layer 122, and avoid the formation of serious dishing defects on the surface of the dielectric material obtained after polishing. As an example, the first dielectric layer 121 is a silicon oxide layer formed by a HARP (high aspect ratio chemical vapor deposition) process, and the second dielectric layer 122 is another silicon oxide layer formed by a HDP (high density plasma chemical vapor deposition) process.

[0055] Reference Figure 3CIn this embodiment, after the first dielectric layer 121 and the second dielectric layer 122 are sequentially formed on the contact etch stop layer 110 through step S3, a CMP process (i.e., a first CMP process) is then performed to expose the contact etch stop layer 110 covering the top of the dummy gate structure, and the remaining first dielectric layer 121 and the second dielectric layer 122 are located around the dummy gate structure as the zeroth interlayer dielectric layer ILD0. As an example, the polishing liquid used in the first CMP process is a silicon oxide polishing liquid, and its selectivity for silicon oxide (exemplarily as the material of the first dielectric layer 121 and the second dielectric layer 122) and silicon nitride (exemplarily as the material of the contact etch stop layer 110) is greater than 5:1.

[0056] In step S3, by providing the second dielectric layer 122 with a relatively high hardness and appropriately setting the parameters of the first CMP process, the contact etch stop layer 110 located at the top of the dummy gate structure can be exposed while the top surface of the zeroth interlayer dielectric layer ILD0 located around the dummy gate structure is made higher than the top surface of the dummy gate DG in the dummy gate structure. While avoiding the generation of severe dishing defects, the lowest point of the dishing depression on the surface of the zeroth interlayer dielectric layer ILD0 is made higher than the dummy gate DG, which can shorten the grinding time and reduce the risk of severe dishing defects and scratch defects formed on the contact etch stop layer 110 and the surface of the zeroth interlayer dielectric layer ILD0 due to long-term grinding.

[0057] After the zeroth interlayer dielectric layer ILD0 is filled around the dummy gate structure, a thickness test may be performed to detect the effect of the first CMP process and provide reference data for the subsequent steps S4 and S5. For example, the first height H1 of the top surface of the zeroth interlayer dielectric layer ILD0 relative to the top surface of the substrate 100 may be measured by the built-in function of the CMP machine, and the second height H2 of the top surface of the stack (or encapsulating structure) formed by the dummy gate structure and the contact etching stop layer 110 relative to the top surface of the substrate 100 may be measured.

[0058] Reference Figure 2 and Figure 3D , then step S4 may be performed to etch the stack formed by the dummy gate structure and the contact etching stop layer 110, so that the top surface of the dummy gate DG is exposed, and a height difference H3 is formed between the top surface of the dummy gate DG and the top surface of the zeroth interlayer dielectric layer ILD0. That is, through step S4, a step with a height of H3 is formed between the dummy gate DG and the zeroth interlayer dielectric layer ILD0 surrounding it.

[0059] The contact etch stop layer 110 and the zeroth interlayer dielectric layer ILD0 have, for example, good etching selectivity, so that the stack formed by the dummy gate structure and the contact etch stop layer 110 can be etched by maskless etching. In this embodiment, the contact etch stop layer 110 and the zeroth interlayer dielectric layer ILD0 are respectively formed of silicon nitride and silicon oxide, both of which have good etching selectivity, and step S4 can be completed by maskless etching, which can simplify the process. Specifically, the stack formed by the dummy gate structure and the contact etch stop layer 110 can be etched by dry etching or wet etching.

[0060] When etching the stack, depending on the etching thickness requirements, only the contact etch stop layer 110 located above the top surface of the dummy gate DG may be etched away without etching the dummy gate DG, or the contact etch stop layer 110 located above the top surface of the dummy gate DG and a partial thickness of the dummy gate DG may be etched away.

[0061] The height difference H3 can be set according to specific needs, and should not be too large or too small. Because if the height difference H3 is too large, after the etching in step S4, the thickness of the remaining dummy gate DG is small, which is easy to affect the thickness of the metal gate that replaces the dummy gate DG later. However, if the height difference H3 is too small, after the etching in step S4, the thickness of the remaining dummy gate DG is large. When the dummy gate DG is further reduced to the target thickness by grinding the CMP process in the subsequent step S5, the grinding amount is large, which is easy to cause scratch defects. In this embodiment, the height difference H3 is, for example, about Preferably, the height difference H3 is greater than or equal to and less than or equal to

[0062] In addition, the value of the height difference H3 can be pre-set before etching the stack formed by the dummy gate structure and the contact etching stop layer 110. In this embodiment, the height difference H3 is the thickness that needs to be removed at least in the second CMP process in the subsequent step S5. Further, in order to shorten the grinding time of the second CMP process, the dummy gate DG formed in step S4 can be used as the grinding stop layer of the second CMP process or the height difference H3 can be used as the target removal amount of the second CMP process, so that the consumption of the dummy gate DG in step S5 is small, and after step S4, the thickness of the remaining dummy gate DG is equal to or slightly greater than the target thickness to be reached by the dummy gate DG in step S5. In this way, the height difference H3 to be formed in step S4 can be set with reference to the difference between the first height H1 corresponding to the zeroth interlayer dielectric layer ILD0 and the target height of the dummy gate DG. For example, the height difference H3 is equal to or slightly less than the difference between the first height H1 corresponding to the zeroth interlayer dielectric layer ILD0 and the target height of the dummy gate DG.

[0063] In this embodiment, the first height H1 and the second height H2 measured after completing step S3 and the value of the height difference H3 can be used to calculate the amount (or etching degree) to be etched in step S4, which can improve the accuracy of the height difference H3 actually obtained and reduce errors. Specifically, the thickness of the stack to be etched and removed can be obtained by calculating (H2-(H1-H3)). After obtaining the thickness of the stack to be etched, the etching parameters can be set based on the thickness to be removed.

[0064] Reference Figure 2 and Figure 3E , step S5 is executed to perform a CMP process (referred to as the second CMP process) to reduce the height difference H3 and make the dummy gate DG reach the target thickness. As an example, the polishing liquid used in the second CMP process is a silicon oxide polishing liquid, and its selection ratio for silicon oxide (exemplarily used as the material of the first dielectric layer 121 and the second dielectric layer 122) and polysilicon (exemplarily used as the material of the dummy gate DG) is greater than 20:1.

[0065] In this embodiment, before the second CMP process is performed, a height difference H3 is formed between the top surface of the dummy gate DG and the top surface of the zeroth interlayer dielectric layer ILD0; when the second CMP process is performed, the top of the dummy gate DG after etching in step S4 can be set as the grinding end point of the second CMP process, or the height difference H3 is set as the target removal amount of the second CMP process. Although there is a difference in the grinding speed of the zeroth interlayer dielectric layer ILD0 and the dummy gate DG, since the top surface of the zeroth interlayer dielectric layer ILD0 is higher, the amount of grinding of the zeroth interlayer dielectric layer ILD0 is larger during the grinding process, and the risk of forming an obvious dish-shaped defect on the surface of the zeroth interlayer dielectric layer ILD0 is reduced, thereby reducing the risk of forming an obvious dish-shaped defect on the surface of the zeroth interlayer dielectric layer ILD0. Figures 1A to 1F In the process shown, after the second CMP process, the flatness of the dummy gate DG and the zeroth interlayer dielectric layer ILD0 is improved. In addition, since the dummy gate DG is located at a lower position, after the second CMP process, the risk of generating a dishing defect is transferred from the zeroth interlayer dielectric layer ILD0 to the dummy gate DG. Since the dummy gate DG will be removed later, the influence of the second CMP process on the lower dummy gate DG (such as possible surface defects, such as dishing defects) is removed, and the metal gate will not be affected. The manufacturing method of the embodiment of the present invention reduces the risk of forming a dishing defect that is easy to leave metal material on the top surface of the zeroth interlayer dielectric layer ILD0, thereby reducing the risk of metal material remaining on the top surface of the zeroth interlayer dielectric layer ILD0, and improving process reliability.

[0066] Reference Figure 2 and Figure 3F , executing step S6, removing the dummy gate DG, and forming a gate groove GT in the region of the dummy gate DG.

[0067] The dummy gate DG can be removed by dry etching or wet etching. In the present embodiment, the dummy gate DG is made of polysilicon. If the dummy gate DG is removed by wet etching, an etching solution containing nitric acid can be selected. If the dummy gate DG is removed by dry etching, chlorine or hydrogen bromide can be used as a process gas. After the dummy gate DG is removed, a gate groove GT is formed in the area where the dummy gate DG was originally set. The sidewall 102 originally located on the side of the dummy gate GT constitutes the sidewall of the gate groove GT. The bottom wall of the gate groove GT, for example, exposes the gate dielectric layer 101 originally located below the dummy gate DG.

[0068] Reference Figure 2, then step S7 may be performed to form a metal gate in the gate groove GT. The metal gate may include a work function metal layer and a metal electrode layer that can meet the work function requirements of the corresponding transistor. Depending on the type of transistor to be formed by the metal gate, the material of the metal gate filled in each gate groove GT may be selected accordingly, and the structure of the metal gate may refer to the technology disclosed in the art.

[0069] As an example, step S7 may include:

[0070] First, a work function metal layer is conformally formed on the inner surface of the gate groove GT and the top surface of the zeroth interlayer dielectric layer ILD0 (not shown). In some embodiments, different work function metal layers need to be formed in two different gate trenches GT. Then, after a work function metal layer is conformally deposited on the inner surface of each gate trench GT and the surface of the zeroth interlayer dielectric layer ILD0, the work function metal layer in a portion of the gate trench GT is removed by photolithography and etching processes, and then another work function metal layer is deposited. In addition, the work function metal layer formed in the same gate groove GT may be one layer or multiple layers.

[0071] Afterwards, refer to Figure 3G , forming a metal electrode layer 130, wherein the metal electrode layer 130 fills the gate groove GT and covers the top surface of the zeroth interlayer dielectric layer ILD0;

[0072] Then, refer to Figure 3H , a CMP process (referred to as the third CMP process) is performed to expose the top surface of the zeroth interlayer dielectric layer ILD0, and the remaining work function metal layer and metal electrode layer 130 are located in the gate groove GT to form a metal gate MG. Each of the metal gates MG and the source region and drain region formed in the substrate 100 on both sides thereof constitute a MOS transistor.

[0073] Through the method for manufacturing a semiconductor device described in the above embodiment, after the second CMP process, the dummy gate DG and the zeroth interlayer dielectric layer ILD0 have a high flatness, so that when the third CMP process is performed, the work function metal layer and the metal electrode layer 130 on the top surface of the zeroth interlayer dielectric layer ILD0 can be easily removed, while ensuring that the metal gate MG formed in the gate groove GT is not over-polished, thereby optimizing the performance of the manufactured semiconductor device.

[0074] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Forming at least one dummy gate structure on the substrate, wherein the dummy gate structure includes a dummy gate and sidewalls covering two sides of the dummy gate; Conformally forming a contact etch stop layer on the dummy gate structure and the substrate surface; Covering the contact etching stop layer with a dielectric material, wherein a top surface of the dielectric material is higher than a top surface of the dummy gate structure; Performing a first CMP process to use the contact etching stop layer covering the top of the dummy gate structure as a grinding stop layer, and the remaining dielectric material is located around the dummy gate structure to form a zeroth interlayer dielectric layer; Etching the stacked layer formed by the dummy gate structure and the contact etching stop layer to expose the top surface of the dummy gate and form a height difference between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer; Performing a second CMP process to reduce the height difference and make the dummy gate reach a target thickness; Removing the dummy gate and forming a gate groove in the region of the dummy gate; as well as A metal gate is formed in the gate groove.

2. The method according to claim 1, characterized in that: Forming the metal gate in the gate groove includes: Conformally forming a work function metal layer on the inner surface of the gate groove and the top surface of the zeroth interlayer dielectric layer; forming a metal electrode layer, the metal electrode layer filling the gate groove and covering the top surface of the zeroth interlayer dielectric layer; and A third CMP process is performed to expose the top surface of the zeroth interlayer dielectric layer, and the remaining work function metal layer and the metal electrode layer are located in the gate groove to form the metal gate.

3. The method according to claim 1, characterized in that: The dielectric material covering the contact etch stop layer includes a first dielectric layer stacked on the surface of the contact etch stop layer and a second dielectric layer stacked on the surface of the first dielectric layer, wherein the hardness of the second dielectric layer is greater than that of the first dielectric layer.

4. The method according to claim 3, characterized in that: The first dielectric layer is a silicon oxide layer formed by a HARP process, and the second dielectric layer is another silicon oxide layer formed by a HDP process.

5. The method according to claim 1, characterized in that: Before etching the stacked layer formed by the dummy gate structure and the contact etching stop layer, the top surface of the dummy gate is lower than the top surface of the surrounding zeroth interlayer dielectric layer.

6. The method according to claim 1, characterized in that: After forming the zeroth interlayer dielectric layer around the dummy gate structure, the manufacturing method comprises: measuring a first height of a top surface of the zeroth interlayer dielectric layer relative to a top surface of the substrate, and measuring a second height of a top surface of the stack relative to a top surface of the substrate; and The thickness of the stack to be etched away is obtained according to the first height, the second height and the height difference to be formed, so as to set parameters for etching the stack according to the thickness of the stack to be etched away.

7. The method according to claim 6, characterized in that: The thickness of the stack to be etched away is equal to (H2-(H1-H3)), where H1 represents the first height, H2 represents the second height, and H3 represents the height difference.

8. The method according to claim 1, characterized in that: The contact etching stop layer and the dummy gate have etching selectivity with the zeroth interlayer dielectric layer, and the stacked layer consisting of the dummy gate structure and the contact etching stop layer is etched by maskless etching.

9. The method according to claim 1, characterized in that: When the second CMP process is performed, the dummy gate is used as a polishing stop layer.

10. The production method according to any one of claims 1 to 9, characterized in that: The height difference formed between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer is greater than or equal to and less than or equal to

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