Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and aims to solve the conductor problem of a semiconductor device. A semiconductor device of the display panel comprises a part arranged on a grid conducting layer, a part arranged on a first active film layer, a part arranged on a second active film layer, and a first electrode and a second electrode which are arranged on a source-drain conducting layer. The display panel further comprises a virtual filling pattern, and the virtual filling pattern is arranged on the source-drain conducting layer. Through the arrangement of the virtual filling pattern, in the process of preparing the display panel, the distribution of the part, needing to be etched and removed, of the source-drain conducting layer on the substrate is more uniform, so that the concentration of etching liquid is more uniform, and the etching efficiency is improved. It is ensured that the part, arranged on the second active film layer, of the semiconductor device is disconnected in the interval area between the first electrode and the second electrode, and electric leakage between the first electrode and the second electrode through the second active film layer is prevented.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the increasing development of consumer electronic products, in the field of display technology, the film structure and semiconductor devices of display panels are becoming more and more complex, and the requirements for production processes are also increasing. Limited by process precision, some semiconductor devices in display panels have conductor problems, which in turn cause problems such as signal crosstalk, affecting product yield.

[0003] How to solve the conductor problem of semiconductor devices has become an issue that needs to be solved urgently in this field. Summary of the invention

[0004] The present application proposes a display panel and a display device, aiming to improve the conductor problem of semiconductor devices.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] On the one hand, a display panel is provided, which includes a substrate, and a gate conductive layer, a first active film layer, a second active film layer and a source-drain conductive layer stacked on the substrate. The display panel also includes a semiconductor device and a dummy fill pattern, and the semiconductor device includes a portion arranged on the gate conductive layer, a portion arranged on the first active film layer, a portion arranged on the second active film layer, and a first electrode and a second electrode arranged on the source-drain conductive layer. Along a first direction parallel to the substrate, there is a spacing region between the first electrode and the second electrode, and in the first direction, the portion of the semiconductor device arranged on the second active film layer is disconnected in the spacing region. The dummy fill pattern is arranged on the source-drain conductive layer, and along a direction parallel to the substrate, the dummy fill pattern is arranged on at least one side of the semiconductor device.

[0007] In some embodiments, the semiconductor device includes a transistor, the transistor includes a gate disposed on the gate conductive layer, an active layer disposed on the first active film layer, a portion disposed on the second active film layer, and a source and a drain disposed on the source-drain conductive layer. Along a first direction, there is the above-mentioned spacing region between the source and the drain, and in the first direction, the portion of the transistor disposed on the second active film layer is disconnected in the spacing region.

[0008] In some embodiments, the display panel includes a display area, and a binding area located on one side of the display area, the binding area includes an IC area and a clearance area arranged along a second direction, the second direction is parallel to the substrate, and is parallel to the boundary of the binding area close to the display area. The display panel also includes a plurality of data lines arranged in the display area, a plurality of transistors, a plurality of connecting lines, a plurality of switch control signal lines, and a plurality of detection signal lines arranged in the IC area, the data line extends from the display area to the IC area, and is electrically connected to the drain of the transistor through a connecting line, the source of the transistor is electrically connected to a detection signal line through another connecting line, and the gate of the transistor is electrically connected to a switch control signal line. The connecting line, the source and drain of the transistor, and the virtual fill pattern are all arranged in the source-drain conductive layer, and the virtual fill pattern is arranged in the clearance area.

[0009] In some embodiments, the virtual fill pattern includes multiple virtual connection lines, which are arranged at intervals along the second direction, the width of the virtual connection line is equal to the width of the connection line, and the spacing between two adjacent virtual connection lines is equal to the spacing between two adjacent connection lines.

[0010] In some embodiments, the binding region includes a first IC region, a clearance region, and a second IC region sequentially arranged along a second direction, and along the second direction, a plurality of detection signal lines extend from the first IC region, through the clearance region, to the second IC region. In the first IC region, a plurality of transistors include a first transistor closest to the clearance region, and in the second IC region, a plurality of transistors include a second transistor closest to the clearance region, and the first transistor and the second transistor are electrically connected to the same detection signal line.

[0011] In some embodiments, the display panel includes a display area, and a peripheral area located on at least one side of the display area. The display panel also includes a plurality of sub-pixels, a plurality of gate lines, and a plurality of data lines arranged in the display area. The plurality of sub-pixels include a plurality of rows and a plurality of columns. The sub-pixels in each row are arranged along a third direction, and the sub-pixels in each column are arranged along a fourth direction. The third direction intersects with the fourth direction and is parallel to the substrate, respectively. The gate line extends along the third direction, and the data line extends along the fourth direction. Each sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes a transistor, the gate of the transistor is electrically connected to the gate line, and the source or drain of the transistor is electrically connected to the data line. The data line, the source and drain of the transistor, and the virtual fill pattern are all arranged in the source-drain conductive layer, and the virtual fill pattern is arranged in the peripheral area.

[0012] In some embodiments, the peripheral area includes a first sub-peripheral area and a second sub-peripheral area, the first sub-peripheral area is located on two opposite sides of the display area along a third direction, and the second sub-peripheral area is located on two opposite sides of the display area along a fourth direction. A plurality of data lines extend from the display area to the second sub-peripheral area, and the dummy fill pattern is disposed in the first sub-peripheral area.

[0013] In some embodiments, the semiconductor device includes a diode, and the diode includes a first auxiliary electrode and a second auxiliary electrode disposed on the gate conductive layer, a first conductive type layer and a second conductive type layer disposed on the first active film layer, a portion disposed on the second active film layer, and a first electrode, a second electrode, and a connecting electrode disposed on the source and drain conductive layer. The first electrode is electrically connected to the first auxiliary electrode and is electrically connected to the first conductive type layer, respectively, the connecting electrode is electrically connected to the first conductive type layer and the second conductive type layer, and the second electrode is electrically connected to the second auxiliary electrode and is electrically connected to the second conductive type layer, respectively. Along the first direction, the first electrode, the connecting electrode, and the second electrode are arranged in sequence, a first spacing region is provided between the first electrode and the connecting electrode, and a second spacing region is provided between the connecting electrode and the second electrode, and in the first direction, the portion of the diode disposed on the second active film layer is disconnected in the first spacing region and the second spacing region.

[0014] In some embodiments, the display panel includes a display area and a peripheral area located on at least one side of the display area. The display panel also includes a plurality of gate lines arranged in the display area, and an electrostatic ring circuit arranged in the peripheral area, the electrostatic ring circuit includes a plurality of diodes, the gate lines extend from the display area to the peripheral area, and are electrically connected to the electrostatic ring circuit. The dummy fill pattern is arranged in the peripheral area and is located around the diodes.

[0015] On the other hand, the present application also provides a display device, which includes the display panel and the controller mentioned in any embodiment of the first aspect above, wherein the controller is electrically connected to the display panel.

[0016] In the above embodiments provided in the present application, the semiconductor device of the display panel includes a portion disposed on the gate conductive layer, a portion disposed on the first active film layer, a portion disposed on the second active film layer, and a first electrode and a second electrode disposed on the source and drain conductive layer. In order to achieve relevant functions, along a first direction parallel to the substrate, there is a spacing region between the first electrode and the second electrode, and in this direction, the portion of the semiconductor device disposed on the second active film layer is disconnected in the spacing region, thereby ensuring that the first electrode and the second electrode are independent of each other and there is no leakage problem between the two.

[0017] In the related art, forming a display panel requires etching the source-drain conductive layer and the second active film layer to form the required semiconductor devices. Since semiconductor devices need to be set in some areas of the display panel and do not need to be set in the clearance area, the area of ​​the source-drain conductive layer that needs to be etched and removed in the clearance area is larger, the etching solution demand is high, and more etching solution is consumed. This will result in a lower etching solution concentration at the edge of the area where the semiconductor devices need to be set, which will lead to unsatisfactory etching effect of the semiconductor devices at the edge of the area. For example, in the spacing area between the first electrode and the second electrode, the second active film layer is not thoroughly etched or material residue of the source-drain conductive layer is likely to occur, resulting in a higher risk of conductorization between the first electrode and the second electrode.

[0018] In an embodiment of the present application, a virtual fill pattern is provided in the source-drain conductive layer, and the virtual fill pattern is provided on at least one side of the semiconductor device along a direction parallel to the substrate. Based on this, in the process of forming the display panel, in order to form the virtual fill pattern, the etching area of ​​the clearance area is reduced, and the demand for etching solution is reduced, so that the consumption rate of the region where the semiconductor device is provided and the clearance area is close, and the concentration of the etching solution can be made more uniform, thereby avoiding the etching difference in different regions, avoiding incomplete etching of the second active film layer in the interval region between the first electrode and the second electrode or the presence of residues of the source-drain conductive layer, thereby ensuring that the first electrode and the second electrode of each semiconductor device formed are independent of each other and there is no leakage problem between the two, solving the conductorization problem existing in some semiconductor devices in the display panel, avoiding signal crosstalk and other problems, and improving the product yield.

[0019] The display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, not the actual size of the product involved in the embodiments of the present application, or the actual process of the method.

[0021] Figure 1 A top view of a display panel provided in an embodiment of the present application;

[0022] Figure 2 is an IV curve diagram of multiple switch transistors in the IC region;

[0023] Figure 3 for Figure 1 The shown is a partial enlarged view of the display panel at position M;

[0024] Figure 4 for Figure 3 A partial cross-sectional view of the display panel along the section line AA' shown;

[0025] Figure 5 for Figure 1 The shown is a partial enlarged view of the display panel in the binding area;

[0026] Figure 6 for Figure 1 The shown is a partial enlarged view of the display panel at position N;

[0027] Figure 7 for Figure 1 The shown is a partial enlarged view of the display panel at position O;

[0028] Figure 8 for Figure 7 The partial cross-sectional view of the display panel along the section line BB' is shown;

[0029] Fig. 9 This is a structural block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0031] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0032] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0033] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0034] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0035] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0036] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0037] In the related art, due to the limitation of process precision, some semiconductor devices in the display panel have conductor problems. For example, in the binding area of ​​the display panel, the edge semiconductor devices leak electricity, causing crosstalk between different drive signals, which in turn causes vertical stripes on the display panel. The above conductor problems are usually caused by the unsatisfactory etching effect of the relevant conductive film layer during the etching stage of the display panel preparation process.

[0038] Based on this, an embodiment of the present application proposes a display panel. Figure 1 A top view of a display panel provided in an embodiment of the present application.

[0039] like Figure 1 As shown, the display panel 100 includes a display area AA, and the display panel 100 also includes a plurality of sub-pixels P, a plurality of gate lines GL and a plurality of data lines DL arranged in the display area AA. The plurality of sub-pixels P include a plurality of rows and a plurality of columns. The sub-pixels P in each row are arranged along a direction X, and the sub-pixels P in each column are arranged along a direction Y. The direction X intersects with the direction Y, and the direction X and the direction Y are respectively parallel to the substrate 10 of the display panel 100.

[0040] Each gate line GL extends along a direction X, each data line DL extends along a direction Y, each sub-pixel P includes a pixel driving circuit D, the pixel driving circuit D includes a plurality of transistors, the plurality of transistors include at least one light-emitting control transistor, a gate of the light-emitting control transistor is electrically connected to the gate line GL, and one of the source or the drain is electrically connected to the data line DL, a gate scanning signal is transmitted to the gate of the light-emitting control transistor through the gate line GL to control the light-emitting control transistor to be turned on, and a data signal transmitted by the data line DL is input through the source or the drain of the light-emitting control transistor to realize driving of the pixel driving circuit D, thereby driving the sub-pixel P to emit light.

[0041] like Figure 1 As shown, the display panel 100 further includes a peripheral area BB located at least on one side of the display area AA, and the display panel 100 further includes an electrostatic ring circuit 11 disposed in the peripheral area BB, and the electrostatic ring circuit 11 includes a plurality of diodes 12. The gate line GL extends from the display area AA to the peripheral area BB and is electrically connected to the electrostatic ring circuit 11.

[0042] In the lighting test phase, the electrostatic ring circuit 11 can transmit a test scanning signal to the gate line GL to drive the sub-pixel P to display. In the process of the gate driver IC driving the gate line, the electrostatic ring circuit 11 plays a role in curbing the leakage of the gate line GL and avoiding the gate scanning signal transmitted by the gate line GL from generating a voltage drop.

[0043] like Figure 1 As shown, the display panel 100 further includes a binding area BA located on one side of the display area AA, the binding area BA includes an IC area 1 and a clearance area 2 arranged along a direction X, a plurality of data lines DL extend from the display area AA to the IC area 1, and the IC area 1 is used to bind a source driver IC, so as to transmit data signals to the data lines DL through the source driver IC to drive the display panel 100 to display a picture. The direction X is parallel to a boundary E of the binding area BA close to the display area AA.

[0044] In the related art, taking the binding area as an example, a switching circuit is arranged in the IC area of ​​the binding area, the switching circuit includes a switching transistor, the switching transistor includes a first active layer, a second active layer, a source and a drain. In the process of preparing the switching transistor, the source and the drain are formed by etching the source-drain conductive layer (SD). Due to the existence of the clearance area, the area of ​​the source-drain conductive layer that needs to be etched and removed in the clearance area is large, and the etching solution requirement is high, so that the etching solution concentration near the clearance area of ​​the IC area is low, resulting in a smaller distance between the source and the drain after etching, and the second active layer located below the source-drain conductive layer is etched and removed less, and the second active layer is not easy to disconnect. Since the second active layer is a doped conductive film layer, it will cause a short circuit between the source and the drain, resulting in the threshold voltage (Vth) of the switching transistor being negative, that is, the switching transistor is conductorized.

[0045] Figure 2 It is an IV curve diagram of multiple switching transistors in the IC area, wherein the horizontal axis of the curve diagram is the gate voltage Vg of the switching transistor, in units of "V"; the vertical axis is the on-current of the switching transistor, in units of "A", and curve 1 is the IV curve of the switching transistor closest to the clear area among the multiple transistors. When the gate voltage changes, the on-current of the switching transistor corresponding to curve 1 remains basically unchanged, and the on-current of the switching transistors corresponding to curves 2 and 3 changes with the change of the gate voltage, indicating that the switching transistor corresponding to curve 1 is conductive.

[0046] In order to solve the above problems, the present application provides the following embodiments: Figure 3 for Figure 1 The shown is a partial enlarged view of the display panel at position M; Figure 4 for Figure 3 The display panel is shown in a partial cross-sectional view along the section line AA'.

[0047] like Figure 3 and Figure 4 As shown, the display panel 100 includes a substrate 10, and a gate conductive layer Gate, a first active film layer ACT1, a second active film layer ACT2 and a source-drain conductive layer SD stacked on the substrate 10, and the second active film layer ACT2 is doped with conductive ions.

[0048] Exemplarily, the materials of the first active film layer ACT1 and the second active film layer ACT2 both include amorphous silicon (a-Si), or the materials of the first active film layer ACT1 and the second active film layer ACT2 both include metal oxide, such as indium gallium zinc oxide (IGZO).

[0049] The IC region 1 includes a semiconductor device 20, which may be, for example, a transistor 21. The transistor 21 includes a gate G disposed on a gate conductive layer Gate, an active layer ACT disposed on a first active film layer ACT1, a portion disposed on a second active film layer ACT2, and a source S and a drain D disposed on a source-drain conductive layer SD. Along a direction Y, there is a spacing region T1 between the source S and the drain D. In the direction Y, the portion of the transistor 21 disposed on the second active film layer ACT2 is disconnected in the spacing region T1.

[0050] like Figure 3 and Figure 4As shown, the display panel 100 further includes a dummy filling pattern 30, which is also disposed in the source-drain conductive layer SD, and is disposed on at least one side of the semiconductor device 20 along a direction parallel to the substrate 10. For example, the dummy filling pattern 30 is disposed in the clearance area 2, that is, the dummy filling pattern 30 is located on one side of the transistor 21 along the direction X.

[0051] The display panel 100 provided by the above embodiment of the present application, by setting a dummy filling pattern 30 in the clearance area 2, the dummy filling pattern 30 is set in the source-drain conductive layer SD, so that the source-drain conductive layer SD forms a conductive pattern in both the IC area 1 and the clearance area 2. Based on this, in the process of etching the source-drain conductive layer SD, the area of ​​the source-drain conductive layer SD that needs to be etched and removed in the IC area 1 and the clearance area 2 is close, so that the consumption rate of the etching solution in the IC area 1 and the clearance area 2 is close, and the concentration of the etching solution in the IC area 1 and the clearance area 2 is close, ensuring that the concentration of the etching solution in the IC area 1 meets the etching requirements, so that the source-drain conductive layer SD is fully etched in the IC area 1, and the spacing area T1 is formed between the source S and the drain D of the transistor 21 through etching, so that the second active film layer ACT2 is etched through the spacing area T1 between the source S and the drain D, so that the second active film layer ACT2 is disconnected in the spacing area T1, and the conductor risk of the transistor 21 is reduced.

[0052] Figure 5 for Figure 1 The shown figure is a partial enlarged view of the display panel in the binding area.

[0053] like Figure 5 As shown, the display panel 100 further includes a plurality of connection lines L disposed in the IC region 1, a plurality of switch control signal lines (such as Figure 5 The switch control signal line SW1 and the switch control signal line SW2 shown in FIG. Figure 5 The detection signal line DO and the detection signal line DE shown in the figure).

[0054] The data line DL extends from the display area AA to the IC area 1 and is electrically connected to the drain D of the transistor 21 through a connection line L1. The source S of the transistor 21 is electrically connected to a detection signal line through another connection line L2. The gate G of the transistor 21 is electrically connected to a switch control signal line.

[0055] As described above, the source S and drain D of the transistor 21 and the virtual filling pattern 30 are all arranged in the source-drain conductive layer SD. In this case, the connecting line L is also arranged in the source-drain conductive layer SD, which can facilitate the connection between the connecting line L and the source S and drain D of the transistor 21.

[0056] Exemplarily, two adjacent data lines DL correspond to two adjacent transistors 21 in the IC region 1. Among the two adjacent transistors 21, the gate G of one transistor 21 is electrically connected to the switch control signal line SW1, and the source S is electrically connected to the detection signal line DO through the connection line L2. The gate G of the other transistor 21 is electrically connected to the switch control signal line SW2, and the source S is electrically connected to the detection signal line DE through the connection line L2.

[0057] Before binding the source driver IC, the transistor 21 is turned on by the switch control signal line SW1 and the switch control signal line SW2, and the data detection signal is transmitted to the plurality of data lines DL through the detection signal line DO and the detection signal line DE, and the data detection signal is used to drive the display panel 100 to display the detection screen. When the display panel 100 displays without problems, the source driver IC is bound to the display panel 100, thereby optimizing the manufacturing process.

[0058] After the source driver IC is bound, the transistor 21 is controlled to be turned off through the switch control signal line SW1 and the switch control signal line SW2, and data signals are transmitted to the plurality of data lines DL through the source driver IC to drive the display panel 100 to display a normal picture.

[0059] In the above embodiment of the present application, the connection line L and the transistor 21 are provided in the IC region 1, and the source S and the drain D of the connection line L and the transistor 21 are both provided in the source-drain conductive layer SD. In this case, by providing a dummy filling pattern 30 in the clearance region 2, the dummy filling pattern 30 is provided in the source-drain conductive layer SD, and a conductive pattern located in the source-drain conductive layer SD is formed in both the IC region 1 and the clearance region 2.

[0060] Based on this, in the process of etching the source-drain conductive layer SD, the areas of the source-drain conductive layer SD that need to be etched and removed in the IC region 1 and the clearance region 2 are close, so that the consumption rates of the etching solution in the IC region 1 and the clearance region 2 are close, and the concentrations of the etching solution in the IC region 1 and the clearance region 2 are close, ensuring that the concentration of the etching solution in the IC region 1 meets the etching requirements, so that the source-drain conductive layer SD is fully etched in the IC region 1, and a spacing region T1 is formed between the source S and the drain D of the transistor 21 through etching, so that the second active film layer ACT2 is etched through the spacing region T1 between the source S and the drain D, so that the second active film layer ACT2 is disconnected in the spacing region T1, thereby reducing the risk of conductorization of the transistor 21.

[0061] In some embodiments, Figure 5As shown, in the IC region 1, a plurality of connection lines L are arranged at intervals along the direction X. In addition, the virtual filling pattern 30 also includes a plurality of virtual connection lines 301, and the plurality of virtual connection lines 301 are arranged at intervals along the direction X. The width of the virtual connection line 301 is equal to the width of the connection line L, and the spacing between two adjacent virtual connection lines 301 is equal to the spacing between two adjacent connection lines L. It can be understood that the virtual connection line 301 has the same pattern as the connection line L and the same routing design.

[0062] Based on this, in the process of etching the source-drain conductive layer SD, the areas of the source-drain conductive layer SD that need to be etched and removed in the IC region 1 and the clearance region 2 are roughly equal, so that the consumption rates of the etching solution in the IC region 1 and the clearance region 2 are roughly equal, and the concentrations of the etching solution in the IC region 1 and the clearance region 2 are roughly equal, ensuring that the concentration of the etching solution in the IC region 1 meets the etching requirements, so that the source-drain conductive layer SD is fully etched in the IC region 1, and a spacing region T1 is formed between the source S and the drain D of the transistor 21 through etching, so that the second active film layer ACT2 is etched through the spacing region T1 between the source S and the drain D, so that the second active film layer ACT2 is disconnected in the spacing region T1, thereby reducing the risk of conductorization of the transistor 21.

[0063] In some embodiments, Figure 5 As shown, the binding area BA includes a first IC area 1a, a clearance area 2 and a second IC area 1b arranged in sequence along a direction X, and the detection signal line DO and the detection signal line DE extend from the first IC area 1a through the clearance area 2 to the second IC area 1b respectively.

[0064] In the first IC region 1a, multiple transistors 21 include a first transistor 2101 closest to the clearance region 2, and in the second IC region 1b, multiple transistors 21 include a second transistor 2102 closest to the clearance region 2, and the first transistor 2101 and the second transistor 2102 are electrically connected to the same detection signal line (for example, detection signal line DE).

[0065] As mentioned above, transistors close to the clearance area are prone to conductorization problems. If the first transistor 2101 and the second transistor 2102 are conductorized, the data signal on the data line DL corresponding to the first IC area 1a will leak through the first transistor 2101 to the detection signal line DE, and leak through the detection signal line DE to the second transistor 2102, and leak through the second transistor 2102 to the data line DL corresponding to the second IC area 1b, causing signal crosstalk.

[0066] For example, a data signal displaying a black picture is transmitted on the data line DL corresponding to the first IC area 1a, and a data signal displaying a white picture is transmitted on the data line DL corresponding to the second IC area 1b. If the first transistor 2101 and the second transistor 2102 are both conductive, the data signal displaying a black picture will leak from the first IC area 1a to the second IC area 1b, causing a "black line" to appear in the white picture displayed in the portion where the display area AA is electrically connected to the second IC area 1b.

[0067] In the above embodiment of the present application, by setting the virtual filling pattern 30 in the clearance area 2, the risk of conductorization of the first transistor 2101 and the second transistor 2102 is reduced, thereby avoiding the problem of signal crosstalk and improving the display quality of the display panel 100.

[0068] In the display panel 100 , in addition to the binding area BA, there are also clearance areas SD in other areas, for example, a peripheral area BB on one side of the display area AA.

[0069] Figure 6 for Figure 1 The shown figure is a partial enlarged view of the display panel at position N.

[0070] like Figure 6 As shown, in the display area AA, the source and drain of the transistor T of the plurality of data lines DL and the pixel driving circuit are all arranged in the source-drain conductive layer SD. If there is also a clearance area in the peripheral area BB on one side of the display area AA, the transistor T near the peripheral area BB in the display area AA will also be made conductive. Based on this, a dummy filling pattern 30 is arranged in the peripheral area BB, and the dummy filling pattern 30 is also arranged in the source-drain conductive layer SD. Conductive patterns located in the source-drain conductive layer SD are formed in both the display area AA and the peripheral area BB.

[0071] Based on this, in the process of etching the source-drain conductive layer SD, the areas of the source-drain conductive layer SD that need to be etched and removed in the display area AA and the peripheral area BB are close, so that the consumption rates of the etching solution in the display area AA and the peripheral area BB are close, and the concentrations of the etching solution in the display area AA and the peripheral area BB are close, ensuring that the concentration of the etching solution in the display area AA meets the etching requirements, so that the source-drain conductive layer SD is fully etched in the display area AA, and a spacing area T1 is formed between the source S and the drain D of the transistor T through etching, so that the second active film layer ACT2 is etched through the spacing area T1 between the source S and the drain D, so that the second active film layer ACT2 is disconnected in the spacing area T1, thereby reducing the risk of conductorization of the transistor T.

[0072] In some embodiments, Figure 6As shown, the peripheral area BB includes a first sub-peripheral area BB1 and a second sub-peripheral area BB2, the first sub-peripheral area BB1 is located on two opposite sides of the display area AA along the direction X, and the second sub-peripheral area BB2 is located on two opposite sides of the display area AA along the direction Y. A plurality of data lines DL extend from the display area AA to the second sub-peripheral area BB2, and the dummy filling pattern 30 is disposed in the first sub-peripheral area BB1.

[0073] It can be understood that in the related technology, multiple data lines extend from the display area to the second sub-peripheral area, and the data lines are located in the source and drain conductive layer, that is, a conductive pattern located in the source and drain conductive layer is arranged in the second sub-peripheral area, while a conductive pattern located in the source and drain conductive layer is not arranged in the first sub-peripheral area, and the first sub-peripheral area is an SD clearance area.

[0074] In order to avoid the conductorization of transistors near the first sub-peripheral area in the display area, in the above-mentioned embodiment of the present application, a virtual filling pattern 30 is set in the first sub-peripheral area BB1, and the virtual filling pattern 30 is set in the source and drain conductive layer SD, and a conductive pattern located in the source and drain conductive layer SD is formed in the display area AA, the first sub-peripheral area BB1 and the second sub-peripheral area BB2.

[0075] Based on this, in the process of etching the source-drain conductive layer SD, the areas of the source-drain conductive layer SD that need to be etched and removed in the display area AA, the first sub-peripheral area BB1, and the second sub-peripheral area BB2 are close, so that the consumption rates of the etching solution in the display area AA, the first sub-peripheral area BB1, and the second sub-peripheral area BB2 are close, and the concentrations of the etching solution in the display area AA, the first sub-peripheral area BB1, and the second sub-peripheral area BB2 are close, ensuring that the concentration of the etching solution in the display area AA meets the etching requirements, so that the source-drain conductive layer SD is fully etched in the display area AA, and a spacing area T1 is formed between the source S and the drain D of the transistor T through etching, so that the second active film layer ACT2 is etched through the spacing area T1 between the source S and the drain D, so that the second active film layer ACT2 is disconnected in the spacing area T1, thereby reducing the risk of conductorization of the transistor T.

[0076] In addition, according to the above, an electrostatic ring circuit 11 is also provided in the peripheral area BB, and the electrostatic ring circuit 11 includes a plurality of diodes 12. Figure 7 for Figure 1 The partial enlarged view of the display panel at position O is shown. Figure 8 for Figure 7 The display panel is shown in a partial cross-sectional view along the section line BB'.

[0077] like Figure 7 and Figure 8As shown, the diode 12 includes a first auxiliary electrode 1101 and a second auxiliary electrode 1102 disposed on the gate conductive layer Gate, a first conductive type layer 1201 and a second conductive type layer 1202 disposed on the first active film layer ACT1, a portion disposed on the second active film layer ACT2, and a first electrode 221, a second electrode 222, and a connecting electrode 223 disposed on the source-drain conductive layer SD. The first electrode 221 is electrically connected to the first auxiliary electrode 1101 and is electrically connected to the first conductive type layer 1201, respectively, the connecting electrode 223 is electrically connected to the first conductive type layer 1201 and the second conductive type layer 1202, and the second electrode 222 is electrically connected to the second auxiliary electrode 1102 and is electrically connected to the second conductive type layer 1202, respectively.

[0078] Exemplarily, the first conductive type layer 1201 is of P type conductive type, and the second conductive type layer 1202 is of N type conductive type. Through the above connection relationship, a PN junction of the diode 12 is formed between the first electrode 221 and the second electrode 222, thereby controlling the current to be unidirectionally conducted.

[0079] like Figure 7 and Figure 8 As shown, the first electrode 221, the connecting electrode 223 and the second electrode 222 are arranged in sequence along the direction X, a first spacing region T11 is provided between the first electrode 221 and the connecting electrode 223, and a second spacing region T12 is provided between the connecting electrode 223 and the second electrode 222. In the direction X, the portion of the diode 12 arranged in the second active film layer ACT2 is disconnected in the first spacing region T11 and the second spacing region T12.

[0080] The display panel 100 further includes a dummy filling pattern 30 . The dummy filling pattern 30 is also disposed in the source-drain conductive layer SD. The dummy filling pattern 30 is disposed on at least one side of the diode 12 along a direction parallel to the substrate 10 .

[0081] In the above-mentioned embodiments of the present application, the first electrode 221, the second electrode 222 and the connecting electrode 223 of the diode 12 are arranged in the source-drain conductive layer SD, and a virtual filling pattern 30 is arranged on one side of the diode 12, and the virtual filling pattern 30 is also arranged in the source-drain conductive layer SD, so that the source-drain conductive layer SD forms a conductive pattern on the diode 12 and its periphery.

[0082] Based on this, in the process of etching the source-drain conductive layer SD, it can be ensured that the first electrode 221, the connecting electrode 223 and the second electrode 222 are disconnected to form the first spacing area T11 and the second spacing area T12, and it can be ensured that the second active film layer ACT2 is disconnected in the first spacing area T11 and the second spacing area T12, thereby reducing the risk of conductorization of the diode 12.

[0083] Exemplarily, the dummy filling pattern 30 is disposed in the peripheral region BB and is located around the diode 12 . Since the distribution of the diodes 12 in the electrostatic ring circuit 11 is relatively dispersed, and some of the diodes 12 are in an island state, according to the foregoing, in order to avoid the problem of the diode 12 being conductive due to the uneven distribution of the etching solution concentration during the etching process, the embodiment of the present application sets a virtual filling pattern 30 around the diode 12. Based on this, in the process of forming the display panel 100, in order to form the virtual filling pattern 30, the etching area of ​​the area is reduced, the etching solution requirement is reduced, and the etching difference between different areas is avoided, so that the concentration of the etching solution can be made more uniform, and the etching effect can be closer to the design requirements. That is, in the process of forming the diode 12, the etching rate of each diode 12 is similar, and the second active film layer ACT2 in the first spacing area T11 and the second spacing area T12 are completely disconnected, which can ensure that the PN junction between the first electrode 221 and the second electrode 222 functions normally and there is no leakage problem between the two electrodes, thereby avoiding the conductor of the diode 12, preventing the electrostatic current from damaging the electronic components on the display panel 100, and improving the product reliability.

[0084] On the other hand, the present application also provides a display device 200, such as Fig. 9 As shown, Fig. 9 The display device 200 includes the display panel 100 and the controller 300 mentioned in any embodiment of the first aspect, wherein the controller 300 is electrically connected to the display panel 100, and is used to control the display panel 100 to display an image.

[0085] Exemplarily, the display device 200 may be an electronic paper display device or an LCD display device.

[0086] In the display panel 100 of the above-mentioned display device 200, a dummy filling pattern 30 is set in the clearance area, and the source S and drain D of the semiconductor device, as well as the dummy filling pattern 30, are all set in the source-drain conductive layer SD. Based on this, in the process of etching the source-drain conductive layer SD, the area of ​​the source-drain conductive layer SD that needs to be etched and removed in the clearance area of ​​the semiconductor device area and its periphery is close, so that the consumption rate of the etching solution in different areas is close, and the concentration of the etching solution in different areas is close, ensuring that the concentration of the etching solution in the semiconductor device area meets the etching requirements, so that the source-drain conductive layer SD is fully etched in the semiconductor device area, and the spacing area T1 is formed by etching the two electrodes of the semiconductor device (for example, the source S and the drain D), so that the second active film layer ACT2 is etched through the spacing area T1 of the two electrodes (for example, the source S and the drain D), so that the second active film layer ACT2 is disconnected in the spacing area T1, thereby reducing the conductor risk of the semiconductor device.

[0087] The display device 200 described above may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether textual or . More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0088] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: It comprises a substrate, and a gate conductive layer, a first active film layer, a second active film layer and a source-drain conductive layer stacked on the substrate; The display panel further includes a semiconductor device and a dummy filling pattern, wherein the semiconductor device includes a portion disposed on the gate conductive layer, a portion disposed on the first active film layer, a portion disposed on the second active film layer, and a first electrode and a second electrode disposed on the source-drain conductive layer, and along a first direction parallel to the substrate, a spacing region is provided between the first electrode and the second electrode; in the first direction, the portion of the semiconductor device disposed on the second active film layer is disconnected in the spacing region; The dummy filling pattern is arranged on the source-drain conductive layer, and along a direction parallel to the substrate, the dummy filling pattern is arranged on at least one side of the semiconductor device.

2. The display panel according to claim 1, characterized in that: The semiconductor device comprises a transistor, wherein the transistor comprises a gate disposed on the gate conductive layer, an active layer disposed on the first active film layer, a portion disposed on the second active film layer, and a source electrode and a drain electrode disposed on the source-drain conductive layer; Along the first direction, there is the spacing region between the source and the drain; In the first direction, a portion of the transistor disposed in the second active film layer is disconnected in the spacing region.

3. The display panel according to claim 2, characterized in that: The display panel includes a display area and a binding area located at one side of the display area, wherein the binding area includes an IC area and a clearance area arranged along a second direction, wherein the second direction is parallel to the substrate and parallel to a boundary of the binding area close to the display area; The display panel further comprises a plurality of data lines arranged in the display area, a plurality of transistors, a plurality of connection lines, a plurality of switch control signal lines and a plurality of detection signal lines arranged in the IC area; the data line extends from the display area to the IC area and is electrically connected to the drain of the transistor through a connection line; the source of the transistor is electrically connected to one of the detection signal lines through another connection line; the gate of the transistor is electrically connected to one of the switch control signal lines; The connecting line, the source and drain of the transistor, and the dummy filling pattern are all arranged in the source-drain conductive layer, and the dummy filling pattern is arranged in the clearance area.

4. The display panel according to claim 3, characterized in that: The virtual filling pattern includes a plurality of virtual connection lines, and the plurality of virtual connection lines are arranged at intervals along the second direction; Along the second direction, a plurality of the connecting lines are arranged at intervals; The width of the virtual connection line is equal to the width of the connection line, and the distance between two adjacent virtual connection lines is equal to the distance between two adjacent connection lines.

5. The display panel according to claim 3, characterized in that: The binding area includes a first IC area, the clearance area, and a second IC area sequentially arranged along the second direction, and along the second direction, the plurality of detection signal lines extend from the first IC area, through the clearance area, to the second IC area respectively; In the first IC region, the plurality of transistors include a first transistor closest to the clearance region; In the second IC region, the plurality of transistors include a second transistor that is closest to the clearance region; and the first transistor and the second transistor are electrically connected to the same detection signal line.

6. The display panel according to any one of claims 2 to 5, characterized in that: The display panel includes a display area and a peripheral area located on at least one side of the display area; The display panel further comprises a plurality of sub-pixels, a plurality of gate lines and a plurality of data lines arranged in the display area, the plurality of sub-pixels comprising a plurality of rows and a plurality of columns, the sub-pixels in each row being arranged along a third direction, the sub-pixels in each column being arranged along a fourth direction, the third direction intersecting the fourth direction and being parallel to the substrate respectively; the gate line extending along the third direction, the data line extending along the fourth direction, each sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising the transistor, the gate of the transistor being electrically connected to the gate line, and the source or drain of the transistor being electrically connected to the data line; The data line, the source and drain of the transistor, and the dummy filling pattern are all arranged in the source-drain conductive layer, and the dummy filling pattern is arranged in the peripheral area.

7. The display panel according to claim 6, characterized in that: The peripheral area includes a first sub-peripheral area and a second sub-peripheral area, the first sub-peripheral area is located at two opposite sides of the display area along the third direction, and the second sub-peripheral area is located at two opposite sides of the display area along the fourth direction; The plurality of data lines extend from the display area to the second sub-peripheral area, and the dummy filling pattern is disposed in the first sub-peripheral area.

8. The display panel according to claim 1, characterized in that: The semiconductor device includes a diode, and the diode includes a first auxiliary electrode and a second auxiliary electrode arranged on the gate conductive layer, a first conductive type layer and a second conductive type layer arranged on the first active film layer, a portion arranged on the second active film layer, and the first electrode, the second electrode and a connecting electrode arranged on the source and drain conductive layer; The first electrode is electrically connected to the first auxiliary electrode and is electrically connected to the first conductive type layer respectively; the connecting electrode is electrically connected to the first conductive type layer and the second conductive type layer; the second electrode is electrically connected to the second auxiliary electrode and is electrically connected to the second conductive type layer respectively; Along the first direction, the first electrode, the connecting electrode and the second electrode are arranged in sequence, with a first spacing region between the first electrode and the connecting electrode, and a second spacing region between the connecting electrode and the second electrode; in the first direction, a portion of the diode arranged in the second active film layer is disconnected in the first spacing region and the second spacing region.

9. The display panel according to claim 8, characterized in that: The display panel includes a display area and a peripheral area located on at least one side of the display area; The display panel further comprises a plurality of gate lines arranged in the display area, and an electrostatic ring circuit arranged in the peripheral area, wherein the electrostatic ring circuit comprises a plurality of the diodes; the gate lines extend from the display area to the peripheral area, and are electrically connected to the electrostatic ring circuit; The dummy filling pattern is arranged in the peripheral area and is located around the diode.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9; A controller is electrically connected to the display panel.

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