Array substrate and preparation method thereof, display panel and display device

Abstract

The invention relates to an array substrate and a preparation method thereof, a display panel and a display device, the array substrate comprises a substrate, a light shielding layer and an array layer, and the light shielding layer is arranged on one side of the substrate in the thickness direction of the light shielding layer; the array layer is arranged on the side, away from the substrate, of the shading layer in the thickness direction, the array layer comprises a spacing part and a plurality of transistors, each transistor comprises a first electrode, a second electrode and an active layer, and a first conductive part and a second conductive part are arranged on the two sides, in the thickness direction, of the spacing part; the first electrode is connected with the first conductive part, the second electrode is connected with the second conductive part, the two ends of the active layer are connected with the first conductive part and the second conductive part respectively, and the orthographic projection of the shading layer on the substrate covers the orthographic projection of the active layer on the substrate. The embodiment of the invention provides an array substrate and a preparation method thereof, a display panel and a display device, which can improve the overall light transmittance of a screen on the basis of forming shading protection for an active layer in a transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, the requirements for the light transmittance of display panels are becoming higher and higher.

[0003] Transparent organic light-emitting diode (OLED) display devices require that the materials constituting the substrate and electrodes are transparent materials, so that the transmittance reaches more than 85% when the device is turned off, and when it is turned on, the light emission can be observed from both sides. The key lies in the use of transparent electrodes and transparent transistors with high transmittance.

[0004] However, the active layers in transistors are mostly made of oxide materials. However, in actual processes, deep energy level defects in oxides cause oxide semiconductor devices to be sensitive to light, making them relatively poor in negative bias temperature and lighting environment tests. Therefore, they need to be designed to be shading, which leads to reduced transparency of the screen. Summary of the invention

[0005] The embodiments of the present invention provide an array substrate and a method for manufacturing the same, a display panel and a display device, which can improve the overall light transmittance of the screen on the basis of forming light shielding protection for an active layer in a transistor.

[0006] In the first aspect, an array substrate is proposed according to an embodiment of the present invention, comprising a substrate, a light-shielding layer and an array layer, wherein the light-shielding layer is arranged on one side of the substrate; the array layer is arranged on the side of the light-shielding layer away from the substrate in the thickness direction, the array layer comprises a spacer and a plurality of transistors, each transistor comprises a first electrode, a second electrode and an active layer, a first conductive portion and a second conductive portion are arranged on both sides of the spacer in the thickness direction of the substrate, the first electrode is connected to the first conductive portion and the second electrode is connected to the second conductive portion, two ends of the active layer are respectively connected to the first conductive portion and the second conductive portion, and an orthographic projection of the light-shielding layer on the substrate covers an orthographic projection of the active layer on the substrate.

[0007] According to one aspect of an embodiment of the present invention, the active layer includes a first extension portion, one end of the first extension portion in its extension direction is connected to the first conductive portion and the other end is connected to the second conductive portion, and an angle 0<α≤90° is formed between the extension direction of the first extension portion and a plane of the spacer portion close to the substrate;

[0008] Preferably, the first conductive portion is located on a side of the spacer close to the substrate in the thickness direction of the substrate and the second conductive portion is located on a side of the spacer away from the substrate;

[0009] Preferably, the angle between the extension direction of the first extension portion and the plane of the spacing portion close to the substrate is 90°.

[0010] Preferably, an orthographic projection of the first conductive portion on the substrate at least partially overlaps with an orthographic projection of the second conductive portion on the substrate.

[0011] According to one aspect of an embodiment of the present invention, the active layer includes a second extension portion, the second extension portion is arranged on a side of the second conductive portion away from the spacer portion and connected to an end of the first extension portion away from the first conductive portion, and the second extension portion covers a surface of the second conductive portion away from the substrate;

[0012] Preferably, the extension direction of the second extension portion is parallel to the plane where the substrate is located;

[0013] Preferably, the angle between the extending directions of the first extension portion and the second extension portion is 90°;

[0014] Preferably, the first extension portion and the second extension portion respectively include an oxide semiconductor layer;

[0015] Preferably, the first conductive part and the second conductive part both comprise transparent conductive material;

[0016] Preferably, the orthographic projection of the light shielding layer on the substrate covers the orthographic projections of the first extending portion and the second extending portion.

[0017] According to one aspect of an embodiment of the present invention, a transistor includes a first insulating layer and a control terminal, wherein the first insulating layer covers the active layer, the control terminal is arranged on a side of the first insulating layer away from the active layer, and an orthographic projection of the control terminal in a thickness direction covers at least a portion of the active layer;

[0018] Preferably, the transistor comprises a second insulating layer, which is arranged on a side of the control terminal away from the first insulating layer and covers the control terminal.

[0019] According to one aspect of an embodiment of the present invention, the control end includes a first part and a second part, the extension direction of the first part intersects with the plane where the substrate is located, and the second part is connected to an end of the first part away from the substrate and parallel to the plane where the substrate is located;

[0020] Preferably, an orthographic projection of the first portion in the extension direction of the second portion covers at least a portion of the active layer, and an orthographic projection of the second portion in the thickness direction covers at least a portion of the active layer.

[0021] According to one aspect of the embodiments of the present invention, the angle β between the first portion and the second portion is ≥ 90°;

[0022] Preferably, the angle between the first portion and the second portion is 90°;

[0023] Preferably, the first portion and the second portion comprise metal layers.

[0024] In a second aspect, a method for preparing an array substrate is provided according to an embodiment of the present invention, comprising:

[0025] Providing a substrate, forming a light-shielding material on the substrate and patterning it to obtain a light-shielding layer;

[0026] forming a first conductive layer on a side of the light shielding layer facing away from the substrate and patterning the layer to obtain a first conductive portion;

[0027] Forming an insulating material on a side of the first conductive portion away from the light shielding layer and patterning the insulating material to obtain a spacer and an opening surrounded by the spacer, wherein at least a portion of the first conductive portion is exposed at the opening;

[0028] A second conductive layer is formed on a side of the spacer away from the first conductive part and patterned to obtain a second conductive part, wherein the second conductive part and the first conductive part are arranged in a staggered layer;

[0029] An active material is formed in the opening and patterned to obtain an active layer corresponding to the light shielding layer, wherein two ends of the active layer are respectively connected to the first conductive part and the second conductive part;

[0030] A first pole and a second pole are respectively formed on the sides of the first conductive part and the second conductive part facing away from the substrate, the first pole is connected to the first conductive part, and the second pole is connected to the second conductive part.

[0031] According to one aspect of an embodiment of the present invention, the step of forming an active material in the opening and patterning it to obtain an active layer corresponding to the light shielding layer, wherein both ends of the active layer are respectively connected to the first conductive part and the second conductive part, comprises:

[0032] forming an active material on a side of the first conductive portion and the second conductive portion facing away from the substrate, wherein at least a portion of the active material is located in the opening;

[0033] The active material is etched to obtain a first extension portion connected to the first conductive portion in the opening and covering the side wall of the spacer portion, and a second extension portion located on a side of the second conductive portion away from the spacer portion. The first extension portion and the second extension portion together form an active layer.

[0034] In a third aspect, a display panel is provided according to an embodiment of the present invention, comprising the array substrate as described above.

[0035] In a fourth aspect, a display device is provided according to an embodiment of the present invention, comprising the display panel as described above.

[0036] The embodiments of the present invention provide an array substrate and a preparation method thereof, a display panel and a display device. By arranging a spacer in the array layer and arranging a first conductive portion and a second conductive portion on both sides of the spacer in the thickness direction, the two ends of the active layer in the transistor are respectively connected to the first conductive portion and the second conductive portion, so that the active layer is staggered in the thickness direction, thereby reducing the orthographic projection size in the thickness direction compared with the structure in the prior art, and reducing the length size of the corresponding shading layer at the same time. Therefore, on the basis of using the shading layer to complete the shading protection of the active layer, the length size of the shading layer is reduced, thereby reducing the influence of the shading layer on the light transmittance, improving the overall light transmittance of the display panel, and meeting higher light transmittance requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Features, advantages, and technical effects of exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.

[0038] Figure 1 is a structural schematic diagram of an array substrate according to an embodiment of the present invention;

[0039] Figure 2 is a structural schematic diagram of another array substrate according to an embodiment of the present invention;

[0040] Figure 3 is a flow chart of a method for preparing an array substrate according to an embodiment of the present invention;

[0041] Figure 4 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0042] Figure 5 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0043] Figure 6 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0044] Figure 7 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0045] Figure 8 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0046] Fig. 9 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0047] Fig.10 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0048] Fig.11 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0049] Fig.12 is a structural diagram of an array substrate during preparation of an embodiment of the present invention;

[0050] Fig.13 It is a structural diagram of the array substrate during the preparation process of an embodiment of the present invention.

[0051] Reference numerals:

[0052] 100-array substrate; 10-substrate; 20-light shielding layer; 30-array layer; 31-spacer; 32-transistor; 1-first electrode; 2-second electrode; 3-active layer; 4-first insulating layer; 5-control terminal; 6-second insulating layer; 40-first conductive part; 50-second conductive part;

[0053] 3a - first extension; 3b - second extension; 5a - first portion; 5b - second portion.

[0054] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0055] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention. In the drawings and the following description, at least part of the known structures and technologies are not shown in order to avoid unnecessary ambiguity of the present invention; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0056] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structures of the array substrate and its preparation method, display panel and display device of the present invention. In the description of the present invention, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0057] In order to better understand the present invention, Figures 1 to 13An array substrate and a manufacturing method thereof, a display panel and a display device according to embodiments of the present invention are described in detail.

[0058] See also Figure 1 According to an embodiment of the present invention, an array substrate 100 is proposed, comprising a substrate 10, a light shielding layer 20 and an array layer 30. The light shielding layer 20 is arranged on one side of the substrate 10 along its own thickness direction; the array layer 30 is arranged on the side of the light shielding layer 20 away from the substrate 10 in the thickness direction, the array layer 30 comprises a spacer 31 and a plurality of transistors 32, each transistor 32 comprises a first electrode 1, a second electrode 2 and an active layer 3, a first conductive portion 40 and a second conductive portion 50 are arranged on both sides of the spacer 31 in the thickness direction, the first electrode 1 is connected to the first conductive portion 40 and the second electrode 2 is connected to the second conductive portion 50, two ends of the active layer 3 are respectively connected to the first conductive portion 40 and the second conductive portion 50, and the orthographic projection of the light shielding layer 20 on the substrate 10 covers the orthographic projection of the active layer 3 on the substrate 10.

[0059] Optionally, a plurality of transistors 32 are provided in the array layer 30, and each transistor 32 is connected to a corresponding sub-pixel through an electrode, so as to drive sub-pixels of different colors to emit light, such as red, green and blue (RGB) light. When adjacent sub-pixels emit light and complete color mixing, an overall color display is obtained.

[0060] Optionally, the first electrode 1 in the transistor 32 may be a drain, the second electrode 2 may be a source, the transistor 32 may be electrically connected to the anode of the sub-pixel through the first electrode 1, thereby forming a conduction of the driving signal, and the active layer 3 in the transistor 32 may be an oxide semiconductor material layer, such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO) and indium gallium oxide (IGO), etc. The present application does not specifically limit the specific material of the active layer 3.

[0061] In this embodiment, the oxide material used in the active layer 3 is mainly considered. Due to deep energy level defects, the oxide semiconductor device is sensitive to light, and thus is relatively poor in the negative bias temperature and illumination environment test. Therefore, it is necessary to design a light shielding design for it, which leads to a reduction in the transparency of the screen. Based on the above considerations, the present application aims to reduce the projection range of the active layer 3 on the substrate 10, thereby reducing the size range of the corresponding light shielding layer 20. Finally, on the basis of meeting the light shielding requirements, the light shielding effect of the light shielding layer 20 on the light output is reduced, thereby improving the overall display transmittance.

[0062] Optionally, a spacer 31 is provided in the array layer 30, and the spacer 31 may be an inorganic material, such as SiOx or SiNx or a stack formed by SiOx and SiNx, or an organic material such as polyimide (PI) may be used. The present application does not specifically limit the specific material of the spacer 31, as long as it can form a certain supporting insulating effect on the active layer 3.

[0063] The two ends of the active layer 3 need to be connected to the first pole 1 and the second pole 2 respectively through the first conductive part 40 and the second conductive part 50. In this embodiment, the first conductive part 40 and the second conductive part 50 are arranged at the two ends of the spacer 31 in the thickness direction, that is, the first conductive part 40 and the second conductive part 50 are staggered, so that the connected active layer 3 forms a staggered connection, forming a certain angle change, and the positive projection of the active layer 3 on the substrate 10 is relatively reduced, and the corresponding coverage range of the shading layer 20 is also reduced, which ultimately reduces the shielding effect of the shading layer 20 on the light output, and improves the overall light transmittance.

[0064] Optionally, the first conductive part 40 and the second conductive part 50 can adopt transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The present application is not limited to this. It is sufficient to ensure the conduction of the current signal. The active layer 3 needs to ensure connection with the first conductive part 40 and the second conductive part 50 of different layers.

[0065] The present application does not impose any special restrictions on the specific size of the shading layer 20, and its size only needs to be aligned with the shadow range of the corresponding active layer 3 on the substrate 10 to ensure that the shading layer 20 can form a more sufficient shielding for the active layer 3 in the thickness direction, and form a more reliable shading protection for the active layer 3. Optionally, the shading layer 20 can be a highly absorptive or highly reflective material, such as inorganic metal, vinyl or other materials, and the present application does not impose any special restrictions on this.

[0066] The embodiment of the present invention provides an array substrate 100, by arranging a spacer 31 in the array layer 30 and arranging a first conductive portion 40 and a second conductive portion 50 on both sides of the spacer 31 in the thickness direction, connecting the two ends of the active layer 3 in the transistor 32 to the first conductive portion 40 and the second conductive portion 50 respectively, so that the active layer 3 is staggered in the thickness direction, thereby reducing the orthographic projection size in the thickness direction compared with the structure in the prior art, and reducing the length dimension of the corresponding shading layer 20. Therefore, on the basis of using the shading layer 20 to complete the shading protection of the active layer 3, the length dimension of the shading layer 20 is reduced, thereby reducing the influence of the shading layer 20 on the light transmittance, improving the overall light transmittance of the display panel, and meeting higher light transmittance requirements.

[0067] As an alternative embodiment, see Figure 2The active layer 3 includes a first extension portion 3a, one end of the first extension portion 3a in its own extension direction is connected to the first conductive portion 40 and the other end is connected to the second conductive portion 50, and the angle 0 between the extension direction of the first extension portion 3a and the plane of the spacer portion 31 on the side close to the substrate 10 is 0<α≤90°.

[0068] Optionally, the active layer 3 specifically includes a first extension portion 3a, which is attached to the side wall of the spacer portion 31 and has its two ends respectively connected to the first conductive portion 40 and the second conductive portion 50. The inclination angle of the first extension portion 3a can be adjusted to be within a predetermined range by adjusting the inclination degree of the side wall of the spacer portion 31.

[0069] The angle between the first extension portion 3a and the plane is set to the above-mentioned angle range, that is, the angle between the first extension portion 3a and the plane can be set to an acute angle or a right angle, so that the first extension portion 3a has a certain degree of inclination, thereby reducing the projection range of the first extension portion 3a on the substrate 10, and the corresponding size range of the light-shielding layer 20 is also reduced synchronously, thereby ultimately improving the overall light transmittance.

[0070] Optionally, the first conductive portion 40 is located on the side of the spacer 31 close to the substrate 10 in the thickness direction and the second conductive portion 50 is located on the side of the spacer 31 away from the substrate 10, and the angle between the extension direction of the first extension portion 3a and the plane of the spacer 31 close to the substrate 10 is 90°. At this time, the first extension portion 3a is a vertically upward extension structure, and the projection range formed on the substrate 10 is the smallest, and the corresponding size range of the shading layer 20 is also the smallest, which reduces the size of the shading layer 20 to the greatest extent and reduces its influence on the transmittance.

[0071] Optionally, an orthographic projection of the first conductive portion 40 on the substrate 10 at least partially overlaps with an orthographic projection of the second conductive portion 50 on the substrate 10 .

[0072] It can be understood that when the angle between the first extension portion 3a and the plane is gradually set from an acute angle to a right angle, its own projection area on the substrate 10 gradually decreases. When a right angle is formed, the minimum projection area is obtained, and the shading effect of the shading layer 20 is minimized.

[0073] An embodiment of the present invention provides an array substrate 100, by setting the angle between the first extension portion 3a and the plane to the above-mentioned angle range, the first extension portion 3a forms a certain inclination angle, thereby reducing its projection range on the substrate 10 and the corresponding range of the light-shielding layer 20, thereby improving the overall light transmittance to a certain extent. At the same time, the structure is also convenient for process molding, reducing the difficulty of process molding.

[0074] As an alternative embodiment, see Figure 2The active layer 3 includes a second extension portion 3b, which is arranged on a side of the second conductive portion 50 away from the spacer portion 31 and connected to an end of the first extension portion 3a away from the first conductive portion 40, and covers a surface of the second conductive portion 50 away from the substrate 10.

[0075] Optionally, the extension direction of the second extension portion 3b is parallel to the plane of the substrate 10, that is, the second extension portion 3b extends in the horizontal direction and intersects with the first extension portion 3a, so that the active layer 3 forms a two-part structure formed by the first extension portion 3a and the second extension portion 3b, which is different from the prior art in which the active layer 3 is completely horizontally set.

[0076] In this embodiment, the first extension portion 3a and the second extension portion 3b are arranged to intersect each other, and the overall orthographic projection on the substrate 10 is reduced, and the corresponding coverage area of ​​the light shielding layer 20 is also reduced, thereby achieving the purpose of improving the overall light transmittance.

[0077] Optionally, the angle between the extension directions of the first extension portion 3a and the second extension portion 3b is 90°, that is, the two are arranged vertically, wherein the first extension portion 3a is perpendicular to the horizontal direction, which reduces the overall projection area on the substrate 10 while facilitating process molding and having better structural stability.

[0078] Optionally, the first extension portion 3a and the second extension portion 3b respectively include oxide semiconductor layers, such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO) and indium gallium oxide (IGO), and the orthographic projection of the light-shielding layer 20 in the thickness direction covers the orthographic projection of the first extension portion 3a and the second extension portion 3b. At this time, the light-shielding layer 20 is used to completely block the light at the position of the first extension portion 3a and the second extension portion 3b, thereby forming a more sufficient light-shielding effect.

[0079] An embodiment of the present invention provides an array substrate 100, which reduces the extension length of the active layer 3 in the horizontal direction by setting the active layer 3 to a structural form in which the first extension portion 3a and the second extension portion 3b intersect, thereby reducing the projection length of the active layer 3 on the substrate 10, reducing the length of the corresponding shading layer 20, and improving the transmittance.

[0080] As an alternative embodiment, see Figure 2 The transistor 32 includes a first insulating layer 4 and a control terminal 5. The first insulating layer 4 covers the active layer 3. The control terminal 5 is arranged on a side of the first insulating layer 4 away from the active layer 3. The orthographic projection of the control terminal 5 in the thickness direction covers at least a portion of the active layer 3.

[0081] Optionally, the control terminal 5 can be the gate of the transistor 32. The active layer 3 is covered and insulated by the first insulating layer 4, and the control terminal 5 is then arranged on the first insulating layer 4 and corresponds to the active layer 3 to ensure normal conduction of the electrical signal. The transistor 32 as a whole forms a top gate structure.

[0082] Optionally, the transistor 32 includes a second insulating layer 6, which is arranged on the side of the control end 5 away from the first insulating layer 4 and covers the control end 5, and the first electrode 1 and the second electrode 2 pass through the first insulating layer 4 and the second insulating layer 6 to be connected to the first conductive part 40 and the second conductive part 50 respectively, forming a complete transistor 32 structure.

[0083] An embodiment of the present invention provides an array substrate 100, which covers the active layer 3 with a first insulating layer 4 and sets the control terminal 5 corresponding to the active layer 3, and uses the control terminal 5 to turn on and off the transistor 32, thereby reducing the influence of the shading layer 20 on the transmittance and ensuring effective control of the transistor 32.

[0084] As an alternative embodiment, see Figure 2 The control end 5 includes a first part 5a and a second part 5b. The extension direction of the first part 5a intersects with the plane where the substrate 10 is located. The second part 5b is connected to an end of the first part 5a away from the substrate 10 and is parallel to the plane where the substrate 10 is located.

[0085] Optionally, the orthographic projection of the first part 5a in the extension direction of the second part 5b covers at least part of the active layer 3, and the orthographic projection of the second part 5b in the thickness direction covers at least part of the active layer 3. That is, when the active layer 3 has a first extension portion 3a and a second extension portion 3b extending in two directions, in order to ensure that the control end 5 fully covers the active layer 3, the control end 5 can also be set to the first part 5a and the second part 5b, and the first part 5a and the second part 5b are respectively set corresponding to the first extension portion 3a and the second extension portion 3b.

[0086] In this embodiment, the first part 5a of the control terminal 5 covers the first extension part 3a of the active layer 3 in the horizontal direction, and the second part 5b covers the second extension part 3b in the vertical direction, so that the control terminal 5 as a whole forms a more sufficient coverage of the active layer 3 as a whole, ensuring the reliability of the control terminal 5 in turning on the transistor 32.

[0087] An embodiment of the present invention provides an array substrate 100, which fully ensures the normal conduction of the current signal by setting the control end 5 as a first part 5a and a second part 5b, and respectively using the first part 5a and the second part 5b to correspond to the first extension part 3a and the second extension part 3b of the active layer 3 to match the bending structure of the active layer 3, thereby meeting the structural characteristics of the active layer 3.

[0088] As an optional embodiment, please refer to 2, the angle β between the first part 5a and the second part 5b is ≥90°.

[0089] When an obtuse angle is formed between the first extension portion 3a and the second extension portion 3b of the active layer 3, the extension length of the active layer 3 in the horizontal direction can be reduced, thereby reducing the length of the corresponding light-shielding layer 20. In this embodiment, in order to set the structure of the control end 5 corresponding to the active layer 3, an obtuse angle is also set between the first part 5a and the second part 5b of the control end 5, so that the first part 5a and the second part 5b can fully cover the first extension portion 3a and the second extension portion 3b.

[0090] Optionally, the angle between the first part 5a and the second part 5b is 90°. At this time, the control end 5 as a whole forms a right-angle structure, which is arranged corresponding to the right-angle structure of the active layer 3. The positive projection area of ​​the active layer 3 on the substrate 10 is minimized. At the same time, the overall structure is convenient for process forming and reduces the process difficulty. The present application does not make any special limitation on the specific angle formed by the control end 5, as long as it can match the structure of the active layer 3.

[0091] Optionally, the first part 5a and the second part 5b include a metal layer, for example, a material such as metal molybdenum may be used, and the present application is not limited to this.

[0092] An embodiment of the present invention provides an array substrate 100, which sets the angle of the control terminal 5 to the above angle to match the structure of the active layer 3, fully covers the structure of the active layer 3, achieves effective control of the transistor 32, and improves the reliability of driving the transistor 32.

[0093] See also Figure 3 According to an embodiment of the present invention, a method for preparing an array substrate 100 is provided, comprising:

[0094] S1, providing a substrate 10, forming a light shielding material on the substrate 10 and patterning it to obtain a light shielding layer 20;

[0095] S2, forming a first conductive layer on a side of the light shielding layer 20 facing away from the substrate 10 and patterning the layer to obtain a first conductive portion 40;

[0096] S3, forming an insulating material on a side of the first conductive portion 40 away from the light shielding layer 20 and patterning it to obtain a spacer 31 and an opening surrounded by the spacer 31, wherein at least a portion of the first conductive portion 40 is exposed at the opening;

[0097] S4, forming a second conductive layer on a side of the spacer 31 away from the first conductive part 40 and patterning it to obtain a second conductive part 50, wherein the second conductive part 50 and the first conductive part 40 are arranged in a staggered layer;

[0098] S5, forming an active material in the opening and patterning it to obtain an active layer 3 corresponding to the light shielding layer 20, wherein two ends of the active layer 3 are respectively connected to the first conductive portion 40 and the second conductive portion 50;

[0099] S6. Form a first pole 1 and a second pole 2 on the sides of the first conductive portion 40 and the second conductive portion 50 facing away from the substrate 10 , respectively. The first pole 1 is connected to the first conductive portion 40 , and the second pole 2 is connected to the second conductive portion 50 .

[0100] In step S1, see Figure 4 and Figure 5 , a light-shielding material can be formed on the substrate 10 by a vapor deposition process. The light-shielding material can be a highly absorptive or highly reflective material such as an inorganic metal or black glue. The entire layer of material is then patterned by an etching process to obtain mutually spaced light-shielding layers 20.

[0101] In step S2, see Figure 5 and Figure 6 , continue to deposit on the film layer to form a first conductive layer, the material of which may be a transparent conductive material, and then pattern it by etching to form a first conductive portion 40.

[0102] Then, in step S3, an insulating material is deposited on the first conductive portion 40, which may be an inorganic or organic material. After etching and patterning, the spacer 31 and the opening formed by the spacer 31 are obtained. At this time, part of the first conductive portion 40 is exposed in the opening, and the spacer 31 covers the edge of the first conductive portion 40. Figure 6 and Figure 7 shown.

[0103] In step S4, a second conductive layer is deposited on the existing film structure and etched to pattern it. The second conductive portion 50 obtained at this time is located above the spacer 31, so that the second conductive portion 50 and the first conductive portion 40 in the opening are arranged in a staggered manner. Figure 8 shown.

[0104] Step S5 is to shape the active layer 3, see Fig. 9 and Fig.10 Specifically, the active material continues to be deposited on the above-mentioned film layer structure. After etching, the retained active layer 3 is connected between the first conductive part 40 and the second conductive part 50. Affected by the spacer 31, the active layer 3 is not on the same horizontal plane at this time, but forms a certain bending angle. Under the effect of the bending, the projection length of the active layer 3 on the substrate 10 is reduced.

[0105] Optionally, a first insulating layer 4, a control terminal 5 and a second insulating layer 6 are subsequently deposited and patterned on the active layer 3, as shown in FIG. Figures 11 to 13 As shown, in step S6, the insulating layer is etched to form a via hole, exposing the first conductive portion 40 and the second conductive portion 50 at the via hole, and then deposition is continued to form the first electrode 1 at the first conductive portion 40 and the second electrode 2 at the second conductive portion 50, and after forming connections respectively, a complete transistor 32 structure is obtained.

[0106] As an optional embodiment, the steps of forming an active material in the opening and patterning it to obtain an active layer 3 corresponding to the light shielding layer 20, wherein both ends of the active layer 3 are respectively connected to the first conductive portion 40 and the second conductive portion 50, include:

[0107] An active material is formed on a side of the first conductive portion 40 and the second conductive portion 50 facing away from the substrate 10 , and at least a portion of the active material is located in the opening;

[0108] The active material is etched to obtain a first extension portion 3a connected to the first conductive portion 40 in the opening and covering the side wall of the spacer 31, and a second extension portion 3b is obtained, which is located on the side of the second conductive portion 50 away from the spacer 31. The first extension portion 3a and the second extension portion 3b together form an active layer 3.

[0109] In the present embodiment, an etching process is utilized to etch the active material deposited in the opening into a two-part structure of a first extension portion 3a and a second extension portion 3b. It is necessary to ensure that the first extension portion 3a is attached to the side surface of the spacer portion 31 and is connected to the first conductive portion 40, and that the second extension portion 3b is attached to the top surface of the second conductive portion 50 to form a connection, thereby obtaining an active layer 3 structure with a reduced horizontal length dimension.

[0110] According to an embodiment of the present invention, a display panel is provided, including the array substrate 100 as described above.

[0111] According to an embodiment of the present invention, a display device is provided, including the display panel as described above. Optionally, the display device can be any product involving OLED display, such as lighting, car lights, mobile phones, televisions, tablets, car displays, etc. The present application does not specifically limit the specific type of the display device.

[0112] The embodiments of the present invention provide an array substrate and a preparation method thereof, a display panel and a display device. By arranging a spacer in the array layer and arranging a first conductive portion and a second conductive portion on both sides of the spacer in the thickness direction, the two ends of the active layer in the transistor are respectively connected to the first conductive portion and the second conductive portion, so that the active layer is staggered in the thickness direction, thereby reducing the orthographic projection size in the thickness direction compared with the structure in the prior art, and reducing the length size of the corresponding shading layer at the same time. Therefore, on the basis of using the shading layer to complete the shading protection of the active layer, the length size of the shading layer is reduced, thereby reducing the influence of the shading layer on the light transmittance, improving the overall light transmittance of the display panel, and meeting higher light transmittance requirements.

[0113] Although the present invention has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A light shielding layer, disposed on one side of the substrate; An array layer is arranged on a side of the light-shielding layer away from the substrate in the direction of the substrate thickness, the array layer includes a spacer and a plurality of transistors, each of the transistors includes a first electrode, a second electrode and an active layer, the spacer is provided with a first conductive portion and a second conductive portion on both sides in the direction of the substrate thickness, the first electrode is connected to the first conductive portion and the second electrode is connected to the second conductive portion, two ends of the active layer are respectively connected to the first conductive portion and the second conductive portion, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the active layer on the substrate.

2. The array substrate according to claim 1, characterized in that: The active layer comprises a first extension portion, one end of the first extension portion in its extension direction is connected to the first conductive portion and the other end is connected to the second conductive portion, and an angle 0<α≤90° is formed between the extension direction of the first extension portion and a plane of the spacer portion close to the substrate; Preferably, the first conductive portion is located on a side of the spacer close to the substrate in the thickness direction of the substrate, and the second conductive portion is located on a side of the spacer away from the substrate; Preferably, the angle between the extension direction of the first extension portion and the plane of the spacer portion close to the substrate is 90°; Preferably, an orthographic projection of the first conductive portion on the substrate at least partially overlaps with an orthographic projection of the second conductive portion on the substrate.

3. The array substrate according to claim 2, characterized in that: The active layer includes a second extension portion, the second extension portion is arranged at a side of the second conductive portion away from the spacer and connected to an end of the first extension portion away from the first conductive portion, and the second extension portion covers a surface of the second conductive portion away from the substrate; Preferably, the extending direction of the second extending portion is parallel to the plane where the substrate is located; Preferably, the angle between the extending directions of the first extension portion and the second extension portion is 90°; Preferably, the first extension portion and the second extension portion both include an oxide semiconductor layer; Preferably, the first conductive part and the second conductive part both comprise transparent conductive material; Preferably, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projections of the first extending portion and the second extending portion on the substrate.

4. The array substrate according to claim 1, characterized in that: The transistor comprises a first insulating layer and a control terminal, wherein the first insulating layer covers the active layer, the control terminal is arranged on a side of the first insulating layer away from the active layer, and an orthographic projection of the control terminal in the thickness direction covers at least a portion of the active layer; Preferably, the transistor comprises a second insulating layer, and the second insulating layer is arranged on a side of the control end away from the first insulating layer and covers the control end.

5. The array substrate according to claim 4, characterized in that: The control end includes a first part and a second part, the extension direction of the first part intersects with the plane where the substrate is located, and the second part is connected to an end of the first part away from the substrate and is parallel to the plane where the substrate is located; Preferably, an orthographic projection of the first portion in the extension direction of the second portion covers at least a portion of the active layer, and an orthographic projection of the second portion in the thickness direction covers at least a portion of the active layer.

6. The array substrate according to claim 5, characterized in that: The angle β between the first part and the second part is ≥ 90°; Preferably, the angle between the first portion and the second portion is 90°; Preferably, the first portion and the second portion comprise metal layers.

7. A method for preparing an array substrate, characterized in that: include: providing a substrate, forming a light-shielding material on the substrate and patterning it to obtain a light-shielding layer; forming a first conductive layer on a side of the light shielding layer away from the substrate and patterning the layer to obtain a first conductive portion; Forming an insulating material on a side of the first conductive portion away from the light shielding layer and patterning the insulating material to obtain a spacer and an opening surrounded by the spacer, wherein at least a portion of the first conductive portion is exposed at the opening; Forming a second conductive layer on a side of the spacer away from the first conductive part and patterning the layer to obtain a second conductive part, wherein the second conductive part and the first conductive part are arranged in a staggered layer; forming an active material in the opening and patterning it to obtain an active layer corresponding to the light shielding layer, wherein two ends of the active layer are respectively connected to the first conductive part and the second conductive part; A first pole and a second pole are respectively formed on the side of the first conductive part and the second conductive part facing away from the substrate, wherein the first pole is connected to the first conductive part and the second pole is connected to the second conductive part.

8. The preparation method according to claim 7, characterized in that: The step of forming an active material in the opening and patterning it to obtain an active layer corresponding to the light shielding layer, wherein both ends of the active layer are respectively connected to the first conductive part and the second conductive part, comprises: forming the active material on a side of the first conductive portion and the second conductive portion facing away from the substrate, wherein at least a portion of the active material is located in the opening; The active material is etched to obtain a first extension portion connected to the first conductive portion in the opening and covering the side wall of the spacer portion, to obtain a second extension portion located on a side of the second conductive portion away from the spacer portion, and the first extension portion and the second extension portion together form the active layer.

9. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 6.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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