Complementary metal oxide semiconductor (CMOS) circuit based on fully amorphous oxide transistor and preparation method
By using all-amorphous oxide transistors in CMOS circuits, the problem that traditional CMOS technology cannot meet the flexibility and wearable needs is solved, and the possibility of preparing flexible base integrated circuits at low temperatures is realized, which improves manufacturability and reduces costs. .
Patent Information
- Application Number
- CN202510031407.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-02-14
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Due to its rigid preparation process, traditional silicon-based CMOS technology cannot meet the needs of flexible and wearable electronic chips, especially the lack of high-performance amorphous p-type oxides limits the development of CMOS technology based on oxide TFT.
The CMOS circuit using all-amorphous oxide transistors is used, and the possibility of preparing flexible substrate integrated circuits at low temperatures is realized by using amorphous oxide materials in both N-type and P-type transistors.
It realizes the preparation of flexible substrate integrated circuits at low temperatures, significantly improves device manufacturability, meets the needs of large-scale flexible electronic products, and reduces production costs, and is environmentally friendly and has excellent environmental stability.
Smart Images
Figure CN119451236A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of radio electronics, and in particular to a CMOS circuit based on a fully amorphous oxide transistor and a preparation method thereof. Background Art
[0002] Complementary metal oxide semiconductor technology (CMOS) is the mainstream technology in the current electronic chip field. With the rapid development of emerging information technologies such as artificial intelligence, the Internet of Things, and human-computer interaction, the demand for flexible and wearable electronic chips is increasing. However, traditional silicon-based CMOS technology can no longer meet these demands due to its rigid preparation process. Amorphous oxide thin-film transistors (TFTs) are electronic devices based on amorphous oxide semiconductor materials. Compared with traditional amorphous silicon-based TFTs, amorphous oxide TFTs have higher carrier mobility, better transparency, and lower manufacturing temperature, giving them significant advantages in flexible electronics and low-power devices.
[0003] At present, TFT technology based on amorphous n-type semiconductor indium gallium zinc oxide (IGZO) has been commercialized in the display field. However, due to the lack of high-performance amorphous p-type oxides, the development of CMOS technology based on oxide TFTs is limited. Therefore, the development of high-mobility, low-cost amorphous P-type TFTs and CMOS circuits has become a key direction to promote the development of new generation information display technology and flexible integrated circuits. The realization of on-chip integration of large-scale CMOS circuits of all-amorphous P-type oxides and N-type oxides has become a core issue that needs to be solved urgently. Summary of the invention
[0004] In order to solve the above problems, the present invention provides a CMOS circuit based on a fully amorphous oxide transistor and a preparation method thereof, wherein amorphous oxide is used in both N-type transistors and P-type transistors, thereby realizing a CMOS circuit of a fully amorphous oxide transistor.
[0005] On the one hand, the present invention provides a CMOS circuit based on a fully amorphous oxide transistor, the CMOS circuit comprising: a substrate, a bottom gate electrode and an interconnection layer, a gate dielectric layer, an N-type channel layer, a P-type channel layer, and a source-drain electrode and an interconnection layer, the N-type channel layer is an amorphous oxide semiconductor layer, the P-type channel layer is an amorphous doped tellurium oxide, and the bottom gate electrode and the interconnection layer and the source-drain electrode and the interconnection layer are all made of metal.
[0006] Furthermore, the substrate is one of silicon wafer, polyimide, polydimethylsiloxane, and polyethylene naphthalate.
[0007] Furthermore, the gate dielectric layer is one or more of aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride.
[0008] Furthermore, the amorphous oxide of the N-type channel layer is one or more of indium, gallium, zinc, tin, and titanium oxide.
[0009] Furthermore, the doping element in the amorphous doped tellurium oxide is one or more of selenium, antimony, phosphorus, sulfur, chlorine, iodine, and bismuth.
[0010] Furthermore, the metal used for the bottom gate electrode and interconnection layer and the source / drain electrode and interconnection layer is one or more of titanium, gold, aluminum, nickel, platinum, palladium, chromium, molybdenum, tungsten, copper, indium, and silver.
[0011] On the other hand, the present invention provides a method for preparing the above-mentioned CMOS circuit based on amorphous oxide transistors, the method comprising the following steps:
[0012] Step S1: using a clean silicon wafer or glass wafer or polyimide or polydimethylsiloxane or polyethylene naphthalate with a thermally oxidized SiO2 layer as a substrate;
[0013] Step S2: depositing a layer of metal on the substrate and patterning it to serve as a bottom gate electrode and an interconnection layer, wherein the thickness of the bottom gate electrode and the interconnection layer is 5 nm to 500 nm, and the deposition method includes thermal evaporation, magnetron sputtering, and electron beam evaporation;
[0014] Step S3: depositing and patterning a gate dielectric layer on the substrate after gate patterning in step S2, wherein the gate dielectric layer is one or more of aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride, with a thickness of 3 nm to 500 nm, and the deposition method includes atomic layer deposition, electron beam evaporation, thermal evaporation, and chemical vapor deposition;
[0015] Step S4: depositing an N-type amorphous oxide semiconductor layer on the sample on which the gate dielectric layer is patterned in step S3 and patterning the layer, wherein the N-type amorphous oxide is one or more of indium, gallium, zinc, tin, and titanium oxide, and the thickness of the N-type amorphous oxide semiconductor layer is 1 nm-100 nm, and the deposition method includes magnetron sputtering and atomic layer deposition;
[0016] Step S5: depositing a P-type amorphous oxide semiconductor layer on the sample completed in step S4 and patterning it, wherein the P-type amorphous oxide semiconductor layer is element-doped tellurium oxide, the doping element is one or more of selenium, antimony, phosphorus, sulfur, chlorine, iodine, and bismuth, the thickness of the P-type amorphous oxide semiconductor layer is 1nm-100nm, and the deposition method includes thermal evaporation;
[0017] Step S6: performing annealing treatment on the sample completed in step S5, the annealing atmosphere is air, nitrogen, or argon, the annealing temperature is 25° C.-400° C., and the annealing time is 0.5 hour-24 hours;
[0018] Step S7: depositing source-drain electrodes and interconnection layers on the sample annealed in step S6. The source-drain electrodes and interconnection layers are made of metal with a thickness of 5nm-500nm. The deposition methods include thermal evaporation, magnetron sputtering, and electron beam evaporation.
[0019] Furthermore, the metal in step S2 and step S7 is one or more of titanium, gold, aluminum, nickel, platinum, palladium, chromium, molybdenum, tungsten, copper, indium, and silver.
[0020] The present invention has the following beneficial technical effects:
[0021] The N-type transistor and the P-type transistor of the all-amorphous oxide transistor CMOS circuit provided by the present invention both use amorphous oxides. By adopting P-type and N-type amorphous oxides compatible with low-temperature processes, the possibility of preparing flexible substrate integrated circuits at low temperatures is realized, and the manufacturability of the device is significantly improved, which can meet the needs of large-scale flexible electronic products. In addition, the amorphous oxide semiconductor technology used is highly compatible with existing production processes, which is conducive to large-scale industrial applications and reducing production costs. At the same time, the use of amorphous oxide materials meets the requirements of green manufacturing, and is environmentally friendly and has excellent environmental stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 A schematic diagram of the structure of a fully amorphous oxide transistor CMOS circuit provided by an embodiment of the present invention;
[0024] Figure 2 This is a dynamic voltage input-output characteristic diagram of the all-amorphous oxide transistor CMOS circuit provided in Example 1 of the present invention.
[0025] Explanation of the reference numerals: 1-substrate, 2-bottom gate electrode and interconnection layer, 3-gate dielectric layer, 4-N-type transistor drain, 5-N-type oxide channel, 6-N-type transistor source and P-type transistor drain, 7-P-type oxide channel, 8-P-type oxide source. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0027] The present invention provides a CMOS circuit based on a fully amorphous oxide transistor and a preparation method thereof. Amorphous oxide is used in both N-type transistors and P-type transistors, thereby realizing a CMOS circuit of a fully amorphous oxide transistor.
[0028] In one aspect, the present invention provides a CMOS circuit based on a fully amorphous oxide transistor, wherein the structure of the CMOS circuit is as follows: Figure 1 As shown, it includes: a substrate, a bottom gate electrode and an interconnection layer, a gate dielectric layer, an N-type channel layer, a P-type channel layer, and a source-drain electrode and an interconnection layer. The N-type channel layer is an amorphous oxide semiconductor layer, the P-type channel layer is an amorphous doped tellurium oxide, and the bottom gate electrode and the interconnection layer and the source-drain electrode and the interconnection layer are all made of metal.
[0029] Preferably, the substrate is one of silicon wafer, polyimide, polydimethylsiloxane, and polyethylene naphthalate.
[0030] Preferably, the gate dielectric layer is one or more of aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride.
[0031] Preferably, the amorphous oxide of the N-type channel layer is one or more of indium, gallium, zinc, tin and titanium oxide.
[0032] Preferably, the doping element in the amorphous doped tellurium oxide is one or more of selenium, antimony, phosphorus, sulfur, chlorine, iodine and bismuth.
[0033] Preferably, the metal used for the bottom gate electrode and interconnection layer and the source / drain electrode and interconnection layer is one or more of titanium, gold, aluminum, nickel, platinum, palladium, chromium, molybdenum, tungsten, copper, indium, and silver.
[0034] On the other hand, the present invention provides a method for preparing the above-mentioned CMOS circuit based on amorphous oxide transistors, the method comprising the following steps:
[0035] Step S1: using a clean silicon wafer or glass wafer or polyimide or polydimethylsiloxane or polyethylene naphthalate with a thermally oxidized SiO2 layer as a substrate;
[0036] Step S2: depositing a layer of metal on the substrate and patterning it to serve as a bottom gate electrode and an interconnection layer, wherein the thickness of the bottom gate electrode and the interconnection layer is 5 nm to 500 nm, and the deposition method includes thermal evaporation, magnetron sputtering, and electron beam evaporation;
[0037] Step S3: depositing and patterning a gate dielectric layer on the substrate after gate patterning in step S2, wherein the gate dielectric layer is one or more of aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride, with a thickness of 3 nm to 500 nm, and the deposition method includes atomic layer deposition, electron beam evaporation, thermal evaporation, and chemical vapor deposition;
[0038] Step S4: depositing an N-type amorphous oxide semiconductor layer on the sample on which the gate dielectric layer is patterned in step S3 and patterning the layer, wherein the N-type amorphous oxide is one or more of indium, gallium, zinc, tin, and titanium oxide, and the thickness of the N-type amorphous oxide semiconductor layer is 1 nm-100 nm, and the deposition method includes magnetron sputtering and atomic layer deposition;
[0039] Step S5: depositing a P-type amorphous oxide semiconductor layer on the sample completed in step S4 and patterning it, wherein the P-type amorphous oxide semiconductor layer is element-doped tellurium oxide, the doping element is one or more of selenium, antimony, phosphorus, sulfur, chlorine, iodine, and bismuth, the thickness of the P-type amorphous oxide semiconductor layer is 1nm-100nm, and the deposition method includes thermal evaporation;
[0040] Step S6: performing annealing treatment on the sample completed in step S5, the annealing atmosphere is air, nitrogen, or argon, the annealing temperature is 25° C.-400° C., and the annealing time is 0.5 hour-24 hours;
[0041] Step S7: depositing source-drain electrodes and interconnection layers on the sample annealed in step S6. The source-drain electrodes and interconnection layers are made of metal with a thickness of 5nm-500nm. The deposition methods include thermal evaporation, magnetron sputtering, and electron beam evaporation.
[0042] Preferably, the metal in step S2 and step S7 is one or more of titanium, gold, aluminum, nickel, platinum, palladium, chromium, molybdenum, tungsten, copper, indium and silver.
[0043] Preferably, after patterning in step S3, inductively coupled plasma etching technology is used to etch away a portion of the gate dielectric layer to form a through hole.
[0044] In order to present and illustrate the specific technical effects, the present invention provides the following specific embodiments:
[0045] Example 1
[0046] (1) A cleaned silicon wafer with 300 nm thick silicon dioxide was used as a substrate, and 50 nm thick metal molybdenum was deposited on the substrate by magnetron sputtering as a bottom gate electrode and interconnect layer, and patterned by ultraviolet lithography;
[0047] (2) A 20 nm thick aluminum oxide film is deposited on the patterned bottom gate electrode as a gate dielectric layer using atomic layer deposition, and patterned using ultraviolet lithography. Then, the aluminum oxide film in a partial area is etched away using inductively coupled plasma etching technology to form a through hole;
[0048] (3) depositing 20 nm thick indium gallium zinc oxide on the above sample using magnetron sputtering technology and patterning it using ultraviolet lithography to form an N-type amorphous oxide semiconductor layer;
[0049] (4) depositing a 20 nm thick selenium-doped tellurium oxide on the sample using a thermal evaporation technique and patterning it using ultraviolet lithography to form a P-type amorphous oxide semiconductor layer;
[0050] (5) Annealing the sample at 225°C in air for two hours;
[0051] (6) A 50 nm thick layer of metal nickel was deposited on the above sample as source / drain electrodes and interconnect layer using thermal evaporation technology, and patterned using ultraviolet lithography.
[0052] Example 2
[0053] (1) A cleaned silicon wafer with 300 nm thick silicon dioxide was used as a substrate. A 5 nm thick titanium layer was deposited on the substrate by magnetron sputtering as a bottom gate electrode and interconnect layer, and patterned by ultraviolet lithography.
[0054] (2) A 3 nm thick silicon nitride film is deposited on the patterned bottom gate electrode as a gate dielectric layer using atomic layer deposition, and patterned using ultraviolet lithography. Then, the silicon nitride film in a partial area is etched away using inductively coupled plasma etching technology to form a through hole;
[0055] (3) depositing 1 nm thick indium gallium tin oxide on the above sample using magnetron sputtering technology and patterning it using ultraviolet lithography to form an N-type amorphous oxide semiconductor layer;
[0056] (4) depositing a 1 nm thick phosphorus-doped tellurium oxide on the sample using a thermal evaporation technique and patterning it using ultraviolet lithography to form a P-type amorphous oxide semiconductor layer;
[0057] (5) Annealing the above sample at 25°C in air for 24 hours;
[0058] (6) A 5 nm thick layer of metal nickel was deposited on the above sample as source / drain electrodes and interconnect layer using thermal evaporation technology, and patterned using ultraviolet lithography.
[0059] Example 3
[0060] (1) A cleaned silicon wafer with 300 nm thick silicon dioxide was used as a substrate, and 500 nm thick metal nickel was deposited on the substrate by magnetron sputtering as a bottom gate electrode and interconnect layer, and patterned by ultraviolet lithography;
[0061] (2) A 500 nm thick silicon oxide film is deposited on the patterned bottom gate electrode as a gate dielectric layer using atomic layer deposition, and patterned using ultraviolet lithography. Then, the silicon oxide film in a partial area is etched away using inductively coupled plasma etching technology to form a through hole;
[0062] (3) depositing a 100 nm thick indium gallium oxide on the above sample using magnetron sputtering technology and patterning it using ultraviolet lithography to form an N-type amorphous oxide semiconductor layer;
[0063] (4) Depositing a 100 nm thick sulfur-doped tellurium oxide on the above sample using a thermal evaporation technique and patterning it using ultraviolet lithography to form a P-type amorphous oxide semiconductor layer;
[0064] (5) Annealing the above sample at 150°C in air for 8 hours;
[0065] (6) A 500 nm thick layer of nickel was deposited on the sample as source / drain electrodes and interconnect layer using thermal evaporation technology, and patterned using UV lithography.
[0066] Example 4
[0067] (1) A cleaned silicon wafer with 300 nm thick silicon dioxide was used as a substrate, and a 100 nm thick metal nickel was deposited on the substrate by magnetron sputtering as a bottom gate electrode and interconnect layer, and patterned by ultraviolet lithography;
[0068] (2) A 200 nm thick silicon oxide film is deposited on the patterned bottom gate electrode as a gate dielectric layer using atomic layer deposition, and patterned using ultraviolet lithography. Then, the silicon oxide film in a partial area is etched away using inductively coupled plasma etching technology to form a through hole;
[0069] (3) depositing a 50 nm thick indium gallium oxide on the sample using magnetron sputtering technology and patterning it using ultraviolet lithography to form an N-type amorphous oxide semiconductor layer;
[0070] (4) Depositing a 50 nm thick antimony-doped tellurium oxide on the above sample using a thermal evaporation technique and patterning it using ultraviolet lithography to form a P-type amorphous oxide semiconductor layer;
[0071] (5) Annealing the above sample at 400°C in air for 0.5 hour;
[0072] (6) A 200 nm thick layer of nickel was deposited on the sample as source / drain electrodes and interconnect layer using thermal evaporation technology, and patterned using UV lithography.
[0073] Figure 2 The dynamic voltage input-output characteristic diagram of the CMOS circuit based on amorphous P-type and N-type oxide thin film transistors prepared by the steps of Example 1 is shown. The CMOS inversion circuit successfully achieves inversion output at an input signal frequency of 1 kHz, and the output signal delay is maintained at the microsecond level, realizing the preparation of low-cost all-amorphous oxide CMOS circuits at low temperatures.
[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A CMOS circuit based on a fully amorphous oxide transistor, characterized in that: The CMOS circuit comprises: a substrate, a bottom gate electrode and an interconnection layer, a gate dielectric layer, an N-type channel layer, a P-type channel layer, and a source-drain electrode and an interconnection layer. The N-type channel layer is an amorphous oxide semiconductor layer, the P-type channel layer is an amorphous doped tellurium oxide, and the bottom gate electrode and the interconnection layer and the source-drain electrode and the interconnection layer are all made of metal.
2. The CMOS circuit based on a fully amorphous oxide transistor according to claim 1, characterized in that: The substrate is one of silicon wafer, polyimide, polydimethylsiloxane and polyethylene naphthalate.
3. The CMOS circuit based on a fully amorphous oxide transistor according to claim 1, characterized in that: The gate dielectric layer is one or more of aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride.
4. The CMOS circuit based on a fully amorphous oxide transistor according to claim 1, characterized in that: The amorphous oxide of the N-type channel layer is one or more of indium, gallium, zinc, tin and titanium oxide.
5. The CMOS circuit based on a fully amorphous oxide transistor according to claim 1, characterized in that: The doping elements in the amorphous doped tellurium oxide are one or more of selenium, antimony, phosphorus, sulfur, chlorine, iodine and bismuth.
6. The CMOS circuit based on a fully amorphous oxide transistor according to claim 1, characterized in that: The metals used for the bottom gate electrode and interconnection layer and the source-drain electrode and interconnection layer are one or more of titanium, gold, aluminum, nickel, platinum, palladium, chromium, molybdenum, tungsten, copper, indium, and silver.
7. A method for preparing a CMOS circuit based on a fully amorphous oxide transistor according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: Step S1: using a clean silicon wafer or glass wafer or polyimide or polydimethylsiloxane or polyethylene naphthalate with a thermally oxidized SiO2 layer as a substrate; Step S2: depositing a layer of metal on the substrate and patterning it to serve as a bottom gate electrode and an interconnection layer, wherein the thickness of the bottom gate electrode and the interconnection layer is 5 nm to 500 nm, and the deposition method includes thermal evaporation, magnetron sputtering, and electron beam evaporation; Step S3: depositing and patterning a gate dielectric layer on the substrate after gate patterning in step S2, wherein the gate dielectric layer is one or more of aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride, with a thickness of 3 nm to 500 nm, and the deposition method includes atomic layer deposition, electron beam evaporation, thermal evaporation, and chemical vapor deposition; Step S4: depositing an N-type amorphous oxide semiconductor layer on the sample on which the gate dielectric layer is patterned in step S3 and patterning the layer, wherein the N-type amorphous oxide is one or more of indium, gallium, zinc, tin, and titanium oxide, and the thickness of the N-type amorphous oxide semiconductor layer is 1 nm-100 nm, and the deposition method includes magnetron sputtering and atomic layer deposition; Step S5: depositing a P-type amorphous oxide semiconductor layer on the sample completed in step S4 and patterning it, wherein the P-type amorphous oxide semiconductor layer is element-doped tellurium oxide, the doping element is one or more of selenium, antimony, phosphorus, sulfur, chlorine, iodine, and bismuth, the thickness of the P-type amorphous oxide semiconductor layer is 1nm-100nm, and the deposition method includes thermal evaporation; Step S6: performing annealing treatment on the sample completed in step S5, the annealing atmosphere is air, nitrogen, or argon, the annealing temperature is 25° C.-400° C., and the annealing time is 0.5 hour-24 hours; Step S7: depositing source-drain electrodes and interconnection layers on the sample annealed in step S6. The source-drain electrodes and interconnection layers are made of metal with a thickness of 5nm-500nm. The deposition methods include thermal evaporation, magnetron sputtering, and electron beam evaporation.
8. The preparation method according to claim 7, characterized in that: The metal in step S2 and step S7 is one or more of titanium, gold, aluminum, nickel, platinum, palladium, chromium, molybdenum, tungsten, copper, indium, and silver.