A combined passivation back contact battery and its post-texturing preparation method

Abstract

The present invention belongs to the technical field of back contact battery, and specifically relates to a combined passivation back contact battery and a post-texturing preparation method thereof, comprising: S102, forming a first semiconductor layer and a mask layer on the back of a silicon substrate in sequence; S103, performing cleaning and texturing to form a texturing surface on the light-receiving surface of the silicon substrate, and the maximum pyramid height of the texturing surface on the light-receiving surface is T1; S104, sequentially forming a passivation layer and an anti-reflection layer on the light-receiving surface of the silicon substrate; S105, forming a second semiconductor opening area; S106, performing cleaning and etching to form a groove structure at least in the second semiconductor opening area on the back of the silicon substrate; S107, depositing a second semiconductor layer on the back, the second semiconductor layer comprising an amorphous passivation layer and a second doped silicon layer. The present invention can reduce the interface contact resistance of the second semiconductor opening area, improve the minority carrier lifetime, and improve the battery efficiency and bifaciality while simplifying the process steps and reducing the material cost.

Description

Technical Field

[0001] The invention belongs to the technical field of back contact batteries, and in particular relates to a combined passivation back contact battery and a post-texturing preparation method thereof. Background Art

[0002] At present, the combined passivation back contact cell has a cell performance superior to that of the conventional heterojunction back contact cell. It is prepared by a post-texturing method with production advantages: the first etching is performed after the first semiconductor layer and the mask layer are formed to form a second semiconductor opening area; then texturing cleaning is performed; then a passivation layer and an anti-reflection layer are formed on the light-receiving surface of the silicon substrate; then single-sided etching is performed to remove the plating layer formed on the back of the silicon substrate during the deposition of the light-receiving surface, and the single-sided etching uses hydrofluoric acid or a weak alkaline solution; then conventional RCA cleaning is performed to make the interface cleanliness of the second semiconductor opening area on the back of the silicon substrate meet the requirements for depositing the second semiconductor layer; then the second semiconductor layer is deposited on the back.

[0003] However, the above-mentioned post-texturing method has the following problems:

[0004] ① After the passivation layer and anti-reflection layer are formed on the light-receiving surface of the silicon substrate, there is serious wrap-around plating on the back of the silicon substrate. It is necessary to remove the back wrap-around plating layer before texturing or cleaning, which increases the process steps;

[0005] ② After the laser engraving opening, there is some damage on the back of the silicon substrate, which requires a large amount of etching to completely remove it. However, there is no damage layer on the light-receiving surface of the silicon substrate. Therefore, the simultaneous texturing of the light-receiving surface and the back increases the etching amount of the light-receiving surface of the silicon substrate, thereby increasing the material cost.

[0006] ③ The simultaneous texturing of the light-receiving surface and the back side of the silicon substrate cannot independently control the surface morphology of the light-receiving surface and the back side opening area of ​​the silicon substrate, which is not conducive to improving the battery efficiency;

[0007] ④ RCA is used to clean the second semiconductor opening area. RCA cleaning is relatively gentle and has almost no etching amount. However, the interface of the second semiconductor opening area of ​​the silicon substrate has been processed by forming a passivation layer and an anti-reflection layer and a single-sided etching process after texturing and cleaning. The interface of the second semiconductor opening area is seriously contaminated, which is difficult to clean with RCA, affecting the passivation and contact performance of the interface, thereby affecting the battery efficiency.

[0008] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0009] The purpose of the present invention is to overcome the defects of the prior art combined passivation back contact battery post-texturing method, such as complicated process steps, high cost, and the need to improve battery efficiency and production yield, and to provide a combined passivation back contact battery and its post-texturing preparation method, which can reduce the interface contact resistance of the second semiconductor opening area while simplifying the process steps and reducing material costs, thereby improving the minority carrier lifetime, battery efficiency and bifaciality.

[0010] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a post-texturing preparation method for a combined passivation back contact battery, comprising the following steps:

[0011] S101, providing a double-sided polished silicon substrate;

[0012] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon substrate; the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer;

[0013] S103, performing cleaning and texturing to form a texturing surface on the light-receiving surface of the silicon substrate, wherein the maximum height of the pyramid of the texturing surface on the light-receiving surface is T1;

[0014] S104, forming a passivation layer and an anti-reflection layer in sequence on the light-receiving surface of the silicon substrate;

[0015] S105, performing a first laser etching opening on the back surface obtained in S104 to form a second semiconductor opening region;

[0016] S106, performing cleaning and etching to form a groove structure at least in the second semiconductor opening region on the back side of the silicon substrate, controlling the maximum height between the bottom of the second semiconductor opening region on the back side of the silicon substrate and the top of the first doped polysilicon layer to be T2, the bottom of the groove structure in the second semiconductor opening region may or may not have a pyramid structure and the maximum height of the pyramid is T3, and satisfies T2>T1≥T3, and T3 is 0-6μm;

[0017] S107 , depositing a second semiconductor layer on the back side, wherein the second semiconductor layer includes an amorphous passivation layer and a second doped silicon layer.

[0018] In some preferred embodiments of the present invention, T1 is 0.5-10 μm.

[0019] In some preferred embodiments of the present invention, T2 is 2.5-15 μm.

[0020] Preferably, T3 is 0.1-6 μm.

[0021] In some preferred embodiments of the present invention, T2:T1:T3 is 1.5-50:1-30:1.

[0022] In some preferred embodiments of the present invention, the conditions for cleaning and texturing in S103 to obtain T1 include: using alkali solution containing texturing additives for texturing, the mass concentration of alkali in the alkali solution is 0.5wt%-5wt%, the mass content of the texturing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 60-85℃, and the treatment time is 5-15min.

[0023] In some preferred embodiments of the present invention, the cleaning and etching in S106 includes any one of texturing, polishing, texturing after polishing, and polishing after texturing.

[0024] In some preferred embodiments of the present invention, S106 further includes a step of removing at least a portion of the thickness of the mask layer after cleaning and etching.

[0025] In some preferred embodiments of the present invention, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-3 μm, and when the groove structure is a texturized structure, T3 is 1-6 μm.

[0026] In some preferred embodiments of the present invention, the groove structure in the second semiconductor opening region in S106 is a polished or semi-textured structure, and the corresponding control conditions for cleaning and etching in S106 include: polishing with alkaline solution or forming a combination of texturing and polishing.

[0027] In some preferred embodiments of the present invention, the groove structure in the second semiconductor opening region in S106 is a texturing structure, and the corresponding control conditions for cleaning and etching in S106 include: texturing with alkaline solution or forming it by a combination of polishing and texturing.

[0028] In some preferred embodiments of the present invention, the polishing process conditions include: the mass concentration of alkali in the corresponding alkali solution is 0.5wt%-5wt%, the alkali solution contains a polishing additive and the mass content of the polishing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 50-85°C, and the treatment time is 0.25-5min; the texturing process conditions include: the mass concentration of alkali in the corresponding alkali solution is 0.5wt%-5wt%, the alkali solution contains a texturing additive and the mass content of the texturing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 60-85°C, and the treatment time is 2-12min.

[0029] In some preferred embodiments of the present invention, the post-texturing preparation method of the combined passivation back contact battery further satisfies at least one of the following conditions:

[0030] Condition 1: The thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 60-200 nm, and the effective doping concentration is 5e19 cm -3 -5e20cm -3 The thickness of the amorphous passivation layer is 3-10nm, the thickness of the second doped silicon layer is 5-40nm, and the effective doping concentration is 5e18cm -3 -2e20cm -3 ;

[0031] Condition 2: the mask layer is a silicon dielectric layer, and the silicon dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride;

[0032] Condition 3: The thickness of the mask layer is 10-80nm;

[0033] Condition 4: the passivation layer includes at least one of silicon oxide, amorphous silicon, and aluminum oxide; the anti-reflection layer is a silicon dielectric film, and the silicon dielectric film includes at least one of silicon nitride, silicon oxynitride, and silicon oxide;

[0034] Condition 5: The thickness of the passivation layer is 2-30 nm, and the thickness of the anti-reflection layer is 50-180 nm.

[0035] In some preferred embodiments of the present invention, the post-texturing preparation method of the combined passivation back contact battery further comprises:

[0036] S108, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0037] S109, depositing a conductive film layer on the back surface obtained in S108;

[0038] S110, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0039] S111 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

[0040] In a second aspect, the present invention provides a combined passivation back contact cell, which is prepared by the post-texturing preparation method of the combined passivation back contact cell described in the first aspect.

[0041] Beneficial effects:

[0042] The present invention has at least the following advantages through the above technical solution, especially by adopting specific S103 to S106:

[0043] ① The light-receiving side and the back side of the silicon substrate of the present invention are wet-etched separately, and the surface morphology is independently controlled, which is beneficial to improving the battery efficiency.

[0044] ② After the passivation layer and the anti-reflection layer are formed on the light-receiving surface of the conventional silicon substrate, there is serious wrap-around plating on the back side of the silicon substrate. The method of the present invention does not need to remove the wrap-around film layer on the back side and then make a rough surface or clean it, thus simplifying the process steps.

[0045] ③ Since the back side of the silicon substrate has certain damage after the first laser etching opening in the conventional method, a large amount of etching is required to completely remove it, while the light-receiving side of the silicon substrate has no damaged layer. Therefore, the method of the present invention is used to separately etch the back side of the light-receiving side to reduce the etching amount of the silicon substrate and reduce material costs. At the same time, it is beneficial to reduce the interface contact resistance of the second semiconductor opening area, increase the minority carrier lifetime, and improve the battery efficiency and bifaciality.

[0046] ④ In the present invention, the second semiconductor layer is deposited immediately after wet cleaning and etching on the interface of the second semiconductor opening area of ​​the silicon substrate. The interface between the second semiconductor layer and the silicon substrate is very clean and can be prevented from being contaminated, thereby improving the production yield and the double-sided rate.

[0047] The present invention controls the textured surface structure of the light-receiving surface and the structure of the second semiconductor opening area so that T2>T1≥T3, and can independently control the etching amount of the light-receiving surface of the silicon substrate and the corresponding opening area on the back side, thereby improving the cleanliness of the interface of the back opening area, which is beneficial to reducing the thickness of the silicon substrate (because the etching amount is reduced, it is necessary to keep the thickness of the silicon substrate after processing consistent, and the corresponding silicon substrate thickness before processing can be appropriately thinner, which is expected to be reduced by 5-10μm), improving the passivation and contact effects of the silicon substrate, and further facilitating the improvement of battery efficiency, production yield, and bifaciality. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 is a schematic structural diagram of a silicon substrate provided in Example 1 of the present invention;

[0050] Figure 2 It is a schematic structural diagram of a first semiconductor layer and a mask layer formed sequentially on the back side of Embodiment 1 of the present invention;

[0051] Figure 3 It is a schematic structural diagram of forming a textured surface on a light-receiving surface in Embodiment 1 of the present invention;

[0052] Figure 4 It is a schematic structural diagram of forming a passivation layer and an anti-reflection layer on a light-receiving surface in Embodiment 1 of the present invention;

[0053] Figure 5 is a schematic structural diagram of forming a second semiconductor opening region on the back side in Embodiment 1 of the present invention;

[0054] Figure 6 This is a schematic diagram of the structure of wet cleaning and etching performed in Example 1 of the present invention;

[0055] Figure 7 is a schematic structural diagram of forming a second semiconductor layer on the back side of Embodiment 1 of the present invention;

[0056] Figure 8 is a schematic structural diagram of forming a first semiconductor opening region on the back side in Embodiment 1 of the present invention;

[0057] Fig. 9 is a schematic structural diagram of forming a transparent conductive film layer on the back side of Embodiment 1 of the present invention;

[0058] Fig.10 is a schematic structural diagram of an isolation groove formed on the back side of Embodiment 1 of the present invention;

[0059] Fig.11 It is a schematic diagram of the structure of forming a metal electrode on the back side in Example 1 of the present invention.

[0060] Description of Reference Numerals

[0061] Silicon substrate 1, tunneling oxide layer 2, N-type doped polysilicon layer 3, mask layer 4, passivation layer 5, anti-reflection layer 6, amorphous silicon passivation layer 7, P-type doped amorphous silicon layer 8, transparent conductive film layer 9, metal electrode 10. DETAILED DESCRIPTION

[0062] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0063] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0064] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0065] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0066] In the present invention, the area close to the silicon substrate is referred to as the inner part, and the area far from the silicon substrate is referred to as the outer part.

[0067] In a first aspect, the present invention provides a post-texturing preparation method for a combined passivation back contact battery, comprising the following steps:

[0068] S101, providing a double-sided polished silicon substrate;

[0069] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon substrate; the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer;

[0070] S103, performing cleaning and texturing to form a texturing surface on the light-receiving surface of the silicon substrate, wherein the maximum height of the pyramid of the texturing surface on the light-receiving surface is T1;

[0071] S104, forming a passivation layer and an anti-reflection layer in sequence on the light-receiving surface of the silicon substrate;

[0072] S105, performing a first laser etching opening on the back surface obtained in S104 to form a second semiconductor opening region;

[0073] S106, performing cleaning and etching to form a groove structure at least in the second semiconductor opening region on the back side of the silicon substrate, controlling the maximum height between the bottom of the second semiconductor opening region on the back side of the silicon substrate and the top of the first doped polysilicon layer to be T2, the bottom of the groove structure in the second semiconductor opening region may or may not have a pyramid structure and the maximum height of the pyramid is T3, and satisfies T2>T1≥T3, and T3 is 0-6μm;

[0074] S107 , depositing a second semiconductor layer on the back side, wherein the second semiconductor layer includes an amorphous passivation layer and a second doped silicon layer.

[0075] In the present invention, the groove structure can be a polished, semi-textured structure or a velvet structure; the semi-textured structure refers to an incomplete pyramid velvet surface, which can generally be formed by incomplete velvet, or by polishing and then cutting off part of the pyramid after velvet. When the groove structure is a polished structure, there is a height difference in the tower base after polishing, and T3 refers to the maximum height of the concave and convex of the tower base, which can be 0.

[0076] In some preferred embodiments of the present invention, T1 is 0.5-10 μm, more preferably 0.5-4 μm. Using a light-receiving surface with a suitable suede structure is more conducive to reducing the reflectivity of the light-receiving surface, thereby increasing the battery current.

[0077] In some preferred embodiments of the present invention, T2 is 2.5-15 μm, preferably 5-15 μm, and T3 is 0.1-6 μm. The use of a second semiconductor opening region with a suitable suede structure is more conducive to reducing the reflectivity of the back side of the battery, thereby improving the bifaciality of the battery.

[0078] In some preferred embodiments of the present invention, T2:T1:T3 is 1.5-50:1-30:1, and specifically can be 1.5:1:1, 2:1:1, 2:10:1, 20:10:1, 4:2:1, 3:2:1, 6:2:1, 9:3:1, 50:30:1, etc. and the range between any two point values. The light-receiving surface with a suitable velvet structure and the second semiconductor opening area cooperate with each other, which is more conducive to improving the short-circuit current of the battery, thereby improving the battery efficiency.

[0079] In some preferred embodiments of the present invention, the conditions for cleaning and texturing in S103 to obtain T1 include: using alkali solution containing texturing additives for texturing, the mass concentration of alkali in the alkali solution is 0.5wt%-5wt%, the mass content of the texturing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 60-85℃, and the treatment time is 5-15min.

[0080] Preferably, in the present invention, the cleaning and etching in S106 includes any one of texturing, polishing, texturing after polishing, and polishing after texturing.

[0081] Preferably, S106 further includes the step of removing at least a portion of the thickness of the mask layer after cleaning and etching, and more preferably removing the entire mask layer.

[0082] In the present invention, preferably, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured or texturized structure, and when the groove structure is a polished or semi-textured structure, T3 is 0.1-3 μm, and when the groove structure is a texturized structure, T3 is 1-6 μm. Further preferably, T3 when the groove structure is a polished or semi-textured structure is less than T3 when the groove structure is a texturized structure.

[0083] In some specific implementations, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-1 μm, and when the groove structure is a texturized structure, T3 is 1.1-6 μm.

[0084] In some other specific implementations, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-3 μm, and when the groove structure is a texturized structure, T3 is 3.1-6 μm.

[0085] In some preferred embodiments of the present invention, the groove structure in the second semiconductor opening region in S106 is a polished or semi-textured structure, and the corresponding control conditions for cleaning and etching in S106 include: polishing with alkaline solution or forming in a combination of first texturing and then polishing. The semi-textured structure of the second semiconductor opening region has a better passivation effect, while taking into account the contact of the interface, which is more conducive to improving the battery efficiency.

[0086] In some preferred embodiments of the present invention, the groove structure in the second semiconductor opening region in S106 is a textured structure, and the corresponding control conditions for cleaning and etching in S106 include: using alkaline solution for texture or forming it by a combination of first polishing and then texture. The second semiconductor opening region is a textured structure, which has better contact resistance and is more conducive to improving the bifaciality of the battery (the power generation efficiency of the back of the battery).

[0087] Further preferably, the above-mentioned polishing process conditions independently include: the mass concentration of alkali in the corresponding alkali solution is 0.5wt%-5wt%, the alkali solution contains a polishing additive and the mass content of the polishing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 50-85°C, and the treatment time is 0.25-5min.

[0088] Further preferably, the above-mentioned texturing process conditions independently include: the mass concentration of alkali in the corresponding alkali solution is 0.5wt%-5wt%, the alkali solution contains a texturing additive and the mass content of the texturing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 60-85℃, and the treatment time is 2-12min.

[0089] In the present invention, selection can be made within the above-mentioned corresponding process conditions according to the required degree of polishing or texturing, as long as the required target degree of polishing or texturing is obtained.

[0090] In some preferred embodiments of the present invention, the thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 60-200 nm, and the effective doping concentration is 5e19 cm -3 -5e20cm -3 .

[0091] Preferably, the thickness of the amorphous passivation layer is 3-10 nm, the thickness of the second doped silicon layer is 5-40 nm, and the effective doping concentration is 5e18 cm -3 -2e20cm -3 .

[0092] In some preferred embodiments of the present invention, the mask layer is a silicon dielectric layer, and the silicon dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, which is more conducive to the laser opening in step S105.

[0093] In some preferred embodiments of the present invention, the thickness of the mask layer is 10-80 nm.

[0094] In some preferred embodiments of the present invention, the passivation layer includes at least one of silicon oxide, amorphous silicon, and aluminum oxide, which is more conducive to improving the passivation effect.

[0095] In some preferred embodiments of the present invention, the anti-reflection layer is a silicon dielectric film, and the silicon dielectric film includes at least one of silicon nitride, silicon oxynitride, and silicon oxide, which is more conducive to reducing the reflectivity of the light-receiving surface of the silicon substrate.

[0096] In some preferred embodiments of the present invention, the thickness of the passivation layer is 2-30 nm, which is more conducive to improving the passivation effect.

[0097] In some preferred embodiments of the present invention, the thickness of the anti-reflection layer is 50-180 nm, which is more conducive to reducing the reflectivity of the light-receiving surface.

[0098] In the present invention, the second doped silicon layer may be doped amorphous silicon or microcrystalline silicon.

[0099] In the present invention, one of the first doped polysilicon layer and the second doped silicon layer is of N type, and the other is of P type.

[0100] In S102, the first semiconductor layer and the mask layer can be formed by tubular PECVD deposition followed by annealing, LPCVD deposition followed by diffusion, or other feasible existing methods. Preferably, the first semiconductor layer and the mask layer are deposited by tubular PECVD and then annealed.

[0101] In some preferred embodiments of the present invention, the post-texturing preparation method of the combined passivation back contact cell also includes: S108, performing a second etching opening on a portion of the second semiconductor layer on the back of the silicon substrate to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area.

[0102] In some preferred embodiments of the present invention, the post-texturing preparation method of the combined passivation back contact battery further comprises:

[0103] S109, depositing a conductive film layer on the back surface obtained in S108;

[0104] S110, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0105] S111 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

[0106] In the present invention, the widths of the first semiconductor opening region, the second semiconductor opening region, and the isolation groove can be determined according to the range of the prior art and actual needs. For example, the width W1 of the second semiconductor opening region can be 300-700 μm, the width W2 of the first semiconductor opening region can be 100-400 μm, and the width W3 of the isolation groove can be, for example, 20-100 μm.

[0107] In a second aspect, the present invention provides a combined passivation back contact cell, which is prepared by the post-texturing preparation method of the combined passivation back contact cell described in the first aspect.

[0108] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0109] Example 1

[0110] A back contact battery is prepared by the following method:

[0111] S101, such as Figure 1 As shown, a double-sided polished N-type silicon substrate 1 is provided;

[0112] S102, such as Figure 2 As shown, a first semiconductor layer and a mask layer 4 are sequentially formed on the back of a silicon substrate 1. The first semiconductor layer includes a tunneling oxide layer 2 and an N-type doped polysilicon layer 3. The mask layer 4 is a silicon dielectric layer (silicon oxide). The first semiconductor layer and the mask layer are deposited by tubular PECVD and then annealed. The tunneling oxide layer 2 has a thickness of 1.5 nm, the N-type doped polysilicon layer 3 has a thickness of 130 nm, and the effective doping concentration is 1e20 cm -3 , the thickness of the mask layer 4 is 60nm.

[0113] S103, such as Figure 3 As shown, cleaning and texturing are carried out to form a texturing surface on the light-receiving surface of the silicon substrate 1; the cleaning and texturing conditions are: using alkali solution for texturing, the mass concentration of alkali in the alkali solution is 2wt%, the content of texturing additive is 0.2%, the temperature of the alkali solution is 75°C, and the processing time is 7min; the maximum height of the pyramid after texturing on the light-receiving surface of the silicon substrate 1 is T1, and the height of T1 is 3μm.

[0114] S104, such as Figure 4 As shown, a passivation layer 5 and an anti-reflection layer 6 are formed on the light-receiving surface of the silicon substrate 1, wherein the passivation layer 5 is aluminum oxide and has a thickness of 4 nm, and the anti-reflection layer 6 is silicon nitride and has a thickness of 75 nm;

[0115] S105, such as Figure 5 As shown, a first laser etching opening is performed on the back surface obtained in S104 to form a second semiconductor opening region, and the width W1 of the second semiconductor opening region is 500 μm;

[0116] S106, such as Figure 6 As shown, wet cleaning and etching are performed to clean and etch the second semiconductor opening area on the back of the silicon substrate 1. The cleaning and etching are formed by first texturing with alkali solution and then polishing. The process conditions of texturing include: texturing with alkali solution, the mass concentration of alkali in the alkali solution is 2wt%, the content of texturing additive is 0.2wt%, the temperature of the alkali solution is 80℃, and the processing time is 10min. The process conditions of polishing include: the mass concentration of alkali in the alkali solution is 3wt%, the content of polishing additive is 0.5wt%, the temperature of the alkali solution is 75℃, and the processing time is 15s.

[0117] The maximum height T2 between the bottom of the second semiconductor opening area on the back side of the silicon substrate 1 and the top of the N-type doped polysilicon layer 3 is 6μm. The groove structure in the second semiconductor opening area is a semi-textured structure. The maximum height of the semi-textured structure is T3. The height of T3 is 1.5μm, and T2>T1>T3; after conversion, T2:T1:T3 is 4:2:1.

[0118] S107, such as Figure 7 As shown, in S106, a second semiconductor layer is deposited on the back surface, and the second semiconductor layer includes an amorphous silicon passivation layer 7 with a thickness of 5 nm and a P-type doped amorphous silicon layer 8; the P-type doped amorphous silicon layer 8 has a thickness of 8 nm and an effective doping concentration of 1e19 cm -3 ;

[0119] S108, such as Figure 8 As shown, a second etching is performed on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and the width W2 of the first semiconductor opening region is 300 μm;

[0120] S109, such as Fig. 9 As shown, a transparent conductive film layer 9 is deposited on the back surface obtained in S108;

[0121] S110, such as Fig.10 As shown, a third etching is performed on a portion of the transparent conductive film layer 9 between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove, wherein the width W3 of the isolation groove is 50 μm;

[0122] S111, such as Fig.11 As shown, metal electrodes 10 are respectively formed on the outer surfaces of the corresponding transparent conductive film layer 9 in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0123] Example 2

[0124] The method of Example 1 is referred to, except that T3 is adjusted to be equal to T1 and the textured structure is formed. To meet this condition, process S106 needs to be adjusted:

[0125] S106, wet cleaning and etching are performed, and the etching process adopts alkaline solution polishing first and then texturing. The polishing process conditions include: the mass concentration of alkali in the alkaline solution is 3wt%, the content of polishing additive is 0.5wt%, the temperature of the alkaline solution is 75℃, and the processing time is 50s; the texturing process conditions include: the mass concentration of alkali in the alkaline solution is 2wt%, the content of texturing additive is 0.2wt%, the temperature of the alkaline solution is 75℃, and the processing time is 7min. T2 remains unchanged.

[0126] Example 3

[0127] The method of Example 1 is referred to, except that T2 is adjusted to 4.5μm. To meet this condition, the process needs to be adjusted: S106, cleaning and etching adopts the method of first texturing with alkali solution and then polishing. The groove structure formed is a semi-texturing structure. The process conditions of texturing include: texturing with alkali solution, the mass concentration of alkali in the alkali solution is 2wt%, the content of texturing additive is 0.2wt%, the temperature of the alkali solution is 80℃, and the treatment time is 7min. The process conditions of polishing include: the mass concentration of alkali in the alkali solution is 3wt%, the content of polishing additive is 0.5wt%, the temperature of the alkali solution is 75℃, and the treatment time is 15s. After conversion, T2:T1:T3 is 3:2:1.

[0128] Example 4

[0129] The method of Example 1 is referred to, except that the groove structure of the second semiconductor opening area is adjusted to a polishing structure, and the process needs to be adjusted to meet this condition: S106, cleaning and etching the second semiconductor opening area on the back of the silicon substrate 1, the cleaning and etching conditions are alkaline solution polishing, and the polishing process conditions include: the mass concentration of alkali in the alkaline solution is 3wt%, the content of the polishing additive is 0.5wt%, the temperature of the alkaline solution is 75°C, and the processing time is 3min. The maximum height T3 of the tower base after polishing is 0.3μm, and the conversion T2:T1:T3 is 20:10:1.

[0130] Example 5

[0131] The method of Example 2 is referred to, except that the groove structure of the second semiconductor opening area is adjusted to a texturing structure, and the process needs to be adjusted to meet this condition: S106, wet cleaning and etching are performed, and the etching process adopts alkaline solution polishing followed by texturing. The process conditions for polishing include: the mass concentration of the alkali in the alkaline solution is 3wt%, the content of the polishing additive is 0.5wt%, the temperature of the alkaline solution is 75°C, and the treatment time is 120s. The process conditions for texturing include: the mass concentration of the alkali in the alkaline solution is 2wt%, the content of the texturing additive is 0.2wt%, the temperature of the alkaline solution is 75°C, and the treatment time is 7min; T2 is 9μm, and after conversion, T2:T1:T3 is 6:2:1.

[0132] Example 6

[0133] The method of Example 1 is referred to, except that the groove structure is adjusted to a semi-textured structure and the height of T2 is different, specifically: it is formed by first texturing with alkali solution and then polishing, and the process conditions of texturing include: texturing with alkali solution, the mass concentration of alkali in the alkali solution is 2wt%, the content of texturing additive is 0.2wt%, the temperature of the alkali solution is 80℃, and the treatment time is 10min. The process conditions of polishing include: the mass concentration of alkali in the alkali solution is 3wt%, the content of polishing additive is 0.5wt%, the temperature of the alkali solution is 75℃, and the treatment time is 30s. T3 is 1μm, T2 is 9μm, and after conversion, T2:T1:T3 is 9:3:1.

[0134] Comparative Example 1

[0135] The method of Example 1 is referred to, except that S103 to S106 are not performed, but a conventional post-texturing process is adopted. Specifically, after S102, the following steps are performed:

[0136] Performing a first laser etching opening on the back surface obtained in S102 to form a second semiconductor opening region, the width of the second semiconductor opening region is the same as that of Embodiment 1;

[0137] Then, the texturing cleaning is performed to form a texturing surface on the light-receiving surface of the silicon substrate and the second semiconductor opening area at the same time, and the maximum pyramid height of the texturing surface is 3 μm; then, all mask layers outside the second semiconductor opening area on the back side of the silicon substrate are removed;

[0138] A passivation layer and an anti-reflection layer are formed on the light-receiving surface of the silicon substrate, and the thickness and material of the passivation layer and the anti-reflection layer are the same as those in Example 1;

[0139] Single-sided etching removes the wrap-around coating formed on the back of the silicon substrate during deposition on the light-receiving side, and single-sided etching uses hydrofluoric acid;

[0140] After conventional RCA cleaning, the interface cleanliness of the second semiconductor opening area on the back of the silicon substrate meets the requirements for depositing the second semiconductor layer; the conventional RCA cleaning conditions are: cleaning with alkaline hydrogen peroxide, hydrochloric acid hydrogen peroxide, and hydrofluoric acid in sequence;

[0141] Then, S107 and subsequent steps of Example 1 are performed.

[0142] Comparative Example 2

[0143] The method of Example 1 is referred to, except that T2 is adjusted to be less than T1. To meet this condition, the process needs to be adjusted: S106, wet cleaning and etching are performed, and the etching process adopts a texturing process. The process conditions of texturing include: the mass concentration of alkali in the alkali solution is 2wt%, the content of the texturing additive is 0.2wt%, the temperature of the alkali solution is 75℃, and the processing time is 5min; T2 is 2μm.

[0144] Comparative Example 3

[0145] The method of Example 1 is referred to, except that the structure of the first semiconductor layer is different, and the passivation structure is a heterojunction. Specifically, the first semiconductor layer is an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer. The thickness of the intrinsic amorphous silicon layer is 6 nm, the thickness of the N-type doped amorphous silicon layer is 15 nm, and the effective doping concentration is 5e19 cm -3 .

[0146] Test Case

[0147] The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0148] Among them, the second semiconductor opening region interface contact resistance refers to the contact resistance between the silicon substrate and the second semiconductor layer in the second semiconductor opening region, which is obtained by testing the battery after the second semiconductor layer is deposited and the metal electrode is formed by the ‌TLM method (transmission line model method). The second semiconductor opening region interface contact resistance of each embodiment and comparative example is converted with embodiment 1 as the reference benchmark, and the second semiconductor opening region interface contact resistance data of embodiment 1 is the normalized benchmark 1, and other examples are converted based on embodiment 1, such as the second semiconductor opening region interface contact resistance of comparative example 1 / the second semiconductor opening region interface contact resistance of embodiment 1 is 2.

[0149] Bifaciality refers to the ratio of the cell efficiency corresponding to light entering from the back of the cell and light entering from the light-receiving surface of the cell under standard test conditions.

[0150] Table 1

[0151]

[0152] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can reduce the interface contact resistance of the second semiconductor opening region, improve the minority carrier lifetime, and improve the battery efficiency and bifaciality while simplifying the process steps and reducing material costs.

[0153] Furthermore, according to Example 1 and Examples 2-6, it can be seen that the preferred solution of the present invention is more conducive to reducing the interface contact resistance of the second semiconductor opening region, increasing the minority carrier lifetime, and improving the battery efficiency and bifaciality.

[0154] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A post-texturing preparation method for a combined passivation back contact battery, characterized in that: The steps include: S101, providing a double-sided polished silicon substrate; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon substrate; the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer; S103, performing cleaning and texturing to form a texturing surface on the light-receiving surface of the silicon substrate, wherein the maximum height of the pyramid of the texturing surface on the light-receiving surface is T1; S104, forming a passivation layer and an anti-reflection layer in sequence on the light-receiving surface of the silicon substrate; S105, performing a first laser etching opening on the back surface obtained in S104 to form a second semiconductor opening region; S106, performing cleaning and etching to form a groove structure at least in the second semiconductor opening region on the back side of the silicon substrate, controlling the maximum height between the bottom of the second semiconductor opening region on the back side of the silicon substrate and the top of the first doped polysilicon layer to be T2, the bottom of the groove structure in the second semiconductor opening region does not have a pyramid structure or the bottom of the groove structure in the second semiconductor opening region has a pyramid structure and the maximum height of the pyramid is T3, and satisfies T2>T1≥T3, 0<T3≤6μm; S107 , depositing a second semiconductor layer on the back side, wherein the second semiconductor layer includes an amorphous passivation layer and a second doped silicon layer.

2. The post-texturing preparation method of the combined passivation back contact battery according to claim 1, characterized in that: T1 is 0.5-10 μm, and / or, T2 is 2.5-15μm and T3 is 0.1-6μm.

3. The post-texturing preparation method of the combined passivation back contact battery according to claim 1 or 2, characterized in that: T2:T1:T3 is 1.5-50:1-30:

1.

4. The post-texturing preparation method of the combined passivation back contact battery according to claim 1, characterized in that: The conditions for cleaning and texturing in S103 to obtain T1 include: using alkali solution containing texturing additives for texturing, the mass concentration of alkali in the alkali solution is 0.5wt%-5wt%, the mass content of the texturing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 60-85℃, and the treatment time is 5-15min.

5. The post-texturing preparation method of the combined passivation back contact battery according to claim 1, characterized in that: The cleaning and etching in S106 includes any one of texturing, polishing, texturing after polishing, and polishing after texturing. S106 also includes the step of removing at least a portion of the thickness of the mask layer after the cleaning and etching. and / or, In S106, the groove structure in the second semiconductor opening region is a polished structure, a semi-textured structure or a texturized structure. When the groove structure is a polished structure or a semi-textured structure, T3 is 0.1-3 μm, and when the groove structure is a texturized structure, T3 is 1-6 μm.

6. The post-texturing preparation method of the combined passivation back contact battery according to claim 1, characterized in that: In S106, the groove structure in the second semiconductor opening region is a polished or semi-textured structure, and the corresponding control conditions for cleaning and etching in S106 include: polishing with alkaline solution or forming by a combination of first texturing and then polishing; and / or, The groove structure in the second semiconductor opening region in S106 is a texturing structure, and the corresponding control conditions for cleaning and etching in S106 include: texturing with alkaline solution or forming the structure by a combination of polishing first and then texturing.

7. The post-texturing preparation method of the combined passivation back contact battery according to claim 6, characterized in that: The polishing process conditions include: the mass concentration of alkali in the corresponding alkali solution is 0.5wt%-5wt%, the alkali solution contains a polishing additive and the mass content of the polishing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 50-85°C, and the processing time is 0.25-5min; The process conditions for texturing include: the mass concentration of alkali in the corresponding alkali solution is 0.5wt%-5wt%, the alkali solution contains a texturing additive and the mass content of the texturing additive is 0.05wt%-2wt%, the temperature of the alkali solution is 60-85℃, and the processing time is 2-12min.

8. The post-texturing preparation method of the combined passivation back contact battery according to claim 1, characterized in that: The post-texturing preparation method of the combined passivation back contact battery also meets at least one of the following conditions: Condition 1: The thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 60-200 nm, and the effective doping concentration is 5e19 cm -3 -5e20cm -3 ; The thickness of the amorphous passivation layer is 3-10nm, the thickness of the second doped silicon layer is 5-40nm, and the effective doping concentration is 5e18cm -3 -2e20cm -3 ; Condition 2: the mask layer is a silicon dielectric layer, and the silicon dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride; Condition 3: The thickness of the mask layer is 10-80nm; Condition 4: the passivation layer includes at least one of silicon oxide, amorphous silicon, and aluminum oxide; the anti-reflection layer is a silicon dielectric film, and the silicon dielectric film includes at least one of silicon nitride, silicon oxynitride, and silicon oxide; Condition 5: The thickness of the passivation layer is 2-30 nm, and the thickness of the anti-reflection layer is 50-180 nm.

9. The post-texturing preparation method of the combined passivation back contact battery according to claim 1, characterized in that: The post-texturing preparation method of the combined passivation back contact battery also includes: S108, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S109, depositing a conductive film layer on the back surface obtained in S108; S110, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S111 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

10. A combined passivation back contact cell, characterized in that: The battery is prepared by the post-texturing preparation method of the combined passivation back contact battery as described in any one of claims 1 to 9.

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