Manufacturing method of semiconductor structure

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure. The method comprises the following steps: providing an initial semiconductor structure which comprises a first region and a second region arranged on at least one side of the first region, storage stacking strips arranged in the first region, and a first material layer arranged between adjacent storage stacking strips in the first region and also arranged in the second region, the surface of the first material layer in the second region is lower than the surface of the first material layer in the first region; forming a second material layer, a third material layer and a fourth material layer in the first region and the second region; performing planarization processing on the first region and the second region to expose the surface of the storage stacking strip in the first region and expose the surface of the third material layer in the second region; wherein the removal rate of the third material layer in the second region is smaller than the removal rate of the second material layer in the first region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, including but not limited to a method for manufacturing a semiconductor structure. Background Art

[0002] By improving the semiconductor manufacturing process, the planar memory cell can be reduced to a smaller size. However, as the critical dimension of the planar memory cell approaches the lower limit, the storage density of the planar memory architecture approaches the upper limit. The three-dimensional memory structure can solve the density limitation in the planar memory architecture.

[0003] Phase Change Memory (PCM) has become one of the most promising storage technologies. PCM uses the conductivity difference of the phase change layer when it transforms between the crystalline state and the amorphous state to store data. The PCM may include a bottom memory cell array (Bottom Stack) and a top memory cell array (Top Stack) stacked to form a three-dimensional storage architecture. The bottom memory cell and the top memory cell may be connected through a bottom word line and a top word line.

[0004] Therefore, how to control the alignment between the bottom word line and the top word line becomes a key issue. Summary of the invention

[0005] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.

[0006] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0007] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing an initial semiconductor structure, comprising a first region and a second region arranged on at least one side of the first region, a storage stack bar arranged in the first region, a first material layer arranged between adjacent storage stack bars in the first region and also in the second region, the surface of the first material layer in the second region being lower than the surface of the first material layer in the first region; forming a second material layer, a third material layer and a fourth material layer in the first region and the second region; performing a planarization process on the first region and the second region to expose the surface of the storage stack bar in the first region and also expose the surface of the third material layer in the second region; wherein a removal rate of the third material layer in the second region is lower than a removal rate of the second material layer in the first region.

[0008] In some embodiments, after the first region and the second region are planarized, the method further includes: forming a first conductive layer in the first region and the second region; etching the first conductive layer and the storage stack strip, wherein the first conductive layer after etching in the first region and the second region forms a first conductive line extending along a first direction, and the storage stack strip after etching in the first region forms a virtual storage unit; wherein the first conductive line provided in the second region is used as an alignment mark.

[0009] In some embodiments, before planarizing the first region and the second region, the method further includes: forming a photoresist layer covering the fourth material layer in the second region; removing the fourth material layer and the third material layer in the first region to expose the surface of the second material layer in the first region; and removing the photoresist layer to expose the surface of the fourth material layer in the second region.

[0010] In some embodiments, the surface of the fourth material layer in the second region is lower than the surface of the second material layer in the first region; before the first region and the second region are planarized, the method further includes: forming a fifth material layer in the first region and the second region; wherein the surface of the fifth material layer in the second region is higher than or equal to the surface of the second material layer in the first region.

[0011] In some embodiments, the planarizing treatment of the first region and the second region includes: performing a first planarizing treatment on the first region and the second region to expose the surface of the second material layer in the first region, and also exposing the surface of the fifth material layer in the second region; wherein the surface of the fifth material layer in the second region is lower than the surface of the second material layer in the first region.

[0012] In some embodiments, a dual abrasive is used in the process of removing the third material layer in the first region; wherein the dual abrasive includes an oxidation aid, and the oxidation aid includes at least one of K2FeO4, KMnO4 and H2O2.

[0013] In some embodiments, the storage stack strip includes a first electrode layer, a gating layer, a second electrode layer, a phase change layer and a third electrode layer in sequence; the planarizing treatment of the first region and the second region also includes: performing a second planarizing treatment on the first region and the second region to expose the surface of the third electrode layer in the first region, and also expose the surface of the third material layer in the second region; wherein, in the second planarizing treatment, the ratio between the removal rate of the second material layer in the first region and the removal rate of the third material layer in the second region is greater than 200.

[0014] In some embodiments, after the first region and the second region are planarized, the surface flatness of the third material layer in the second region is less than 50 angstroms.

[0015] In some embodiments, providing an initial semiconductor structure includes: providing a second conductive layer and a storage stack layer arranged on one side of the second conductive layer; etching the storage stack layer and the second conductive layer to form a groove extending along a second direction in the first region, and removing the storage stack layer and the second conductive layer in the second region; wherein the second conductive layer after etching in the first region forms a second conductive line, and the storage stack layer after etching in the first region forms the storage stack bar; forming a first material layer in the groove in the first region and in the second region; performing a third planarization treatment on the first region and the second region to expose the surface of the storage stack bar in the first region; wherein the first direction and the second direction intersect.

[0016] In some embodiments, both the first region and the second region are disposed in a scribe line region.

[0017] The disclosed embodiment provides a method for manufacturing a semiconductor structure. In the disclosed embodiment, the initial semiconductor structure includes a first region and a second region, and the surface of the first material layer in the second region is lower than the surface of the first material layer in the first region; a second material layer, a third material layer and a fourth material layer are formed in the first region and the second region; the first region and the second region are planarized, and since the removal rate of the third material layer is lower than the removal rate of the second material layer, after the planarization, the surface of the storage stack bar in the first region and the surface of the third material layer in the second region can be exposed. In this way, the window for planarization of the second material layer can be enlarged, and the surface flatness of the third material layer in the second region can be improved, which is conducive to the subsequent formation of alignment marks on the third material layer in the second region, so as to improve the alignment quality between the bottom word line and the top word line, thereby improving the yield of manufacturing semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A A cross-sectional view of a phase change memory is provided for some examples;

[0019] Figure 1B A cross-sectional view of a bottom storage unit is provided for some examples;

[0020] FIG. 2A to FIG. 2E Cross-sectional views of semiconductor structures during fabrication are provided for some examples;

[0021] Figure 3 Schematic diagram of alignment marks in the scribe line area provided for some examples;

[0022] Figure 4 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0023] FIG. 5A to FIG. 5F A cross-sectional view of a semiconductor structure during manufacturing provided for some embodiments;

[0024] 6A to 6H Cross-sectional views of semiconductor structures during the manufacturing process are provided for some other embodiments. DETAILED DESCRIPTION

[0025] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0027] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0029] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0030] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0032] Before introducing the embodiments of the present disclosure, various directions that may be involved in the following are defined. The stacking direction between the bottom memory cell and the top memory cell in the phase change memory is defined as the Z direction. Intersecting X direction and Y direction are defined in a plane perpendicular to the Z direction. In some embodiments, the X direction and the Y direction may be perpendicular to each other. The X direction may be, for example, a bit line direction, and the Y direction may be, for example, a word line direction.

[0033] refer to Figure 1A , Figure 1A A cross-sectional view of a phase change memory is provided for some examples. Figure 1A As shown, the phase change memory 100 may include: a bottom cell 104 and a top cell 110 stacked along the Z direction, the bottom cell 104 (or, the top cell 110) being arranged at intervals along the X direction and the Y direction; a bottom cell bit line 102 (BCBL) and a bottom cell word line 106 (BCWL) respectively arranged at two opposite sides of the bottom cell 104 along the Z direction, the bottom bit line 102 extending along the X direction and arranged at intervals along the Y direction, the bottom word line 106 extending along the Y direction and arranged at intervals along the X direction; a top word line 108 and a top bit line 112 respectively arranged at two opposite sides of the top cell 110 along the Z direction, the top word line 108 extending along the Y direction and arranged at intervals along the X direction, the top bit line 112 extending along the X direction and arranged at intervals along the Y direction; wherein the bottom word line 106 and the top word line 108 are connected in a one-to-one correspondence.

[0034] refer to Figure 1B , Figure 1B The following is a cross-sectional view of a bottom storage unit provided for some examples. The specific structure of the bottom storage unit will be described below by taking the bottom storage unit as an example. Figure 1B As shown, the bottom memory cell 104 may include: a bottom electrode layer 114, a gating layer 116, an intermediate electrode layer 118, a phase change layer 120, and a top electrode layer 122 stacked in sequence along the Z direction. A barrier layer 124 may also be provided on the sidewall of the bottom memory cell 104. The specific structure of the top memory cell 110 may refer to the bottom memory cell 104, and will not be described in detail here.

[0035] In the above phase change memory, the bottom memory cell and the top memory cell can be connected one-to-one through the bottom word line and the top word line. The alignment quality between the bottom word line and the top word line can be fed back by using the alignment mark (OverlayMark) set in the scribe line area (Scribe Line).

[0036] refer to FIG. 2A to FIG. 2E , FIG. 2A to FIG. 2E The following is a cross-sectional view of a semiconductor structure during the manufacturing process provided for some examples. FIG. 2A to FIG. 2E , briefly explaining how to form alignment marks in a scribe line area provided by some examples.

[0037] like Figure 2A As shown, the scribe line region may include a first region 218 and a second region 220 disposed on at least one side of the first region 218. The first region 218 may include: a dummy bottom bit line 204, a memory stack bar 206 and a mask layer 202 stacked in sequence along the Z direction, and a filling layer 208 disposed between adjacent dummy bottom bit lines 204, between adjacent memory stack bars 206 and between adjacent mask layers 202. The filling layer 208 disposed in the first region 218 may fill the gap between adjacent memory stack bars 206 and cover the surface of the mask layer 202. The filling layer 208 is also disposed in the second region 220, and the surface of the filling layer 208 in the first region 218 is flush with the surface of the filling layer 208 in the second region 220. Here, the dummy bottom bit line 204 extends along the X direction and is arranged at intervals along the Y direction.

[0038] It should be noted that, at this time, the chip region is also provided with a bottom bit line, and the bottom bit line in the chip region and the dummy bottom bit line in the cutting path region are formed simultaneously.

[0039] like Figure 2B As shown, the filling layer 208 in the first region 218 and the second region 220 is planarized to expose the surface of the mask layer 202 in the first region 218. Since the first region 218 is provided with the dummy bottom bit line 204, the memory stack bar 206, the mask layer 202 and the filling layer 208, the second region 220 is provided with the filling layer 208 as a whole, and the second region 220 is in a large open area with a loading effect, the surface of the filling layer 208 in the second region 220 is lower than the surface of the filling layer 208 (or the mask layer 202) in the first region 218 after the planarization.

[0040] like Figure 2CAs shown, a silicon nitride layer 210 is formed in the first region 218; the filling layer 208 in the second region 220 is removed; a silicon oxide layer 212 is formed in the first region 218 and the second region 220; and the silicon oxide layers in the first region 218 and the second region 220 are planarized to expose the surface of the silicon nitride layer 210 in the first region 218 and also expose the surface of the silicon oxide layer 212 in the second region 220. Since the removal rate of the silicon oxide layer 212 in the second region 220 is greater than the removal rate of the silicon nitride layer 210 in the first region 218, after the planarization process, the surface of the silicon oxide layer 212 in the second region 220 is lower than the surface of the silicon nitride layer 210 in the first region 218, and the surface flatness of the silicon oxide layer 212 in the second region 220 is poor, and more specifically, the surface of the silicon oxide layer 212 in the second region 220 is concave.

[0041] It should be noted that at this time, the filling layer is also etched away in the chip area, and the space occupied by the filling layer is replaced by a silicon oxide layer to facilitate the subsequent formation of a word line contact structure.

[0042] In a specific example, Figure 2B The height difference between the surface of the filling layer 208 in the second region 220 and the surface of the filling layer 208 in the first region 218 is about 600 angstroms. Figure 2C The height difference between the surface of the silicon oxide layer 212 in the second region 220 and the surface of the silicon nitride layer 210 in the first region 218 is about 300 angstroms. That is, the height difference between the first region 218 and the second region 220 is reduced, but the surface flatness of the silicon oxide layer 212 in the second region 220 is poor.

[0043] like Figure 2D As shown, the first region 218 and the second region 220 are planarized to expose the surface of the storage stack bar 206 (more specifically, the top electrode layer 222) in the first region 218, and also expose the surface of the silicon oxide layer 212 in the second region 220. The storage stack bar 206 may include: a bottom electrode layer, a gating layer, an intermediate electrode layer, a phase change layer, and a top electrode layer 222 stacked in sequence along the Z direction. Since the removal rate of the silicon oxide layer 212 in the second region 220 is greater than the removal rate of the top electrode layer 222 in the first region 218, the removal rates of the portion of the silicon oxide layer 212 close to the first region 218 and the portion of the silicon oxide layer 212 far from the first region 218 are faster, and therefore, after the planarization process, the surface flatness of the silicon oxide layer 212 in the second region 220 is poor, and more specifically, the surface of the silicon oxide layer 212 in the second region 220 is convex.

[0044] Here, the surface flatness of the material layer refers to the difference between the highest point and the lowest point of the surface of the material layer along the Z direction. If the difference between the highest point and the lowest point of the surface of the material layer along the Z direction is greater than a preset value, then the surface flatness of the material layer is poor; if the difference between the highest point and the lowest point of the surface of the material layer along the Z direction is less than or equal to the preset value, then the surface flatness of the material layer is good. Exemplarily, Figure 2C It is shown that the surface of the silicon oxide layer 212 in the second region 220 is concave. Figure 2D It is shown that the surface of the silicon oxide layer 212 in the second region 220 is convex, and the difference between the highest point and the lowest point of the surface of the silicon oxide layer 212 along the Z direction is large. Therefore, the surface flatness of the silicon oxide layer 212 in the second region 220 is poor.

[0045] like Figure 2E As shown, a conductive layer is formed in the first region 218 and the second region 220; the conductive layer and the memory stack bar 206 are etched along the Z direction, and the etched conductive layer in the first region 218 and the second region 220 forms a dummy bottom word line 214, and the etched memory stack bar 206 in the first region 218 forms a dummy memory cell 216. Here, the dummy bottom word line 214 extends along the Y direction and is arranged at intervals along the X direction. The dummy bottom word line 214 provided in the second region 220 can be used as an alignment mark.

[0046] refer to Figure 3 , Figure 3 Schematic diagram of alignment marks in the scribe line area provided for some examples. Figure 3 As shown in FIG. (a), during the process of forming the dummy bottom bit line, the storage stack layer in the second region in the cutting path region is removed, and a filling layer is formed in the second region. Figure 3 As shown in Figure (b), the space occupied by the filling layer in the second area of ​​the cutting path area is replaced by a silicon oxide layer. Figure 3 As shown in FIG. 5( c ), a dummy bottom word line is formed in the second region in the scribe line region, and the dummy bottom word line is used as an alignment mark.

[0047] In the above-mentioned process of forming the alignment mark in the cutting road area, since the alignment mark is formed in the empty area in the cutting road area, there is a large load effect during the flattening process, resulting in poor uniformity of the silicon oxide layer before the formation of the alignment mark, that is, the surface flatness of the silicon oxide layer is poor, and the subsequently formed alignment mark for the bottom word line (that is, the virtual bottom word line provided in the second area in the cutting road area) is prone to measurement inaccuracy, making it difficult to use the measurement of the alignment mark to feedback the alignment quality between the bottom word line and the top word line in the chip area.

[0048] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.

[0049] refer to Figure 4 , Figure 4 The flowchart of the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is as follows. Figure 4 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0050] Step S410: providing an initial semiconductor structure, comprising a first region and a second region disposed on at least one side of the first region, a memory stack bar disposed in the first region, a first material layer disposed between adjacent memory stack bars in the first region and also disposed in the second region, wherein a surface of the first material layer in the second region is lower than a surface of the first material layer in the first region;

[0051] Step S420: forming a second material layer, a third material layer and a fourth material layer in the first region and the second region;

[0052] Step S430: Flatten the first and second regions to expose the surface of the storage stack strips in the first region and also expose the surface of the third material layer in the second region; wherein a removal rate of the third material layer in the second region is less than a removal rate of the second material layer in the first region.

[0053] In some embodiments, the first region and the second region are both disposed in the scribe line region.

[0054] Here, a wafer is usually composed of hundreds to tens of thousands of chips, and a cutting road area is provided between adjacent chip areas. After the chip manufacturing process is completed in the chip area, the chips on a wafer can be separated by cutting and separation using a cutting process. The cutting road area includes a first area and a second area provided on at least one side of the first area. The first area in the cutting road area is used to form a dummy memory cell, and the dummy memory cell and the memory cell provided in the chip area are formed at the same time; the second area in the cutting road area is used to form an alignment mark, and the alignment quality between the bottom word line and the top word line in the chip area is fed back by measuring the alignment mark in the cutting road area, thereby improving the yield of manufacturing semiconductor devices.

[0055] refer to FIG. 5A to FIG. 5F , FIG. 5A to FIG. 5F The cross-sectional view of the semiconductor structure during the manufacturing process provided by some embodiments. FIG. 5A to FIG. 5F , describing in detail the manufacturing methods of the semiconductor structures provided by some embodiments.

[0056] like Figure 5AAs shown, step S410 includes: providing a second conductive layer and a storage stack layer disposed on one side of the second conductive layer. In some embodiments, the storage stack layer may include: a first electrode layer, a phase change layer, a second electrode layer, a gating layer, and a third electrode layer stacked in sequence along the Z direction; wherein the first electrode layer is in contact with the second conductive layer.

[0057] Here, the material of the second conductive layer may include a conductive material, such as a metal material. Exemplarily, the material of the second conductive layer may include metal tungsten.

[0058] Here, the process of forming the storage stack layer may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof.

[0059] like Figure 5A As shown, a mask layer 522 is formed on the storage stack layer; the storage stack layer and the second conductive layer are sequentially etched along the Z direction using the mask layer 522 to form a first groove extending along the second direction (i.e., the X direction) in the first region 504, and the storage stack layer and the second conductive layer in the second region 506 are removed. The second conductive layer after etching in the first region 504 forms a second conductive line 508, and the storage stack layer after etching in the first region 504 forms a storage stack bar 510. The first region 504 is provided with a storage stack bar 510 extending along the X direction and a first groove provided between adjacent storage stack bars 510. Here, the storage stack bar 510 may include: a first electrode layer 512, a gating layer 514, a second electrode layer 516, a phase change layer 518, and a third electrode layer 520 sequentially stacked along the Z direction; wherein the first electrode layer 512 is in contact with the second conductive line 508.

[0060] Here, the first electrode layer 512, the second electrode layer 516 and the third electrode layer 520 can be used to transmit electrical signals and can include conductive materials, such as metal materials, metal nitrides or any combination thereof. The metal material can be, for example, platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) or titanium (Ti). In some embodiments, the first electrode layer 512, the second electrode layer 516 and the third electrode layer 520 can include carbon electrodes.

[0061] Here, the gating layer 514 may include a threshold switch material, such as an Ovonic Threshold Switching (OTS) material. The OTS material may be a chalcogenide material, such as GeSeAs, GeTeAs, GeSeTeSe, GeSe, SeAs, GeTe, SiTe, etc. The bidirectional threshold switch uses an electrical signal to control the switch of the gating device. When the applied electrical signal is higher than the threshold voltage, the OTS material changes from a high resistance state to a low resistance state, and the OTS is in an on state; when the electrical signal is removed, the OTS material changes from a low resistance state to a high resistance state, and the OTS is in an off state. The gating layer is used to control the current flowing through the phase change layer, and remains in an on state when the phase change layer is erased and written, and remains in a off state after the erase and write operation is completed, so as to avoid read-write crosstalk between storage cells.

[0062] Here, the phase change layer 518 may include a phase change material. The phase change material may be an alloy of a chalcogenide compound, such as a germanium antimony telluride compound (Ge-Sb-Te compound, GST), a germanium antimony compound, an indium germanium telluride compound, an aluminum selenide telluride compound, an indium selenide telluride compound, an aluminum indium selenide telluride compound, and the like. In this embodiment, taking the material of the phase change layer as GST as an example, the GST material can realize a reversible transition between an amorphous state and a crystalline state. In the amorphous state, the GST material has a short-range atomic energy level and a low free electron density, so that it has a high resistivity; in the crystalline state, the GST material has a long-range atomic energy level and a high free electron density, so that it has a low resistivity. Phase change memory uses the resistance difference between different phases of phase change materials to realize information storage. By applying different voltage or current pulse signals to the phase change layer, the phase change material undergoes a physical phase change, that is, a reversible phase change occurs between the crystalline state (low resistance state) and the amorphous state (high resistance state), thereby realizing the writing and erasing operations of information to store data.

[0063] Here, the second conductive lines 508 may also be referred to as dummy bottom bit lines, which extend along the X direction and are arranged at intervals along the Y direction.

[0064] Here, the material of the mask layer 522 may include a silicon nitride material.

[0065] It should be noted that, at this time, the chip region is also provided with a bottom bit line, and the bottom bit line in the chip region and the dummy bottom bit line in the cutting path region are formed simultaneously.

[0066] like Figure 5AAs shown, a method including but not limited to spin coating can be used to fill the dielectric material in the first groove of the first region 504 and the second region 506, and a first material layer 524 is formed by coating and rotating. At this time, the first material layer 524 in the first region 504 fills the first groove and covers the surface of the mask layer 522, and the surfaces of the first material layer 524 in the first region 504 and the second region 506 are flush.

[0067] Here, the first material layer 524 may also be referred to as a spin-on dielectric (SOD). The first material layer 524 is formed in the first region 504 and the second region 506 by spin coating, and the centrifugal force enables the spin-on dielectric to be evenly distributed in the first region 504 and the second region 506, so that the surfaces of the first material layer 524 in the first region 504 and the second region 506 are flush.

[0068] like Figure 5B As shown, step S410 includes: performing a third planarization process on the first region 504 and the second region 506, removing a portion of the first material layer 524 to expose the surface of the mask layer 522 in the first region 504. Here, the initial semiconductor structure 502 may include the first region 504 and the second region 506 disposed on at least one side of the first region 504, and the storage stack bar 510 (such as Figure 5B The first material layer 524 is provided between adjacent storage stacking strips 510 in the first region 504 and is also provided in the second region 506, wherein the surface of the first material layer 524 in the second region 506 is lower than the surface of the first material layer 524 (or, the mask layer 522) in the first region 504.

[0069] Here, since the first region 504 is provided with a second conductive line 508, a storage stack bar 510 and a first material layer 524, the second region 506 is provided with the first material layer 524 as a whole, and the second region 506 is in a large open area and there is a loading effect (Loading Effect), therefore, after the planarization treatment, the surface of the first material layer 524 in the second region 506 is lower than the surface of the first material layer 524 in the first region 504.

[0070] like Figure 5CAs shown, step S420 includes: forming a second material layer 526 in the first region 504 and the second region 506, wherein a surface of the second material layer 526 in the second region 506 is lower than a surface of the second material layer 526 in the first region 504; forming a third material layer 528 covering the second material layer 526 in the first region 504 and the second region 506, wherein a surface of the third material layer 528 in the second region 506 is lower than a surface of the third material layer 528 in the first region 504; forming a fourth material layer 530 covering the third material layer 528 in the first region 504 and the second region 506, wherein a surface of the fourth material layer 530 in the second region 506 is lower than a surface of the fourth material layer 530 in the first region 504.

[0071] In some embodiments, the material of the second material layer 526 may include silicon nitride material. In some embodiments, the thickness of the second material layer 526 may be about 300 angstroms.

[0072] In some embodiments, the material of the third material layer 528 and the material of the third electrode layer 520 may be the same or different. If the material of the third material layer 528 and the material of the third electrode layer 520 are the same, then in the same planarization process, the removal rate of the third material layer 528 and the removal rate of the third electrode layer 520 are the same; if the material of the third material layer 528 and the material of the third electrode layer 520 are different, then it is also necessary to consider using a material with a removal rate close to that of the third electrode layer 520 as the third material layer 528.

[0073] In some embodiments, the material of the third material layer 528 may include a carbon material. In some embodiments, the thickness of the third material layer 528 may be about 50 angstroms.

[0074] In some embodiments, the surface of the third material layer 528 in the second region 506 may be higher, equal to, or lower than the surface of the third electrode layer in the first region 504. For example, the height difference between the surface of the third material layer 528 in the second region 506 and the surface of the third electrode layer in the first region 504 may be ±50 angstroms.

[0075] Here, the fourth material layer 530 may be used as a protective layer for protecting the third material layer 528. In some embodiments, the material of the fourth material layer 530 may include a silicon oxide material.

[0076] It should be noted that at this time, the spin-coated insulating medium needs to be etched away in the chip area, and the space occupied by the spin-coated insulating medium is replaced by a silicon oxide layer. Therefore, in this step, a mask layer needs to be formed in both the chip area and the cutting road area, and the second material layer 526 can be, for example, a mask layer.

[0077] Here, before step S430, the method further includes: forming a fifth material layer in the first region 504 and the second region 506; wherein the surface of the fifth material layer in the second region 506 is higher than or equal to the surface of the fourth material layer 530 in the first region 504. Figure 5C As shown, before the fifth material layer is formed, the surface of the fourth material layer 530 in the first region 504 is higher than the surface of the fourth material layer 530 in the second region 506. Figure 5C The height difference between the surface of the fourth material layer 530 in the first region 504 and the surface of the fourth material layer 530 in the second region 506 is denoted as H1. After the fifth material layer covering the fourth material layer 530 in the first region 504 and the fourth material layer 530 in the second region 506 is formed, the surface of the fifth material layer in the first region 504 is also higher than the surface of the fifth material layer in the second region 506.

[0078] Here, the material of the fifth material layer may include a silicon oxide material.

[0079] Here, the process of forming the fifth material layer may include but is not limited to CVD, and the raw material of CVD is tetraethoxysilane (Tetraethyl Orthosilicate, TEOS).

[0080] It should be noted that the spin-coated insulating medium needs to be removed from the chip region at this time, and the space occupied by the spin-coated insulating medium is replaced by a silicon oxide layer. Therefore, in this step, a silicon oxide layer needs to be formed in both the chip region and the cutting path region, and the fifth material layer can be, for example, a silicon oxide layer.

[0081] like Figure 5D As shown, step S430 includes: performing a first planarization process on the first region 504 and the second region 506 to expose the surface of the second material layer 526 in the first region 504, and also expose the surface of the fifth material layer 538 in the second region 506; wherein the surface of the remaining fifth material layer 538 in the second region 506 is lower than the surface of the second material layer 526 in the first region 504. It should be noted that Figure 5D The complete morphology of the fifth material layer formed in the first region 504 and the second region 506 is not illustrated, and only the remaining portion of the fifth material layer 538 in the second region 506 after the first planarization process is illustrated.

[0082] Here, the first region 504 and the second region 506 are subjected to a first planarization treatment. In the first planarization treatment, the fifth material layer, the fourth material layer 530 and the third material layer 528 in the first region 504 need to be removed to expose the surface of the second material layer 526 in the first region 504; and part of the fifth material layer 538 in the second region 506 needs to be removed to expose the surface of the fifth material layer 538 in the second region 506.

[0083] Here, after the first planarization process, the surface of the second material layer 526 in the first region 504 is exposed, and the surface of the fifth material layer 538 in the second region 506 is also exposed, and the surface of the fifth material layer 538 is concave. Figure 5D The height difference between the surface of the second material layer 526 in the first region 504 and the surface of the fifth material layer 538 in the second region 506 is denoted as H2, and H2 Figure 5C and Figure 5D As shown, before the fifth material layer is formed and after the fifth material layer is formed and the first planarization process is performed, the height difference between the first region 504 and the second region 506 is reduced.

[0084] In some embodiments, the third material layer 528 may include a carbon material. In order to speed up the removal rate of the third material layer 528 in the first region 504, a double abrasive may be used to remove the third material layer 528 in the first region 504 in the first planarization process. Here, an oxidizing agent is added to the abrasive to form a double abrasive, so that the removal rate of the carbon material layer can be increased, and the removal rate of the carbon material layer by the double abrasive is greater than 50 angstroms / minute. Exemplarily, the oxidizing agent may be, for example, at least one of K2FeO4, KMnO4, and H2O2.

[0085] like Figure 5E As shown, step S430 also includes: performing a second planarization treatment on the first region 504 and the second region 506 to expose the surface of the third electrode layer 520 in the first region 504, and also expose the surface of the third material layer 528 in the second region 506; wherein the surface of the third material layer 528 in the second region 506 and the surface of the third electrode layer 520 in the first region 504 are substantially flush.

[0086] Here, the surface is basically flat means that the height difference between the surface of the third material layer 528 in the second region 506 and the surface of the third electrode layer 520 in the first region 504 along the Z direction is 0, or the height difference between the surface of the third material layer 528 in the second region 506 and the surface of the third electrode layer 520 in the first region 504 along the Z direction meets the process error range requirements.

[0087] ​Here, the first region 504 and the second region 506 are subjected to a second planarization treatment. In the second planarization treatment, the second material layer 526 and the mask layer 522 in the first region 504 need to be removed to expose the surface of the third electrode layer 520 in the first region 504; and the fifth material layer 538 and the fourth material layer 530 in the second region need to be removed to expose the surface of the third material layer 528 in the second region 506.

[0088] In some embodiments, in the second planarization process, the ratio between the removal rate of the second material layer 526 in the first region 504 and the removal rate of the third material layer 528 in the second region 506 is greater than 200. That is, in the second planarization process, the removal rate of the second material layer 526 in the first region 504 is much greater than the removal rate of the third material layer 528 in the second region 506, and damage to the third material layer 528 can be reduced during the removal of the second material layer 526.

[0089] Here, the surface flatness of the third material layer 528 in the second region 506 is good, that is, the surface of the third material layer 528 in the second region 506 is substantially flat. In some embodiments, after the first region 504 and the second region 506 are planarized, the surface flatness of the third material layer 528 in the second region 506 is less than 50 angstroms.

[0090] In some embodiments, in the second planarization process, the removal rate of the third material layer 528 in the second region 506 is substantially the same as the removal rate of the third electrode layer 520 in the first region 504. Here, after the second planarization process is performed, the surface of the third electrode layer 520 in the first region 504 is exposed, and the surface of the third material layer 528 in the second region 506 is also exposed.

[0091] Here, the removal rates being substantially the same means that the difference between the removal rate of the third material layer 528 in the second region 506 and the removal rate of the third electrode layer 520 in the first region 504 is 0, or that the difference between the removal rate of the third material layer 528 in the second region 506 and the removal rate of the third electrode layer 520 in the first region 504 is less than or equal to a preset difference.

[0092] Exemplarily, the materials of the third electrode layer 520 and the third material layer 528 may include carbon materials, the material of the second material layer 526 may include silicon nitride materials, and the materials of the fourth material layer 530 and the fifth material layer 538 may include silicon oxide materials. Here, in the planarization process, the removal rate of the carbon material layer is lower than the removal rate of the silicon oxide layer, and the removal rate of the carbon material layer is lower than the removal rate of the silicon nitride layer; the removal rate of the silicon nitride layer is lower than the removal rate of the silicon oxide layer.

[0093] In some embodiments, in the same planarization process, a ratio between a removal rate of the silicon nitride layer (or silicon oxide layer) and a removal rate of the carbon material layer is greater than 200.

[0094] In the disclosed embodiment, by forming a second material layer (e.g., a mask layer), a third material layer (e.g., a carbon material layer) and a fourth material layer (e.g., a silicon oxide layer), a third material layer with a high selectivity is deposited in the second region as a stop layer (Stop Layer) for subsequent planarization of the second material layer and the mask layer. Not only can the window for planarization of the second material layer be increased, but also the surface flatness of the third material layer in the second region can be improved, so that the overall flatness of the second region is less than 50 angstroms. In this way, it is beneficial to subsequently form an alignment mark on the third material layer in the second region to improve the alignment quality between the bottom word line and the top word line, thereby improving the yield of manufacturing semiconductor devices.

[0095] Here, in the first area of ​​the chip area and the cutting road area, the third electrode layer in the storage stack strip can be a carbon electrode layer, and the carbon electrode layer has a high selectivity, that is, the carbon electrode layer itself can be used as a stop layer in this area. In the process of removing the mask layer, the loss of the carbon electrode layer is less than 20 angstroms. Exemplarily, the selectivity of the silicon nitride layer or the silicon oxide layer to the carbon electrode layer exceeds 200, so in the process of removing the silicon nitride layer or the silicon oxide layer, the loss of the carbon electrode layer is very small. After the first material layer is subjected to the third planarization treatment, a second material layer (for example, a silicon nitride layer), a third material layer (for example, a carbon electrode layer) and a fourth material layer (for example, a silicon oxide layer) are formed, and combined with Figure 5C and Figure 5D As shown, after removing the silicon oxide layer in the first region, when contacting the third material layer (ie, the carbon material layer), dual slurry may be selected to remove the carbon material layer in the first region.

[0096] like Fig. 5F As shown, after step S430, the method further includes: forming a first conductive layer in the first region 504 and the second region 506; etching the first conductive layer and the storage stack bar 510 in sequence along the Z direction to form a second groove extending along the first direction (Y direction) in the first region 504, and forming a third groove extending along the Y direction in the second region 506. The etched first conductive layer in the first region 504 and the second region 506 forms a first conductive line 532 extending along the Y direction, and the etched storage stack bar 510 in the first region 504 forms a dummy storage unit 534. Here, the first region 504 is provided with dummy storage units 534 spaced apart in both the X direction and the Y direction, and the first conductive line 532 provided in the second region 506 is used as an alignment mark.

[0097] Here, the material of the first conductive layer may include a conductive material, such as a metal material. Exemplarily, the material of the first conductive layer may include metal tungsten.

[0098] Here, the first conductive lines 532 may also be referred to as dummy bottom word lines, which extend along the Y direction and are arranged at intervals along the X direction.

[0099] It should be noted that, at this time, a bottom word line is also provided in the chip region, and the bottom word line in the chip region and the dummy bottom word line in the cutting path region are formed simultaneously.

[0100] refer to 6A to 6H , 6A to 6H The cross-sectional view of the semiconductor structure during the manufacturing process provided by some embodiments. 6A to 6H , describing in detail the manufacturing methods of the semiconductor structures provided in other embodiments.

[0101] like Fig. 6A As shown, step S410 includes: providing a second conductive layer and a storage stack layer disposed on one side of the second conductive layer; forming a mask layer 622 on the storage stack layer; using the mask layer 622, sequentially etching the storage stack layer and the second conductive layer along the Z direction to form a first groove extending along the X direction in the first region 604, and removing the storage stack layer and the second conductive layer in the second region 606; wherein the etched second conductive layer in the first region 604 forms a second conductive line 608, and the etched storage stack layer in the first region 604 forms a storage stack bar 610. A first material layer 624 is formed in the first groove of the first region 604 and in the second region 606. Here, the storage stack bar 610 may include: a first electrode layer 612, a gating layer 614, a second electrode layer 616, a phase change layer 618, and a third electrode layer 620 sequentially stacked along the Z direction.

[0102] like Figure 6B As shown, step S410 includes: performing a third planarization process on the first region 604 and the second region 606 to expose the surface of the mask layer 622 in the first region 604. Here, the initial semiconductor structure 602 includes the first region 604 and the second region 606 disposed on at least one side of the first region 604, and the storage stack bar 610 (such as Figure 6B The first material layer 624 is provided between adjacent storage stacking strips 610 in the first area 604 and also in the second area 606, and the surface of the first material layer 624 in the second area 606 is lower than the surface of the first material layer 624 in the first area 604.

[0103] like Figure 6CAs shown, step S420 includes: forming a second material layer 626, a third material layer 628 and a fourth material layer 630 in the first region 604 and the second region 606 in sequence. For the relevant description of the second material layer 626, the third material layer 628 and the fourth material layer 630, please refer to FIG. 5A to FIG. 5F The relevant descriptions in the provided embodiments will not be repeated here.

[0104] like Fig.6D As shown, before step S430 , the method further includes: forming a photoresist layer 636 covering the fourth material layer 630 in the second region 606 .

[0105] like Fig. 6E As shown, before step S430, the method further includes: removing the fourth material layer 630 and the third material layer 628 in the first region 604 to expose the surface of the second material layer 626 in the first region 604; and removing the photoresist layer to expose the surface of the fourth material layer 630 in the second region 606. At this time, since the fourth material layer 630 in the second region 606 is protected by the photoresist layer, after removing the fourth material layer 630 and the third material layer 628 in the first region 604, the photoresist layer is removed, and at this time, the surface flatness of the fourth material layer 630 in the second region 606 is better.

[0106] Here, before step S430 , the method further includes: forming a fifth material layer in the first region 604 and the second region 606 ; wherein a surface of the fifth material layer in the second region 606 is higher than or equal to a surface of the second material layer 626 in the first region 604 .

[0107] refer to Fig. 6E As shown, before the fifth material layer is formed, the surface of the second material layer 626 in the first region 604 is higher than the surface of the fourth material layer 630 in the second region 606. Fig. 6E The height difference between the surface of the second material layer 626 in the first region 604 and the surface of the fourth material layer 630 in the second region 606 is denoted as H3. After forming the fifth material layer covering the second material layer 626 in the first region 604 and the fourth material layer 630 in the second region 606, the surface of the fifth material layer in the first region 604 is higher than the surface of the fifth material layer in the second region 606.

[0108] like Fig. 6FAs shown, step S430 includes: performing a first planarization process on the first region 604 and the second region 606 to expose the surface of the second material layer 626 in the first region 604, and also expose the surface of the fifth material layer 638 in the second region 606; wherein the surface of the fifth material layer 638 in the second region 606 is lower than the surface of the second material layer 626 in the first region 604. It should be noted that Fig. 6F The complete morphology of the fifth material layer formed in the first region 604 and the second region 606 is not illustrated, and only the remaining portion of the fifth material layer 638 in the second region 606 after the first planarization process is illustrated.

[0109] Will Fig. 6F The height difference between the surface of the second material layer 626 in the first region 604 and the surface of the fifth material layer 638 in the second region 606 is denoted as H4, and H4<H3. Fig. 6E and Fig. 6F As shown, before the fifth material layer is formed and after the fifth material layer is formed and the first planarization process is performed, the height difference between the first region 604 and the second region 606 is reduced.

[0110] Here, the first region 604 and the second region 606 are subjected to a first planarization treatment. In the first planarization treatment, it is necessary to remove the fifth material layer in the first region 604 to expose the surface of the second material layer 626 in the first region 604; and it is necessary to remove part of the fifth material layer 638 in the second region 606 to expose the fifth material layer 638 in the second region 606.

[0111] Compared to FIG. 5A to FIG. 5F In the illustrated embodiment, in the first planarization process, the fifth material layer, the fourth material layer and the third material layer in the first region need to be removed. 6A to 6H In the illustrated embodiment, the fourth material layer and the third material layer in the first region have been removed before the first planarization treatment; therefore, in the first planarization treatment, only the fifth material layer in the first region needs to be removed, thereby reducing the process difficulty of the first planarization treatment.

[0112] like Figure 6G As shown, step S430 further includes: performing a second planarization process on the first region 604 and the second region 606 to expose the surface of the third electrode layer 620 in the first region 604, and also expose the surface of the third material layer 628 in the second region 606; wherein the surface of the third material layer 628 in the second region 606 is substantially flush with the surface of the third electrode layer 620 in the first region 604. Here, the surface flatness of the third material layer 628 in the second region 606 is good, that is, the surface of the third material layer 628 in the second region 606 is substantially flat.

[0113] Here, the first region 604 and the second region 606 are subjected to a second planarization treatment. In the second planarization treatment, the second material layer 626 and the mask layer 622 in the first region 604 need to be removed to expose the surface of the third electrode layer 620 in the first region 604; and the fifth material layer 638 and the fourth material layer 630 in the second region need to be removed to expose the surface of the third material layer 628 in the second region 606.

[0114] In some embodiments, after the first region 604 and the second region 606 are planarized, the surface flatness of the third material layer 628 in the second region 606 is less than 50 angstroms.

[0115] like Figure 6H As shown, after step S430, the method further includes: forming a first conductive layer in the first region 604 and the second region 606; etching the first conductive layer and the memory stack bar 610 in sequence along the Z direction to form a second groove extending along the Y direction in the first region 604, and forming a third groove extending along the Y direction in the second region 606. The etched first conductive layer in the first region 604 and the second region 606 forms a first conductive line 632 extending along the Y direction, and the etched memory stack bar 610 in the first region 604 forms a dummy memory cell 634. Here, the first region 604 is provided with dummy memory cells 634 spaced apart in both the X direction and the Y direction, and the first conductive line 632 provided in the second region 606 is used as an alignment mark.

[0116] The disclosed embodiment provides a method for manufacturing a semiconductor structure. In the disclosed embodiment, the initial semiconductor structure includes a first region and a second region, and the surface of the first material layer in the second region is lower than the surface of the first material layer in the first region; a second material layer, a third material layer and a fourth material layer are formed in the first region and the second region; the first region and the second region are planarized, and since the removal rate of the third material layer is lower than the removal rate of the second material layer, after the planarization, the surface of the storage stack bar in the first region and the surface of the third material layer in the second region can be exposed. In this way, the window for planarization of the second material layer can be enlarged, and the surface flatness of the third material layer in the second region can be improved, which is conducive to the subsequent formation of alignment marks on the third material layer in the second region, so as to improve the alignment quality between the bottom word line and the top word line, thereby improving the yield of manufacturing semiconductor devices.

[0117] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0118] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing an initial semiconductor structure, comprising a first region and a second region disposed at least on one side of the first region, a memory stack bar disposed in the first region, and a first material layer disposed between adjacent memory stack bars in the first region and also disposed in the second region, wherein a surface of the first material layer in the second region is lower than a surface of the first material layer in the first region; forming a second material layer, a third material layer and a fourth material layer in the first region and the second region; The first region and the second region are planarized to expose the surface of the storage stack strip in the first region and also to expose the surface of the third material layer in the second region; wherein a removal rate of the third material layer in the second region is less than a removal rate of the second material layer in the first region.

2. The manufacturing method according to claim 1, characterized in that: After the first region and the second region are planarized, the method further includes: forming a first conductive layer in the first region and the second region; The first conductive layer and the storage stack strip are etched, and the first conductive layer after etching in the first area and the second area forms a first conductive line extending along a first direction, and the storage stack strip after etching in the first area forms a dummy storage unit; wherein the first conductive line arranged in the second area is used as an alignment mark.

3. The manufacturing method according to claim 1, characterized in that: Before performing the planarization process on the first region and the second region, the method further includes: forming a photoresist layer covering the fourth material layer in the second region; removing the fourth material layer and the third material layer in the first area to expose a surface of the second material layer in the first area; The photoresist layer is removed to expose the surface of the fourth material layer in the second region.

4. The manufacturing method according to claim 1 or 3, characterized in that: The surface of the fourth material layer in the second region is lower than the surface of the second material layer in the first region; Before performing the planarization process on the first region and the second region, the method further includes: A fifth material layer is formed in the first region and the second region; wherein a surface of the fifth material layer in the second region is higher than or equal to a surface of the second material layer in the first region.

5. The manufacturing method according to claim 4, characterized in that: The planarizing the first region and the second region comprises: The first region and the second region are subjected to a first planarization treatment to expose the surface of the second material layer in the first region and also expose the surface of the fifth material layer in the second region; wherein the surface of the fifth material layer in the second region is lower than the surface of the second material layer in the first region.

6. The manufacturing method according to claim 5, characterized in that: A dual abrasive is used in the process of removing the third material layer in the first region; wherein the dual abrasive includes an oxidation aid, and the oxidation aid includes at least one of K2FeO4, KMnO4 and H2O2.

7. The manufacturing method according to claim 5, characterized in that: The storage stack bar includes a first electrode layer, a gate layer, a second electrode layer, a phase change layer and a third electrode layer in sequence; the planarization process of the first region and the second region also includes: A second planarization treatment is performed on the first region and the second region to expose the surface of the third electrode layer in the first region and also expose the surface of the third material layer in the second region; wherein, in the second planarization treatment, the ratio between the removal rate of the second material layer in the first region and the removal rate of the third material layer in the second region is greater than 200.

8. The manufacturing method according to claim 1, characterized in that: After the planarization process is performed on the first region and the second region, the surface flatness of the third material layer in the second region is less than 50 angstroms.

9. The manufacturing method according to claim 2, characterized in that: The method of providing an initial semiconductor structure comprises: Providing a second conductive layer and a storage stack layer disposed on one side of the second conductive layer; Etching the storage stack layer and the second conductive layer to form a groove extending in the second direction in the first region, and removing the storage stack layer and the second conductive layer in the second region; wherein the second conductive layer after etching in the first region forms a second conductive line, and the storage stack layer after etching in the first region forms the storage stack bar; forming a first material layer in the groove of the first region and in the second region; A third planarization process is performed on the first region and the second region to expose the surface of the storage stack bar in the first region; wherein the first direction intersects with the second direction.

10. The manufacturing method according to claim 1, characterized in that: The first region and the second region are both disposed in a scribe line region.

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