Light detection device

Abstract

Provided is a light detection device that counts the number of pulses using a counter, in which picture quality is improved. The first sensor unit generates a first pulse signal according to incidence of photons. The second sensor unit generates a second pulse signal according to incidence of photons. The first counter performs counting synchronously with any one of a plurality of signals including the first pulse signal and the second pulse signal to obtain a count value, and outputs a first digital signal indicating the count value and a first carry flag indicating whether overflow occurs or not. The second counter performs counting synchronously with the first carry flag or the second pulse signal to obtain a count value, and outputs a second digital signal indicating the count value.

Description

Technical Field

[0001] The present technology relates to a light detection device, and more particularly to a light detection device that counts the number of photons. Background Art

[0002] Conventionally, in an imaging device or the like, a solid-state imaging element in which a plurality of pixels are arranged is used to capture image data. For example, a light detection device is proposed in which a single photon avalanche diode (SPAD), a waveform shaper for generating a pulse signal, and a counter for counting the number of pulses are provided for each pixel (for example, see Patent Document 1). In this light detection device, when one of the counters of two pixels is saturated, a composite signal of the pulse signals of the two pixels is counted using the other counter.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-140537 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above conventional technology, when one of the counters in two pixels is saturated, pixel addition is performed to ensure the linearity of the combined signal. However, in the above light detection device, the maximum count value of each pixel cannot be increased, and the dynamic range cannot be expanded. If the resolution of each counter of the pixel is increased, the dynamic range can be expanded and the image quality can be improved, but the circuit scale of the counter increases, which is not preferable.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the image quality in a photodetection device that counts the number of pulses using a counter.

[0009] Solution to the problem

[0010] The present technology is made to solve the above-mentioned problems. The first mode of the present invention is a light detection device, including: a first sensor unit, which generates a first pulse signal in response to the incidence of photons; a second sensor unit, which generates a second pulse signal in response to the incidence of photons; a first counter, which synchronously counts one of a plurality of signals including the first pulse signal and the second pulse signal to obtain a count value, and outputs a first digital signal indicating the count value and a first carry flag indicating whether an overflow occurs; and a second counter, which synchronously counts one of the first carry flag and the second pulse signal to obtain a count value, and outputs a second digital signal indicating the count value. Therefore, this brings about the effect of extending the resolution of the counter.

[0011] In addition, in the first aspect, the light detection device may further include: a first multiplexer that selects one of the first pulse signal and the second pulse signal and outputs the selected signal as a first output signal to the first counter; and a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs the selected one as a second output signal to the second counter. The first counter counts synchronously with the first output signal. The second counter counts synchronously with the second output signal. Therefore, an effect of counting the number of pulses synchronously with the output signal of the multiplexer is produced.

[0012] In addition, in the first aspect, the first multiplexer selects the first pulse signal when a low illumination mode in which the illumination does not exceed a predetermined value is set, and the first multiplexer alternately selects the first pulse signal and the second pulse signal when a high illumination mode in which the illumination is higher than a predetermined value is set. Therefore, this brings about the effect of extending the resolution of the counter under high illumination.

[0013] In addition, in the first aspect, the light detection device may further include a determiner that determines whether the illumination is higher than a predetermined value based on the first digital signal and the second digital signal, and sets one of a high illumination mode and a low illumination mode. Therefore, this brings about the effect of determining the brightness in the pixel.

[0014] Furthermore, in the first aspect, at least one of the first counter and the second counter outputs a specific bit of the digital signal to the determiner, and the determiner sets one of the high illumination mode and the low illumination mode based on the specific bit. Therefore, this brings about an effect of simplifying the determiner.

[0015] In addition, in the first aspect, the first sensor unit may be arranged in one of the first pixel and the second pixel of the same color among the plurality of pixels arranged in the pixel array unit, and the second sensor unit may be arranged in the other pixel of the first pixel and the second pixel. Therefore, this brings about the effect of suppressing the difference in the count value of each pixel.

[0016] In addition, in the first aspect, the light detection device may further include a microlens that guides incident light to a plurality of pixels of the same color including the first pixel and the second pixel. Therefore, this brings about an effect of facilitating detection of phase difference.

[0017] In addition, in the above-mentioned first aspect, it is also possible that the above-mentioned light detection device further includes: a control circuit that controls the first sensor unit and the second sensor unit. Each of the first sensor unit and the second sensor unit includes: an avalanche photodiode, and a recharge transistor that performs recharging to return the cathode potential of the avalanche photodiode to a predetermined potential. The control circuit controls the counting interval as an interval for performing recharging to be one of a plurality of intervals. In the case where the counting interval is a long interval longer than the predetermined interval, the first multiplexer selects the first pulse signal, and in the case where the counting interval is a short interval shorter than the predetermined interval, the first multiplexer alternately selects the first pulse signal and the second pulse signal. In the case where the counting interval is a long interval, the second multiplexer selects the second pulse signal, and in the case where the counting interval is a short interval, the second multiplexer selects the first carry flag. Therefore, this brings about the effect of reducing power consumption.

[0018] In addition, in the first aspect, the light detection device may further include: a determiner that determines whether the count of each of the first counter and the second counter is set to be valid in a period in which the count interval is one of a long interval and a short interval based on the first digital signal and the second digital signal. Each of the first sensor unit and the second sensor unit further includes a logic gate that turns off the recharge transistor when determining that the count is set to be invalid. Therefore, this brings about an effect of controlling the count to be valid or invalid according to the illuminance.

[0019] In addition, in the first aspect, the first sensor unit is arranged in one of the first pixel and the second pixel among the plurality of pixels arranged in the pixel array unit, and the second sensor unit is arranged in the other of the first pixel and the second pixel. The control circuit switches the count interval multiple times in a frame period for imaging one frame. The first multiplexer and the second multiplexer switch the selection target multiple times in the frame period. Therefore, this brings about the effect of reducing power consumption.

[0020] Furthermore, in the first aspect, the control circuit may sequentially select a plurality of rows of the pixel array unit and start exposure. Therefore, this brings about the effect of increasing the frame rate.

[0021] Furthermore, in the first aspect, the control circuit can select all pixels of the pixel array unit and start exposure at the same time when the frame period starts, and select all pixels and end exposure at the same time just before the frame period ends. Therefore, this brings about the effect of suppressing rolling shutter distortion.

[0022] Furthermore, in the first aspect, the control circuit may sequentially select a plurality of rows of the pixel array unit in a frame period and start exposure, thereby bringing about an effect of increasing the frame rate.

[0023] Furthermore, in the first aspect, the control circuit can select all pixels and end exposure at the same time in the frame period, switch the count interval after all pixel reading is completed, and then select all pixels and start exposure at the same time. Therefore, this brings about the effect of suppressing rolling shutter distortion.

[0024] In addition, in the first aspect, the control circuit can simultaneously select and expose one of the first row and the second row that share the signal line for transmitting the digital signal, and simultaneously select and expose the other of the first row and the second row during reading of one digital signal. Therefore, this brings about the effect of improving the frame rate.

[0025] In addition, in the above-mentioned first aspect, it can also be that the above-mentioned light detection device also includes: a first logic gate, which outputs the result of performing a logic operation on the first pulse signal and the second pulse signal as a first operation result; a first multiplexer, which selects one of a plurality of signals including the first pulse signal and the first operation result, and outputs the selected one to the first counter as a first output signal; and a second multiplexer, which selects one of the first carry flag and the second pulse signal, and outputs the selected one to the second counter as a second output signal. The first counter counts synchronously with the first output signal. The second counter counts synchronously with the second output signal. Therefore, this brings about the effect of enabling pixel addition.

[0026] In addition, in the above-mentioned first aspect, it is also possible that the above-mentioned light detection device further includes: a control circuit that controls the first sensor unit and the second sensor unit. Each of the first sensor unit and the second sensor unit includes: an avalanche photodiode, and a recharge transistor that performs recharging to return the cathode potential of the avalanche photodiode to a predetermined potential. The control circuit controls the counting interval as an interval for performing recharging to be one of a plurality of intervals. In the case where the counting interval is a long interval longer than the predetermined interval, the first multiplexer selects the first pulse signal, and in the case where the counting interval is a short interval shorter than the predetermined interval, the first multiplexer alternately selects the first pulse signal and the second pulse signal. In the case where the counting interval is a long interval, the second multiplexer selects the second pulse signal, and in the case where the counting interval is a short interval, the second multiplexer selects the first carry flag. Therefore, this brings about the effect of reducing power consumption.

[0027] In addition, in the first aspect, the light detection device may further include: a third sensor unit generating a third pulse signal in response to the incidence of a photon; a fourth sensor unit generating a fourth pulse signal in response to the incidence of a photon; a second logic gate outputting a result of performing a logic operation on the third pulse signal and the fourth pulse signal as a second operation result; a third logic gate outputting a result of performing a logic operation on the output of each of the first logic gate and the second logic gate as a third operation result; a third multiplexer outputting one of the following as a third output signal: a third pulse signal, a second operation result, and a second carry flag indicating whether an overflow has occurred; a third counter counting synchronously with the third output signal to obtain a count value and outputting a third digital signal indicating the count value and a third carry flag indicating whether an overflow has occurred; a fourth multiplexer outputting one of the third carry flag or the fourth pulse signal as a fourth output signal; and a fourth counter counting synchronously with the fourth output signal to obtain a count value and outputting a fourth digital signal indicating the count value. The first multiplexer selects one of the first pulse signal, the first operation result, and the third operation result. The second counter further generates a second carry flag. Therefore, this brings about an effect of enabling the addition of four pixels or two pixels.

[0028] In addition, in the first aspect, the first multiplexer selects the first pulse signal when a non-additive low illumination mode in which the illumination does not exceed a predetermined value is set, the first multiplexer alternately selects the first pulse signal and the first operation result when a non-additive high illumination mode in which the illumination is higher than a predetermined value is set, and selects the first operation result when the addition mode is set. The second multiplexer selects the second pulse signal when the non-additive low illumination mode is set, the second multiplexer selects the first carry flag when the non-additive high illumination mode is set, and selects the first carry flag when the addition mode is set. Therefore, this brings about the effect of extending the resolution of the counter under high illumination or pixel addition.

[0029] In addition, in the first aspect, part of the first sensor unit and part of the second sensor unit may be arranged on a predetermined pixel chip. The rest of the first sensing unit, the rest of the second sensing unit, and the first counter and the second counter may be arranged on a predetermined circuit chip. Therefore, this brings about the effect of facilitating the increase of the number of pixels.

[0030] In addition, in the first aspect, the light detection device may further include a control circuit that controls a plurality of pixels. The first sensor unit is arranged in one of the first pixel and the second pixel among the plurality of pixels, and the second sensor unit is arranged in another of the first pixel and the second pixel. The control circuit controls some of the plurality of pixels to generate a pulse signal. Therefore, this brings about the effect of reducing the reading time and the amount of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology.

[0032] Figure 2 : is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0033] Figure 3 is a circuit diagram showing a configuration example of a pixel block in the first embodiment of the present technology.

[0034] Figure 4 is a circuit diagram showing a configuration example of a counter in the first embodiment of the present technology.

[0035] Figure 5 : is a diagram showing an example of the operation of the control circuit in the first embodiment of the present technology.

[0036] Figure 6 : is a diagram illustrating an example of a state of a pixel block in a low illumination mode according to the first embodiment of the present technology.

[0037] Figure 7 : is a diagram showing an example of a state of a pixel block when the pixel A is exposed in the high illuminance mode according to the first embodiment of the present technology.

[0038] Figure 8 is a diagram illustrating an example of a state of a pixel block when the pixel B is exposed in the high illuminance mode according to the first embodiment of the present technology.

[0039] Fig. 9 : is a timing chart showing an example of the operation of the solid-state imaging element in the low illumination mode according to the first embodiment of the present technology.

[0040] Fig.10 : is a timing chart showing an example of the operation of the solid-state imaging element in the high illuminance mode according to the first embodiment of the present technology.

[0041] Fig.11 is a flowchart describing an example of the operation of the solid-state imaging element according to the first embodiment of the present technology.

[0042] Fig.12 is a circuit diagram showing a configuration example of a pixel block in a second embodiment of the present technology.

[0043] Fig.13 This is an example of a timing chart when switching from the low illuminance mode to the high illuminance mode in the second embodiment of the present technology.

[0044] Fig.14 This is an example of a timing chart when switching from the high illuminance mode to the low illuminance mode in the second embodiment of the present technology.

[0045] Fig.15 is a circuit diagram showing a configuration example of a pixel block in a third embodiment of the present technology.

[0046] Fig.16 This is an example of a timing chart when switching from the low illuminance mode to the high illuminance mode in the third embodiment of the present technology.

[0047] Fig.17 This is an example of a timing chart when switching from the high illuminance mode to the low illuminance mode in the third embodiment of the present technology.

[0048] Fig.18 : is a diagram showing an arrangement example of each pixel in a pixel block according to a fourth embodiment of the present technology.

[0049] Fig.19 : is a diagram showing an arrangement example of each pixel of a quad-Bayer array according to a fourth embodiment of the present technology.

[0050] Fig. 20 : is a diagram showing an arrangement example of each pixel in a pixel block according to a fifth embodiment of the present technology.

[0051] Fig.21 is a circuit diagram showing a configuration example of a pixel block in a sixth embodiment of the present technology.

[0052] Fig. 22 : is a diagram showing an example of the operation of the control circuit in the sixth embodiment of the present technology.

[0053] Fig.23 : is a timing chart showing an example of the operation of the solid-state imaging element in the long interval count period according to the sixth embodiment of the present technology.

[0054] Fig.24 : is a timing chart showing an example of the operation of the solid-state imaging element in the short-interval count period in the exposure period of the pixel A according to the sixth embodiment of the present technology.

[0055] Fig.25: is a timing chart showing an example of the operation of the solid-state imaging element in the exposure period of the pixel B in the short interval count period according to the sixth embodiment of the present technology.

[0056] Fig.26 : is a diagram illustrating an example of the operation of the control circuit in the modification example of the sixth embodiment of the present technology.

[0057] Fig. 27 is a circuit diagram showing a configuration example of a pixel block in a seventh embodiment of the present technology.

[0058] Fig.28 : is a timing chart showing an example of the operation of the solid-state imaging element in the exposure period of the pixel A in the short interval count period according to the seventh embodiment of the present technology.

[0059] Fig.29 : is a timing chart showing an example of the operation of the solid-state imaging element in the exposure period of the pixel B in the short interval count period according to the seventh embodiment of the present technology.

[0060] Fig.30 : is a timing chart showing an example of the operation of the solid-state imaging element in the long interval count period according to the seventh embodiment of the present technology.

[0061] Fig.31 : is a diagram illustrating an example of a counting interval in a 1 V period of a predetermined row according to the eighth embodiment of the present technology.

[0062] Fig.32 : is a timing chart showing an example of exposure and reading operations of the solid-state imaging element in the ninth embodiment of the present technology.

[0063] Fig.33 : is a timing chart showing an example of exposure and reading operations of the solid-state imaging element in the tenth embodiment of the present technology.

[0064] Fig.34 : is a timing chart showing an example of exposure and reading operations of the solid-state imaging element in the eleventh embodiment of the present technology.

[0065] Fig.35 : is a timing chart showing an example of exposure and reading operations of the solid-state imaging element in the twelfth embodiment of the present technology.

[0066] Fig.36 is a circuit diagram showing a configuration example of a pixel block in a thirteenth embodiment of the present technology.

[0067] Fig.37 : is a diagram showing an example of the operation of the control circuit in the thirteenth embodiment of the present technology.

[0068] Fig.38 is a circuit diagram showing a configuration example of a pixel block in a fourteenth embodiment of the present technology.

[0069] Fig.39 : is a timing chart showing an example of the operation of the solid-state imaging element in the addition mode according to the fourteenth embodiment of the present technology.

[0070] Fig.40 : is a diagram showing a configuration example of each pixel in a pixel block according to a fifteenth embodiment of the present technology.

[0071] Fig.41 is a circuit diagram showing a configuration example of a pixel block in a fifteenth embodiment of the present technology.

[0072] Fig.42 : is a diagram showing an example of the operation of the control circuit in the fifteenth embodiment of the present technology.

[0073] Fig.43 : is a diagram showing an example of the operation of the control circuit in the sixteenth embodiment of the present technology.

[0074] Fig.44 is a circuit diagram showing a configuration example of a pixel block in a seventeenth embodiment of the present technology.

[0075] Fig.45 is a circuit diagram showing another example of the pixel block in the seventeenth embodiment of the present technology.

[0076] Fig.46 : is a diagram illustrating an example of a region to be controlled according to an eighteenth embodiment of the present technology.

[0077] Fig.47 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0078] Fig.48 : is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0079] Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

[0080] 1. First Embodiment (Example of Extending the Counter under High Illuminance)

[0081] 2. Second Embodiment (Example of Determining Illuminance and Extension Counter)

[0082] 3. Third Implementation (Example Based on Specific Bit Extension Counter)

[0083] 4. Fourth Embodiment (Example of Expanding the Counter When Two Pixels of the Same Color Are at High Illuminance)

[0084] 5. Fifth Embodiment (Example of Extending the Counter When Two Pixels Under the Microlens Are at High Illumination)

[0085] 6. Sixth Embodiment (Example of Extending the Counter When the Count Interval is a Short Interval)

[0086] 7. Seventh Embodiment (Example of extending the counter at short intervals and setting the count to be valid or invalid)

[0087] 8. Eighth Embodiment (Example of Switching Count Intervals in One Frame and Extending Counters in Short Intervals)

[0088] 9. Ninth Embodiment (Example of Extending a Counter at Short Intervals Using a Rolling Shutter Method)

[0089] 10. Tenth Embodiment (Example of Extending the Counter at Short Intervals Using the Global Shutter Method at the Start and End of a Frame)

[0090] 11. Eleventh Embodiment (Example of Extending a Counter at Short Intervals Using a Global Shutter Method)

[0091] 12. Twelfth Embodiment (Example of Reading During Exposure Using Global Shutter Method and Extending Counter in Short Intervals)

[0092] 13. Thirteenth Embodiment (Example of Extending Counter During Pixel Addition Period)

[0093] 14. Fourteenth Embodiment (Example of Extending the Counter During Pixel Addition or When the Counter Interval is a Short Interval)

[0094] 15. Fifteenth Embodiment (Example of Extending Counter During Pixel Addition of Four Pixels)

[0095] 16. Sixteenth Embodiment (Example of Extending Counter During Pixel Addition or During High Illumination)

[0096] 17. Seventeenth Embodiment (Example of Reverse Extension under High Illumination Using a Laminated Structure)

[0097] 18. Eighteenth Embodiment (Example of Controlling Some Pixels and Enlarging Counters at High Illuminance)

[0098] 19. Application examples of mobile objects

[0099] <1. First Embodiment>

[0100] [Configuration Example of Imaging Device]

[0101] Figure 1 1 is a block diagram showing a configuration example of an imaging device 100 according to an embodiment of the present technology. The imaging device 100 captures image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. As the imaging device 100, for example, a smartphone, a digital camera, a personal computer, or a vehicle-mounted camera is assumed. In addition, the imaging element 100 is an example of a light detection device described in the claims.

[0102] The imaging lens 110 condenses incident light and guides the light to the solid-state imaging element 200. The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies the captured image data to the recording unit 120 via the signal line 209. The recording unit 120 records the image data.

[0103] The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. The imaging control unit 130 supplies, for example, a synchronization signal (such as a vertical synchronization signal) to the solid-state imaging element 200 via the signal line 139 .

[0104] Note that the imaging device 100 may further include an interface and transmit the image data to the outside via the interface, or may further include a display unit and display the image data on the display unit.

[0105] [Configuration example of solid-state imaging element]

[0106] Figure 2 1 is a block diagram showing a configuration example of the solid-state imaging element 200 in the first embodiment of the present technology. The solid-state imaging element 200 includes a control circuit 210, a pixel array unit 220, and a signal processing unit 230. These circuits are arranged on a single semiconductor chip.

[0107] A plurality of pixels are arranged in a two-dimensional lattice in the pixel array unit 220. Hereinafter, a group of pixels arranged in a predetermined direction such as a horizontal direction is referred to as a "row", and a group of pixels arranged in a direction perpendicular to the row is referred to as a column.

[0108] In addition, the pixel array unit 220 is divided into a plurality of pixel blocks 300. A plurality of pixels are arranged in each pixel block 300. For example, it is assumed that two pixels are arranged in a column direction in the pixel block 300. It should be noted that each pixel in the pixel block 300 may be arranged in a row direction or an oblique direction.

[0109] The control circuit 210 sequentially selects rows in synchronization with the vertical synchronization signal. The pixel counts the number of incident photons during the exposure period, and outputs a digital signal indicating the count value to the signal processing unit 230 as a pixel signal.

[0110] In addition, a mode signal MODE for specifying one of a plurality of modes including a high illumination mode and a low illumination mode is input to the control circuit 210. The high illumination mode is a mode in which the illumination is arranged at high illumination when the illumination is higher than a predetermined value, and the low illumination mode is a mode in which the illumination is arranged at low illumination when the illumination is equal to or lower than a predetermined value. A determination circuit that performs photometry to determine whether the illumination is higher than a predetermined value and sets a mode is arranged at a later stage of the pixel array unit 220 (such as the signal processing unit 230) in the solid-state imaging element 200 or outside the solid-state imaging element 200.

[0111] Note that the high illuminance mode and the low illuminance mode may also be set by a manual operation of the user. In this case, the determination circuit becomes unnecessary.

[0112] The signal processing unit 230 performs various types of signal processing on the image data (frame) in which the pixel signals are arranged, and outputs the processed frame to the recording unit 120 .

[0113] [Pixel configuration example]

[0114] Figure 3 3 is a circuit diagram showing a configuration example of a pixel block 300 in the first embodiment of the present technology. In the pixel block 300, pixels 301 and 302 are arranged. The pixel 301 includes a sensor unit 310, a multiplexer 351, and a counter 360. The pixel 302 includes a sensor unit 330, a multiplexer 352, and a counter 370.

[0115] The sensor unit 310 includes pMOS transistors 311 and 312, a SPAD 313, and a pulse shaping unit 314. The pMOS transistors 311 and 312 are connected in series between the cathode of the SPAD 313 and the power supply voltage VDD, with the pMOS transistor 311 as the power supply side. The enable signal EN-A from the control circuit 210 is input to the gate of the pMOS transistor 311, and a predetermined bias voltage BIAS is applied to the gate of the pMOS transistor 312.

[0116] When the enable signal EN_A is at a low level, the pixel 301 is enabled, and the cathode potential of the SPAD 313 decreases in response to the incidence of photons. On the other hand, when the enable signal EN-A is at a high level, the pixel 301 is disabled, and the cathode potential does not decrease even if photons are incident.

[0117] The pulse shaping unit 314 detects the drop of the cathode potential of the SPAD 313 , shapes the waveform, and generates a pulse signal PLS_A. The pulse shaping unit 314 supplies the pulse signal PLS_A to the multiplexer 351 .

[0118] The sensor unit 330 includes pMOS transistors 331 and 332, a SPAD 333, and a pulse shaping unit 334, and its circuit configuration is similar to that of the sensor unit 310. However, an enable signal EN_B from the control circuit 210 is input to the gate of the pMOS transistor 331, and the pulse shaping unit 334 generates a pulse signal PLS_B and provides the pulse signal PLS_B to the multiplexers 351 and 352.

[0119] The multiplexer 351 selects one of the pulse signals PLS_A and PLS_B according to the selection signal IN_SEL from the control circuit 210, and outputs the selected one as the output signal OUT_A to the counter 360. For example, the pulse signal PLS_A is selected when the selection signal IN_SEL is "1", and the pulse signal PLS_B is selected when the selection signal IN_SEL is "0".

[0120] The counter 360 counts synchronously with the output signal OUT_A to obtain a count value, and outputs a digital signal CNT_A indicating the count value to the signal processing unit 230. In addition, the counter 360 generates a carry flag CF indicating whether the count result exceeds the range that the digital signal CNT_A can represent (i.e., an overflow has occurred), and outputs the carry flag CF to the multiplexer 352.

[0121] The multiplexer 352 selects one of the pulse signal PLS_B and the carry flag CF according to the selection signal CNT_SEL from the control circuit 210, and outputs the selected one as the output signal OUT_B to the counter 370. For example, the carry flag CF is selected when the selection signal CNT_SEL is "1", and the pulse signal PLS_B is selected when the selection signal CNT_SEL is "0".

[0122] The counter 370 counts in synchronization with the output signal OUT_B to obtain a count value, and outputs a digital signal CNT_B indicating the count value to the signal processing unit 230 .

[0123] In summary, the sensor unit 310 generates a pulse signal PLS_A in response to the incidence of photons. The sensor unit 330 generates a pulse signal PLS_B in response to the incidence of photons. The multiplexer 351 selects one of the pulse signals PLS_A and PLS_B, and outputs the selected one as the output signal OUT_A to the counter 360. The counter 360 counts synchronously with the output signal OUT_A to obtain a count value, and outputs a digital signal CNT_A indicating the count value and a carry flag CF indicating whether an overflow has occurred.

[0124] Furthermore, the multiplexer 352 selects one of the pulse signal PLS_B and the carry flag CF and outputs the selected one as the output signal OUT_B to the counter 370. The counter 370 counts a count value in synchronization with the output signal OUT_B and outputs a digital signal CNT_B indicating the count value.

[0125] It is noted that the sensor units 310 and 330 are examples of the first sensor unit and the second sensor unit described in the claims. The multiplexers 351 and 352 are examples of the first multiplexer and the second multiplexer described in the claims. It is noted that the counters 360 and 370 are examples of the first counter and the second counter described in the claims.

[0126] In addition, although two pixels are arranged in the pixel block 300, three or more pixels may be arranged. In this case, a sensor unit, a multiplexer, and a counter are added according to the number of pixels. In addition, when the number of pixels is M (M is an integer), the carry flag of the m_th (m is an integer from 0 to M-1) counter is input to the (m+1)th counter via the (m+1)th multiplexer.

[0127] [Configuration example of counter]

[0128] Figure 4 360 and 370 in the first embodiment of the present technology. The counter 360 includes flip-flops 361 to 364 , and the counter 370 includes flip-flops 371 to 374 .

[0129] Each of the flip-flops 361 to 364 keeps an input signal input to the input terminal D in synchronization with a signal input to the clock terminal, and outputs the input signal from the output terminal Q.

[0130] The output signal OUT_A from the multiplexer 351 is input to the clock terminal of the flip-flop 361. In addition, the inverting output terminal xQ of the flip-flop 361 is connected to the input terminal D and the clock terminal of the flip-flop 362. The inverting output terminal xQ of the flip-flop 362 is connected to the input terminal D and the clock terminal of the flip-flop 363. The inverting output terminal xQ of the flip-flop 363 is connected to the input terminal D and the clock terminal of the flip-flop 364. The inverting output terminal xQ of the flip-flop 364 is connected to its input terminal D. In addition, the carry flag CF is output from the inverting output terminal xQ of the flip-flop 364 to the multiplexer 352.

[0131] The bits from the output terminals Q of the flip-flops 361 to 364 are output as the first to fourth bits of the digital signal CNT_A.

[0132] The circuit configuration of the counter 370 is similar to that of the counter 360, except that the carry flag CF is not output.

[0133] Note that although the resolution of the counters 360 and 370 is 4 bits, the resolution of these counters is not limited to 4 bits. In addition, the circuit configuration of each of the counters 360 and 370 is not limited to the circuit configuration illustrated in the drawings as long as it can count in synchronization with the signals from the multiplexers 351 and 352.

[0134] [Operation Example of Solid-State Imaging Element]

[0135] Figure 5 1 is a diagram showing an example of the operation of the control circuit 210 in the first embodiment of the present technology. One of two pixels (pixels 301 and 302) in the pixel block 300 is defined as pixel A, and the other pixel is defined as pixel B.

[0136] In the case of setting the low illumination mode, the control circuit 210 sets the selection signal IN_SEL to "1" and the selection signal CNT_SEL to "0". Therefore, the pulse signal PLS_A is selected in the pixel A, and the pulse signal PLS_B is selected in the pixel B. In addition, the control circuit 210 sets both the enable signals EN_A and EN_B to "0" (i.e., enabled). With these controls, both pixels A and B are exposed.

[0137] On the other hand, in the case of setting the high illumination mode, only one of the pixels A and B is exposed, and the exposure target is switched at regular time intervals. During the exposure period of pixel A, the control circuit 210 sets the selection signal IN_SEL to "1" and sets the selection signal CNT_SEL to "1". Therefore, the pulse signal PLS_A is selected in pixel A, and the carry flag CF is selected in pixel B. In addition, the control circuit 210 sets the enable signal EN_A to "0" (enabled), and sets the enable signal EN_B to "1" (i.e., disabled).

[0138] In addition, during the exposure period of pixel B, the control circuit 210 sets the selection signal IN_SEL to "0" and sets the selection signal CNT_SEL to "1". Therefore, the pulse signal PLS_B is selected in pixel A, and the carry flag CF is selected in pixel B. In addition, the control circuit 210 sets the enable signal EN_A to "1" (disabled) and sets the enable signal EN_B to "0" (enabled).

[0139] Figure 6is a diagram showing an example of the state of the pixel block 300 in the low illumination mode according to the first embodiment of the present technology. When the low illumination mode is set, the multiplexer 351 selects the pulse signal PLS_A, and the multiplexer 352 selects the pulse signal PLS_B. In addition, the counter 360 counts synchronously with the output signal OUT_A (i.e., the pulse signal PLS_A), and the counter 370 counts synchronously with the output signal OUT_B (i.e., the pulse signal PLS_B). As described above, in the low illumination mode, the number of pulses of the pixel is counted for each pixel. When the resolution of the counter of each pixel is N (N is an integer) bits, the maximum value of each count value is 2 N .

[0140] Figure 7 3 is a diagram showing an example of a state of a pixel block when a pixel A is exposed in a high illumination mode according to the first embodiment of the present technology. In the high illumination mode, the multiplexer 351 selects the pulse signal PLS_A during the exposure period of the pixel A, and the multiplexer 352 selects the carry flag CF from the counter 360. In addition, the counter 360 counts synchronously with the output signal OUT_A (pulse signal PLS_A), and the counter 370 counts synchronously with the output signal OUT_B (i.e., the carry flag CF).

[0141] Figure 8 3 is a diagram showing an example of a state of a pixel block when exposing a pixel B in a high illumination mode according to the first embodiment of the present technology. In the high illumination mode, the multiplexer 351 selects the pulse signal PLS_B during the exposure period of the pixel B, and the multiplexer 352 selects the carry flag CF from the counter 360. In addition, the counter 360 counts synchronously with the output signal OUT_A (pulse signal PLS_B), and the counter 370 counts synchronously with the output signal OUT_B (ie, the carry flag CF).

[0142] like Figure 6 and Figure 7 As shown in , when the high illumination mode is set, counters 360 and 370 are connected in series, and when an overflow occurs in the counter 360 in the previous stage, the counter 370 in the subsequent stage performs counting. In this way, under high illumination, counters 360 and 370 are shared by two pixels in the pixel block 300.

[0143] Under high illumination, the signal processing unit 230 acquires a 2N-bit digital signal for each of the pixels A and B, wherein the output of the counter 360 (digital signal CNT_A) is set to a higher bit string, and the output of the counter 370 (digital signal CNT_B) is set to a lower bit string. Under high illumination when the counting frequency is high, the resolution of the counter of each pixel is extended to 2N bits, and the maximum value of each count value is extended to 2 2N Therefore, the dynamic range can be expanded under high illumination, and the image quality of the image data can be improved.

[0144] Fig. 9 1 is a timing chart showing an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology in the low illuminance mode. It is assumed that the low illuminance mode is set at time T0.

[0145] The control circuit 210 sets the enable signals EN_A and EN_B to a high level, sets the selection signal IN_SEL to a high level, and sets the selection signal CNT_SEL to a low level. A pulse signal PLS_A is generated at a timing T1, etc., and the counter 360 counts up the digital signal CNT_A in synchronization with the pulse signal. A pulse signal PLS_B is generated at a timing T2, etc., and the counter 370 counts up the digital signal CNT_B in synchronization with the pulse signal. As shown in the figure, in the low illumination mode, two pixels are exposed at the same time, and the number of pulses is counted in parallel in each pixel.

[0146] Fig.10 1 is a timing diagram showing an example of the operation of the solid-state imaging element in the high illumination mode according to the first embodiment of the present technology. It is assumed that the high illumination mode is set at time T10. It is assumed that the pixel A is exposed in the period from time T10 to time T12, and the pixel B is exposed in the period from time T12 to time T14. Similarly, after timing T14, the pixels A and B are exposed alternately.

[0147] In the period from timing T10 to timing T12, the control circuit 210 sets the enable signal EN_A to a high level and sets the enable signal EN_B to a low level. In addition, the control circuit 210 sets the selection signals IN_SEL and CNT_SEL to a high level. After time T10, the pulse signal PLS_A is generated, and the counter 360 counts up the digital signal CNT_A in synchronization with the pulse signal.

[0148] Then, when the digital signal CNT_A overflows at the timing T11 , the counter 370 counts up the digital signal CNT_B in synchronization with the carry flag.

[0149] Then, in the time period from timing T12 to timing T14, the control circuit 210 sets the enable signal EN_A to a low level and sets the enable signal EN_B to a high level. In addition, the control circuit 210 sets the selection signal IN_SEL to a low level and sets the selection signal CNT_SEL to a high level. After timing T12, the pulse signal PLS_B is generated, and the counter 360 counts up the digital signal CNT_A in synchronization with the pulse signal.

[0150] Then, when the digital signal CNT_A overflows at timing T13 , the counter 370 counts up the digital signal CNT_B in synchronization with the carry flag.

[0151] Fig.11 1 is a flowchart describing an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, when the low illumination mode is set, the operation is started.

[0152] In all pixels, a counter in the pixel counts the number of pulses (step S901). The signal processing unit 230 performs signal processing to generate a frame (step S902).

[0153] A circuit outside the pixel (such as the signal processing unit 230) determines whether the illuminance is high based on the frame (step S903). For example, when the total value or average value of the count values ​​of all pixels is equal to or greater than a threshold value, it is determined that the illuminance is high.

[0154] In a case where the illuminance is not high (step S903 : No), the solid-state imaging element 200 sets the low illuminance mode and executes step S901 and subsequent steps.

[0155] On the other hand, when the illumination is high (step S903: Yes), the solid-state imaging element 200 sets the high illumination mode, and the counter in pixel A counts the number of pulses in pixel A (step S904). Next, in pixel B, the counter in the pixel counts the number of pulses (step S905). The signal processing unit 230 performs signal processing to generate a frame (step S906). After step S906, the solid-state imaging element 200 repeatedly performs step S903 and subsequent steps.

[0156] Note that the solid-state imaging element 200 determines whether the illuminance is high for each frame, but is not limited to this configuration, and may also determine whether the illuminance is high when two or more frames are imaged after mode switching.

[0157] As described above, according to the first embodiment of the present technology, since the counter 370 counts in synchronization with the carry flag from the counter 360 in the high illuminance mode, the dynamic range can be expanded under high illuminance.

[0158] <2. Second Embodiment>

[0159] In the first embodiment described above, it is determined whether the circuit outside the pixel has high illumination, but the determination can be performed in the pixel. The solid-state imaging element 200 according to the second embodiment is different from the solid-state imaging element of the first embodiment in that the determiner for determining whether the illumination is high is arranged in the pixel block 300.

[0160] Fig.12 2 is a circuit diagram showing a configuration example of a pixel block 300 in a second embodiment of the present technology. The pixel block 300 of the second embodiment is different from the first embodiment in that a determiner 380 is further provided. The determiner 380 is shared by two pixels in the pixel block 300.

[0161] The digital signals CNT_A and CNT_B from the counters 360 and 370 are input to the determiner 380. The determiner 380 determines whether the illuminance is high based on the digital signals.

[0162] (1) For example, the determiner 380 calculates the total value or average value of the count values ​​of all pixels or some representative pixels (pixels near the center, etc.) in the pixel block 300, determines that the illuminance is high when the total value or the average value is equal to or greater than a threshold, and determines that the illuminance is low when the total value or the average value is less than the threshold.

[0163] (2) Alternatively, the determiner 380 determines for each pixel whether the count value is equal to or greater than a threshold value, and determines the illuminance based on the result.

[0164] (2-1) In the determination method (2), for example, when the number of pixels having count values ​​equal to or greater than the threshold is equal to or greater than the number of pixels having count values ​​less than the threshold, the determiner 380 determines that the illuminance is high.

[0165] (2-2) Alternatively, when the number of pixels whose count values ​​are smaller than the threshold value is equal to or larger than the number of pixels whose count values ​​are equal to or larger than the threshold value, the determiner 380 determines that the illuminance is low.

[0166] (2-3) Alternatively, when the number of pixels whose count value is equal to or greater than the threshold value is one or more, the determiner 380 determines that the illuminance is high.

[0167] (2-4) Alternatively, when the number of pixels whose count values ​​are smaller than the threshold value is one or more, the determiner 380 determines that the illuminance is low.

[0168] The determiner 380 controls the enable signals EN_A and EN_B and the selection signals IN_SEL and CNT_SEL based on the determination result. The control method of these signals is similar to that of the first embodiment.

[0169] As shown in the drawing, since it is determined whether each pixel block 300 has high illuminance, appropriate control according to the illuminance of each pixel can be performed.

[0170] Fig.13 is an example of a timing diagram when switching from the low illumination mode to the high illumination mode in the second embodiment of the present technology. It is assumed that the above (2-3) is used as a method for determining whether the illumination is high. It is assumed that the low illumination mode is set for the focused pixel block 300, and the count value (CNT_B) of the pixel B becomes equal to or greater than the threshold value at time T0.

[0171] The determiner 380 determines that the illuminance is high, and switches to the high illuminance mode at timing T1 after reading the count value. In the high illuminance mode, the pixel A is exposed from time T1 to time T2, and the pixel B is exposed after time T2. Note that the illuminance is also determined individually for each pixel block in the pixel blocks other than the focused pixel block.

[0172] Fig.14 3 is an example of a timing diagram when switching from a high illumination mode to a low illumination mode in the second embodiment of the present technology. Assume that the high illumination mode is set for the focused pixel block 300, and the corresponding count values ​​(CNT_A and CNT_B) of pixels A and B are both less than the threshold value. The determiner 380 determines that the illumination is low, and switches to the low illumination mode at timing T10.

[0173] As described above, according to the second embodiment of the present technology, since the determiner 380 in the pixel block 300 determines whether the illuminance is high, appropriate control can be performed according to the illuminance of each pixel block 300 .

[0174] <3. Third Embodiment>

[0175] In the above-mentioned second embodiment, the determiner 380 compares the count value with the threshold value. However, in this configuration, when the resolution of the counters 360 and 370 is high, the circuit scale of the determiner 380 may increase. The solid-state imaging element 200 according to the third embodiment is different from the solid-state imaging element of the second embodiment in that the determiner 380 determines whether the illuminance is high based on a specific bit of the digital signal.

[0176] Fig.15 3 is a circuit diagram showing a configuration example of a pixel block 300 in a third embodiment of the present technology. The pixel block 300 of the third embodiment is different from the pixel block 300 of the second embodiment in that counters 360 and 370 supply specific bits of digital signals to a determiner 380 .

[0177] When the threshold value compared with the count value is 2 n(n is an integer) and counters 360 and 370 are binary counters, the n-th bit QAn and QBn are output. Determiner 380 determines whether the illumination is high based on the bit. Determines whether the count value is equal to or greater than threshold value 2 based on whether each of QAn and QBn is "1". n .

[0178] Since it is sufficient to determine whether the bits QAn and QBn are "1", the circuit scale of the determiner 380 can be reduced compared to the first embodiment. In addition, the number of wirings from the counters 360 and 370 to the determiner 380 can be reduced compared to the second embodiment.

[0179] It should be noted that the counters 360 and 370 may provide high-order bits (such as high-order 2 bits of 4 bits) instead of specific bits to the determiner 380, and the determiner 380 may make a determination based on these bits.

[0180] Fig.16 is an example of a timing diagram when switching from the low illumination mode to the high illumination mode in the third embodiment of the present technology. It is assumed that the above (2-3) is used as a method for determining whether the illumination is high. It is assumed that the low illumination mode is set for the focused pixel block 300, and for the count value (CNT_B) of the pixel B, QAn becomes "1" at time T0.

[0181] Because the count value has become equal to or greater than the threshold 2 n , so the determiner 380 determines that the illuminance is high, and switches to the high illuminance mode at timing T1 after reading the count value. In the high illuminance mode, the pixel A is exposed from time T1 to time T2, and the pixel B is exposed after time T2.

[0182] Fig.17 is an example of a timing diagram when switching from high illumination mode to low illumination mode in the third embodiment of the present technology. Assume that the high illumination mode is set for the focused pixel block 300, and both QAn and QBn are "0". Because all count values ​​are less than the threshold value 2 n , so the determiner 380 determines that the illuminance is low, and switches to the low illuminance mode at timing T10.

[0183] As described above, according to the third embodiment of the present technology, since the determiner 380 determines whether the illuminance is high based on specific bits from the counters 360 and 370 , the circuit scale of the determiner 380 can be reduced compared to the second embodiment.

[0184] <4. Fourth Embodiment>

[0185] In the above-mentioned first embodiment, the two pixels of the shared counters 360 and 370 are arranged adjacent to each other in the column direction. However, in the case where the two pixels are arranged in a Bayer array, the colors of the color filters of the two pixels adjacent to each other in the column direction are different from each other. However, since the transmittance for each color of the color filter is different, in the case of the shared counters 360 and 370, it is preferred that the two pixels in the pixel block 300 have the same color. The solid-state imaging element 200 according to the fourth embodiment is different from the solid-state imaging element of the first embodiment in that pixels of the same color are arranged in the pixel block 300.

[0186] Fig.18 2 is a circuit diagram showing an example of the arrangement of each pixel in the pixel block 300 according to the fourth embodiment of the present technology. In the pixel array unit 220, a plurality of pixels are arranged in a Bayer array. In addition, a color filter (not shown) and a microlens (not shown) are arranged for each pixel. The color filter transmits any color of red, green and blue. The pixels in which the color filters of each color are arranged are respectively referred to as r pixels, g pixels and b pixels. In the Bayer array, in 2 rows × 2 columns, two g pixels are arranged in an oblique direction, and r pixels and b pixels are arranged in the remaining part.

[0187] For example, r pixel 303 , g pixel, r pixel 304 and g pixel are arranged in the column direction. Sensor unit 310 , multiplexer 351 and counter 360 are arranged in r pixel 303 , and sensor unit 330 , multiplexer 352 and counter 370 are arranged in r pixel 304 .

[0188] As shown in the figure, since two pixels of the same color are arranged in the pixel block 300 , the count value of each pixel may be set to the same level.

[0189] It should be noted that Fig.19 As shown, in the quad-Bayer array, two pixels of the same color may be arranged in the pixel block 300 .

[0190] Note that the second or third embodiment can be applied to the fourth embodiment. In this case, since the count value of each pixel can be made similar, the determiner 380 can accurately determine the illuminance.

[0191] As described above, according to the fourth embodiment of the present technology, since two pixels have the same color in the pixel block 300 , the count value of each pixel can be set to the same level.

[0192] <5. Fifth embodiment>

[0193] In the fourth embodiment described above, a microlens is arranged for each pixel. However, in order to realize image plane phase difference autofocus (AF) in this configuration, in addition to r pixels, g pixels, and b pixels, it is necessary to further arrange pixels for phase difference detection. The solid-state imaging element 200 in the fifth embodiment is different from the solid-state imaging element 200 in the fourth embodiment in that a plurality of pixels are arranged just below the microlens.

[0194] Fig. 20 300 in the fifth embodiment of the present technology. In the fifth embodiment, the pixels are arranged in a four-Bayer array. In addition, for every four adjacent pixels of the same color, a microlens 221 is arranged to guide incident light to those pixels. Multiple pixels (such as r pixels 303 and 304) under the microlens 221 share counters 360 and 370.

[0195] A circuit (such as the signal processing unit 230) at the subsequent stage of the pixel detects the distance between the corresponding peaks of the image of the pixel signal on the left side (or upper side) where each of the microlenses 221 is arranged and the image of the pixel signal on the right side (or lower side) where each of the microlenses is arranged as a phase difference. A focus lens (not shown) is driven according to the phase difference. Therefore, image plane phase difference AF can be realized without arranging pixels for phase difference detection.

[0196] Note that the second or third embodiment can be applied to the fifth embodiment.

[0197] As described above, according to the fifth embodiment of the present technology, since two pixels sharing the counters 360 and 370 are arranged below the microlens 221 , image plane phase difference AF can be easily realized.

[0198] <6. Sixth Implementation>

[0199] In the first embodiment described above, the count interval of the pulse signal is constant, but the count interval may be switched during imaging. The solid-state imaging element 200 according to the sixth embodiment differs from that of the first embodiment in that the count interval is switched during imaging.

[0200] Fig.21 3 is a circuit diagram showing a configuration example of a pixel block 300 in a sixth embodiment of the present technology. In the sixth embodiment, a sensor unit 310 includes a recharge transistor 321, a clamp transistor 322 (clip transistor), a SPAD 313, pMOS transistors 323 and 324, an nMOS transistor 325, and a buffer 326.

[0201] Furthermore, the sensor unit 330 includes a recharge transistor 341 , a clamp transistor 342 , a SPAD 333 , pMOS transistors 343 and 344 , an nMOS transistor 345 , and a buffer 346 .

[0202] The recharge transistor 321 and the clamp transistor 322 are connected in series between the cathode of the SPAD 313 and the power supply voltage VDD with the recharge transistor 321 as the power supply side.

[0203] The recharge transistor 321 performs charging to return the cathode potential of the SPAD 313 to the power supply voltage VDD according to the control signal XRE_A from the control circuit 210. The counting interval as the interval for performing recharge is controlled by the control circuit 210. In the case where there is incidence of one or more photons within this counting interval, one pulse is generated.

[0204] The clamp transistor 322 disconnects the SPAD 313 from the connection node of the recharge transistor 321 and the clamp transistor 322 according to the control signal CLP_A from the control circuit 210. The SPAD 313 is disconnected from the connection node immediately before the recharge starts, and the SPAD 313 is connected to the node during the recharge period. The clamp transistor 322 can reduce the cathode capacitance.

[0205] The pMOS transistors 323 and 324 and the nMOS transistor 325 are connected in series between the power supply voltage VDD and the ground node with the pMOS transistor 323 as the power supply side and the nMOS transistor 325 as the ground side. The control signal INI_A from the control circuit 210 is input to the gates of the pMOS transistor 323 and the nMOS transistor 325. In addition, the gate of the pMOS transistor 324 is connected to the connection node between the recharge transistor 321 and the clamp transistor 322.

[0206] The buffer 326 outputs a signal of the potential of the connection node between the pMOS transistor 324 and the nMOS transistor 325 as a pulse signal PLS_A to the multiplexer 351. Note that, instead of the buffer 326, two-stage inverters may be inserted.

[0207] The circuit configuration of the sensor unit 330 is similar to that of the sensor unit 310. However, control signals XRE_B, CLP_B, and INI_B are input.

[0208] The control circuit 210 controls the count interval to be a long interval longer than a predetermined time or a short interval equal to or less than a predetermined time. By switching the count interval during imaging, the number of pulses can be counted even when the frequency of light is higher than that in the first embodiment. In addition, when the frequency is the same, the count value can be made smaller than the count value of the first embodiment. Therefore, the bit depth and power consumption of the digital signal can be reduced.

[0209] Fig. 22 is a diagram showing an example of the operation of the control circuit 210 in the sixth embodiment of the present technology. When the count interval is set to a long interval, the control circuit 210 sets the selection signal IN_SEL to "1" and sets the selection signal CNT_SEL to "0". Therefore, the pulse signal PLS_A is selected in the pixel A, and the pulse signal PLS_B is selected in the pixel B. In addition, the control circuit 210 sets both the enable signals EN_A and EN_B to "0" (enabled). With these controls, both pixels A and B are exposed.

[0210] On the other hand, when the count interval is set to a short interval, only one of pixels A and B is exposed, and the exposure target is switched at regular time intervals. During the exposure period of pixel A, the control circuit 210 sets the selection signal IN_SEL to "1" and sets the selection signal CNT_SEL to "1". Therefore, the pulse signal PLS_A is selected in pixel A, and the carry flag CF is selected in pixel B. In addition, the control circuit 210 sets the enable signal EN_A to "0" (enabled), and sets the enable signal EN_B to "1" (disabled).

[0211] In addition, during the exposure period of pixel B, the control circuit 210 sets the selection signal IN_SEL to "0" and sets the selection signal CNT_SEL to "1". Therefore, the pulse signal PLS_B is selected in pixel A, and the carry flag CF is selected in pixel B. In addition, the control circuit 210 sets the enable signal EN_A to "1" (disabled) and sets the enable signal EN_B to "0" (enabled).

[0212] Fig.23 1 is a timing diagram showing an example of the operation of the solid-state imaging element 200 in the long interval counting period according to the sixth embodiment of the present technology. In the period from timing T0 to timing T1, the counting interval is controlled to be a long interval. In a predetermined time period from timing T0, the control signal XRE_A is controlled to a low level, and the first recharge is performed. In addition, the second and third charges are performed at times T11 and T12. Thereafter, recharging is repeated periodically. The recharge interval (i.e., the counting interval) is controlled to be a long interval.

[0213] In the period from the timing T0 to the timing T1, the control circuit 210 sets the selection signal IN_SEL to the high level and sets the selection signal CNT_SEL to the low level. Therefore, when a photon is incident in each counting interval, the digital signals CNT_A and CNT_B count up.

[0214] Fig.24 1 is a timing diagram showing an example of the operation of the solid-state imaging element in the short interval counting period during the exposure period of pixel A according to the sixth embodiment of the present technology. After timing T1, the counting interval is controlled to be a short interval. Note that the short interval counting period is controlled to be, for example, 10% or less of the entire period.

[0215] In the period from timing T1 to timing T2 , the control circuit 210 sets the selection signal IN_SEL to high level, sets the selection signal CNT_SEL to high level, and enables only pixel A through the enable signal. Therefore, when a photon is incident in each counting interval, the digital signal CNT_A counts up.

[0216] Fig.25 2 is a timing chart showing an example of the operation of the solid-state imaging element in the exposure period of the pixel B in the short interval counting period according to the sixth embodiment of the present technology. After the timing T2, the control circuit 210 sets the selection signal IN_SEL to a low level, sets the selection signal CNT_SEL to a high level, and enables only the pixel B by the enable signal. Therefore, when a photon is incident in each counting interval, the digital signal CNT_B counts up.

[0217] Note that the fourth or fifth embodiment can be applied to the sixth embodiment.

[0218] As described above, according to the sixth embodiment of the present technology, since the count interval is switched, the bit depth of the digital signal and the power consumption can be reduced compared to the case where the count interval is not switched.

[0219] [Modifications]

[0220] In the above-mentioned sixth embodiment, the solid-state imaging element 200 switches the counting interval to one of two intervals, but the counting interval may be switched to one of three or more intervals. The solid-state imaging element 200 in the modification of the sixth embodiment is different from the solid-state imaging element of the sixth embodiment in that the counting interval is switched to one of three or more intervals.

[0221] Fig.26: is a diagram showing an example of the operation of the control circuit 210 in the modification of the sixth embodiment of the present technology. In the modification of the sixth embodiment, the counting interval is switched to one of three or more intervals. For example, the counting interval is switched to one of the intervals P1, P2, P3, and P4. Assume that P1 is the longest, P2 is shorter than P1, P3 is shorter than P2, and P4 is the shortest.

[0222] The four are divided into a long interval group longer than a predetermined interval and a short interval group shorter than a predetermined interval. The number of intervals in each group is one or more. For example, P1 and P2 are long interval groups, and P3 and P4 are short interval groups. Note that P1 can be a long interval group, and P2, P3, and P4 can be short interval groups.

[0223] In the case where the count interval is switched to one of the long interval groups, the control circuit 210 sets the selection signal IN_SEL to "1" and sets the selection signal CNT_SEL to "0". In addition, the control circuit 210 exposes both pixels A and B. On the other hand, in the case where the count interval is switched to one of the short interval groups, the control circuit 210 sets the selection signal IN_SEL to "1" and sets the selection signal CNT_SEL to "1". In addition, the control circuit 210 exposes only one of the pixels A and B, and switches the exposure target at regular time intervals.

[0224] As described above, according to the modification example of the sixth embodiment of the present technology, the count interval can be switched to one of three or more intervals.

[0225] <7. Seventh Implementation Method>

[0226] In the sixth embodiment described above, the control circuit 210 controls the count interval to be a long interval or a short interval. However, when the number of pulses is counted in a long interval under high illumination, the count value may be saturated. The solid-state imaging element 200 in the seventh embodiment is different from the solid-state imaging element 200 in the sixth embodiment in that the count when the count interval is a long interval is set to be valid or invalid based on the digital signals of pixels A and B.

[0227] Fig. 27 : is a circuit diagram showing a configuration example of a pixel block 300 in a seventh embodiment of the present technology. The pixel block 300 of the seventh embodiment differs from the pixel block 300 of the sixth embodiment in that it further includes resistor elements 328 and 348, OR (logical AND) gates 327 and 347, and a determiner 381.

[0228] The resistance element 328 is inserted between the SPAD 313 and the clamp transistor 322, and the resistance element 348 is inserted between the SPAD 333 and the clamp transistor 342. These resistance elements are inserted as needed.

[0229] The determiner 381 determines whether to set the count of each of the counters 360 and 370 to be valid in the period of the long count interval based on the digital signals CNT_A and CNT_B in the period of the short count interval.

[0230] The selection signal CNT_SEL from the control circuit 210 and the digital signals CNT_A and CNT_B from the counters 360 and 370 are input to the determiner 381. The determiner 381 acquires the digital signals CNT_A and CNT_B generated in the period when the selection signal CNT_SEL is at a high level (that is, the counting interval is a short interval). Then, the determiner 381 determines whether the illuminance is high based on these digital signals.

[0231] For example, the determiner 381 determines the illuminance by one of the above-described determination methods (1), (2-1), and (2-3).

[0232] (3) Alternatively, the determiner 381 determines that the illuminance is high if there are one or more pixels in which the value of the upper bit of the digital signal is equal to or greater than a threshold value.

[0233] (4) Alternatively, the determiner 381 determines that the illuminance is high if there are one or more pixels in which the value of the most significant bit (MSB) of the digital signal becomes a high level.

[0234] In addition, the determiner 381 supplies the enable signal DIS to the OR gates 327 and 347. In the period in which the count interval is a short interval, the enable signal DIS is controlled to be a low level (enabled). Therefore, this sets the counts of the counters 360 and 370 to be valid.

[0235] In the case where it is determined that the illumination is high, the determiner 381 sets the enable signal DIS to a high level (disabled) in the period in which the selection signal CNT_SEL is at a high level (i.e., the counting interval is a short interval). Therefore, the counts of the counters 360 and 370 become invalid in the period in which the counting interval is a long interval. On the other hand, in the case in which it is determined that the illumination is low, the determiner 381 maintains the enable signal DIS at a low level and sets the counts of the counters 360 and 370 to be valid.

[0236] Fig.28 : is a timing chart showing an example of the operation of the solid-state imaging element 200 in the exposure period of the pixel A in the short interval count period according to the seventh embodiment of the present technology.

[0237] Fig.29 : is a timing chart showing an example of the operation of the solid-state imaging element 200 in the exposure period of the pixel B in the short interval count period according to the seventh embodiment of the present technology.

[0238] like Fig.28 and Fig.29 As shown, in the seventh embodiment, control similar to that of the sixth embodiment is performed. In addition, in a period in which the counting interval is a short interval, the counting of the counters 360 and 370 is controlled to be valid by the enable signal DIS of a low level (enable).

[0239] Fig.30 3 is a timing diagram showing an example of the operation of the solid-state imaging element according to the seventh embodiment of the present technology in the long interval counting period. It is assumed that the determiner 381 determines that the illumination is high based on the digital signal in the time period of the short time interval. In this case, the determiner 381 sets the enable signal DIS to a high level (disabled). Therefore, as shown in the figure, the counts of the counters 360 and 370 in the period where the counting interval is a long interval become invalid.

[0240] As shown in the figure, by setting the count in a long interval to be invalid at high illumination, it is possible to prevent the count value from being saturated when the resolution is not extended.

[0241] Note that the determiner 381 can also determine whether to set the count of each of the counters 360 and 370 to be valid in the period of the short count interval based on the digital signals CNT_A and CNT_B in the period of the long count interval. In this case, the count in the short time interval is controlled to be invalid under low illumination. Whether the illumination is low is determined by one of the above-mentioned determination methods (1), (2-2) and (2-4).

[0242] (5) Alternatively, in the case where there are one or more pixels in which the value of the upper bit of the digital signal is smaller than the threshold value in the period in which the count interval is a long interval, the determiner 381 determines that the illuminance is low.

[0243] (6) Alternatively, in the case where there are one or more pixels in which the MSB value of the digital signal becomes a low level in a period in which the count interval is a long interval, the determiner 381 determines that the illuminance is low.

[0244] The fourth embodiment or the fifth embodiment can be applied to the seventh embodiment. In addition, the modification of the sixth embodiment can also be applied to the seventh embodiment.

[0245] As described above, according to the seventh embodiment of the present technology, the determiner 381 sets the count in the period in which the count interval is a long interval to be valid or invalid based on the digital signals CNT_A and CNT_B, so that saturation of the count value can be prevented.

[0246] <8. Eighth Implementation Method>

[0247] In the sixth embodiment described above, the control circuit 210 controls the count interval to be a long interval or a short interval, but the count interval can be switched in the 1V period for imaging one frame. The solid-state imaging element 200 in the eighth embodiment is different from the solid-state imaging element 200 in the sixth embodiment in that the count interval is switched in the 1V period. In addition, the 1V period is an example of a frame period described in the claims.

[0248] Fig.31 : is a diagram showing an example of the count interval in the 1V period of a predetermined row according to the eighth embodiment of the present technology. In the eighth embodiment, the control circuit 210 switches the count interval in the 1V period from the time T0 to the time T4.

[0249] For example, in the period from timing T0 to timing T1, the count interval is controlled to be a long interval. Then, the control circuit 210 switches the count interval to a short interval at timing T1. In the period from timing T1 to timing T2, pixel A is exposed, and in the period from timing T2 to timing T3, pixel B is exposed. The control circuit 210 switches the count interval to a long interval at timing T3. Thereafter, similar control is repeatedly performed until timing T4.

[0250] The signal processing unit 230 acquires a long interval digital signal and a short interval digital signal for each pixel in a 1 V period. The signal processing unit 230 calculates a statistical value (average value or total value) of the digital signal in each period as a pixel signal for each pixel, and outputs a frame in which the pixel signal is arranged.

[0251] As shown in the figure, by switching the count interval during the 1 V period, it is possible to suppress blurring when photographing a moving object.

[0252] In addition, the fourth, fifth, and seventh embodiments can also be applied to the eighth embodiment. In addition, the modification of the sixth embodiment can also be applied to the eighth embodiment.

[0253] As described above, according to the eighth embodiment of the present technology, since the control circuit 210 switches the count interval in the 1 V period, blurring can be suppressed.

[0254] <9. Ninth Implementation Method>

[0255] In the above-mentioned eighth embodiment, the control circuit 210 switches the counting interval in the 1V period, but at this time, exposure control can be performed by the rolling shutter method. The solid-state imaging element 200 in the ninth embodiment is different from the solid-state imaging element 200 in the eighth embodiment in that exposure control is performed by the rolling shutter method.

[0256] Fig.32 1 is a timing chart showing an example of exposure and reading operations of the solid-state imaging element 200 in the ninth embodiment of the present technology. For example, two pixels sharing the counters 360 and 370 are arranged in the column direction.

[0257] The control circuit 210 sequentially selects a plurality of rows in the pixel array unit 220 and resets the counter to start exposure. During exposure, the signal processing unit 230 reads only the most significant bit (MSB) of the digital signal of the selected row a predetermined number of times during exposure.

[0258] Then, the control circuit 210 sequentially selects a plurality of rows in the pixel array unit 220 and ends the exposure by stopping the counter. The signal processing unit 230 sequentially reads the digital signals of the plurality of rows. In addition, the control circuit 210 switches the counting interval in the 1V period.

[0259] For example, in the drawing, the count interval of the first row is controlled to be a long interval in the period from timing T1 to timing T8, and the count interval of the second row is controlled to be a long interval in the period from timing T2 to timing T9 in the period immediately after timing T1. The first row is exposed from time T1 to time T7. Next, the second row is exposed from timing T2 to timing T8. In this way, a rolling shutter method is used in which exposure is performed sequentially in row units.

[0260] The MSB of the first row is read at timing T3 to T4 and timing T5 to T6 during exposure. The MSB of the second row is read within a predetermined time period from timing T4 and within a predetermined time period from timing T6. All bits of the digital signal of the first row are read in the period from timing T7 to timing T8, and all bits of the digital signal of the second row are read in the period from timing T8 to timing T9.

[0261] Then, at timing T9, the control circuit 210 switches the counter intervals of the first row and the second row to a short interval. Pixel A (in other words, the first row) is exposed in the period from time T9 to time T10, and all bits of the row are read in the period from time T10 to time T11. In addition, the MSB of the first row is read during exposure. Pixel B (in other words, the second row) is exposed in the period from timing T11 to timing T12, and all bits of the row are read in the period from timing T12 to timing T13. In addition, during exposure, the MSB of the second row is read a predetermined number of times.

[0262] The signal processing unit 230 obtains a bit string indicating the number of times the MSB changes from "1" to "0" (i.e., the number of overflows) as a high-order bit based on each read MSB. Then, the signal processing unit 230 uses the bit string obtained by reading all bits as low bits to obtain a digital signal including high bits and low bits for each pixel. Therefore, the bit depth of the digital signal can be extended.

[0263] As shown in the figure, by performing exposure control by the rolling shutter method, the frame rate can be increased compared with the case of the global shutter method described later.

[0264] Note that each of the fourth, fifth, and seventh embodiments can be applied to the ninth embodiment. In addition, the modification example of the sixth embodiment can also be applied to the ninth embodiment.

[0265] As described above, according to the ninth embodiment of the present technology, since the control circuit 210 performs exposure control by the rolling shutter method, the frame rate can be improved compared to the case of the global shutter method.

[0266] <10. Tenth Implementation Method>

[0267] In the above-mentioned ninth embodiment, the control circuit 210 performs exposure control by the rolling shutter method, but in this control, rolling shutter distortion may occur. The solid-state imaging element 200 according to the tenth embodiment is different from the solid-state imaging element 200 of the ninth embodiment in that exposure is controlled by the global shutter method.

[0268] Fig.33 1 is a timing chart showing an example of exposure and reading operations of the solid-state imaging element 200 in the tenth embodiment of the present technology.

[0269] At timing T0 when the 1V period starts, the control circuit 210 selects all rows (i.e., all pixels) at the same time and starts exposure. Then, at timing T3 immediately before the end of the 1V period, the control circuit 210 selects all rows at the same time and ends exposure. Between timing T3 and the end of the 1V period, the signal processing unit 230 sequentially reads all bits of the digital signal of each of the plurality of rows.

[0270] In addition, the control circuit 210 switches the count interval in the 1V period. When switching, the control circuit 210 performs exposure control by the rolling shutter method. For example, the count interval is switched to a short interval at timing T1, and the row including pixel A is sequentially exposed. After timing T2, the row including pixel B is sequentially exposed.

[0271] Furthermore, during exposure, the signal processing unit 230 sequentially reads the MSB of each row a predetermined number of times. At the end of exposure, the signal processing unit 230 sequentially reads the digital signal of each row.

[0272] As shown in the figure, since exposure control is performed by the global shutter method at the beginning and end of the 1 V period, rolling shutter distortion is suppressed.

[0273] Note that each of the fourth, fifth, and seventh embodiments can be applied to the tenth embodiment. Furthermore, the modification of the sixth embodiment can be applied to the tenth embodiment.

[0274] As described above, according to the tenth embodiment of the present technology, since the control circuit 210 performs exposure control by the global shutter method at the start and end of the 1 V period, rolling shutter distortion can be suppressed.

[0275] <11. Eleventh Implementation Method>

[0276] In the above-mentioned tenth embodiment, the control circuit 210 performs exposure control by the rolling shutter method in the middle of the IV period, but in this control, rolling shutter distortion may occur. The solid-state imaging element 200 according to the eleventh embodiment is different from the solid-state imaging element of the tenth embodiment in that exposure control is performed by the global shutter method even in the 1V period.

[0277] Fig.34 1 is a timing chart showing an example of exposure and reading operations of the solid-state imaging element 200 of the eleventh embodiment of the present technology.

[0278] At the start time T0 of the 1V period, the control circuit 210 simultaneously selects all rows (all pixels) and starts exposure, and at the time T1 of the 1V period, simultaneously selects all pixels and ends exposure. During this exposure period, the signal processing unit 230 sequentially reads the MSB of each row a predetermined number of times. Then, between the timing T1 and the timing T2, the signal processing unit 230 sequentially reads the digital signal of each row.

[0279] The control circuit 210 switches the count interval to a short interval at timing T2, selects all rows including pixel A (i.e., odd rows), and starts exposure at the same time, and selects rows at the same time and ends exposure at timing T3. During this exposure, the signal processing unit 230 sequentially reads the MSB of each row a predetermined number of times. Then, between timing T3 and timing T4, the signal processing unit 230 sequentially reads the digital signal of each row.

[0280] Next, the control circuit 210 selects all rows (i.e., even-numbered rows) including pixel B at timing T4 and starts exposure at the same time, and selects these rows at the same time at timing T5 and ends exposure. During this exposure, the signal processing unit 230 sequentially reads the MSB of each row a predetermined number of times. Then, between time T5 and time T6, the signal processing unit 230 sequentially reads the digital signal of each row. After timing T6, similar control is repeatedly performed.

[0281] As shown in the figure, since exposure control is performed by the global shutter method even in the middle of the 1 V period, rolling shutter distortion is further suppressed.

[0282] Note that each of the fourth, fifth, and seventh embodiments can be applied to the eleventh embodiment. In addition, the modification of the sixth embodiment can be applied to the eleventh embodiment.

[0283] As described above, according to the eleventh embodiment of the present technology, since the control circuit 210 performs exposure control by the global shutter method even in the middle of the 1 V period, rolling shutter distortion can be further suppressed.

[0284] <12. Twelfth Implementation Method>

[0285] In the above-mentioned eleventh embodiment, the control circuit 210 starts the next exposure after completing the reading of all rows, but in this configuration, it is difficult to further increase the frame rate. The solid-state imaging element 200 in the twelfth embodiment is different from the solid-state imaging element in the eleventh embodiment in that exposure and reading in a short interval counting period are performed complementarily.

[0286] Fig.35 1 is a timing chart showing an example of exposure and reading operations of the solid-state imaging element 200 in the twelfth embodiment of the present technology.

[0287] In the twelfth embodiment, the control until the count period is switched to the timing T2 of the short interval is similar to the control in the eleventh embodiment. Here, a signal line (not shown) for transmitting a digital signal to the signal processing unit 230 is wired in the column direction. In addition, each pixel A (or pixel B) in the column sharing the signal line is exposed by half.

[0288] For example, in the period from timing T2 to timing T3, the control circuit 210 simultaneously exposes half of the pixel A. Since the pixel A is arranged in odd rows, half of the odd rows (such as the first row and the fifth row) are simultaneously exposed. Then, in the period from timing T4 to timing T5, the control circuit 210 simultaneously exposes the remaining half of the pixel A (the third row, the seventh row, etc.).

[0289] Next, in the period from timing T6 to timing T7, the control circuit 210 simultaneously exposes half of the pixels B. Since the pixels B are arranged in even-numbered rows, half of the even-numbered rows (the second row, the sixth row, etc.) are exposed. Then, in the period from timing T8 to timing T9, the control circuit 210 exposes the remaining half of the pixels B (the fourth row, the eighth row, etc.).

[0290] During these exposure periods, the signal processing unit 230 sequentially reads the MSB of each row a predetermined number of times. In addition, in the period from timing T3 to timing T5, the signal processing unit 230 sequentially reads half of the pixels A in row units. The remaining half of the pixels A can be exposed in these readout periods.

[0291] Furthermore, in the period from the timing T5 to the timing T7, the signal processing unit 230 sequentially reads the remaining half of the pixels A in units of rows. In these readout periods, half of the pixels B can be exposed.

[0292] Then, in the period from timing T7 to timing T9, the signal processing unit 230 sequentially reads half of the pixels B in row units. The remaining half of the pixels B can be exposed in these readout periods. After timing T9, the signal processing unit 230 sequentially reads the remaining half of the pixels B in row units.

[0293] As shown in the figure, the frame rate can be further increased by exposing the other half of the pixels A (or pixels B) during the readout of the other half of the pixels.

[0294] Note that each of the fourth, fifth, and seventh embodiments can be applied to the twelfth embodiment. Furthermore, the modification of the sixth embodiment can be applied to the twelfth embodiment.

[0295] As described above, according to the twelfth embodiment of the present technology, during the reading of the other half of the pixels A, the control circuit 210 exposes the other half of the pixels A (or the pixels B), so that the frame rate can be further improved.

[0296] <13. Thirteenth Implementation Method>

[0297] In the above-described first embodiment, a digital signal is generated for each pixel, but in this configuration, it is difficult to further improve the sensitivity. The solid-state imaging element 200 of the thirteenth embodiment is different from that of the first embodiment in that pixel addition is performed.

[0298] Fig.363 is a circuit diagram showing a configuration example of a pixel block 300 in a thirteenth embodiment of the present technology. The pixel block 300 of the thirteenth embodiment differs from the pixel block of the first embodiment in that a logic gate for performing a logic operation for pixel addition is further included. In the case where a pulse signal rises in response to photon incidence, an OR gate 391 is used as a logic gate.

[0299] The OR gate 391 outputs the logical sum of the pulse signals PLS_A and PLS_B to the multiplexer 351. Note that the logical operation on the two pulse signals is not limited to the logical sum. In the case where the pulse signal falls in response to the photon incidence, an AND (logical product) gate is inserted instead of the OR gate 391. Alternatively, a NOT (negation) gate may be used instead of the OR gate 391 to operate the logical difference.

[0300] Note that the OR gate 391 is an example of the first logic gate described in the claims of this disclosure.

[0301] Fig.37 1 is a diagram showing an example of the operation of the control circuit 210 in the thirteenth embodiment of the present technology. In the thirteenth embodiment, one of a plurality of modes including an addition mode and a non-addition mode is set. The addition mode is a mode in which corresponding pulse signals of two pixels in the pixel block 300 are added, and the non-addition mode is a mode in which signals are not added.

[0302] In the case of setting the non-addition mode, the control circuit 210 sets the selection signal IN_SEL to "1" and sets the selection signal CNT_SEL to "0". Therefore, the pulse signal PLS_A is selected in the pixel A, and the pulse signal PLS_B is selected in the pixel B. In addition, the control circuit 210 sets the enable signals EN_A and EN_B to "0" (enable).

[0303] On the other hand, in the case of setting the addition mode, the control circuit 210 sets the selection signal IN_SEL to "0" and sets the selection signal CNT_SEL to "1". Therefore, the logical sum of the pulse signals PLS_A and PLS_B is selected in pixel A, and the carry flag is selected in pixel B. In addition, the control circuit 210 sets the enable signals EN_A and EN_B to "0" (enable).

[0304] As shown in the figure, by adding the pulse signals PLS_A and PLS_B in the addition mode, the number of pixels is reduced compared to the non-addition case, but the sensitivity can be improved.

[0305] It should be noted that although two pixels are added, three or more pixels may be arranged in the pixel block 300 and three or more pixels may be added as described later.

[0306] Furthermore, each of the fourth and fifth embodiments can be applied to the thirteenth embodiment. In addition, the modification of the sixth embodiment can be applied to the thirteenth embodiment.

[0307] As described above, according to the thirteenth embodiment of the present technology, since the pixel block 300 adds the pulse signals PLS_A and PLS_B in the addition mode, the sensitivity can be improved compared to the non-addition case.

[0308] <14. Fourteenth Implementation Method>

[0309] In the above thirteenth embodiment, the count interval of the pulse signal is constant, but the count interval can be switched during imaging. The solid-state imaging element 200 according to the fourteenth embodiment is different from the solid-state imaging element of the thirteenth embodiment in that the count interval is switched during imaging.

[0310] Fig.38 3 is a circuit diagram showing a configuration example of a pixel block 300 in a fourteenth embodiment of the present technology. In the fourteenth embodiment, a sensor unit 310 includes a recharge transistor 321, a clamp transistor 322, a SPAD 313, pMOS transistors 323 and 324, an nMOS transistor 325, and a buffer 326.

[0311] Furthermore, the sensor unit 330 includes a recharge transistor 341 , a clamp transistor 342 , a SPAD 333 , pMOS transistors 343 and 344 , an nMOS transistor 345 , and a buffer 346 .

[0312] The circuit configurations of these sensor units 310 and 330 are similar to those in Fig.21 The circuit configuration of the sixth embodiment illustrated in FIG.

[0313] Furthermore, in the fourteenth embodiment, the control circuit 210 can switch the count interval in the non-addition mode. In the case where the count interval is a short interval in the non-addition mode, similarly to the sixth embodiment, the counters are connected in series and the resolution of the counters is extended.

[0314] Fig.39 : is a timing chart showing an example of the operation of the solid-state imaging element 200 in the addition mode according to the fourteenth embodiment of the present technology.

[0315] When the addition mode is set at timing T0, the control circuit 210 sets the selection signal IN_SEL to a low level and sets the selection signal CNT_SEL to a high level. Therefore, the logical sum is selected in the pixel A, and the carry flag is selected in the pixel B.

[0316] When the pulse signals PLS_A and PLS_B are generated at timings T1 and T2 , the digital signal CNT_A counts up, and when the digital signal CNT_A is saturated at timing T3 , the digital signal CNT_B counts up.

[0317] In addition, the 4th, 5th, and 7th to 12th embodiments can also be applied to the 14th embodiment. Furthermore, the modification of the 6th embodiment can be applied to the 14th embodiment.

[0318] As described above, according to the fourteenth embodiment of the present technology, since the count interval is switched in the non-addition mode, the bit depth of the digital signal and the power consumption can be reduced compared to the case where the count interval is not switched.

[0319] <15. Fifteenth Implementation Method>

[0320] In the above-described thirteenth embodiment, the solid-state imaging element 200 adds two pixels, but three or more pixels may be added. The solid-state imaging element 200 of the fifteenth embodiment is different from that of the thirteenth embodiment in that four pixels are added.

[0321] Fig.40 1 is a diagram showing an example of the arrangement of pixels in a pixel block 300 in a fifteenth embodiment of the present technology. In the fifteenth embodiment, pixels are arranged in a four-Bayer array. In addition, for every four adjacent pixels of the same color, a microlens 221 that guides incident light to those pixels is arranged. The lower four pixels (r pixels 303, 304, 305, 306, etc.) of the microlens 221 share a counter.

[0322] Fig.41 1 is a circuit diagram showing a configuration example of a pixel block 300 in a fifteenth embodiment of the present technology. The pixel block 300 of the fifteenth embodiment includes multiplexers 353 to 356 instead of multiplexers 351 and 352, and also includes sensor units 315 and 335, OR gates 392 and 393, and counters 365 and 375.

[0323] The sensor unit 315 generates a pulse signal PLS_C in response to the incidence of photons. The sensor unit 335 generates a pulse signal PLS_D in response to the incidence of photons. The circuit configurations of these sensor units are similar to the circuit configuration of the sensor unit 310. Note that the sensor units 315 and 335 are examples of the third and fourth sensor units described in the claims.

[0324] OR gate 392 outputs the logical sum of pulse signals PLS_C and PLC_D to multiplexer 355 and OR gate 393. OR gate 393 outputs the logical sum of the outputs of OR gates 391 and 392 to multiplexer 353. Note that the logical operation on two pulse signals is not limited to the logical sum. In the case where the pulse signal falls in response to the incidence of photons, an AND gate is inserted instead of OR gates 391 to 393. Alternatively, a NOT (negation) gate may be used instead of an OR gate to operate the logical difference.

[0325] Note that the OR gates 392 and 393 are examples of second and third logic gates described in the claims of this disclosure.

[0326] The multiplexer 353 selects one of the logical sum of the OR gate 393, the pulse signal PLS_A, and the logical sum of the OR gate 391 according to the selection signal IN_SEL1 from the control circuit 210, and outputs the selected one to the counter 360 as the output signal OUT_A. For example, the logical sum of the OR gate 393 is selected when the selection signal IN_SEL1 is "2", the pulse signal PLS_A is selected when the selection signal IN_SEL1 is "1", and the logical sum of the OR gate 391 is selected when the selection signal IN_SEL1 is "0". Note that the multiplexer 353 is an example of the first multiplexer described in the claims.

[0327] Furthermore, the counter 360 according to the fifteenth embodiment supplies the carry flag as CF_A to the multiplexer 354 .

[0328] The multiplexer 354 selects the carry flag CF_A or the pulse signal PLS_B according to the selection signal CNT_SEL1 from the control circuit 210, and outputs the selected one to the counter 370 as the output signal OUT_B. For example, in the case where the selection signal CNT_SEL1 is "1", the carry flag CF_A is selected, and in the case where the selection signal CNT_SEL1 is "0", the pulse signal PLS_B is selected. It is to be noted that the multiplexer 354 is an example of the second multiplexer described in the claims.

[0329] Furthermore, the counter 370 according to the fifteenth embodiment further generates a carry flag and supplies the carry flag as CF_B to the multiplexer 355 .

[0330] The multiplexer 355 selects one of the carry flag CF_B, the pulse signal PLS_C, and the logical sum of the OR gate 392 according to the selection signal IN_SEL2 from the control circuit 210, and outputs the selected one to the counter 365 as the output signal OUT_C. For example, the carry flag CF_B is selected when the selection signal IN_SEL2 is "2", the pulse signal PLS_C is selected when the selection signal IN_SEL2 is "1", and the logical sum of the OR gate 392 is selected when the selection signal IN_SEL2 is "0". Note that the multiplexer 355 is an example of the third multiplexer described in the claims.

[0331] The counter 365 counts in synchronization with the output signal OUT_C ​​to obtain a count value, and outputs a digital signal CNT_C indicating the count value to the signal processing unit 230. In addition, the counter 365 generates a carry flag CF_C indicating whether an overflow occurs, and outputs the carry flag CF_C to the multiplexer 356. Note that the counter 365 is an example of a third counter described in the claims.

[0332] The multiplexer 356 selects the carry flag CF_C or the pulse signal PLS_D according to the selection signal CNT_SEL2 from the control circuit 210, and outputs the selected one to the counter 375 as the output signal OUT_D. For example, in the case where the selection signal CNT_SEL2 is "1", the carry flag CF_C is selected, and in the case where the selection signal CNT_SEL2 is "0", the pulse signal PLS_D is selected. Note that the multiplexer 356 is an example of the fourth multiplexer described in the claims.

[0333] The counter 375 counts a count value in synchronization with the output signal OUT_D and outputs a digital signal CNT_D indicating the count value to the signal processing unit 230. Note that the counter 375 is an example of a fourth counter described in the claims.

[0334] The pixel block 300 in the figure is used as Fig.40 The r pixels 303 to 306 are shown in FIG.

[0335] Fig.42is a diagram showing an example of the operation of the control circuit 210 in the fifteenth embodiment of the present technology. In the fifteenth embodiment, one of a plurality of modes including a non-addition mode, a 2-pixel addition mode, and a 4-pixel addition mode is set. The 2-pixel addition mode is a mode for adding two pixels at a time among four pixels in the pixel block 300, and the 4-pixel addition mode is a mode for adding all four pixels. The non-addition mode is a mode in which each pixel is not added. It should be noted that one of the 2-pixel addition mode and the 4-pixel addition mode as well as the addition mode can be switched.

[0336] In the case of setting the non-addition mode, the control circuit 210 sets the selection signal IN_SEL1 to "1", the selection signal CNT_SEL1 to "0", the selection signal IN_SEL2 to "1", and the selection signal CNT_SEL2 to "0". Therefore, the pulse signal PLS_A is selected in the multiplexer 353, the pulse signal PLS_B is selected in the multiplexer 354, the pulse signal PLS_C is selected in the multiplexer 355, and the pulse signal PLS_D is selected in the multiplexer 356. In addition, the control circuit 210 sets the enable signals of all pixels to "0" (enabled).

[0337] In addition, in the case of setting the 2-pixel addition mode, the control circuit 210 sets the selection signal IN_SEL1 to "0", sets the selection signal CNT_SEL1 to "1", sets the selection signal IN_SEL2 to "0", and sets the selection signal CNT_SEL2 to "1". Therefore, the logical sum of the pulse signals PLS_A and PLS_B is selected in the multiplexer 353, and the carry flag CF_A is selected in the multiplexer 354. The logical sum of the pulse signals PLS_C and PLS_D is selected in the multiplexer 355, and the carry flag CF_C is selected in the multiplexer 356. In addition, the control circuit 210 sets the enable signals of all pixels to "0" (enabled).

[0338] In addition, in the case of setting the 4-pixel addition mode, the control circuit 210 sets the selection signal IN_SEL1 to "2", the selection signal CNT_SEL1 to "1", the selection signal IN_SEL2 to "2", and the selection signal CNT_SEL2 to "1". Therefore, the logical sum of the pulse signals PLS_A, PLS_B, PLS_C, and PLS_D is selected in the multiplexer 353, and the carry flag CF_A is selected in the multiplexer 354. The carry flag CF_B is selected in the multiplexer 355, and the carry flag CF_C is selected in the multiplexer 356. In addition, the control circuit 210 sets the enable signals of all pixels to "0" (enabled).

[0339] In the 2-pixel addition mode, a circuit (such as the signal processing unit 230) at the subsequent stage of the pixel detects the distance between the corresponding peaks of the image of the pixel signal on the left side (or upper side) where each microlens 221 is arranged and the image of the pixel signal on the right side (or lower side) where each microlens is arranged as a phase difference. The focus lens (not shown) is driven according to the phase difference. Therefore, image plane phase difference AF can be achieved.

[0340] As described above, according to the fifteenth embodiment of the present technology, since the pixel block 300 adds the pulse signals PLS_A, PLS_B, PLS_C, and PLS_D in the 4-pixel addition mode, the sensitivity can be further improved.

[0341] <16. Sixteenth Implementation>

[0342] In the above-mentioned thirteenth embodiment, in the non-additive mode, the resolution of the counter is made constant, but in this configuration, the resolution of the counter may be insufficient under high illuminance. The solid-state imaging element 200 according to the sixteenth embodiment is different from the solid-state imaging element of the thirteenth embodiment in that the resolution of the counter is extended under high illuminance in the non-additive mode.

[0343] The circuit configuration of the pixel block 300 in the sixteenth embodiment is similar to Fig.36 A circuit configuration of a thirteenth embodiment is shown in FIG.

[0344] Fig.43 is a diagram showing an example of the operation of the control circuit 210 in the sixteenth embodiment of the present technology. In the sixteenth embodiment, one of a plurality of modes including a non-additive low illumination mode, a non-additive high illumination mode, and an additive mode is set. The additive mode is a mode for adding corresponding pulse signals of two pixels in the pixel block 300, and the non-additive low illumination mode and the non-additive high illumination mode are modes for not adding signals. In addition, the non-additive low illumination mode is a mode set at low illumination when the illumination is equal to or less than a predetermined value, and the non-additive high illumination mode is a mode set at high illumination when the illumination is higher than a predetermined value.

[0345] The control content of the non-additive low illumination mode of the sixteenth embodiment is similar to Figure 5 The control content of the low illumination mode of the first embodiment shown in FIG. The control content of the non-additive high illumination mode of the sixteenth embodiment is similar to Figure 5 The control contents of the high illumination mode of the first embodiment shown in FIG. 16 are the same as those of the addition mode of the first embodiment shown in FIG. Fig.36 The control contents of the addition mode of the thirteenth embodiment shown in FIG. 1 are similar.

[0346] As described above, according to the sixteenth embodiment of the present technology, since the resolution of the counter is extended at high illuminance in the non-addition mode, the dynamic range can be extended at high illuminance.

[0347] <17. Seventeenth Implementation Method>

[0348] In the first embodiment described above, the circuit in the solid-state imaging element 200 is arranged on a single semiconductor chip, but in this configuration, it is difficult to reduce the circuit scale of each chip. The solid-state imaging element 200 in the seventeenth embodiment is different from the solid-state imaging element in the first embodiment in that the circuit is dispersedly arranged on two stacked chips.

[0349] Fig.44 17 is a circuit diagram showing a configuration example of a pixel block 300 in the seventeenth embodiment of the present technology. The solid-state imaging element 200 according to the seventeenth embodiment includes a stacked pixel chip 201 and a circuit chip 202. These chips are electrically connected via a connecting portion such as a via. Note that the connection can also be made by Cu-Cu bonding or a bump other than a via. The connection can also be made by a scheme different from these (such as magnetic coupling). In addition, although two chips are stacked, three or more layers can be stacked.

[0350] The SPADs 313 and 333 are arranged on the pixel chip 201 , and the remaining circuits and elements are arranged on the circuit chip 202 .

[0351] As shown in the figure, by adopting a stacked structure, the circuit scale of each chip can be reduced and the number of pixels can be easily increased.

[0352] Furthermore, the second to sixteenth embodiments can also be applied to the seventeenth embodiment.

[0353] exist Fig.21 In the case where the circuit shown in has a stacked structure, as Fig.45 As shown, clamp transistors 322 and 342 are arranged in the pixel chip 201 .

[0354] As described above, according to the seventeenth embodiment of the present technology, due to the stacked structure, the number of pixels can be easily increased.

[0355] <18. Eighteenth Implementation Method>

[0356] In the first embodiment described above, the control circuit 210 causes all pixels in the pixel array unit 220 to output pulse signals, but in this configuration, it is difficult to reduce the reading time and the amount of data. The solid-state imaging element 200 according to the eighteenth embodiment is different from the solid-state imaging element of the first embodiment in that the control circuit 210 causes some pixels in the pixel array unit 220 to output pulse signals.

[0357] Fig.46 2 is a diagram showing an example of a region to be controlled according to an eighteenth embodiment of the present technology. In the pixel array unit 220, a region 225 such as a region of interest (ROI) is set as a control target. For example, the region 225 is set by a user operation or execution of various applications.

[0358] The control circuit 210 sets the pixels in the area 225 to be effective in all pixels by the enable signal and outputs a pulse signal. Therefore, the time required for reading and the amount of data to be read can be reduced compared to the case of controlling all pixels.

[0359] Furthermore, the second to seventeenth embodiments can also be applied to the eighteenth embodiment.

[0360] As described above, according to the eighteenth embodiment of the present technology, since the control circuit 210 causes some pixels to output pulse signals, the reading time and the amount of data can be reduced.

[0361] <19. Application examples of mobile objects

[0362] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure can be implemented in the form of a device installed on any kind of mobile body, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0363] Fig.47 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0364] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.47 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0365] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0366] The body system control unit 12020 controls the operation of various devices arranged on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave or a signal of various switches transmitted from a mobile device as a substitute for a key may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0367] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or detect their distances, based on the received image.

[0368] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0369] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0370] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0371] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0372] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030.

[0373] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.47 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0374] Fig.48 12031 is a diagram illustrating an example of the installation position of the imaging unit 12031.

[0375] exist Fig.48 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0376] The imaging units 12101, 12102, 12103, 12104, 12105 are arranged, for example, at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield in the interior of the vehicle 12100. The imaging unit 12101 arranged at the front nose in the interior of the vehicle and the imaging unit 12105 arranged at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield in the interior of the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0377] Please note that Fig.47 An example of the imaging range of the imaging units 12101 to 12104 is described. The imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing image data imaged by the imaging units 12101 to 12104.

[0378] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0379] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting objects that exist on the driving path of the vehicle 12100 and are traveling in the same direction as the vehicle 12100 at a prescribed speed (e.g., equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can pre-set the following distance to keep ahead of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, coordinated control for automatic driving that allows the vehicle to travel automatically without relying on the driver's operation, etc., can be performed.

[0380] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0381] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0382] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging device 100 in the embodiment can be applied to the imaging section 12031. By applying the technology of the present disclosure to the imaging section 12031, a captured image that is easier to view can be obtained, thereby reducing the fatigue of the driver.

[0383] It should be noted that the above-mentioned embodiments show examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the scope of the present technology.

[0384] It should be noted that the advantageous effects described in this specification are merely examples and are not limiting, and other advantageous effects may be provided.

[0385] It should be noted that the present technology may also have the following configurations.

[0386] (1) A light detection device comprising:

[0387] A first sensor unit generates a first pulse signal in response to the incidence of photons;

[0388] a second sensor unit generating a second pulse signal in response to the incidence of photons;

[0389] a first counter that synchronously counts one of a plurality of signals including a first pulse signal and a second pulse signal to obtain a count value, and outputs a first digital signal indicating the count value and a first carry flag indicating whether an overflow occurs; and

[0390] The second counter synchronously counts one of the first carry flag and the second pulse signal to obtain a count value, and outputs a second digital signal indicating the count value.

[0391] (2) The light detection device according to (1), further comprising: a first multiplexer that selects one of the first pulse signal and the second pulse signal and outputs the selected signal as the first output signal to the first counter; and

[0392] The second multiplexer selects one of the first carry flag and the second pulse signal, and outputs the selected one as a second output signal to the second counter, wherein,

[0393] The first counter counts in synchronization with the first output signal, and

[0394] The second counter counts in synchronization with the second output signal.

[0395] (3) The light detection device according to (2), wherein:

[0396] The first multiplexer selects the first pulse signal when a low illumination mode in which the illumination does not exceed a predetermined value is set, and the first multiplexer alternately selects the first pulse signal and the second pulse signal when a high illumination mode in which the illumination is higher than a predetermined value is set, and

[0397] The second multiplexer selects the second pulse signal if the low illumination mode is set, and selects the first carry flag if the high illumination mode is set.

[0398] (4) The light detection device according to (3), further comprising:

[0399] A determiner determines whether the illuminance is higher than a predetermined value based on the first digital signal and the second digital signal, and sets one of a high illuminance mode and a low illuminance mode.

[0400] (5) The light detection device according to (4), wherein:

[0401] At least one of the first counter and the second counter outputs a specific bit of the digital signal to the determiner, and

[0402] The determiner sets one of the high illumination mode and the low illumination mode based on the specific bit.

[0403] (6) The light detection device according to any one of (1) to (5), wherein:

[0404] The first sensing unit is arranged in one of first and second pixels of the same color among a plurality of pixels arranged in a pixel array unit, and the second sensing unit is arranged in the other of the first and second pixels.

[0405] (7) The light detection device according to (6), further comprising:

[0406] The microlens guides incident light to a plurality of pixels of the same color including the first pixel and the second pixel.

[0407] (8) The light detection device according to (2), further comprising:

[0408] A control circuit controls the first sensor unit and the second sensor unit, wherein:

[0409] Each of the first sensor unit and the second sensor unit includes:

[0410] Avalanche photodiodes, and

[0411] a recharging transistor that performs recharging to return the cathode potential of the avalanche photodiode to a predetermined potential,

[0412] The control circuit controls the counting interval as the interval for performing recharging to be one of the plurality of intervals,

[0413] The first multiplexer selects the first pulse signal in the case where the count interval is a long interval longer than the predetermined interval, and alternately selects the first pulse signal and the second pulse signal in the case where the count interval is a short interval shorter than the predetermined interval, and

[0414] In the case where the count interval is a long interval, the second multiplexer selects the second pulse signal, and in the case where the count interval is a short interval, the second multiplexer selects the first carry flag.

[0415] (9) The light detection device according to (8), further comprising:

[0416] a determiner that determines whether the count of each of the first counter and the second counter is set to be valid in a period in which the count interval is one of a long interval and a short interval based on the first digital signal and the second digital signal, wherein

[0417] Each of the first sensor unit and the second sensor unit further includes a logic gate that turns off the recharge transistor if it is determined that the count is set to invalid.

[0418] (10) The light detection device according to (8) or (9), wherein:

[0419] The first sensor unit is arranged in one of a first pixel and a second pixel among a plurality of pixels arranged in a pixel array unit, and the second sensor unit is arranged in the other pixel among the first pixel and the second pixel,

[0420] The control circuit switches the count interval a plurality of times in a frame period for imaging one frame, and

[0421] The first multiplexer and the second multiplexer switch the selection target a plurality of times in a frame period.

[0422] (11) The light detection device according to (10), wherein:

[0423] The control circuit sequentially selects a plurality of rows of the pixel array unit and starts exposure.

[0424] (12) The light detection device according to (10), wherein:

[0425] The control circuit selects all pixels of the pixel array unit and starts exposure at the same time at the beginning of a frame period, and selects all pixels and ends exposure at the same time just before the end of the frame period.

[0426] (13) The light detection device according to (12), wherein:

[0427] The control circuit sequentially selects a plurality of rows of the pixel array unit in a frame period and starts exposure.

[0428] (14) The light detection device according to (12), wherein:

[0429] The control circuit selects all pixels in a frame period and ends exposure at the same time, switches the count interval after reading of all pixels is completed, and then selects all pixels and starts exposure at the same time.

[0430] (15) The light detection device according to (14), wherein:

[0431] The control circuit simultaneously selects and exposes one of a first row and a second row that share a signal line for transmitting a digital signal, and simultaneously selects and exposes the other of the first row and the second row during reading of one digital signal.

[0432] (16) The light detection device according to (1), further comprising:

[0433] A first logic gate outputs a result of performing a logic operation on the first pulse signal and the second pulse signal as a first operation result;

[0434] a first multiplexer that selects one of a plurality of signals including a first pulse signal and a first operation result, and outputs the selected one to the first counter as a first output signal; and

[0435] The second multiplexer selects one of the first carry flag and the second pulse signal and outputs the selected one to the second counter as a second output signal, wherein

[0436] The first counter counts in synchronization with the first output signal, and

[0437] The second counter counts in synchronization with the second output signal.

[0438] (17) The light detection device according to (16), further comprising:

[0439] A control circuit controls the first sensor unit and the second sensor unit, wherein:

[0440] Each of the first sensor unit and the second sensor unit includes:

[0441] Avalanche photodiodes, and

[0442] a recharging transistor that performs recharging to return the cathode potential of the avalanche photodiode to a predetermined potential,

[0443] The control circuit controls the counting interval as the interval for performing recharging to be one of the plurality of intervals,

[0444] The first multiplexer selects the first pulse signal in the case where the count interval is a long interval longer than the predetermined interval, and alternately selects the first pulse signal and the second pulse signal in the case where the count interval is a short interval shorter than the predetermined interval, and

[0445] In the case where the count interval is a long interval, the second multiplexer selects the second pulse signal, and in the case where the count interval is a short interval, the second multiplexer selects the first carry flag.

[0446] (18) The light detection device according to (16), further comprising:

[0447] a third sensor unit, generating a third pulse signal in response to the incidence of photons;

[0448] a fourth sensor unit, generating a fourth pulse signal in response to the incidence of photons;

[0449] A second logic gate outputs a result of performing a logic operation on the third pulse signal and the fourth pulse signal as a second operation result;

[0450] a third logic gate that outputs a result of performing a logic operation on an output of each of the first logic gate and the second logic gate as a third operation result;

[0451] a third multiplexer that outputs one of the following as a third output signal: a third pulse signal, a second operation result, and a second carry flag indicating whether an overflow has occurred;

[0452] a third counter, which counts synchronously with the third output signal to obtain a count value, and outputs a third digital signal indicating the count value and a third carry flag indicating whether an overflow occurs;

[0453] a fourth multiplexer, outputting one of the third carry flag or the fourth pulse signal as a fourth output signal; and

[0454] A fourth counter performs counting in synchronization with the fourth output signal to obtain a count value and outputs a fourth digital signal indicating the count value, wherein:

[0455] The first multiplexer selects one of the first pulse signal, the first operation result, and the third operation result, and

[0456] The second counter further generates a second carry flag.

[0457] (19) The light detection device according to (16), wherein:

[0458] The first multiplexer selects the first pulse signal in a case where a non-additive low illumination mode in which the illumination does not exceed a predetermined value is set, the first multiplexer alternately selects the first pulse signal and the first operation result in a case where a non-additive high illumination mode in which the illumination is higher than a predetermined value is set, and selects the first operation result in a case where the addition mode is set, and

[0459] The second multiplexer selects the second pulse signal if the non-addition low illumination mode is set, the second multiplexer selects the first carry flag if the non-addition high illumination mode is set, and selects the first carry flag if the addition mode is set.

[0460] (20) The light detection device according to any one of (1) to (19), wherein:

[0461] A portion of the first sensor unit and a portion of the second sensor unit are arranged on a predetermined pixel chip, and

[0462] The remaining portion of the first sensing unit, the remaining portion of the second sensing unit, and the first counter and the second counter are arranged on a predetermined circuit chip.

[0463] (21) The light detection device according to any one of (1) to (20), further comprising:

[0464] A control circuit controls a plurality of pixels, wherein:

[0465] The first sensor unit is arranged in one of a first pixel and a second pixel among the plurality of pixels, and the second sensor unit is arranged in the other pixel among the first pixel and the second pixel, and

[0466] The control circuit controls some pixels of the plurality of pixels to generate a pulse signal.

[0467] Reference Symbols List

[0468] 100 Imaging Device

[0469] 110 Imaging lens

[0470] 120 Recording Units

[0471] 130 Imaging control unit

[0472] 200 Solid-state imaging element

[0473] 201 pixel chip

[0474] 202 Circuit Chip

[0475] 210 Control circuit

[0476] 220 pixel array unit

[0477] 221 Microlens

[0478] 230 Signal Processing Unit

[0479] 300 pixel blocks

[0480] 301,302 pixels

[0481] 303,304,305,306r pixels

[0482] 310,330,315,335 sensor units

[0483] 311,312,323,324,331,332,343,344pMOS transistors

[0484] 313,333SPAD

[0485] 314,334 Pulse shaping unit

[0486] 321,341 Recharge transistor

[0487] 322,342 clamp transistor

[0488] 325,345nMOS transistors

[0489] 326,346 Buffer

[0490] 327, 347, 391 to 393 OR (Logical AND) Gates

[0491] 328,348 resistor elements

[0492] 351 to 356 Multiplexer

[0493] 360,365,370,375 counters

[0494] 361 to 364, 371 to 374 triggers

[0495] 380,381 Determinator

[0496] 12031 Imaging Department.

Claims

1. A light detection device, comprising: A first sensor unit generates a first pulse signal in response to the incidence of photons; a second sensor unit generating a second pulse signal in response to the incidence of photons; a first counter, which synchronously counts one of a plurality of signals including the first pulse signal and the second pulse signal to obtain a count value, and outputs a first digital signal indicating the count value and a first carry flag indicating whether an overflow occurs; as well as The second counter synchronously counts one of the first carry flag and the second pulse signal to obtain a count value, and outputs a second digital signal indicating the count value.

2. The light detection device according to claim 1, further comprising: a first multiplexer that selects one of the first pulse signal and the second pulse signal and outputs the selected signal as a first output signal to the first counter; as well as a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs the selected one as a second output signal to the second counter, wherein: The first counter counts in synchronization with the first output signal, and the second counter counts in synchronization with the second output signal.

3. The light detection device according to claim 2, wherein: The first multiplexer selects the first pulse signal when a low illumination mode in which illumination does not exceed a predetermined value is set, and the first multiplexer alternately selects the first pulse signal and the second pulse signal when a high illumination mode in which illumination is higher than the predetermined value is set, and The second multiplexer selects the second pulse signal if the low illumination mode is set, and selects the first carry flag if the high illumination mode is set.

4. The light detection device according to claim 3, further comprising: A determiner determines whether the illuminance is higher than a predetermined value based on the first digital signal and the second digital signal, and sets one of the high illuminance mode and the low illuminance mode.

5. The light detection device according to claim 4, wherein: At least one of the first counter and the second counter outputs a specific bit of the digital signal to the determiner, and The determiner sets one of the high illumination mode and the low illumination mode based on the specific bit.

6. The light detection device according to claim 1, wherein: The first sensing unit is arranged in one of first and second pixels of the same color among a plurality of pixels arranged in a pixel array unit, and the second sensing unit is arranged in the other of the first and second pixels.

7. The light detection device according to claim 6, further comprising: The microlens guides incident light to a plurality of pixels of the same color including the first pixel and the second pixel.

8. The light detection device according to claim 2, further comprising: A control circuit controls the first sensor unit and the second sensor unit, wherein: Each of the first sensor unit and the second sensor unit includes: Avalanche photodiodes, and a recharging transistor that performs recharging to return the cathode potential of the avalanche photodiode to a predetermined potential, the control circuit controls a counting interval as an interval for performing the recharging to be one of a plurality of intervals, The first multiplexer selects the first pulse signal in a case where the count interval is a long interval longer than a predetermined interval, and alternately selects the first pulse signal and the second pulse signal in a case where the count interval is a short interval shorter than the predetermined interval, and In the case where the count interval is the long interval, the second multiplexer selects the second pulse signal, and in the case where the count interval is the short interval, the second multiplexer selects the first carry flag.

9. The light detection device according to claim 8, further comprising: a determiner that determines whether the count of each of the first counter and the second counter is set to be valid in a period in which the count interval is one of the long interval and the short interval based on the first digital signal and the second digital signal, wherein Each of the first sensor unit and the second sensor unit further includes a logic gate that turns off the recharge transistor if it is determined that the count is set to invalid.

10. The light detection device according to claim 8, wherein: The first sensor unit is arranged in one of a first pixel and a second pixel among a plurality of pixels arranged in a pixel array unit, and the second sensor unit is arranged in the other of the first pixel and the second pixel, The control circuit switches the count interval a plurality of times in a frame period for imaging one frame, and The first multiplexer and the second multiplexer switch the selection target a plurality of times in the frame period.

11. The light detection device according to claim 10, wherein: The control circuit sequentially selects a plurality of rows of the pixel array unit and starts exposure.

12. The light detection device according to claim 10, wherein: The control circuit selects all pixels of the pixel array unit and starts exposure at the same time when the frame period starts, and selects all pixels and ends exposure at the same time just before the frame period ends.

13. The light detection device according to claim 12, wherein: The control circuit sequentially selects a plurality of rows of the pixel array unit in a frame period and starts exposure.

14. The light detection device according to claim 12, wherein: The control circuit selects all pixels and ends exposure at the same time in a frame period, switches the count interval after reading of all pixels is completed, and then selects all pixels and starts exposure at the same time.

15. The light detection device according to claim 14, wherein: The control circuit simultaneously selects and exposes one of a first row and a second row that share a signal line for transmitting a digital signal, and simultaneously selects and exposes the other of the first row and the second row during reading of one of the digital signals.

16. The light detection device according to claim 1, further comprising: a first logic gate, outputting a result of performing a logic operation on the first pulse signal and the second pulse signal as a first operation result; a first multiplexer that selects one of a plurality of signals including the first pulse signal and the first operation result, and outputs the selected one signal as a first output signal to the first counter; as well as a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs the selected one as a second output signal to the second counter, wherein The first counter counts in synchronization with the first output signal, and the second counter counts in synchronization with the second output signal.

17. The light detection device according to claim 16, further comprising: A control circuit controls the first sensor unit and the second sensor unit, wherein: Each of the first sensor unit and the second sensor unit includes: Avalanche photodiodes, and a recharging transistor that performs recharging to return the cathode potential of the avalanche photodiode to a predetermined potential, the control circuit controls a counting interval as an interval for performing the recharging to be one of a plurality of intervals, The first multiplexer selects the first pulse signal in a case where the count interval is a long interval longer than a predetermined interval, and alternately selects the first pulse signal and the second pulse signal in a case where the count interval is a short interval shorter than the predetermined interval, and In the case where the count interval is the long interval, the second multiplexer selects the second pulse signal, and in the case where the count interval is the short interval, the second multiplexer selects the first carry flag.

18. The light detection device according to claim 16, further comprising: a third sensor unit, generating a third pulse signal in response to the incidence of photons; a fourth sensor unit, generating a fourth pulse signal in response to the incidence of photons; A second logic gate, outputting a result of performing a logic operation on the third pulse signal and the fourth pulse signal as a second operation result; a third logic gate, which outputs a result of performing a logic operation on an output of each of the first logic gate and the second logic gate as a third operation result; a third multiplexer that outputs one of the following as a third output signal: the third pulse signal, the second operation result, and a second carry flag indicating whether an overflow has occurred; a third counter, which counts synchronously with the third output signal to obtain a count value, and outputs a third digital signal indicating the count value and a third carry flag indicating whether an overflow occurs; a fourth multiplexer, outputting one of the third carry flag and the fourth pulse signal as a fourth output signal; as well as a fourth counter that counts synchronously with the fourth output signal to obtain a count value and outputs a fourth digital signal indicating the count value, wherein: The first multiplexer selects one of the first pulse signal, the first operation result, and the third operation result, and The second counter further generates the second carry flag.

19. The light detection device according to claim 16, wherein: the first multiplexer selects the first pulse signal when a non-addition low illumination mode in which illumination does not exceed a predetermined value is set, the first multiplexer alternately selects the first pulse signal and the first operation result when a non-addition high illumination mode in which illumination is higher than the predetermined value is set, and selects the first operation result when an addition mode is set, and The second multiplexer selects the second pulse signal when the non-addition low illumination mode is set, the second multiplexer selects the first carry flag when the non-addition high illumination mode is set, and selects the first carry flag when the addition mode is set.

20. The light detection device according to claim 1, wherein A portion of the first sensor unit and a portion of the second sensor unit are arranged on a predetermined pixel chip, and The remaining portion of the first sensing unit, the remaining portion of the second sensing unit, and the first counter and the second counter are arranged on a predetermined circuit chip.

21. The light detection device according to claim 1, further comprising: A control circuit controls a plurality of pixels, wherein: The first sensor unit is arranged in one of a first pixel and a second pixel among the plurality of pixels, and the second sensor unit is arranged in the other of the first pixel and the second pixel, and The control circuit controls some of the plurality of pixels to generate a pulse signal.

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