Hybrid bonding surface planarization process method for wafer and chemical mechanical polishing equipment

Abstract

The present invention provides a hybrid bonding surface flattening process method for wafers and a chemical mechanical polishing device. The method comprises: controlling a grinding head to absorb a first wafer to be surface flattened, and grinding the first wafer on a first grinding pad to remove the copper film above the grooves of the first wafer, thereby obtaining a second wafer; controlling the grinding head to move to a second grinding pad, and grinding the second wafer on the second grinding pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the grooves having the same thickness as the dielectric layer, thereby obtaining a third wafer with an exposed interface layer; controlling the grinding head to move to a third grinding pad, and grinding the third wafer on the third grinding pad to make the surface height of the interface layer the same as the surface height of the copper in the grooves, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than that of the first grinding pad and the second grinding pad. The present invention can produce a wafer with a flat and smooth surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a hybrid bonding surface planarization process method for a wafer. Background Art

[0002] During wafer-level hybrid bonding, large surface differences (dishes) on the wafer can cause bonding bubbles after the hybrid bonding process, affecting chip yield. Therefore, the wafer surface needs to be treated with a chemical mechanical planarization (CMP) process to obtain a flat and smooth surface.

[0003] In related technologies, the copper layer and the dielectric layer are mainly ground, but large copper depressions may be formed during the grinding process, resulting in large surface height differences on the wafer surface, affecting the hybrid bonding of the wafer and the yield of the chip. Summary of the Invention

[0004] The embodiment of the present invention provides a hybrid bonding surface planarization process method and chemical mechanical polishing equipment for wafers, so as to repair copper depressions on the wafer surface, reduce surface height differences, and obtain a flat and smooth surface.

[0005] In a first aspect, an embodiment of the present invention provides a hybrid bonding surface planarization process method for a wafer, comprising:

[0006] Controlling the polishing head to absorb the first wafer to be planarized, and polishing the first wafer on a first polishing pad to remove the copper thin film above the groove of the first wafer, thereby obtaining a second wafer;

[0007] Controlling the polishing head to move onto a second polishing pad, and polishing the second wafer on the second polishing pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the trench having the same thickness as the dielectric layer, to obtain a third wafer with an exposed interface layer;

[0008] The polishing head is controlled to move to a third polishing pad, and the third wafer is polished on the third polishing pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third polishing pad is less than the hardness of the first polishing pad and the hardness of the second polishing pad.

[0009] In one possible implementation, controlling a polishing head to absorb a first wafer to be planarized and polishing the first wafer on a first polishing pad to remove a copper thin film above a groove of the first wafer to obtain a second wafer includes:

[0010] Controlling the polishing head to absorb the first wafer to be planarized;

[0011] Pre-flowing a first polishing liquid on the first polishing pad; wherein the first polishing liquid is a polishing liquid for removing copper thin films;

[0012] performing a first grinding operation on the surface of the first wafer on a first grinding pad, and monitoring the thickness of the copper film on the surface of the first wafer;

[0013] When the thickness of the copper thin film reaches a first preset thickness, grinding the surface of the first wafer for a second time and monitoring the thickness of the copper thin film;

[0014] When the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the groove to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

[0015] In a possible implementation, before controlling the polishing head to move onto the second polishing pad and polishing the second wafer on the second polishing pad, the method further includes:

[0016] Determining a second polishing liquid according to a preset first selection ratio of the removal rate of the dielectric layer and the removal rate of copper;

[0017] pre-flowing the second polishing liquid on the second polishing pad;

[0018] Before controlling the grinding head to move to the third grinding pad and grinding the third wafer on the third grinding pad, the method further includes:

[0019] determining a third polishing liquid according to a preset second selection ratio of the interface layer removal rate and the copper removal rate;

[0020] The third polishing liquid is pre-flowed on the third polishing pad.

[0021] In one possible implementation, the removal rate of the copper film in the third grinding is lower than that in the first grinding, and the removal rate of the copper film in the third grinding is lower than that in the second grinding.

[0022] In a possible implementation, the first polishing pad and the second polishing pad are hard polishing pads, and the hardness of the first polishing pad is the same as the hardness of the second polishing pad;

[0023] The third polishing pad is a soft polishing pad.

[0024] In a possible implementation, the first selection ratio ranges from 2.6 to 3.2;

[0025] The second selection ratio ranges from 2.0 to 2.5.

[0026] In a possible implementation, the flow rates of the second polishing liquid and the third polishing liquid range from 200 mL / min to 300 mL / min.

[0027] In one possible implementation, a grinding pressure of grinding the first wafer on the first grinding pad ranges from 1.2 psi to 2.5 psi;

[0028] The second wafer is ground on the second polishing pad at a polishing pressure in a range of 1.3 psi to 2.0 psi;

[0029] The grinding pressure of grinding the third wafer on the third grinding pad ranges from 1.2 psi to 1.6 psi.

[0030] In a second aspect, an embodiment of the present invention provides another wafer hybrid bonding surface planarization process method, comprising:

[0031] Controlling the polishing head to absorb the first wafer to be planarized, and polishing the first wafer on a first polishing pad to remove a copper thin film of a preset thickness above the grooves of the first wafer, to obtain a fourth wafer;

[0032] Controlling the grinding head to move to a second grinding pad, and grinding the fourth wafer on the second grinding pad to remove the remaining thickness of the copper film above the groove of the fourth wafer to obtain a fifth wafer;

[0033] The grinding head is controlled to move to the third grinding pad, and the fifth wafer is ground on the third grinding pad so that the interface layer of the fifth wafer is exposed, and the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface.

[0034] In a third aspect, an embodiment of the present invention provides a chemical mechanical polishing device, comprising a polishing head, a first polishing pad, a second polishing pad, a third polishing pad, a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein when the processor executes the computer program, the steps of the method described in the first aspect or any possible implementation of the first aspect are implemented, or when the processor executes the computer program, the steps of the method described in the second aspect are implemented.

[0035] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of the method described in the first aspect or any possible implementation method of the first aspect.

[0036] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0037] The embodiment of the present invention grinds the wafer surface three times to repair the surface height difference, maintaining it within a stable range and reducing the impact on hybrid bonding. The first grinding can remove the copper film above the groove, which will form a larger copper depression. The second grinding removes the dielectric layer, the barrier layer, and the copper in the groove with the same thickness as the dielectric layer. This can reduce the amount of copper removed during the grinding process, repair the copper depression, and reduce the height difference between the surface of the exposed interface layer and the surface of the copper in the groove. The third grinding removes part of the interface layer and part of the copper in the groove. This can also reduce the amount of copper removed during the grinding process, further repair the copper depression, and make the surface height of the interface layer the same as the surface height of the copper in the groove, thereby reducing the surface height difference of the wafer and obtaining a flat and smooth surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is an application scenario diagram of the hybrid bonding surface planarization process method for wafers provided by an embodiment of the present invention;

[0040] Figure 2 is a schematic structural diagram of a first wafer to be surface planarized according to an embodiment of the present invention;

[0041] Figure 3 This is a flow chart of a wafer hybrid bonding surface planarization process method provided by an embodiment of the present invention;

[0042] Figure 4 This is a schematic flow chart of a hybrid bonding surface planarization process method for a wafer provided by an embodiment of the present invention;

[0043] Figure 5 This is a flow chart of another wafer hybrid bonding surface planarization process method provided by an embodiment of the present invention;

[0044] Figure 6 This is a schematic flow chart of a hybrid bonding surface planarization process method for a wafer provided by an embodiment of the present invention;

[0045] Figure 7 1 is a schematic structural diagram of a wafer after wafer-level hybrid bonding according to an embodiment of the present invention;

[0046] Figure 8 1 is a schematic structural diagram of a wafer hybrid bonding surface planarization process apparatus provided by an embodiment of the present invention;

[0047] Figure 9 Schematic diagram of a chemical mechanical polishing device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0049] The inventors have discovered that wafer-level hybrid bonding typically requires maintaining a minimal surface height difference on the wafer surface. However, during the wafer grinding and planarization process, large copper depressions (Cudishing) may form on the wafer surface, leading to bond bubble defects after the hybrid bonding process, which affects the chip yield. Therefore, it is necessary to consider a new wafer hybrid bonding surface planarization process method.

[0050] In order to reduce the height difference of the wafer surface, in an embodiment of the present invention, the wafer surface is ground multiple times. The copper film on the wafer surface is first removed by grinding, and then the dielectric layer and interface layer on the wafer surface are ground to repair the copper depressions formed when the copper film is removed, thereby reducing the surface height difference of the wafer and obtaining a flat and smooth surface.

[0051] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below with reference to the accompanying drawings.

[0052] See also Figure 1 The application scenario diagram of the hybrid bonding surface planarization process method for wafers is shown in the figure. Figure 1The figure shows a partial structure of a chemical mechanical polishing apparatus, which includes a first polishing pad, a second polishing pad, a third polishing pad, and at least one polishing head. The polishing head can move, such as by rotating along an axis on which the polishing head is located, and can be positioned according to the placement of the polishing pads. The polishing head can also absorb wafers, and when the polishing head moves, it can move the absorbed wafers with it.

[0053] Here, the polishing pad can be Figure 1 As shown, they are placed on three grinding discs in sequence, and can be selected according to actual needs. For example, only the first grinding disc and the second grinding disc can be used for grinding, and they can be set according to specific process requirements.

[0054] In addition, four grinding heads can be provided, three of which correspond to one grinding disk respectively, so that the wafer adsorbed on the grinding head can be ground on the corresponding grinding disk, and three wafers can be ground at the same time. Moreover, as the grinding head rotates, each wafer can be ground on three grinding disks in turn, thereby improving the efficiency of planarization of the hybrid bonding surface of the wafer.

[0055] Figure 2 A schematic structural diagram of a first wafer to be planarized is shown. An interface layer (the material of the interface layer here can be SiCN) is formed on the surface of the first wafer, a dielectric layer (Dielectric) is formed on the interface layer, and a groove is also formed on the surface of the first wafer. A barrier layer (Barrier) is formed on the dielectric layer and the groove; the groove is filled with copper (Cu), and the copper is higher than the groove, forming a copper film on the surface of the first wafer.

[0056] See also Figure 3 The embodiment of the present invention provides a flow chart of a wafer hybrid bonding surface planarization process method, which is described in detail as follows:

[0057] In step S301 , the polishing head is controlled to absorb the first wafer to be planarized, and the first wafer is polished on a first polishing pad to remove the copper film of a preset thickness above the groove of the first wafer to obtain a fourth wafer.

[0058] In this embodiment, the grinding head can absorb the first wafer in the processing area. The processing area is where the first wafer to be flattened is placed. The processing area can be a fixed area or an area with a conveyor belt.

[0059] The grinding head can be moved to the first grinding pad by moving or rotating, and the first round of grinding can be performed on the first grinding pad.

[0060] See also Figure 4The schematic flow chart of a hybrid bonding surface planarization process method for a wafer is shown. After the first round of grinding, the thickness of the copper film on the surface of the fourth wafer is reduced.

[0061] Step S302 , controlling the polishing head to move to the second polishing pad, and polishing the fourth wafer on the second polishing pad to remove the remaining copper film above the groove of the fourth wafer, to obtain a fifth wafer.

[0062] In this embodiment, after the first round of grinding is completed, the grinding head can be further moved or rotated so that the grinding head is located on the second grinding pad and a second round of grinding is performed to remove the copper film above the groove. Figure 4 A schematic diagram of a hybrid bonding surface planarization process for wafers shows that after the second round of grinding, the surface of the fifth wafer is free of copper film. Furthermore, the grinding also removes some of the copper in the trenches, creating copper depressions on the surface of the fifth wafer. This means that the copper surface in the trenches is lower than the surrounding barrier layer.

[0063] Step S303, control the grinding head to move to the third grinding pad, and grind the fifth wafer on the third grinding pad to expose the interface layer of the fifth wafer, and the surface height of the interface layer is the same as the surface height of the copper in the groove, to obtain a wafer with a flat surface.

[0064] In this embodiment, after the second round of grinding is completed, considering the copper depressions, in order to achieve the planarization of the wafer surface, the copper depressions can be repaired to reduce the surface height difference.

[0065] Here, the third round of grinding is continued on the fifth wafer. During the grinding process, more dielectric layers and interface layers can be removed, thereby reducing the surface height difference of the wafer and obtaining a wafer with a flat surface.

[0066] See also Figure 4 The flow chart of a wafer hybrid bonding surface flattening process method is shown. After the third round of grinding, the surface height difference of the wafer after surface flattening is significantly reduced, which can meet the requirements of wafer-level hybrid bonding.

[0067] Optionally, the polishing pressure and polishing liquid may be selected so that the removal rate of the dielectric layer and the interface layer is greater than the removal rate of copper, thereby achieving greater removal of the dielectric layer and the interface layer.

[0068] Optionally, the first polishing pad, the second polishing pad and the third polishing pad can all be hard polishing pads, wherein the hardness of the third polishing pad is the smallest, the hardness of the first polishing pad and the second polishing pad can be the same or different, and the hardness of the first polishing pad and the second polishing pad is not less than the hardness of the third polishing pad.

[0069] The surface-planarized wafer obtained by the method provided in the above embodiment can reduce Cu dishing to a range of 1nm-5nm, with a surface roughness of less than 1nm. However, Cu dishing in large-scale and high-density copper wire pattern areas may still be relatively large. On this basis, the present invention further improves the method provided in the above embodiment and provides another hybrid bonding surface planarization process for wafers to improve the effect of wafer surface planarization.

[0070] Figure 5 The implementation flow chart of the hybrid bonding surface planarization process method for wafers provided in an embodiment of the present invention is detailed as follows:

[0071] Step S501 , controlling the polishing head to absorb the first wafer to be planarized, and polishing the first wafer on a first polishing pad to remove the copper film above the grooves of the first wafer, to obtain a second wafer.

[0072] In this embodiment, during the first round of grinding on the first grinding pad, the copper film above the groove of the first wafer is directly and completely removed, and the subsequent two rounds of grinding are used to repair the generated Cu dishing to further reduce the surface height difference of the wafer.

[0073] See also Figure 6 The flow chart of another hybrid bonding surface planarization process method for wafers is shown. After the first round of grinding, a large copper depression is generated on the surface of the second wafer.

[0074] Optionally, the first polishing pad may be a hard polishing pad to quickly remove the copper film.

[0075] Optionally, the grinding pressure for grinding the first wafer on the first grinding pad may be in the range of 1.2 psi to 2.5 psi. The copper film may be quickly removed by combining the hard grinding pad with the grinding pressure.

[0076] In step S502, the polishing head is controlled to move to the second polishing pad, and the second wafer is polished on the second polishing pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the groove with the same thickness as the dielectric layer, to obtain a third wafer with the interface layer exposed.

[0077] In this embodiment, a second polishing cycle is performed on the second wafer on a second polishing pad. This cycle completely removes only the dielectric layer, the barrier layer above the dielectric layer, and the copper within the trench that is the same thickness as the dielectric layer. The interface layer is temporarily omitted. This second polishing cycle removes more of the dielectric and barrier layers while minimizing copper removal, thus repairing Cu dishing.

[0078] Here, a fixed polishing time can be used for polishing. The amount of film removal caused by this method is controllable within a certain range, and the barrier layer, the dielectric layer and a very small amount of the interface layer can be removed.

[0079] During the second round of grinding, the effectiveness of copper dishing repair varies for areas with different copper line pattern sizes and pattern densities. For wider and denser areas, the copper dishing formed by the first round of grinding is deeper, so after the second round of grinding, some dishing may still exist and can be further repaired during the third round of grinding. For smaller and less dense areas, the copper dishing formed by the first round of grinding is relatively shallow, so after the second round of grinding, the dishing may completely disappear or even turn from concave to convex, forming a protrusion.

[0080] See also Figure 6 The flow chart of another hybrid bonding surface planarization process method for wafers is shown. After the second round of grinding, the surface height difference of the wafer after the surface planarization is significantly reduced.

[0081] Optionally, the second polishing pad may be a hard polishing pad to quickly remove the dielectric layer and the barrier layer.

[0082] Here, the hardness of the second polishing pad may be the same as the hardness of the first polishing pad.

[0083] Optionally, the grinding pressure for grinding the second wafer on the second grinding pad may be in the range of 1.3 psi to 2.0 psi. By combining the hard grinding pad, the grinding fluid and the grinding pressure, the dielectric layer, the barrier layer and the copper may be quickly removed.

[0084] Step S503, controlling the grinding head to move to the third grinding pad, and grinding the third wafer on the third grinding pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than the hardness of the first grinding pad and the hardness of the second grinding pad.

[0085] In this embodiment, the third wafer is subjected to a third round of grinding on the third grinding pad to remove part of the interface layer and part of the copper in the groove so that the surface of the interface layer is at the same height as the surface of the copper, further repairing the Cu dishing, flattening the wafer surface, and reducing the height difference and roughness of the wafer surface.

[0086] Here, a fixed grinding time is used for grinding. Since the amount removed by the third round of grinding is small, a shorter fixed grinding time can be used to repair the Cu dishing.

[0087] See also Figure 6The flow chart of another wafer hybrid bonding surface flattening process method is shown. After the third round of grinding, the surface height difference of the wafer after surface flattening is further reduced, which can fully meet the requirements of wafer-level hybrid bonding.

[0088] Optionally, the third polishing pad may be a soft polishing pad to remove the interface layer, reduce the surface height difference, and reduce the surface roughness.

[0089] Optionally, the grinding pressure for grinding the third wafer on the third grinding pad may be in the range of 1.2 psi to 1.6 psi. The combination of the soft grinding pad, the grinding fluid and the grinding pressure may quickly remove the interface layer and copper and reduce the surface roughness.

[0090] The embodiment of the present invention grinds the wafer surface three times to repair the surface height difference, maintaining it within a stable range and reducing the impact on hybrid bonding. The first grinding can remove the copper film above the groove, which will form a larger copper depression. The second grinding removes the dielectric layer, the barrier layer, and the copper in the groove with the same thickness as the dielectric layer. This can reduce the amount of copper removed during the grinding process, repair the copper depression, and reduce the height difference between the surface of the exposed interface layer and the surface of the copper in the groove. The third grinding removes part of the interface layer and part of the copper in the groove. This can also reduce the amount of copper removed during the grinding process, further repair the copper depression, and make the surface height of the interface layer the same as the surface height of the copper in the groove, thereby reducing the surface height difference of the wafer and obtaining a flat and smooth surface.

[0091] In some embodiments, the grinding head is controlled to adsorb the first wafer to be surface-planarized, and the first wafer is ground on a first grinding pad to remove the copper film above the grooves of the first wafer to obtain a second wafer. The method can be to first control the grinding head to adsorb the first wafer to be surface-planarized; then pre-flow the first grinding liquid on the first grinding pad; wherein the first grinding liquid is a grinding liquid for removing the copper film; then, the surface of the first wafer is ground for the first time on the first grinding pad, and the thickness of the copper film on the surface of the first wafer is monitored; again, when the thickness of the copper film reaches a first preset thickness, the surface of the first wafer is ground for a second time, and the thickness of the copper film is monitored; finally, when the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the grooves to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

[0092] In this embodiment, the first round of grinding can be divided into three grinding steps to gradually remove the copper film.

[0093] In the first grinding, part of the copper film is removed first, and in the second grinding, part of the copper film is removed again. Through two grindings, most of the copper film can be removed, and the thickness of the remaining copper film at each position on the wafer is ensured to be the same to avoid increasing the final copper depression.

[0094] Here, algorithms can be used to monitor the grinding process during the first and second grinding, and eddy current sensors can be used to detect the thickness of the copper film on the wafer surface. Based on the detected thickness, the pressure in the corresponding zone of the grinding head can be adjusted in real time to achieve relatively consistent thickness changes of the copper film in different zones of the grinding head, until the thickness reaches the set target value.

[0095] In the third grinding, the remaining small portion of the copper film is removed to remove all the copper film above the trench.

[0096] Here, a laser sensor can be used to assist in the third grinding. By optimizing the signal of the laser sensor and using the curve data and algorithm-assisted judgment obtained, the grinding process can be stopped when all the copper film is removed.

[0097] Since the first round of grinding is mainly for removing the copper film, the grinding fluid used has a high removal rate for the copper film, but a very low removal rate for the barrier layer. Therefore, when the first round of grinding is completed, a large depression will be formed in the copper film in the groove, that is, Cu dishing.

[0098] Optionally, the first grinding can remove 45% to 55% of the copper film, and the second grinding can remove 35% to 40% of the copper film. Here, if the first grinding removes 45% of the copper film, the second grinding can remove 40% of the copper film; if the first grinding removes 55% of the copper film, the second grinding can remove 35% of the copper film, so that 10% to 15% of the copper film remains after the two grindings are completed.

[0099] In the third grinding, the remaining 10% to 15% of the copper film can be removed.

[0100] Optionally, the removal rate of the copper film in the third grinding is lower than the removal rate of the copper film in the first grinding, and the removal rate of the copper film in the third grinding is lower than the removal rate of the copper film in the second grinding.

[0101] In this embodiment, since the copper film remaining after the third polishing is small and in order to reduce the cudishing, a lower removal rate can be used in the third polishing. Here, the difference in removal rate can be achieved by adjusting the polishing pressure and the polishing liquid flow rate.

[0102] Optionally, the grinding pressure of the first grinding and the second grinding may be in the range of 1.7 psi to 2.5 psi, and the grinding pressure of the third grinding may be in the range of 1.2 psi to 1.7 psi.

[0103] The flow rate of the grinding liquid in the first grinding can range from 250mL / min to 300mL / min, the flow rate of the grinding liquid in the second grinding can range from 250mL / min to 300mL / min, and the flow rate of the grinding liquid in the third grinding can range from 200mL / min to 250mL / min.

[0104] Here, the range of the removal rate of the copper film during the first grinding and the second grinding can be The range of the removal rate of the copper film during the third grinding can be

[0105] In some embodiments, before controlling the polishing head to move to the second polishing pad and polishing the second wafer on the second polishing pad, the second polishing liquid can be determined based on a preset dielectric layer removal rate and a first selection ratio of copper removal rate; and the second polishing liquid can be pre-flowed on the second polishing pad.

[0106] Correspondingly, before controlling the grinding head to move to the third grinding pad and grinding the third wafer on the third grinding pad, the third grinding liquid can be determined based on the preset interface layer removal rate and the second selection ratio of the copper removal rate; and the third grinding liquid can be pre-flowed on the third grinding pad.

[0107] In this embodiment, before grinding the wafer, grinding liquid may be pre-flowed on the corresponding grinding pad to facilitate subsequent grinding.

[0108] Here, considering that the second round of polishing primarily removes the dielectric layer and copper and repairs the copper recesses in the trench, the polishing slurry can be selected based on the removal rate of the dielectric layer and copper. Accordingly, considering that the third round of polishing primarily removes the interface layer and copper and further repairs the copper recesses in the trench, the polishing slurry can be selected based on the removal rate of the interface layer and copper.

[0109] Optionally, in this embodiment, the first selectivity ratio of the dielectric layer removal rate to the copper removal rate may be in the range of 2.6 to 3.2, so that the polishing liquid can remove more dielectric layer and less copper, thereby repairing Cu dishing.

[0110] Here, the polishing liquid has a high removal rate for both the barrier layer and the dielectric layer. For example, the range of the removal rate can be Additionally, the copper removal rate can range from

[0111] In addition, in the second round of grinding, the interface layer will also be touched, and the removal of the interface layer needs to be reduced. Therefore, a polishing liquid with a selectivity ratio between the removal rate of the dielectric layer and the removal rate of the interface layer of 2.2 to 2.6 can be selected. Accordingly, the range of the removal rate of the interface layer can be

[0112] In this embodiment, the second selectivity ratio of the interface layer removal rate to the copper removal rate can be in the range of 2.0 to 2.5, which can make the polishing liquid remove more interface layer and less copper, thereby further repairing Cu dishing. The removal rate of the interfacial layer can range from

[0113] Here, a small amount of dielectric layer may remain on the wafer in the third round of grinding, and this part of the dielectric layer also needs to be removed. Therefore, when selecting the grinding liquid, the selection ratio between the removal rate of the dielectric layer and the removal rate of the interface layer can be made into 1.2-1.5. Among them, the removal rate of the dielectric layer can be

[0114] Optionally, in this embodiment, the flow rate of the second polishing liquid ranges from 200 mL / min to 300 mL / min, and the flow rate of the third polishing liquid ranges from 200 mL / min to 300 mL / min.

[0115] In some possible embodiments, see Figure 7 The schematic diagram of the structure of the wafer after wafer-level hybrid bonding is shown. Figure 7 Figure 2 shows the hybrid bonding of wafers obtained using the two methods provided by the present invention. The wafers repaired once (obtained using the first hybrid bonding surface flattening process for wafers provided by an embodiment of the present invention) are less likely to produce bubble-type defects after hybrid bonding. However, the wafers repaired twice (obtained using the second hybrid bonding surface flattening process for wafers provided by an embodiment of the present invention) are substantially free of bubble-type defects after hybrid bonding.

[0116] In other feasible embodiments, the second wafer hybrid bonding surface planarization process provided by the embodiment of the present invention is used to grind wafers with copper pattern sizes of 0.9um×0.9um, 1.1um×1.1um, and 1.3um×1.3um. The data of copper depressions on the wafer surface after surface planarization are shown in Table 1:

[0117] Table 1 Data of copper concavities on wafer surfaces of different sizes

[0118]

[0119] As can be seen from Table 1, by grinding the wafer using the second hybrid bonding surface planarization process method for wafers provided by an embodiment of the present invention, the copper depressions on the wafer surface after the surface planarization can be maintained within 1 nm.

[0120] Table 2 Data table of surface roughness of wafers of different sizes

[0121]

[0122] As can be seen from Table 2, by grinding the wafer using the second hybrid bonding surface planarization process method for wafers provided by an embodiment of the present invention, the surface roughness of the wafer after surface planarization can be maintained within 0.5 nm.

[0123] The embodiment of the present invention grinds the wafer surface three times to repair the surface height difference, maintaining it within a stable range and reducing the impact on hybrid bonding. The first grinding can remove the copper film above the groove, which will form a larger copper depression. The second grinding removes the dielectric layer, the barrier layer, and the copper in the groove with the same thickness as the dielectric layer. This can reduce the amount of copper removed during the grinding process, repair the copper depression, and reduce the height difference between the surface of the exposed interface layer and the surface of the copper in the groove. The third grinding removes part of the interface layer and part of the copper in the groove. This can also reduce the amount of copper removed during the grinding process, further repair the copper depression, and make the surface height of the interface layer the same as the surface height of the copper in the groove, thereby reducing the surface height difference of the wafer and obtaining a flat and smooth surface.

[0124] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0125] The following are device embodiments of the present invention. For details not fully described therein, reference may be made to the corresponding method embodiments described above.

[0126] Figure 8 A schematic structural diagram of a hybrid bonding surface planarization process apparatus for wafers provided in an embodiment of the present invention is shown. For ease of explanation, only the portion related to the embodiment of the present invention is shown, which is described in detail as follows:

[0127] The wafer hybrid bonding surface planarization process apparatus 80 includes:

[0128] The first control module 81 is used to control the polishing head to absorb the first wafer to be planarized and polish the first wafer on the first polishing pad to remove the copper film above the groove of the first wafer to obtain a second wafer;

[0129] a second control module 82 for controlling the polishing head to move to the second polishing pad and polish the second wafer on the second polishing pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the trench having the same thickness as the dielectric layer, thereby obtaining a third wafer with the interface layer exposed;

[0130] The third control module 83 is used to control the grinding head to move to the third grinding pad and grind the third wafer on the third grinding pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than the hardness of the first grinding pad and the hardness of the second grinding pad.

[0131] In a possible implementation, the second control module 82 is specifically configured to:

[0132] Controlling the polishing head to absorb the first wafer to be planarized;

[0133] Pre-flowing a first polishing liquid on a first polishing pad; wherein the first polishing liquid is a polishing liquid for removing a copper thin film;

[0134] performing a first grinding operation on the surface of the first wafer on the first grinding pad, and monitoring the thickness of the copper film on the surface of the first wafer;

[0135] When the thickness of the copper film reaches the first preset thickness, grinding the surface of the first wafer for the second time and monitoring the thickness of the copper film;

[0136] When the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the groove to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

[0137] In a possible implementation, the second control module 82 is further configured to:

[0138] determining a second polishing liquid according to a first selection ratio of a predetermined removal rate of the dielectric layer and a removal rate of copper;

[0139] pre-flowing a second polishing liquid on the second polishing pad;

[0140] The third control module 83 is further configured to:

[0141] determining a third polishing liquid according to a preset interface layer removal rate and a second selectivity ratio of copper removal rate;

[0142] Pre-flow the third polishing liquid on the third polishing pad.

[0143] In a possible implementation, the removal rate of the copper film in the third grinding is lower than that in the first grinding, and the removal rate of the copper film in the third grinding is lower than that in the second grinding.

[0144] In one possible implementation, the first polishing pad and the second polishing pad are hard polishing pads, and the hardness of the first polishing pad is the same as the hardness of the second polishing pad;

[0145] The third polishing pad is a soft polishing pad.

[0146] In one possible implementation, the first selection ratio ranges from 2.6 to 3.2;

[0147] The second selection ratio ranges from 2.0 to 2.5.

[0148] In a possible implementation, the flow rates of the second polishing liquid and the third polishing liquid range from 200 mL / min to 300 mL / min.

[0149] In one possible implementation, a grinding pressure of grinding the first wafer on the first grinding pad ranges from 1.2 psi to 2.5 psi;

[0150] The second wafer is polished on the second polishing pad at a polishing pressure in a range of 1.3 psi to 2.0 psi;

[0151] The polishing pressure of polishing the third wafer on the third polishing pad ranges from 1.2 psi to 1.6 psi.

[0152] In one possible implementation, the first control module 81 is further configured to control the polishing head to absorb the first wafer to be planarized, and polish the first wafer on the first polishing pad to remove a copper film having a predetermined thickness above the grooves of the first wafer, thereby obtaining a fourth wafer.

[0153] The second control module 82 is further configured to control the polishing head to move to the second polishing pad and polish the fourth wafer on the second polishing pad to remove the remaining copper film above the groove of the fourth wafer to obtain a fifth wafer.

[0154] The third control module 83 is also used to control the grinding head to move to the third grinding pad and grind the fifth wafer on the third grinding pad so that the interface layer of the fifth wafer is exposed, and the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface.

[0155] Figure 9Schematic diagram of the chemical mechanical polishing equipment provided by the embodiment of the present invention. Figure 9 As shown, the chemical mechanical polishing device 90 of this embodiment includes: a processor 91, a memory 92, and a computer program 93 stored in the memory 92 and executable on the processor 91. The chemical mechanical polishing device 90 also includes: a polishing head 94, a first polishing pad 95, a second polishing pad 96, and a third polishing pad 97. When the processor 91 executes the computer program 93, the steps of the hybrid bonding surface planarization process method of each wafer described above are implemented, such as Figure 3 Steps S301 to S303 shown, or, Figure 5 Alternatively, when the processor 91 executes the computer program 93, the functions of the modules in the above-mentioned device embodiments are realized, for example, Figure 8 Functions of modules 81 to 83 are shown.

[0156] For example, the computer program 93 may be divided into one or more modules / units, one or more modules / units being stored in the memory 92 and executed by the processor 91 to implement the present invention. One or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program 93 in the chemical mechanical polishing apparatus 90. For example, the computer program 93 may be divided into Figure 8 Modules 81 to 83 are shown.

[0157] The chemical mechanical polishing device 90 may include, but is not limited to, a processor 91 and a memory 92. Those skilled in the art will understand that Figure 9 This is merely an example of the chemical mechanical polishing device 90 and does not constitute a limitation of the chemical mechanical polishing device 90 . The device may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the chemical mechanical polishing device may also include input and output devices, network access devices, buses, etc.

[0158] The processor 91 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0159] Memory 92 can be an internal storage unit of the chemical mechanical polishing apparatus 90, such as a hard drive or memory of the chemical mechanical polishing apparatus 90. Memory 92 can also be an external storage device of the chemical mechanical polishing apparatus 90, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped with the chemical mechanical polishing apparatus 90. Furthermore, memory 92 can include both an internal storage unit of the chemical mechanical polishing apparatus 90 and an external storage device. Memory 92 is used to store computer programs and other programs and data required by the chemical mechanical polishing apparatus. Memory 92 can also be used to temporarily store data that has been output or is about to be output.

[0160] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0161] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0162] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0163] In the embodiments provided herein, it should be understood that the disclosed devices / chemical mechanical polishing equipment and methods can be implemented in other ways. For example, the device / chemical mechanical polishing equipment embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as multiple units or components being combined or integrated into another system, or some features being ignored or not implemented. In addition, the coupling or direct coupling or communication connection shown or discussed may be through some interface, or the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0164] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0165] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0166] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. Computer-readable media may include: any entity or device that can carry computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0167] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A wafer hybrid bonding surface planarization process method, characterized in that: include: Controlling the polishing head to absorb the first wafer to be planarized, and polishing the first wafer on a first polishing pad to remove the copper thin film above the groove of the first wafer, thereby obtaining a second wafer; Controlling the polishing head to move onto a second polishing pad, and polishing the second wafer on the second polishing pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the trench having the same thickness as the dielectric layer, to obtain a third wafer with an exposed interface layer; Controlling the polishing head to move to a third polishing pad, and polishing the third wafer on the third polishing pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third polishing pad is less than the hardness of the first polishing pad and the hardness of the second polishing pad; The removal rate of the dielectric layer and the interface layer is greater than the removal rate of copper; and the wafer with the surface planarized is used for hybrid bonding of wafers.

2. The hybrid bonding surface planarization process method for wafers according to claim 1, characterized in that: Controlling a polishing head to absorb a first wafer to be planarized, and polishing the first wafer on a first polishing pad to remove a copper film above the groove of the first wafer to obtain a second wafer, comprising: Controlling the polishing head to absorb the first wafer to be planarized; Pre-flowing a first polishing liquid on the first polishing pad; wherein the first polishing liquid is a polishing liquid for removing copper thin films; performing a first grinding operation on the surface of the first wafer on a first grinding pad, and monitoring the thickness of the copper film on the surface of the first wafer; When the thickness of the copper thin film reaches a first preset thickness, grinding the surface of the first wafer for a second time and monitoring the thickness of the copper thin film; When the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the groove to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

3. The hybrid bonding surface planarization process method for wafers according to claim 1, characterized in that: Before controlling the grinding head to move to the second grinding pad and grinding the second wafer on the second grinding pad, the method further includes: Determining a second polishing liquid according to a preset first selection ratio of the removal rate of the dielectric layer and the removal rate of copper; pre-flowing the second polishing liquid on the second polishing pad; Before controlling the grinding head to move to the third grinding pad and grinding the third wafer on the third grinding pad, the method further includes: determining a third polishing liquid according to a preset second selection ratio of the interface layer removal rate and the copper removal rate; The third polishing liquid is pre-flowed on the third polishing pad.

4. The wafer hybrid bonding surface planarization process according to claim 2, characterized in that: The removal rate of the copper thin film in the third polishing is lower than that in the first polishing, and the removal rate of the copper thin film in the third polishing is lower than that in the second polishing.

5. The wafer hybrid bonding surface planarization process according to claim 1, characterized in that: The first polishing pad and the second polishing pad are hard polishing pads, and the hardness of the first polishing pad is the same as the hardness of the second polishing pad; The third polishing pad is a soft polishing pad.

6. The wafer hybrid bonding surface planarization process according to claim 3, characterized in that: The first selection ratio ranges from 2.6 to 3.2; The second selection ratio ranges from 2.0 to 2.

5.

7. The wafer hybrid bonding surface planarization process according to claim 3, characterized in that: The flow rates of the second polishing liquid and the third polishing liquid range from 200 mL / min to 300 mL / min.

8. The hybrid bonding surface planarization process method for a wafer according to any one of claims 1 to 7, characterized in that: The first wafer is ground on the first polishing pad at a polishing pressure in a range of 1.2 psi to 2.5 psi; The second wafer is ground on the second polishing pad at a polishing pressure in a range of 1.3 psi to 2.0 psi; The grinding pressure of grinding the third wafer on the third grinding pad ranges from 1.2 psi to 1.6 psi.

9. A wafer hybrid bonding surface planarization process method, characterized in that: include: Controlling a polishing head to absorb a first wafer to be planarized, and polishing the first wafer on a first polishing pad to remove a copper thin film of a predetermined thickness above the grooves of the first wafer, thereby obtaining a fourth wafer; wherein an interface layer is formed on a surface of the first wafer, a dielectric layer is formed on the interface layer, a barrier layer is formed on the dielectric layer and the grooves, and the grooves are filled with copper; Controlling the grinding head to move to a second grinding pad, and grinding the fourth wafer on the second grinding pad to remove the remaining thickness of the copper film above the groove of the fourth wafer to obtain a fifth wafer; Controlling the polishing head to move onto a third polishing pad, and polishing the fifth wafer on the third polishing pad so that an interface layer is exposed on the fifth wafer, and a surface height of the interface layer is the same as a surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; The removal rate of the dielectric layer and the interface layer is greater than the removal rate of copper; and the wafer with the surface planarized is used for hybrid bonding of wafers.

10. A chemical mechanical polishing device comprising a polishing head, a first polishing pad, a second polishing pad, a third polishing pad, a memory, and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

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