Pulse aging method and device for semiconductor light-emitting device

Abstract

The invention discloses a pulse aging method and device of a semiconductor light-emitting device. The method is applied to an upper computer of a pulse aging system, and a first pulse adjustment parameter is sent to each frequency circuit through the upper computer, so that the corresponding frequency circuit generates a first pulse signal of a first frequency; sending a second pulse adjustment parameter to each pulse circuit to enable the corresponding pulse circuit to adjust the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used for controlling the first switching device to be switched on and off to generate a third pulse signal, and an aging environment corresponding to the to-be-tested device is built through the third pulse signal; and sending a plurality of level signals to a current reading circuit, and switching a connection relationship between the to-be-tested devices and a first pulse current acquisition meter in the current reading circuit through the plurality of level signals so as to obtain voltage values of the to-be-tested devices in the aging environment. According to the invention, the universality of the aging test method of the semiconductor light-emitting device can be improved, and the aging test cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of reliability life test of semiconductor optoelectronic devices, and in particular to a pulse aging method and device for semiconductor light-emitting devices. Background Art

[0002] The development of the intelligent driving industry provides a broader market prospect for the LiDAR industry. As the basic core component of the industry, the importance of reliability during the use of laser chips is self-evident. In order to ensure reliability in the harsh working environment of automobiles, all laser chips must pass strict automotive-grade reliability tests. The existing reliability standard AEC-Q102 for optoelectronic semiconductor components stipulates that laser chips used in automotive LiDARs need to undergo power-on aging tests such as high temperature and high humidity operating life tests (High Temperature Humidity Operating Life Test, WHTOL), power temperature cycling tests (Power Temperature Cycling Test, PTC), high temperature operating life tests (High Temperature Operating Life Test, HTOL), and high temperature operating life tests (Low Temperature Operating Life Test, LTOL).

[0003] The above tests require the laser chip to operate under constant current pulse drive, and different laser chips or aging tests require the development of different pulse drive circuits. In addition, each sample needs to use independent monitoring equipment to obtain test data during the test, which results in high test costs and poor versatility.

[0004] Therefore, how to improve the versatility of laser chip reliability testing methods under different power-on environmental tests at a lower test cost is a technical problem that needs to be solved at present. Summary of the invention

[0005] The present application provides a pulse aging method and device for a semiconductor light-emitting device to solve the technical problem of how to improve the versatility of a laser chip reliability test method under different power-on environmental tests at a lower test cost.

[0006] In order to solve the above technical problems, in a first aspect, an embodiment of the present application provides a pulse aging method for a semiconductor light-emitting device, which is applied to a host computer of a pulse aging system, comprising:

[0007] Wherein, the pulse aging system further comprises: a plurality of frequency circuits, a plurality of pulse circuits, a plurality of first switch device switches and a current reading circuit;

[0008] Sending a first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of a first frequency;

[0009] Sending a second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, and an aging environment corresponding to the device under test is established through the third pulse signal;

[0010] A plurality of level signals are sent to the current reading circuit, and the connection relationship between the device under test and the first pulse current acquisition table in the current reading circuit is switched by the plurality of level signals to obtain the voltage value of each device under test in the aging environment.

[0011] Compared with the prior art, the embodiments of the present application have the following beneficial effects: in order to improve the universality of reliability testing under different types of devices under test, different numbers of devices under test and different power-on environment test requirements, through the host computer, multiple frequency circuits and pulse circuits are controlled to generate second pulse signals with different frequencies and pulse widths, and the first switching device is controlled to perform high-speed switching actions based on the second pulse signal, thereby affecting the waveform, frequency and amplitude of the subsequently generated pulse output current, i.e., the third pulse signal, to meet the aging environment construction under different test requirements, and improve the versatility of the reliability test method of the device under test. At the same time, the current reading circuit is adopted, so that the user can control the host computer to output the corresponding level signal according to their own needs, and flexibly obtain the voltage value of each device under test in the current aging environment, thereby improving the flexibility of the device under test in obtaining the operating status during the test, and avoiding connecting an independent measuring device to each device under test, thereby reducing the hardware cost of the aging system.

[0012] In some embodiments of the first aspect of the present application, the current reading circuit further includes: a plurality of relay switch circuits and a first sampling resistor corresponding to each relay switch circuit;

[0013] Among them, the first end of the first sampling resistor is electrically connected to the input end of the corresponding device under test; the second end of the first sampling resistor is electrically connected to the first input end of the corresponding relay switch circuit; the input end of the first pulse current acquisition meter is electrically connected to the first output end of each relay switch circuit; the second output end of each relay switch circuit is electrically connected to the first ground end; the output end of the first pulse current acquisition meter is electrically connected to the first ground end; and the host computer is electrically connected to the second input end of each relay switch circuit.

[0014] Compared with the prior art, the above embodiment has the following beneficial effects: the first sampling resistor is connected in parallel with the corresponding device under test, the first sampling resistor is connected in series with the corresponding relay switch circuit, and the input end of the first pulse current acquisition meter is connected to the first output end of each relay switch circuit, so that the connection relationship between the first pulse current acquisition meter and the first sampling resistor can be switched through the relay switch circuit, and the voltage value of the device under test can be further obtained, which effectively reduces the demand for ammeters or voltmeters and the hardware cost of the test method.

[0015] In some embodiments of the first aspect of the present application, the switching of the connection relationship between each of the devices under test and the first pulse current acquisition table in the current reading circuit by the plurality of level signals to obtain the voltage value of each of the devices under test in the aging environment includes:

[0016] Inputting the plurality of level signals to the relay switch circuit in sequence to control the connection state between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit;

[0017] When the first pulse current acquisition meter is connected to the first sampling resistor corresponding to the relay switch circuit, a first current value of the first pulse current acquisition meter is read;

[0018] A voltage value corresponding to the device under test in the aging environment is obtained according to the first resistance value of the first sampling resistor and the first current value.

[0019] Compared with the prior art, the above embodiment has the following beneficial effects: by connecting a corresponding relay switch circuit to each device under test, a control chip with multiple I / O interfaces can be used to realize flexible reading of test data of batch devices under test, thereby reducing the cost of the test method and improving the flexibility of test data reading.

[0020] In some embodiments of the first aspect of the present application, the relay switch circuit includes: a first relay, a second relay, a first relay input circuit and a second relay input circuit; the first input end of the relay switch circuit includes: a common end of the first relay and a common end of the second relay; the second input end of the relay switch circuit includes: an input end of the first relay input circuit and an input end of the second relay input circuit; the first output end of the relay switch circuit includes a normally closed end of the first relay; the second output end of the relay switch circuit includes a normally open end of the second relay;

[0021] Among them, the host computer is electrically connected to the input end of the first relay input circuit; the host computer is electrically connected to the input end of the second relay input circuit; the output end of the first relay input circuit is electrically connected to the power supply end of the first relay; the output end of the second relay input circuit is electrically connected to the power supply end of the second relay; the first end of the first sampling resistor is electrically connected to the common end of the first relay; the first end of the first sampling resistor is electrically connected to the common end of the second relay.

[0022] Compared with the prior art, the above embodiment has the following beneficial effects: by connecting the first pulse current acquisition meter to the normally closed end of the first relay, connecting the first sampling resistor to the common end of the first relay and the second relay, connecting the output end of the first pulse current acquisition meter to the ground end, and connecting the normally open end of the second relay to the ground end, that is, the series connection of the first sampling resistor and the first pulse current acquisition meter can be achieved by controlling the normally closed end of the first relay and the normally closed end of the second relay to close, and when the normally open end of the first relay and the normally open end of the second relay are closed, the first pulse current acquisition meter is short-circuited, so that the first pulse current acquisition meter can be used to measure the voltage values ​​of other devices to be tested.

[0023] In some embodiments of the first aspect of the present application, the step of sequentially inputting the plurality of level signals to the relay switch circuit to control the connectivity between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit includes:

[0024] Input a low level to the first relay input circuit, and simultaneously input a low level to the second relay input circuit, so as to connect the first pulse current acquisition meter to the first sampling resistor corresponding to the device under test;

[0025] A high level is input to the first relay input circuit, and a high level is input to the second relay input circuit at the same time, so as to disconnect the first pulse current acquisition meter from the first sampling resistor corresponding to the device under test.

[0026] Compared with the prior art, the above embodiment has the following beneficial effects: the control chip based on multiple I / O interfaces can output a level signal to the first relay input circuit and the second relay input circuit to control the first relay and the second relay to switch to a closed state, thereby flexibly controlling the connection state between each first sampling resistor and the first pulse current acquisition table. Therefore, when collecting the voltage value of the device under test, it is only necessary to connect the first sampling resistor corresponding to the device under test that needs to be collected at present to the first pulse current acquisition table, and disconnect the first sampling resistors corresponding to the other devices under test from the first pulse current acquisition table, so as to realize the measurement of the voltage value of each device under test in turn, thereby reducing the hardware cost of the test method.

[0027] In some embodiments of the first aspect of the present application, the sending of the first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of the first frequency includes:

[0028] Wherein, the frequency circuit includes: a first sliding resistor, a first fixed resistor, a first capacitor and a first timer chip; the first end of the first sliding resistor is electrically connected to the discharge end of the first timer chip; the second end of the first sliding resistor is electrically connected to the threshold end of the first timer chip; the second end of the first sliding resistor is electrically connected to the trigger end of the first timer chip; the second end of the first fixed resistor is electrically connected to the discharge end of the first timer chip; the first end of the first fixed resistor is electrically connected to the reset end of the first timer chip; the first end of the first fixed resistor is electrically connected to the power supply end of the first timer chip; the first end of the first capacitor is electrically connected to the threshold end of the first timer chip; the first end of the first capacitor is electrically connected to the trigger end of the first timer chip; the second end of the first capacitor is electrically connected to the ground end of the first timer chip; the power supply end of the first timer chip is externally connected to the first power supply; the reset end of the first timer chip is externally connected to the first power supply; the output end of the first timer chip is electrically connected to the corresponding pulse circuit; the power supply end of the first timer chip is electrically connected to the corresponding pulse circuit;

[0029] A first pulse adjustment parameter is sent to each of the frequency circuits, so that the corresponding frequency circuit adjusts the corresponding first sliding resistor according to the first pulse adjustment parameter to generate a first pulse signal of a first frequency.

[0030] Compared with the prior art, the above embodiment has the following beneficial effects: by adjusting the resistance value of the first sliding resistor in combination with the first fixed resistor, the frequency of the first pulse signal is accurately adjusted, and at the same time, the adjustable range of the frequency of the first pulse signal is adjusted by the first capacitor, thereby ensuring that a third pulse signal that meets multiple needs can be generated subsequently.

[0031] In some embodiments of the first aspect of the present application, the second pulse signal is used to control the first switching device to generate a third pulse signal, including:

[0032] The pulse aging system also includes: a number of amplification circuits and a constant power supply;

[0033] Amplifying the second pulse signal through the amplifying circuit to obtain a fourth pulse signal;

[0034] The constant power supply is provided to the first switching device through the constant power supply, and the first switching device is controlled to perform a switching operation according to the fourth pulse signal to generate the third pulse signal.

[0035] Compared with the prior art, the above-mentioned embodiment has the following beneficial effects: through the combination of the amplification circuit and the constant power supply, the pulse signal can be effectively amplified, and it is ensured that the first switching device performs precise switching operation under the stable fourth pulse signal, thereby avoiding the test error caused by the unstable pulse signal; further, a stable working power supply is input to the first switching device through the constant power supply, thereby ensuring the stability of each device under test corresponding to the aging environment.

[0036] In some embodiments of the first aspect of the present application, sending the second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal includes:

[0037] Wherein, the pulse circuit includes: a second sliding resistor, a second capacitor and a second timer chip;

[0038] Wherein, the first end of the second sliding resistor is electrically connected to the power supply end of the first timer chip; the first end of the second sliding resistor is electrically connected to the reset end of the first timer chip; the first end of the second sliding resistor is electrically connected to the power supply end of the second timer chip; the second end of the second sliding resistor is electrically connected to the discharge end of the second timer chip; the second end of the second sliding resistor is electrically connected to the threshold end of the second timer chip; the first end of the second capacitor is electrically connected to the discharge end of the second timer chip; the first end of the second capacitor is electrically connected to the threshold end of the second timer chip; the second end of the second capacitor is electrically connected to the ground end of the second timer chip; the reset end of the second timer chip is electrically connected to the output end of the first timer chip; the trigger end of the second timer chip is electrically connected to the output end of the first timer chip; the power supply end of the second timer chip is externally connected to the first power supply; the output end of the second timer chip is electrically connected to the corresponding amplification circuit;

[0039] A second pulse adjustment parameter is sent to each of the pulse circuits, so that the corresponding pulse circuit adjusts the second sliding resistor according to the second pulse adjustment parameter, thereby adjusting the pulse width of the first pulse signal to generate a second pulse signal.

[0040] Compared with the prior art, the above embodiment has the following beneficial effects: the pulse width of the second pulse signal is accurately adjusted by adjusting the resistance value of the second sliding resistor, and the adjustable range of the pulse width of the second pulse signal is adjusted by the second capacitor, thereby ensuring that a third pulse signal that meets various needs can be generated subsequently.

[0041] In some embodiments of the first aspect of the present application, establishing an aging environment corresponding to the device under test by using the third pulse signal includes:

[0042] The pulse aging system further includes: a test board; the test board includes a plurality of first interfaces and a plurality of second interfaces; the first interface is used to be electrically connected to the device under test or to be electrically connected to a device for providing a pulse light aging environment; the second interface is electrically connected to the output end of the switch of the first switch device;

[0043] The third pulse signal is received through the second interface, and the third pulse signal is transmitted to the device under test or a first device for providing a pulse light aging environment to the device under test through the first interface, so as to establish an aging environment for the device under test.

[0044] Compared with the prior art, the above embodiment has the following beneficial effects: through the design of the test board, the device under test can be flexibly connected to the pulse aging system, and a pulse signal is provided through the interface, so as to quickly build an aging environment that meets the requirements, thereby improving the convenience and versatility of the test.

[0045] In a second aspect, the embodiment of the present application further provides a pulse aging device for a semiconductor light emitting device, which is applied to a host computer of a pulse aging system, and includes: a first pulse signal acquisition module, a second pulse signal acquisition module, and a test data reading module;

[0046] Wherein, the pulse aging system further comprises: a plurality of frequency circuits, a plurality of pulse circuits, a plurality of first switch device switches and a current reading circuit;

[0047] The first pulse signal acquisition module is used to send a first pulse adjustment parameter to each of the frequency circuits, so that the corresponding frequency circuit generates a first pulse signal of a first frequency;

[0048] The second pulse signal acquisition module is used to send a second pulse adjustment parameter to each of the pulse circuits, so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, and the aging environment of the corresponding device under test is established through the third pulse signal;

[0049] The test data reading module is used to send a number of level signals to the current reading circuit, and switch the connection relationship between the device under test and the first pulse current acquisition table in the current reading circuit through the number of level signals to obtain the voltage value of each device under test in the aging environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic flow chart of a pulse aging method for a semiconductor light-emitting device provided in some embodiments of the present application;

[0051] Figure 2 A schematic diagram of the structure of a pulse aging system for a semiconductor light-emitting device provided in some embodiments of the present application;

[0052] Figure 3 A design idea of ​​a pulse constant current driving circuit in a pulse aging system of a semiconductor light emitting device provided in some embodiments of the present application;

[0053] Figure 4 A schematic diagram of a pulse constant current driving circuit in a pulse aging system of a semiconductor light emitting device provided in some embodiments of the present application;

[0054] Figure 5 A schematic diagram of a current reading circuit in a pulse aging system of a semiconductor light-emitting device provided in some embodiments of the present application;

[0055] Figure 6 An example of an aging board for a TO package structure in a pulse aging system for a semiconductor light-emitting device provided in some embodiments of the present application;

[0056] Figure 7 An example of an aging board for a COC packaging structure in a pulse aging system for a semiconductor light-emitting device provided in some embodiments of the present application;

[0057] Figure 8 A schematic diagram of the structure of a light source board for a detector in a pulse aging system of a semiconductor light-emitting device provided in some embodiments of the present application;

[0058] Fig. 9 This is a schematic structural diagram of a pulse aging device for a semiconductor light-emitting device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0059] Since the aging test requires the laser chip to operate under constant current pulse drive, and different laser chips or aging tests require the development of different pulse drive circuits, and each sample needs to use independent monitoring equipment to obtain test data during the test, resulting in high test costs and poor versatility.

[0060] In order to solve the above technical problems, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] Embodiment 1

[0062] Please refer to Figure 1 , a pulse aging method for a semiconductor light-emitting device provided in an embodiment of the present application, is applied to a host computer of a pulse aging system, wherein the pulse aging system also includes: a plurality of frequency circuits, a plurality of pulse circuits, a plurality of first switching device switches and a current reading circuit.

[0063] Specifically, in some embodiments of the present application, a pulse aging method for a semiconductor light emitting device provided in the present application can be used for Figure 2 A pulse aging system is shown, which consists of three parts. First, the first part designs a driver board that generates multiple third pulse signals in parallel through multiple channels. The driver board carries a pulse constant current drive circuit or a pulse constant voltage drive circuit (for the convenience of description, the two circuits are collectively referred to as pulse constant source drive circuits below), wherein the host computer provides adjustment parameters to the above two pulse drive circuits to generate a third pulse signal, thereby realizing microsecond-level aging power supply for the device under test; the second part develops an aging board (i.e., a test board) and a test fixture for the device under test that match the pulse constant current drive circuit or the pulse constant voltage drive circuit corresponding to the driver board, thereby realizing aging compatibility of the device under test under various packaging structures, and the aging board is placed in an aging test box; the third part electrically connects the host computer to the aging board, and communicates data with the aging board through the host computer to monitor the test data of the device under test in the aging board.

[0064] Preferably, in some embodiments of the present application, the difference between the pulse constant current drive circuit and the pulse constant voltage drive circuit lies in the power supply that provides a constant power output to the first switching device switch. If the power supply is a constant current source, it corresponds to a pulse constant current drive circuit; if the power supply is a constant voltage source, it corresponds to a pulse constant voltage drive circuit.

[0065] Preferably, in some embodiments of the present application, reference Figure 3The design idea of ​​the pulse constant current drive circuit shown in the figure, the pulse constant current drive circuit and the pulse constant voltage drive circuit both include at least a number of pulse generating circuits, a number of power amplifier circuits (i.e., amplifier circuits), and a number of high-speed switching circuits (i.e., switching circuits). Among them, the pulse generating circuit generates a pulse voltage that drives the high-speed switching element (i.e., the first switching device), i.e., the second pulse signal. Furthermore, a constant power supply is used in combination with a high-speed switching element method to realize pulse driving. Specifically, a constant current source or a constant voltage source can be selected according to the test requirements. Among them, the host computer is used to adjust the parameters of the pulse generating circuit.

[0066] Furthermore, the pulse generating circuit includes a frequency circuit and a pulse circuit. The power supplies of the two circuits are adaptively selected according to the test requirements, such as using a constant current source or a constant voltage source. If the second pulse signal generated by the pulse generating circuit does not meet the design standard, it can be shaped by a shaping circuit to obtain a second pulse signal that meets the requirements. Among them, the frequency circuit is used to generate a first pulse signal that meets the first frequency, and the pulse circuit is used to adjust the pulse width of the first pulse signal.

[0067] Preferably, in some embodiments of the present application, the devices to be tested include but are not limited to laser chips such as EEL (Edge-Emitting Laser) and VCSEL (Vertical Cavity Surface Emitting Laser) used in lidar, and semiconductor light emitting diode devices such as LED (Light Emitting Diode).

[0068] Further, Figure 1 The pulse aging method of the semiconductor light emitting device shown includes S10 to S30, specifically:

[0069] S10: Sending a first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of a first frequency.

[0070] Further, in some embodiments of the present application, sending the first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of the first frequency includes:

[0071] Wherein, the frequency circuit includes: a first sliding resistor, a first fixed value resistor, a first capacitor and a first timer chip;

[0072] A first pulse adjustment parameter is sent to each of the frequency circuits, so that the corresponding frequency circuit adjusts the corresponding first sliding resistor according to the first pulse adjustment parameter to generate a first pulse signal of a first frequency.

[0073] Preferably, reference Figure 4In some embodiments of the present application, a frequency circuit is provided, comprising: a first sliding resistor R2, a first fixed resistor R1, a first capacitor C1 and a first timer chip U1; wherein the first sliding resistor adopts a sliding resistor with a resistance range of 0 to 1KΩ; and the first timer chip adopts a 555 timer. The first end of the first sliding resistor R2 is electrically connected to the discharge end 7 (DISCH) of the first timer chip U1; the second end of the first sliding resistor R2 is electrically connected to the threshold end 6 (THRES) of the first timer chip U1; the second end of the first sliding resistor R2 is electrically connected to the trigger end 2 (TRIG) of the first timer chip; the second end of the first fixed resistor R1 is electrically connected to the discharge end 7 (DISCH) of the first timer chip U1; the first end of the first fixed resistor R1 is electrically connected to the reset end 4 (RST) of the first timer chip U1; the first end of the first fixed resistor R1 is electrically connected to the power supply end 8 (VCC) of the first timer chip U1; the The first end of the first capacitor C1 is electrically connected to the threshold end 6 (THRES) of the first timer chip U1; the first end of the first capacitor C1 is electrically connected to the trigger end 2 (TRIG) of the first timer chip; the second end of the first capacitor C1 is electrically connected to the ground end 1 (GND) of the first timer chip U1; the power end of the first timer chip U1 is externally connected to the first power supply (the first power supply adopts a 5V power supply); the reset end 4 (RST) of the first timer chip U1 is externally connected to the first power supply; the output end 3 (OUT) of the first timer chip U1 is electrically connected to the corresponding pulse circuit; the power end 8 (VCC) of the first timer chip U1 is electrically connected to the corresponding pulse circuit;

[0074] Preferably, reference Figure 4 A frequency circuit provided in some embodiments of the present application further includes: a third capacitor C6 and a fourth capacitor C2; wherein the first end of the third capacitor C6 is electrically connected to the power supply terminal 8 (VCC) of the first timer chip U1; the second end of the third capacitor C6 is electrically connected to the ground terminal; the first end of the fourth capacitor C2 is electrically connected to the control terminal 5 (CONT) of the first timer chip U1; the second end of the fourth capacitor C2 is electrically connected to the ground terminal.

[0075] It can be seen from the above preferred embodiments that by adjusting the resistance value of the first sliding resistor in combination with the first fixed resistor, the frequency of the first pulse signal can be accurately adjusted, and at the same time, the adjustable range of the first pulse signal frequency can be adjusted by the first capacitor, thereby ensuring that a third pulse signal that meets various needs can be generated subsequently.

[0076] S20: Sending a second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, and an aging environment for the corresponding device under test is established through the third pulse signal.

[0077] Further, in some embodiments of the present application, sending the second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal includes:

[0078] Wherein, the pulse circuit includes: a second sliding resistor, a second capacitor and a second timer chip;

[0079] A second pulse adjustment parameter is sent to each of the pulse circuits, so that the corresponding pulse circuit adjusts the second sliding resistor according to the second pulse adjustment parameter, thereby adjusting the pulse width of the first pulse signal to generate a second pulse signal.

[0080] Preferably, reference Figure 4 , a pulse circuit provided in some embodiments of the present application includes: a second sliding resistor R3, a second capacitor C3 and a second timer chip U2; wherein the second timer chip adopts a 555 timer;

[0081] Among them, the first end of the second sliding resistor R3 is electrically connected to the power supply terminal 8 (VCC) of the first timer chip U1; the first end of the second sliding resistor R3 is electrically connected to the reset terminal 4 (RST) of the first timer chip U1; the first end of the second sliding resistor R3 is electrically connected to the power supply terminal 8 (VCC) of the second timer chip U2; the second end of the second sliding resistor R3 is electrically connected to the discharge terminal 7 (DISCH) of the second timer chip U2; the second end of the second sliding resistor R3 is electrically connected to the threshold terminal 6 (THRES) of the second timer chip U2; the first end of the second capacitor C3 is electrically connected to the discharge terminal 7 (DISCH) of the second timer chip U2 ISCH) is electrically connected; the first end of the second capacitor C3 is electrically connected to the threshold end 6 (THRES) of the second timer chip U2; the second end of the second capacitor C3 is electrically connected to the ground end 1 (GND) of the second timer chip U2; the reset end 4 (RST) of the second timer chip U2 is electrically connected to the output end of the first timer chip U1; the trigger end 6 (THRES) of the second timer chip U2 is electrically connected to the output end 3 (OUT) of the first timer chip; the power supply end 8 (VCC) of the second timer chip U2 is externally connected to the first power supply; the output end 3 (OUT) of the second timer chip U2 is electrically connected to the corresponding amplification circuit.

[0082] Preferably, reference Figure 4 A pulse circuit provided in some embodiments of the present application further includes: a fifth capacitor C4; a first end of the fifth capacitor C4 is electrically connected to the control end 5 (CONT) of the second timer chip U2; and a second end of the fifth capacitor C4 is electrically connected to the ground end.

[0083] It can be seen from the above preferred embodiments that the pulse width of the second pulse signal is accurately adjusted by adjusting the resistance value of the second sliding resistor, and the adjustable range of the pulse width of the second pulse signal is adjusted by the second capacitor, thereby ensuring that a third pulse signal that meets various requirements can be generated subsequently.

[0084] Furthermore, in some embodiments of the present application, the second pulse signal is used to control the first switching device to generate a third pulse signal, including:

[0085] The pulse aging system also includes: a number of amplification circuits and a constant power supply;

[0086] Amplifying the second pulse signal through the amplifying circuit to obtain a fourth pulse signal;

[0087] The constant power supply is provided to the first switching device through the constant power supply, and the first switching device is controlled to perform a switching operation according to the fourth pulse signal to generate the third pulse signal.

[0088] Preferably, reference Figure 4 In some embodiments of the present application, the amplifier circuit includes: a sixth capacitor C5 and a signal amplifier chip U3; wherein the signal amplifier chip is specifically a UCC27424P high-speed dual MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor Driver) driver. The first end of the sixth capacitor C5 is electrically connected to the ground terminal 3 (GND) of the signal amplifier chip U3; the second end of the sixth capacitor C5 is electrically connected to the power supply terminal 6 (VDD) of the signal amplifier chip U3; the power supply terminal 6 (VDD) of the signal amplifier chip U3 is externally connected to the second power supply (the second power supply adopts a 15V power supply); the first input terminal 2 (INA) of the signal amplifier chip U3 is electrically connected to the output terminal 3 (OUT) of the second timer chip U2; the first output terminal 7 (OUTA) of the signal amplifier chip U3 is electrically connected to the switch circuit. The UCC27424P high-speed dual MOSFET driver is used in the amplifier circuit to amplify the 5V second pulse signal generated by the pulse generating circuit to 15V and then output it to the switch circuit.

[0089] Preferably, reference Figure 4In some embodiments of the present application, the switch circuit includes a first switch device S1, and further includes a second fixed resistor R4 and a third fixed resistor R5; wherein the first switch device S1 is specifically an IGBT (Insulated Gate Bipolar Transistor) switch or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) switch. The first end of the second fixed resistor R4 is electrically connected to the first output terminal 7 (OUTA) of the signal amplifier chip U3; the second end of the second fixed resistor R4 is electrically connected to the gate of the first switch device S1; the first end of the third fixed resistor R5 is electrically connected to the gate of the first switch device S1; the second end of the third fixed resistor R5 is electrically connected to the ground terminal; the input end of the first switch device S1 is externally connected to a constant power source VL, which can be a constant current source or a constant voltage source; the output end of the first switch device S1 is electrically connected to the input end of the device under test.

[0090] Preferably, in some embodiments of the present application, the switching circuit is based on an IGBT or MOSFET device as the core, and devices with different switching speeds and bandwidths are selected according to the parameters of the required pulse signal, and discrete devices with surface mount packages are selected to reduce interference and facilitate integration. Furthermore, the pulse generating circuit generates a gate voltage (i.e., a third pulse signal) sufficient to turn on the IGBT or MOSFET, and the first switching device is quickly turned off and turned on under the drive of the gate voltage. Further, in conjunction with a constant power supply, a constant power supply output is provided, and a pulse constant output is achieved under the control of the switching circuit. The constant power supply can be independently designed through an additional circuit or a commercial multi-channel constant power supply can be used.

[0091] Preferably, in some embodiments of the present application, the design of the constant current source needs to meet the test conditions of the laser chip, including current, accuracy, etc. The constant current source is connected to the driving circuit, and a constant high current pulse signal is generated through high-speed switching of the driving circuit. Similarly, the constant current source is replaced with a constant voltage source to generate a constant voltage pulse signal to meet the constant voltage pulse requirements under high voltage.

[0092] Preferably, in some embodiments of the present application, in order to meet the needs of mass testing and independent control of power supply, the design of the overall driver board needs to merge multiple pulse constant source drive circuits and place them in a 2U or other standard chassis. A standard interface is left outside the chassis to allow external constant power supply to be connected. By integrating multiple pulse constant source drive circuits, the cost and system volume are effectively reduced. Each pulse constant power supply is designed and powered separately to achieve separate drive, control or aging environment construction for each device under test.

[0093] S30: sending a plurality of level signals to the current reading circuit, and switching the connection relationship between the device under test and the first pulse current acquisition table in the current reading circuit through the plurality of level signals to obtain the voltage value of each device under test in the aging environment.

[0094] Preferably, in some embodiments of the present application, reference Figure 5 , the current reading circuit includes: a first pulse current acquisition meter U4, a plurality of relay switch circuits and a first sampling resistor R11 corresponding to each relay switch circuit; wherein the relay switch circuit includes: a first relay K1, a second relay K2, a first relay input circuit and a second relay input circuit; the first input end of the relay switch circuit includes: a common end 2 of the first relay K1 and a common end 2 of the second relay K2; the second input end of the relay switch circuit includes: an input end NET1 of the first relay input circuit and an input end NET2 of the second relay input circuit; the first output end of the relay switch circuit includes a normally closed end 4 of the first relay K1; the second output end of the relay switch circuit includes a normally open end 3 of the second relay K2. Among them, the first end of the first sampling resistor R11 is electrically connected to the input end of the corresponding device under test; the second end of the first sampling resistor R11 is electrically connected to the first input end of the corresponding relay switch circuit; the input end 1 of the first pulse current acquisition meter U4 is electrically connected to the first output end of each relay switch circuit; the second output end of each relay switch circuit is electrically connected to the first ground end; the output end 2 of the first pulse current acquisition meter U4 is electrically connected to the first ground end; the host computer is electrically connected to the second input end of each relay switch circuit. The host computer is electrically connected to the input end of the first relay input circuit; the host computer is electrically connected to the input end of the second relay input circuit; the output end of the first relay input circuit is electrically connected to the power supply ends 5 and 1 of the first relay; the output end of the second relay input circuit is electrically connected to the power supply ends 5 and 1 of the second relay; the first end of the first sampling resistor R11 is electrically connected to the common end 2 of the first relay; the first end of the first sampling resistor R11 is electrically connected to the common end 2 of the second relay.

[0095] Preferably, in some embodiments of the present application, the first relay input circuit includes: a fifth fixed resistor R6, a sixth fixed resistor R7, a first transistor Q1, an input terminal NET1 and a first diode D1; wherein, the first end of the fifth fixed resistor R6 is externally connected to a 5V power supply; the second end of the fifth fixed resistor R6 is electrically connected to the input terminal NET1; the first end of the sixth fixed resistor R7 is electrically connected to the input terminal NET1; the second end of the sixth fixed resistor R7 is electrically connected to the base of the first transistor Q1; the collector of the first transistor Q1 is electrically connected to the power supply terminal 5 of the first relay; the emitter of the first transistor Q1 is electrically connected to the ground terminal; the positive electrode of the first diode D1 is electrically connected to the power supply terminal 5 of the first relay; the negative electrode of the first diode D1 is externally connected to a 12V power supply; and the negative electrode of the first diode D1 is electrically connected to the power supply terminal 1 of the first relay.

[0096] Preferably, in some embodiments of the present application, the second relay input circuit includes: a seventh fixed resistor R8, an eighth fixed resistor R9, a ninth fixed resistor R10, a second transistor Q3, a second diode D2, an input terminal NET2 and LED2; wherein the first end of the seventh fixed resistor R8 is externally connected to a 5V power supply; the second end of the seventh fixed resistor R8 is electrically connected to the input terminal NET2; the first end of the eighth fixed resistor R9 is electrically connected to the input terminal NET2; the second end of the eighth fixed resistor R9 is electrically connected to the base of the second transistor Q3; the emitter of the second transistor Q3 is electrically connected to the ground terminal; The collector of the second transistor Q3 is electrically connected to the power supply terminal 5 of the second relay; the anode of the second diode D2 is electrically connected to the power supply terminal 5 of the second relay; the cathode of the second diode D2 is electrically connected to the power supply terminal 1 of the second relay; the cathode of the second diode D2 is electrically connected to the second end of the ninth fixed resistor R10; the cathode of the second diode D2 is externally connected to a 12V power supply; the cathode of the LED2 is electrically connected to the power supply terminal 5 of the second relay; the anode of the LED2 is electrically connected to the first end of the ninth fixed resistor R10; the second end of the ninth fixed resistor R10 is electrically connected to the power supply terminal 1 of the second relay.

[0097] It can be seen from the above preferred embodiments that by connecting the first pulse current acquisition meter to the normally closed end of the first relay, connecting the first sampling resistor to the common end of the first relay and the second relay, connecting the output end of the first pulse current acquisition meter to the ground end, and connecting the normally open end of the second relay to the ground end, the first sampling resistor and the first pulse current acquisition meter can be connected in series by controlling the normally closed end of the first relay and the normally closed end of the second relay to close. When the normally open end of the first relay and the normally open end of the second relay are closed, the first pulse current acquisition meter is short-circuited, so that the first pulse current acquisition meter can be used to measure the voltage values ​​of other devices to be tested.

[0098] Further, in some embodiments of the present application, the switching of the connection relationship between each of the devices under test and the first pulse current acquisition table in the current reading circuit by the plurality of level signals to obtain the voltage value of each of the devices under test in the aging environment includes:

[0099] Inputting the plurality of level signals to the relay switch circuit in sequence to control the connection state between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit;

[0100] When the first pulse current acquisition meter is connected to the first sampling resistor corresponding to the relay switch circuit, a first current value of the first pulse current acquisition meter is read;

[0101] A voltage value corresponding to the device under test in the aging environment is obtained according to the first resistance value of the first sampling resistor and the first current value.

[0102] By connecting the corresponding relay switch circuit to each device under test, the control chip with multiple I / O interfaces can be used to flexibly read the test data of batch devices under test, which reduces the cost of the test method and improves the flexibility of test data reading. At the same time, the output state of the constant power supply is monitored by adding a sampling resistor. When the device under test ages, the resistance of the corresponding device under test changes, causing the output of the constant power supply to change, which is then monitored and recorded by the host computer, ultimately achieving accurate recording of the failure time of each test sample.

[0103] Further, in some embodiments of the present application, the step of sequentially inputting the plurality of level signals to the relay switch circuit to control the connection state between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit includes:

[0104] Input a low level to the first relay input circuit, and simultaneously input a low level to the second relay input circuit, so as to connect the first pulse current acquisition meter to the first sampling resistor corresponding to the device under test;

[0105] A high level is input to the first relay input circuit, and a high level is input to the second relay input circuit at the same time, so as to disconnect the first pulse current acquisition meter from the first sampling resistor corresponding to the device under test.

[0106] The control chip based on multiple I / O interfaces can output a level signal to the first relay input circuit and the second relay input circuit to control the first relay and the second relay to switch to a closed state, thereby flexibly controlling the connection state between each first sampling resistor and the first pulse current acquisition table. Therefore, when collecting the voltage value of the device under test, it is only necessary to connect the first sampling resistor corresponding to the device under test that needs to be collected at present to the first pulse current acquisition table, and disconnect the first sampling resistors corresponding to the other devices under test from the first pulse current acquisition table, so as to realize the measurement of the voltage value of each device under test in turn, thereby reducing the hardware cost of the test method.

[0107] Preferably, in some embodiments of the present application, the data collected by the first pulse current collection table in the current reading circuit is monitored by the host computer. When the sample fails, an alarm is sent to the test personnel through the network, and the operation of the pulse drive circuit corresponding to the channel is terminated. At the same time, by recording the real-time test data, the product failure time and failure rate are counted, and the test result chart is generated in the host computer program to facilitate subsequent data analysis.

[0108] Furthermore, in some embodiments of the present application, the step of establishing an aging environment corresponding to the device under test by using the third pulse signal includes:

[0109] The pulse aging system further includes: a test board; the test board includes a plurality of first interfaces and a plurality of second interfaces; the first interface is used to be electrically connected to the device under test or to be electrically connected to a device for providing a pulse light aging environment; the second interface is electrically connected to the output end of the switch of the first switch device;

[0110] The third pulse signal is received through the second interface, and the third pulse signal is transmitted to the device under test or a first device for providing a pulse light aging environment to the device under test through the first interface, so as to establish an aging environment for the device under test.

[0111] Preferably, reference Figure 6 and Figure 7, is an example of an aging board for different packaging structures such as TO and COC provided in some embodiments of the present application. In order to make the design of the aging board and the test fixture compatible with different packaging structures (sockets), such as Figure 6 and Figure 7 As shown, aging tests of multiple samples can be carried out simultaneously on the aging board. For different commonly used packaging structures such as TO and COC, it is necessary to design a fixture separately, but the circuit board wiring remains unchanged. Among them, the electrical connection between the aging board and the driver board can be in the form of a gold finger and a slot connector (i.e., the second interface), and the power supply circuit of each device under test in the aging board corresponds to the load circuit of the connector and the driver board one by one. In addition, the test can also be carried out by separate wiring, and each device under test is connected to each pulse constant source drive circuit separately by wiring. Therefore, the first interface includes but is not limited to the interface connected to the device under test in the aging board or the wiring connected to the device under test separately. At the same time, the heat dissipation of the chip should also be considered, and the aging structure design should support passive heat dissipation or water cooling of the matching heat sink. Furthermore, the host computer can independently control each pulse constant source drive circuit by adjusting parameters such as the output pulse signal pulse width and period.

[0112] Preferably, reference Figure 8 , is a schematic diagram of the structure of a light source board for a detector provided in some embodiments of the present application. The light source in the light source board is a first device for providing a pulse light aging environment to the device under test, so each light source is placed on the light source board according to the socket position (i.e., the distribution position of the device under test). From the above, it can be seen that the first interface also includes an output interface corresponding to the light source board or other first device that provides a pulse aging environment for the device under test. In order to make each device on the aging board receive light evenly, a uniform light plate is used to convert a linear light source or a point light source into a surface light source to ensure that each device on the aging board receives light evenly and is in the same aging condition. When selecting the light source, consider as many light sources that have passed the vehicle regulation certification as possible to ensure that the light source is in normal working condition during the entire test certification process. The light source board is powered by a current source, and the light intensity input into the photoelectric detection device can be controlled by adjusting the current source. Generally, a 1550nm infrared light source matches an APD, and a 905nm light source matches a SPAD and a SiPM.

[0113] It should be noted that the pulse constant source drive circuit in the drive board provided in some embodiments of the present application can be Figure 6 to Figure 7 The aging board shown provides a constant power output. The pulse constant source drive circuit can be used for Figure 6 and Figure 7 The device under test in the aging board shown in the figure directly provides the third pulse signal, so as to directly test the reliability of the device under test under the fourth pulse signal corresponding to the third pulse signal. The third signal is generated by the pulse constant source driving circuit, and further Figure 8 The light source board shown provides a fourth pulse signal with corresponding current, period, and duty cycle to ensure that the device under test is aged in the actual application scenario. Similarly, the pulse aging system can also independently control the lamp beads in the light source board and adjust the light-emitting state of the lamp beads to meet different test requirements.

[0114] In summary, a pulse aging method for a semiconductor light-emitting device provided in an embodiment of the present application has the following beneficial effects: in order to improve the universality of reliability testing under different types of devices under test, different numbers of devices under test, and different power-on environmental test requirements, a host computer is used to control multiple frequency circuits and pulse circuits to generate second pulse signals at different frequencies and pulse widths, and the first switching device is controlled to perform high-speed switching actions based on the second pulse signal, thereby affecting the waveform, frequency, and amplitude of the subsequently generated pulse output current, i.e., the third pulse signal, to meet the aging environment construction under different test requirements, and improve the versatility of the reliability test method for the device under test. At the same time, a current reading circuit is used, so that the user can control the host computer to output the corresponding level signal according to their own needs, and flexibly obtain the voltage value of each device under test in the current aging environment, thereby improving the flexibility of the device under test in obtaining the operating status during the test, while avoiding connecting an independent measuring device to each device under test, and reducing the hardware cost of the aging system.

[0115] Embodiment 2

[0116] refer to Fig. 9 , is a pulse aging device for a semiconductor light emitting device provided in some embodiments of the present application, applied to a host computer of a pulse aging system, wherein the pulse aging system further comprises: a plurality of frequency circuits, a plurality of pulse circuits, a plurality of first switch device switches and a current reading circuit, Fig. 9 The pulse aging device for a semiconductor light emitting device shown comprises: a first pulse signal acquisition module 11 , a second pulse signal acquisition module 12 and a test data reading module 13 .

[0117] Furthermore, in some embodiments of the present application, the first pulse signal acquisition module 11 is used to send a first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of a first frequency; the second pulse signal acquisition module 12 is used to send a second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, and to establish an aging environment for the corresponding device under test through the third pulse signal; the test data reading module 13 is used to send a number of level signals to the current reading circuit, and to switch the connection relationship between the device under test and the first pulse current acquisition table in the current reading circuit through the number of level signals to obtain the voltage value of each of the devices under test in the aging environment.

[0118] Furthermore, in some embodiments of the present application, the current reading circuit also includes: a plurality of relay switch circuits and a first sampling resistor corresponding to each relay switch circuit; wherein the first end of the first sampling resistor is electrically connected to the input end of the corresponding device under test; the second end of the first sampling resistor is electrically connected to the first input end of the corresponding relay switch circuit; the input end of the first pulse current acquisition meter is electrically connected to the first output end of each relay switch circuit; the second output end of each relay switch circuit is electrically connected to the first ground end; the output end of the first pulse current acquisition meter is electrically connected to the first ground end; and the host computer is electrically connected to the second input end of each relay switch circuit.

[0119] Further, in some embodiments of the present application, the connection relationship between each of the devices under test and the first pulse current acquisition table in the current reading circuit is switched by the plurality of level signals to obtain the voltage value of each of the devices under test in the aging environment, including: inputting the plurality of level signals into the relay switch circuit in sequence to control the connectivity state of the first pulse current acquisition table and the first sampling resistor corresponding to the relay switch circuit; when the first pulse current acquisition table is connected to the first sampling resistor corresponding to the relay switch circuit, reading the first current value of the first pulse current acquisition table; and obtaining the voltage value corresponding to the device under test in the aging environment according to the first resistance value of the first sampling resistor and the first current value.

[0120] Further, in some embodiments of the present application, the relay switch circuit includes: a first relay, a second relay, a first relay input circuit and a second relay input circuit; the first input end of the relay switch circuit includes: a common end of the first relay and a common end of the second relay; the second input end of the relay switch circuit includes: an input end of the first relay input circuit and an input end of the second relay input circuit; the first output end of the relay switch circuit includes a normally closed end of the first relay; the second output end of the relay switch circuit includes a normally open end of the second relay; wherein the host computer is electrically connected to the input end of the first relay input circuit; the host computer is electrically connected to the input end of the second relay input circuit; the output end of the first relay input circuit is electrically connected to the power supply end of the first relay; the output end of the second relay input circuit is electrically connected to the power supply end of the second relay; the first end of the first sampling resistor is electrically connected to the common end of the first relay; the first end of the first sampling resistor is electrically connected to the common end of the second relay.

[0121] Furthermore, in some embodiments of the present application, the plurality of level signals are sequentially inputted into the relay switch circuit to control the connectivity between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit, including: inputting a low level to the first relay input circuit and simultaneously inputting a low level to the second relay input circuit to connect the first pulse current acquisition meter with the first sampling resistor corresponding to the device under test; inputting a high level to the first relay input circuit and simultaneously inputting a high level to the second relay input circuit to disconnect the connectivity between the first pulse current acquisition meter and the first sampling resistor corresponding to the device under test.

[0122] Further, in some embodiments of the present application, the sending of the first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of the first frequency includes: wherein the frequency circuit includes: a first sliding resistor, a first fixed resistor, a first capacitor and a first timer chip; the first end of the first sliding resistor is electrically connected to the discharge end of the first timer chip; the second end of the first sliding resistor is electrically connected to the threshold end of the first timer chip; the second end of the first sliding resistor is electrically connected to the trigger end of the first timer chip; the second end of the first fixed resistor is electrically connected to the discharge end of the first timer chip; the first end of the first fixed resistor is electrically connected to the reset end of the first timer chip; the first end of the first fixed resistor is electrically connected to the reset end of the first timer chip; the first end of the first fixed resistor is electrically connected to the discharge end of the first timer chip The first end of the first capacitor is electrically connected to the power supply end of the first timer chip; the first end of the first capacitor is electrically connected to the threshold end of the first timer chip; the first end of the first capacitor is electrically connected to the trigger end of the first timer chip; the second end of the first capacitor is electrically connected to the ground end of the first timer chip; the power supply end of the first timer chip is externally connected to the first power supply; the reset end of the first timer chip is externally connected to the first power supply; the output end of the first timer chip is electrically connected to the corresponding pulse circuit; the power supply end of the first timer chip is electrically connected to the corresponding pulse circuit; the first pulse adjustment parameter is sent to each frequency circuit, so that the corresponding frequency circuit adjusts the corresponding first sliding resistor according to the first pulse adjustment parameter to generate a first pulse signal of the first frequency.

[0123] Furthermore, in some embodiments of the present application, the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, including: the pulse aging system also includes: a plurality of amplification circuits and a constant power supply; through the amplification circuit, amplifying the corresponding second pulse signal to obtain a fourth pulse signal; providing a constant power input to the first switching device through the constant power supply, and controlling the first switching device to perform a switching operation according to the fourth pulse signal to generate the third pulse signal.

[0124] Further, in some embodiments of the present application, the second pulse adjustment parameter is sent to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal, including: wherein the pulse circuit includes: a second sliding resistor, a second capacitor and a second timer chip; wherein the first end of the second sliding resistor is electrically connected to the power supply end of the first timer chip; the first end of the second sliding resistor is electrically connected to the reset end of the first timer chip; the first end of the second sliding resistor is electrically connected to the power supply end of the second timer chip; the second end of the second sliding resistor is electrically connected to the discharge end of the second timer chip; the second end of the second sliding resistor is electrically connected to the threshold end of the second timer chip; the second The first end of the capacitor is electrically connected to the discharge end of the second timer chip; the first end of the second capacitor is electrically connected to the threshold end of the second timer chip; the second end of the second capacitor is electrically connected to the ground end of the second timer chip; the reset end of the second timer chip is electrically connected to the output end of the first timer chip; the trigger end of the second timer chip is electrically connected to the output end of the first timer chip; the power supply end of the second timer chip is externally connected to the first power supply; the output end of the second timer chip is electrically connected to the corresponding amplification circuit; the second pulse adjustment parameter is sent to each pulse circuit, so that the corresponding pulse circuit adjusts the second sliding resistor according to the second pulse adjustment parameter, thereby adjusting the pulse width of the first pulse signal to generate a second pulse signal.

[0125] Furthermore, in some embodiments of the present application, the aging environment corresponding to the device under test is established through the third pulse signal, including: the pulse aging system, also including: a test board; the test board includes a plurality of first interfaces and a plurality of second interfaces; the first interface is used to electrically connect to the device under test or to electrically connect to a device used to provide a pulse light aging environment; the second interface is electrically connected to the output end of the switch of the first switching device; the third pulse signal is received through the second interface, and the third pulse signal is transmitted to the device under test or the first device used to provide a pulse light aging environment to the device under test through the first interface, so as to establish the aging environment of the device under test.

[0126] It can be understood that the above-mentioned device item embodiments correspond to the method item embodiments of the present invention. The pulse aging device of a semiconductor light-emitting device provided by the embodiment of the present invention can implement any method item embodiment of the present invention, that is, the pulse aging method of a semiconductor light-emitting device provided in Embodiment 1.

[0127] In summary, a pulse aging device for a semiconductor light-emitting device provided in an embodiment of the present application has the following beneficial effects: in order to improve the universality of reliability testing under different types of devices under test, different numbers of devices under test, and different power-on environment test requirements, a host computer is used to control multiple frequency circuits and pulse circuits to generate second pulse signals at different frequencies and pulse widths, and the first switching device is controlled to perform high-speed switching actions based on the second pulse signal, thereby affecting the waveform, frequency, and amplitude of the subsequently generated pulse output current, i.e., the third pulse signal, to meet the aging environment construction under different test requirements, and improve the versatility of the reliability test method for the device under test. At the same time, a current reading circuit is used, so that the user can control the host computer to output the corresponding level signal according to their own needs, and flexibly obtain the voltage value of each device under test in the current aging environment, thereby improving the flexibility of the device under test in obtaining the operating status during the test, while avoiding connecting an independent measuring device to each device under test, and reducing the hardware cost of the aging system.

[0128] Embodiment 3

[0129] Based on the above-mentioned embodiment of the pulse aging method of the semiconductor light-emitting device, another embodiment of the present application provides a pulse aging terminal device of the semiconductor light-emitting device, and the pulse aging terminal device of the semiconductor light-emitting device includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the pulse aging method of the semiconductor light-emitting device of any embodiment of the present application is implemented.

[0130] Exemplarily, in this embodiment, the computer program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present application. The one or more modules may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program in the pulse aging device of the semiconductor light-emitting device.

[0131] The pulse aging device of the semiconductor light emitting device may be a computing device such as a desktop computer, a notebook, a palm computer, a cloud server, etc. The pulse aging terminal device of the semiconductor light emitting device may include, but is not limited to, a processor and a memory.

[0132] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The processor is the control center of the pulse aging device of the semiconductor light-emitting device, and uses various interfaces and lines to connect the various parts of the pulse aging device of the entire semiconductor light-emitting device. The memory may be used to store the computer program and / or module, and the processor implements various functions of the pulse aging device of the semiconductor light-emitting device by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function, etc.; the data storage area may store data created according to the use of the mobile phone, etc. In addition, the memory may include high-speed random access memory and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0133] Embodiment 4

[0134] Based on the above-mentioned embodiment of the pulse aging method for a semiconductor light-emitting device, another embodiment of the present application provides a storage medium, wherein the storage medium includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute the pulse aging method for a semiconductor light-emitting device of any embodiment of the present application.

[0135] In this embodiment, the storage medium is a computer-readable storage medium, and the computer program includes computer program code, which may be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0136] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A pulse aging method for a semiconductor light emitting device, characterized in that: The host computer used in the pulse aging system includes: Wherein, the pulse aging system further comprises: a plurality of frequency circuits, a plurality of pulse circuits, a plurality of first switch device switches and a current reading circuit; Sending a first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of a first frequency; Sending a second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, and an aging environment corresponding to the device under test is established through the third pulse signal; A plurality of level signals are sent to the current reading circuit, and the connection relationship between the device under test and the first pulse current acquisition table in the current reading circuit is switched by the plurality of level signals to obtain the voltage value of each device under test in the aging environment.

2. A pulse aging method for a semiconductor light emitting device as claimed in claim 1, characterized in that: The current reading circuit further includes: a plurality of relay switch circuits and a first sampling resistor corresponding to each relay switch circuit; Among them, the first end of the first sampling resistor is electrically connected to the input end of the corresponding device under test; the second end of the first sampling resistor is electrically connected to the first input end of the corresponding relay switch circuit; the input end of the first pulse current acquisition meter is electrically connected to the first output end of each relay switch circuit; the second output end of each relay switch circuit is electrically connected to the first ground end; the output end of the first pulse current acquisition meter is electrically connected to the first ground end; and the host computer is electrically connected to the second input end of each relay switch circuit.

3. A pulse aging method for a semiconductor light emitting device as claimed in claim 2, characterized in that: The switching of the connection relationship between each of the devices under test and the first pulse current acquisition table in the current reading circuit by the plurality of level signals to obtain the voltage value of each of the devices under test in the aging environment includes: Inputting the plurality of level signals into the relay switch circuit in sequence to control the connection state between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit; When the first pulse current acquisition meter is connected to the first sampling resistor corresponding to the relay switch circuit, a first current value of the first pulse current acquisition meter is read; A voltage value corresponding to the device under test in the aging environment is obtained according to the first resistance value of the first sampling resistor and the first current value.

4. A pulse aging method for a semiconductor light emitting device as claimed in claim 2, characterized in that: The relay switch circuit comprises: a first relay, a second relay, a first relay input circuit and a second relay input circuit; the first input end of the relay switch circuit comprises: a common end of the first relay and a common end of the second relay; the second input end of the relay switch circuit comprises: an input end of the first relay input circuit and an input end of the second relay input circuit; the first output end of the relay switch circuit comprises a normally closed end of the first relay; the second output end of the relay switch circuit comprises a normally open end of the second relay; Among them, the host computer is electrically connected to the input end of the first relay input circuit; the host computer is electrically connected to the input end of the second relay input circuit; the output end of the first relay input circuit is electrically connected to the power supply end of the first relay; the output end of the second relay input circuit is electrically connected to the power supply end of the second relay; the first end of the first sampling resistor is electrically connected to the common end of the first relay; the first end of the first sampling resistor is electrically connected to the common end of the second relay.

5. A pulse aging method for a semiconductor light emitting device as claimed in claim 3 or 4, characterized in that: The step of sequentially inputting the plurality of level signals to the relay switch circuit to control the connection state between the first pulse current acquisition meter and the first sampling resistor corresponding to the relay switch circuit includes: Input a low level to the first relay input circuit, and simultaneously input a low level to the second relay input circuit, so as to connect the first pulse current acquisition meter to the first sampling resistor corresponding to the device under test; A high level is input to the first relay input circuit, and a high level is input to the second relay input circuit at the same time, so as to disconnect the first pulse current acquisition meter from the first sampling resistor corresponding to the device under test.

6. A pulse aging method for a semiconductor light emitting device as claimed in claim 1, characterized in that: sending a first pulse adjustment parameter to each of the frequency circuits so that the corresponding frequency circuit generates a first pulse signal of a first frequency, include: Wherein, the frequency circuit includes: a first sliding resistor, a first fixed resistor, a first capacitor and a first timer chip; the first end of the first sliding resistor is electrically connected to the discharge end of the first timer chip; the second end of the first sliding resistor is electrically connected to the threshold end of the first timer chip; the second end of the first sliding resistor is electrically connected to the trigger end of the first timer chip; the second end of the first fixed resistor is electrically connected to the discharge end of the first timer chip; the first end of the first fixed resistor is electrically connected to the reset end of the first timer chip; the first end of the first fixed resistor is electrically connected to the power supply end of the first timer chip; the first end of the first capacitor is electrically connected to the threshold end of the first timer chip; the first end of the first capacitor is electrically connected to the trigger end of the first timer chip; the second end of the first capacitor is electrically connected to the ground end of the first timer chip; the power supply end of the first timer chip is externally connected to the first power supply; the reset end of the first timer chip is externally connected to the first power supply; the output end of the first timer chip is electrically connected to the corresponding pulse circuit; the power supply end of the first timer chip is electrically connected to the corresponding pulse circuit; A first pulse adjustment parameter is sent to each of the frequency circuits, so that the corresponding frequency circuit adjusts the corresponding first sliding resistor according to the first pulse adjustment parameter to generate a first pulse signal of a first frequency.

7. A pulse aging method for a semiconductor light emitting device as claimed in claim 1, characterized in that: The second pulse signal is used to control the first switching device to generate a third pulse signal, including: The pulse aging system also includes: a number of amplification circuits and a constant power supply; Amplifying the second pulse signal through the amplifying circuit to obtain a fourth pulse signal; The constant power supply is provided to the first switching device through the constant power supply, and the first switching device is controlled to perform a switching operation according to the fourth pulse signal to generate the third pulse signal.

8. A pulse aging method for a semiconductor light emitting device as claimed in claim 6 or 7, characterized in that: The sending of the second pulse adjustment parameter to each of the pulse circuits so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal includes: Wherein, the pulse circuit includes: a second sliding resistor, a second capacitor and a second timer chip; Wherein, the first end of the second sliding resistor is electrically connected to the power supply end of the first timer chip; the first end of the second sliding resistor is electrically connected to the reset end of the first timer chip; the first end of the second sliding resistor is electrically connected to the power supply end of the second timer chip; the second end of the second sliding resistor is electrically connected to the discharge end of the second timer chip; the second end of the second sliding resistor is electrically connected to the threshold end of the second timer chip; the first end of the second capacitor is electrically connected to the discharge end of the second timer chip; the first end of the second capacitor is electrically connected to the threshold end of the second timer chip; the second end of the second capacitor is electrically connected to the ground end of the second timer chip; the reset end of the second timer chip is electrically connected to the output end of the first timer chip; the trigger end of the second timer chip is electrically connected to the output end of the first timer chip; the power supply end of the second timer chip is externally connected to the first power supply; the output end of the second timer chip is electrically connected to the corresponding amplification circuit; A second pulse adjustment parameter is sent to each of the pulse circuits, so that the corresponding pulse circuit adjusts the second sliding resistor according to the second pulse adjustment parameter, thereby adjusting the pulse width of the first pulse signal to generate a second pulse signal.

9. A pulse aging method for a semiconductor light emitting device as claimed in claim 1, characterized in that: The step of establishing an aging environment corresponding to the device under test by using the third pulse signal includes: The pulse aging system further includes: a test board; the test board includes a plurality of first interfaces and a plurality of second interfaces; the first interface is used to be electrically connected to the device under test or to be electrically connected to a device for providing a pulse light aging environment; the second interface is electrically connected to the output end of the switch of the first switch device; The third pulse signal is received through the second interface, and the third pulse signal is transmitted to the device under test or a first device for providing a pulse light aging environment to the device under test through the first interface, so as to establish an aging environment for the device under test.

10. A pulse aging device for a semiconductor light emitting device, characterized in that: The host computer used in the pulse aging system includes: a first pulse signal acquisition module, a second pulse signal acquisition module and a test data reading module; Wherein, the pulse aging system further comprises: a plurality of frequency circuits, a plurality of pulse circuits, a plurality of first switch device switches and a current reading circuit; The first pulse signal acquisition module is used to send a first pulse adjustment parameter to each of the frequency circuits, so that the corresponding frequency circuit generates a first pulse signal of a first frequency; The second pulse signal acquisition module is used to send a second pulse adjustment parameter to each of the pulse circuits, so that the corresponding pulse circuit adjusts the pulse width of the first pulse signal to generate a second pulse signal; wherein the second pulse signal is used to control the switch of the first switching device to generate a third pulse signal, and the aging environment of the corresponding device under test is established through the third pulse signal; The test data reading module is used to send a number of level signals to the current reading circuit, and switch the connection relationship between the device under test and the first pulse current acquisition table in the current reading circuit through the number of level signals to obtain the voltage value of each device under test in the aging environment.

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