Apparatus, method and system for field channel testing and repair using three-dimensional integrated circuits

Abstract

Devices, methods, and systems for field channel testing and repair using three-dimensional integrated circuits are disclosed. Techniques and mechanisms for integrated circuit (IC) dies to support field testing and / or repair of channels in a three-dimensional (3D) IC formed with multiple IC dies. In an embodiment, a 3D IC includes test cells, each test cell corresponding to a different partition including a respective circuit resource. During field operation of the 3D IC, a given test unit is operable to detect both a first condition in which the two partitions are each in an idle state and a second condition in which a first link between the two partitions does not meet performance criteria. The idle state is indicated by a power management controller (PMC) agent during runtime operation of the 3D IC. In another embodiment, the one or more test units configure an operating mode based on the detected condition to replace communication via the first channel with communication via the repair channel.

Description

background 1. Technical Field

[0001] The present disclosure relates generally to performance testing of inter-die communications and, more particularly but not exclusively, to field testing and repair of channel three-dimensional (3D) integrated circuits (ICs). 2. Background technology

[0002] Over time, the design of integrated circuits (ICs) has become increasingly complex in pursuit of higher computational throughput, efficiency, and reduced power consumption. Interconnect scaling is a major barrier to IC performance improvement. Interconnect scaling is a major contributor to circuit latency and power consumption. Three-dimensional (3-D) integration, particularly stacked 3D ICs, is a technology that helps overcome this barrier. Compared to traditional two-dimensional (2D) ICs, the average interconnect length (i.e., the distance between discrete ICs that are communicatively connected via the interconnect (which is the communication medium)) of 3D stacked ICs is significantly smaller. Using 3D stacked ICs provides for shorter interconnect lengths. Due to the shorter interconnect length, 3D stacked ICs have lower power consumption and a smaller form factor than 2D ICs with similar computing power.

[0003] ICs are typically formed on (one or more) dies, which include a block of semiconductor material on which a given IC is manufactured. The dies can be designed using different techniques. These die manufacturing techniques can be integrated using 3D stacking of ICs, thereby improving system integration efficiency. Such stacking is commonly used in various computing architectures, including system on a chip (SOC) architectures.

[0004] Two common methods of stacking dies in 3D space are "face-to-face" (F2F) bonding and "face-to-back" (F2B) bonding. In F2B bonding, the outermost metal layer (front side) of one die is connected to TSVs (through-silicon vias) on the substrate layer (back side) of another die. In contrast, F2F bonding connects the metal layers of two dies through microbumps, and TSVs are specifically used to connect any major input / output (IO) to the package bumps. "Bumps" in this context refer to interfaces that are usually located in a connection package and are used to provide an interface between the die and the package or housing of the IC, or between a packaged IC and a circuit board, or between a packaged IC and another packaged IC.

[0005] However, using these 3D stacked ICs presents problems in testing the operation of each stacked IC in the stack and the interconnections therebetween.As the number and variety of 3D IC technologies continue to grow, it is expected that more attention will be paid to improving solutions for how to detect and resolve 3D IC performance issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which:

[0007] Figure 1 A functional block diagram illustrating features of a system for determining whether to perform live channel repair is shown, according to an embodiment.

[0008] Figure 2 A flow chart illustrating features of a method of performing field operations using a 3D IC is shown, according to an embodiment.

[0009] Figure 3 A functional block diagram illustrating features of a die for selectively replacing a 3D IC channel with a replacement 3D IC channel in accordance with an embodiment.

[0010] Figure 4 A functional block diagram illustrating features of a system for performing live channel repair in multiple partitioned clock domains is shown, according to an embodiment.

[0011] Figure 5 A functional block diagram illustrating features of a die for configuring a field channel repair function of a built-in self-test unit is shown, according to an embodiment.

[0012] Fig. 6A , Figure 6B Functional block diagrams are shown that each illustrate respective features of a system that provides various operating modes to facilitate field channel repair, according to an embodiment.

[0013] Figure 7 A functional block diagram illustrating features of a system for facilitating predictive live channel repair functionality is shown, according to an embodiment.

[0014] Figure 8 A functional block diagram illustrating features of an apparatus for providing in-situ channel testing and repair functionality is shown, according to an embodiment.

[0015] Fig. 9 An exemplary system is shown.

[0016] Fig.10 A block diagram of an example processor that may have more than one core and may have an integrated memory controller is shown.

[0017] Fig.11Ais a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to examples.

[0018] Fig. 11B is a block diagram illustrating both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0019] Fig.12 The figure shows an example of execution unit(s) circuitry.

[0020] Fig.13 is a block diagram of a register architecture according to some examples. DETAILED DESCRIPTION

[0021] The embodiments discussed herein provide the following techniques and mechanisms for a given channel in various ways: facilitating inter-die communication for field testing, and optionally replacing such inter-die communication with another line. The terms "repair channel" and "replacement channel" are used in various ways herein to refer to a channel that can be used as a replacement for some other channel for inter-die communication. Unless otherwise indicated, a repair channel is a channel that has not yet been allocated for inter-die communication. A channel that has been used for (e.g., is being used for) inter-die communication and is a candidate for being replaced by a repair channel is referred to herein as a "functional channel."

[0022] However, in some embodiments, a given channel is both a functional channel and a candidate channel to be used as a replacement for another functional channel, for example, where a repair channel (not yet allocated for use) is similarly a candidate channel to be used as a replacement for the given functional channel. By way of example and not limitation, in some embodiments, repairing a functional channel includes decoupling the functional channel from a first transmitter (Tx) circuitry of a first die and a first receiver (Rx) circuitry of a second die, wherein repairing further includes coupling the repair channel to the first Tx circuitry and to the first Rx circuitry.

[0023] However, in other embodiments, the channel repair operation includes decoupling the first functional channel from both the first Tx circuit system of the first tube core and the first Rx circuit system of the second tube core, wherein the operation further includes decoupling the second functional channel from the second Tx circuit system of the first tube core and the second Rx circuit system of the second tube core. In addition, this repair operation includes coupling the second functional channel to the first Tx circuit system and the first Rx circuit system, and coupling the repair channel to the second Tx circuit system and to the second Rx circuit system. It should be understood that unless otherwise specified, "channel" or "the channel" (i.e., without the adjective "repair" or "replacement") refers to a functional channel in this article. Some embodiments extend this type of channel repair-for example, wherein the switch circuit system is operated so that the corresponding correspondence of two or more functional channels is shifted to the corresponding Tx circuit in the Tx circuit sequence in various ways, and the corresponding correspondence of two or more functional channels is shifted to the corresponding Rx circuit in the Rx circuit sequence. After such operation, one functional channel is disabled from participating in communications between any of the Tx circuits and the Rx circuits - for example, where the repair channel is coupled as a replacement for the one functional channel.

[0024] Three-dimensional (3D) integrated circuit or "3D IC" technologies have been widely used in various packaged system architectures. These 3D IC technologies provide three-dimensional integrated circuits (ICs) in various ways, where multiple integrated circuit (IC) dies or wafers are stacked together vertically - for example, stacked into a single package. Within such a package, the dies are interconnected in various ways using through-silicon vias (TSVs), hybrid bonding, etc.

[0025] In a typical example of a 3D IC system, multiple dies are coupled to each other in various ways to form one or more stacked arrangements. As an illustration and not limitation, one or more dies (e.g., including some or all of a computing die, an input / output (IO) expansion die, a system on chip (SOC) die, a graphics processor (GFX) die, etc.) are coupled in various ways to an underlying die, which includes, for example, cache memory and / or any of a variety of other memory resources. For a given communication in such a 3D IC system, one die will operate as a transmitter (Tx) die, and another die will operate as a receiver (Rx) die. For example, a SoC die is used as a transmitting die for communication via a first path (or "channel" herein), wherein a computing die is used as a receiving die for the communication.

[0026] Some embodiments variously include or otherwise facilitate replacing a signal communication path (channel) with a replacement signal communication path - for example, based on determining that a signal communication path is defective or is predicted to become defective according to some predetermined criteria. In various embodiments, a 3D IC system includes at least one channel - referred to herein as a "repair channel" or "redundant channel" - that is switchably coupled to a corresponding transmitter tube core (and / or switchably coupled to a corresponding receiver tube core). For example, such a repair channel can be used to replace a defective channel - for example, wherein, after such replacement, the repair channel is used for runtime signal communication and / or other suitable functional operations as a replacement for the defective channel.

[0027] Prior art replaces defective channels with repair channels at the manufacturing stage or packaging stage (e.g., before the die in question (or the package including the die) is sent to an original equipment manufacturer, an end user, or other such consumer). For example, the die in question (or a 3D IC formed with the die) includes or is otherwise coupled to a test access point (TAP), through which the die or 3D IC is subjected to channel testing performed by an external test unit. However, existing methods of testing and repairing channels cannot be implemented directly in the field, at least without significantly affecting the performance of the field system. For example, one major reason is to perform channel testing on transmitter and receiver dies in a single synchronous clock domain. In many use cases, such a synchronous clock domain covers different transmitter resources and receiver resources, and according to the prior art, each resource needs to be in a corresponding idle (IDLE) state during channel testing. However, for (for example) various data center and server SOCs, it is unlikely that such multiple resources will be in a corresponding idle state at the same time.

[0028] Existing channel testing mechanisms (e.g., used offline in a lab environment and / or during any of the various manufacturing stages) do not take into account, at a resource-specific level of granularity, whether a particular one of a set of transmitter and receiver resources is currently in an idle state as occurs during field operation. In an example embodiment, one such resource is the transmitter circuitry or receiver circuitry of one die, where the resource is configured for communication with another such resource, which is the receiver circuitry or transmitter circuitry of another die (and is to operate in the same common clock domain). In a typical 3D IC system, only a microcontroller (such as a power management controller (PMC)) has relatively fine knowledge of which particular transmitter resource(s) or which receiver resource(s), if any, is currently in an idle state.

[0029] For at least these reasons, existing technologies are unable to efficiently screen and repair 3D IC channel defects that occur in the field. Some of these existing technologies will require at least multiple dies of the 3D IC system to be offline to enable channel testing and repair. However, many end users (such as data centers) are very sensitive to such constraints.

[0030] The techniques described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the techniques described herein include any type of mobile and / or fixed device, such as a camera, a cellular phone, a computer terminal, a desktop computer, an e-reader, a fax machine, a kiosk, a laptop computer, a netbook computer, a notebook computer, an Internet appliance, a payment terminal, a personal digital assistant, a media player and / or recorder, a server (e.g., a blade server, a rack-mounted server, a combination thereof, etc.), a set-top box, a smart phone, a tablet personal computer, an ultra-mobile personal computer, a wired telephone, a combination of the above, and the like. More generally, the techniques described herein may be employed in any of a variety of electronic devices, the various electronic devices including one or more IC die, wherein each IC die includes a corresponding built-in self-test (BIST) unit to facilitate field channel testing and repair functions.

[0031] Figure 1 Features of a system 100 for determining whether to perform field channel repair according to an embodiment are shown. System 100 illustrates an example of an embodiment that supports evaluation of one or more field performance characteristics of a given functional channel. In an embodiment, system 100 adapts or otherwise improves the prior art by facilitating field channel testing and repair. For example, system 100 improves various prior art at least to the extent that it enables field detection of defective channels without completely offline resource clusters (in SoCs, servers, client platforms, or other such systems). In one such embodiment, system 100 is operable to perform channel repair when first resources in a clock domain are each in a corresponding idle state and other resources in the same clock domain (e.g., including other signal source circuits and / or other signal sink circuits) are each in a corresponding active (i.e., non-idle) state.

[0032] like Figure 1As shown in , system 100 includes integrated circuit (IC) dies 110, 150 coupled to each other in a 3D IC arrangement including one or more functional channels (such as the illustrative channel 102 shown) and one or more repair channels (such as the illustrative repair channel 104 shown). A first hardware interface of die 110 includes conductive contacts 114 (e.g., including metal pads, balls, bumps, etc.) and conductive contacts 116, wherein a second hardware interface of die 150 similarly includes conductive contacts 154 and conductive contacts 156. In the example embodiment shown, conductive contacts 114 are each coupled to different corresponding ones of conductive contacts 154 of die 150 via channel 102 in various ways, for example, wherein conductive contacts 116 are each coupled to corresponding ones of conductive contacts 156 via repair channel 104 in various ways.

[0033] In an embodiment, die 110 includes source circuitry 112, mode circuitry 140, transmit (Tx) built-in self-test (BIST) unit 130, power management control (PMC) agent 120, and interface circuitry 122. Similarly, die 150 includes sink circuitry 152, mode circuitry 180, receive (Rx) BIST unit 170, PMC agent 160, and interface circuitry 162. In some alternative embodiments, the functions of PMC agents 120, 160 are combined in a single PMC agent. Additionally or alternatively, in some other embodiments, PMC agent 120 is external to die 110 and / or PMC agent 160 is external to die 150.

[0034] In various embodiments, the Tx BIST unit 130 and the Rx BIST unit 170 (e.g., each including any of various suitable types of hardware, firmware, and / or execution software) provide functionality for performing field channel testing based on one or more idle states, each idle state for a different corresponding partition of a clock domain. In this particular context, "partition" herein refers to a set of circuit resources for which channel testing and repair functionality is supported by a corresponding test unit (such as a BIST unit). In some embodiments, the 3D IC includes multiple sets of circuit resources that are partitioned at least to the extent that each set corresponds to and is supported by a different corresponding test unit. In one such embodiment, the resource sets are partitioned from each other in one or more additional or alternative aspects. As an illustration and not limitation, in an embodiment, a set of circuit resources of one die is partitioned from another set of circuit resources of a different die. Alternatively or additionally, different sets of circuit resources of the same die are partitioned from each other according to their corresponding functions-for example, where some or all signal source resources of a given die are partitioned from some or all signal sink resources of the same given die. In some embodiments, multiple partitions of the 3D IC each operate in the same clock domain.

[0035] In the example embodiment shown, a first partition of the 3D IC includes source circuitry 112 of die 110 that includes any of a variety of suitable circuits to generate, forward, or otherwise provide one or more signals to be communicated from die 110 via a first hardware interface. Additionally, a second partition of the 3D IC includes sink circuitry 152 of die 150 that includes any of a variety of suitable circuits to receive (and, e.g., parse, decode, forward, and / or otherwise process) one or more signals to be communicated to die 150 via a second hardware interface.

[0036] Some embodiments perform in-field channel repair in various ways based on channel testing, such as the channel testing supported by Tx BIST unit 130 and Rx BIST unit 170. In one such embodiment, in-field channel repair is performed on a predictive basis—e.g., where a repair channel is substituted for a functional channel prior to an expected future failure of the functional channel.

[0037] In the example embodiment shown, Tx BIST unit 130 is coupled to receive status information from PMC agent 120 during field operation of the 3D IC. For example, PMC agent 120 includes any of various suitable types of hardware, firmware, and / or executive software operable to facilitate management of power and / or performance characteristics of die 110 and / or other circuitry of system 100. In one such embodiment, PMC agent 120 includes, for example, microcontroller circuitry adapted from any of various conventional power management control techniques.

[0038] The state information provided by the PMC agent 120 specifies or otherwise indicates one or more operating states for a respective one of the plurality of partitions of the 3DIC - for example, where the first partition includes the source circuit system 112 and the second partition includes the sink circuit system 152. In one embodiment, the state information identifies one or more operating states at each partition granularity level - for example, where the source circuit system 112 and the sink circuit system 152 are respectively identified as being in a respective state in an idle state or a non-idle (i.e., "active") state. In this particular context, an "idle state" refers to an operating state in which signal communication to or from a given partition is not currently occurring and / or is not expected (e.g., at least for a certain threshold minimum time period). In contrast, an "active state" (or "non-idle" state) refers to an operating state in which signal communication to or from a given partition is occurring and / or is expected (e.g., at least for a certain threshold minimum time period) to occur.

[0039] In some embodiments, Rx BIST unit 170 is similarly coupled to receive the same (or related) status information from PMC agent 160, e.g., during field operation of the 3D IC. In the example embodiment shown, die 110 includes PMC agent 120, and die 150 includes Rx BIST unit 170. However, in alternative embodiments, PMC agent 120 is external to die 110 and / or PMC agent 160 is external to die 150. Additionally or alternatively, one of PMC agent 120 or PMC agent 160 provides status information to the other of PMC agent 120 or PMC agent 160—e.g., for relaying the status information to a corresponding one of Tx BIST unit 130 or Rx BIST unit 170. In yet another embodiment, Tx BIST unit 130 and Rx BIST unit 170 receive status information from the same PMC agent—e.g., where system 100 omits one of PMC agents 120, 160.

[0040] Based on the status information provided by the power management logic (such as the power management logic of PMC agent 120 and / or PMC agent 160), Tx BIST unit 130 and PMC agent 160 detect the occurrence of one or more conditions in various ways, which one or more conditions (for example) will be used as the basis for channel testing operations and / or the basis for channel repair operations. For example, Tx BIST unit 130 and PMC agent 160 (respectively) detect a first condition in various ways based on the status information from PMC agent 120 and PMC agent 160, in which the first partition (including source circuit system 112) and the second partition (including sink circuit system 152) are each in a corresponding idle state.

[0041] In some embodiments, the Tx BIST unit 130 and / or the Rx BIST unit 170 further generates, receives, or otherwise identifies performance information that at least in part determines whether to perform channel repair during the first condition. For example, the PMC agent 120 (or any of a variety of other suitable PMC resources) programs or otherwise configures one or more registers of the Tx BIST unit 130 (such as the illustrated (one or more) illustrative configuration registers 132) with information for facilitating channel testing. For example, such information describes the channel test to be performed—e.g., by specifying or otherwise identifying the duration of the channel test, the channel to be tested, the test signature (or other suitable test information) to be communicated via the tested channel, etc. In some embodiments, the (one or more) configuration registers 132 further serve as a repository for given channel test results. Similarly, the PMC agent 160 (or any of a variety of other suitable PMC resources) programs or otherwise configures one or more registers of the Rx BIST unit 170 (such as the illustrative configuration register(s) 172 shown) with information (such as provided to the configuration register(s) 132).

[0042] In one such embodiment, the performance information is generated as a result of a channel test performed, for example, based on the detection of a first condition. For example, such a channel test includes Tx BIST unit 130 transmitting test information via the first channel (i.e., the channel under test) when the first channel is not being used by source circuit system 112 and sink circuit system 152. RxBIST unit 170 performs operations to determine whether the value (if any) received via the first channel during the channel test matches some predetermined reference value (such as the original defined value of the test information). In the event that the channel test detects that a given functional channel is unable to convey such test information (or fails to meet some other performance criteria), Tx BIST unit 130 and Rx BIST unit 170 perform channel repair operations to replace the functional channel in question with a repair channel for communication between die 110 and die 150.

[0043] In the example embodiment shown, the mode circuitry 140 is coupled to the Tx BIST unit 130 and is further coupled between the source circuitry 112 and a hardware interface including the conductive contacts 114 and the conductive contacts 116. The mode circuitry 140 includes any of various combinations of switches, multiplexers, and / or other suitable circuit structures that are operable to (e.g., in response to the controller 138 of the Tx BIST unit 130) selectively enable or disable one or more conductive paths, each between a respective input of the source circuitry 112 and a respective one of the conductive contacts 114, 116. Additionally, the mode circuitry 180 is coupled to the Rx BIST unit 170 and is further coupled between the sink circuitry 152 and a hardware interface including the conductive contacts 154 and the conductive contacts 156. Mode circuitry 180 is operable (eg, in response to controller 178 of Rx BIST unit 170 ) to selectively enable or disable one or more conductive paths each between a respective input from sink circuitry 152 and a respective one of conductive contacts 154 , 156 .

[0044] In another embodiment, the Tx BIST unit 130 and the Rx BIST unit 170 perform channel repair based on information received from one or more sensors (not shown) that are coupled to monitor one or more characteristics of communication via the functional channel. For example, in some embodiments, the system 100 further includes one or more sensors (included in one or both of the PMC agents 120, 160, or coupled to one or both of the PMC agents 120, 160), which provide sensor information that specifies or otherwise indicates to the Tx BIST unit 130 and / or the Rx BIST unit 170 one or more performance metrics, including but not limited to the setup time required to communicate information via the first channel.

[0045] In an illustrative scenario according to one embodiment, Tx BIST unit 130 and / or Rx BIST unit 170 detects that the setup time (or other such performance metric) fails to meet a threshold condition based on such performance information. Based on such failure, a channel repair operation is performed to replace the first channel with a repair channel for communication between die 110 and die 150. For example, such channel repair operations include controller 138, 178 signaling mode circuitry 140 and mode circuitry 180 (respectively) in various ways to selectively enable or disable various signal paths through which source circuitry 112 and sink circuitry 152 will participate in communication via the respective hardware interfaces of die 110, 150.

[0046] Some embodiments adapt in various ways circuit structures that facilitate other channel testing and / or channel repair operations that are performed using external test units in accordance with conventional techniques—e.g., prior to field operation of system 100 (e.g., during any of semiconductor manufacturing, packaging, assembly, and / or various other stages). For example, some embodiments incorporate the use of any of a variety of interconnect structures used in conventional channel testing operations and / or channel repair operations. By way of illustration and not limitation, die 110 further includes interface circuitry 122 that is coupled to receive status information, configuration information, performance information, etc. from PMC agent 120 and to provide such information to Tx BIST unit 130 via bus 124 that is (e.g.) compatible with any of a variety of conventional test bus standards. In one such embodiment, the test bus standard is a standard developed by the Joint Test Action Group—for example, where the test bus standard is defined or otherwise identified in the IEEE 1149.1 specification published on May 13, 2013 by the Institute of Electrical and Electronics Engineers, Piscataway, New Jersey, USA.

[0047] Alternatively or additionally, die 150 further includes interface circuitry 162 coupled to similarly receive information from PMC agent 160 and to provide such information to Rx BIST unit 170 via bus 164 that is compatible with such test bus standard. In some embodiments, interface circuitry 122 and / or interface circuitry 162 provide functionality to convert, reformat, or otherwise process information to accommodate communications via bus 124, 164 in various ways—e.g., by converting information from a format that enables communication via a PMC protocol bus to another format that enables communication via a JTAG protocol bus.

[0048] In one such embodiment, the interface circuitry 122 or the interface circuitry 162 is further coupled to another test bus (not shown) that is a product of a structure used in conventional channel testing prior to field use of the system 100. For example, such conventional channel testing is performed when the system 100 (or at least one or more components thereof) is coupled to an external test unit via a test access point (TAP), which is subsequently decoupled from any or all components of the system 100. In one such embodiment, the interface circuitry 122 includes a multiplexer circuitry for selecting between coupling the bus 124 to the PMC agent 120 and coupling the bus 124 to a production test bus. Alternatively or additionally, the interface circuitry 162 includes a multiplexer circuitry for selecting between coupling the bus 164 to the PMC agent 160 and coupling the bus 164 to a production test bus.

[0049] Figure 2 Features of a method 200 for performing field operations using a 3D IC according to an embodiment are shown. For example, operations such as those of method 200 are performed using some or all of system 100. Figure 2 As shown in , method 200 includes (at 210) receiving status information from a PMC agent at a test unit of a first IC die. The first IC die and the second IC die are coupled to form some or all of a 3D IC, wherein the test unit receives status information during field operation of the 3D IC. In this context, "field operation" refers to any of a variety of operations other than operations that are used only for performance evaluation of the 3D IC by an external test unit (if any) that is directly or indirectly coupled to the 3D IC. As an illustration and not limitation, field operation of the 3D IC includes execution of a sequence of instructions by one or more processors of the 3D IC, or is concurrent with execution of a sequence of instructions by one or more processors of the 3D IC. Alternatively or additionally, field operation of the 3D IC is performed when a system including the 3D IC is decoupled from any external test unit that would otherwise perform testing of the 3D IC.

[0050] In one embodiment, the receiving at 210 includes: the Tx BIST unit 130 receives information from the PMC agent 120, which specifies or otherwise indicates (e.g., at a partition-specific granularity level) that one or more of the plurality of partitions of the 3D IC are currently each in (or expected to be in) a corresponding idle state. For example, the plurality of partitions each operate in a first clock domain. In some embodiments, the receiving at 210 additionally or alternatively includes (e.g.,) the Rx BIST unit 170 receives information from the PMC agent 160.

[0051] In various embodiments, an interface circuit system (such as interface circuit system 122) is coupled between the PMC agent and the test unit, wherein the interface circuit system provides status information to the test unit via a bus compatible with a test bus standard. In one such embodiment, the test bus standard is identified in the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 specification.

[0052] Based on the status information received at 210, method 200 detects (at 212) a first condition in which a first partition of the first IC die and a second partition of the second IC die are each in a corresponding idle state. In some embodiments, the 3D IC includes a first channel that is coupled to enable communication between the first partition and the second partition. In one such embodiment, the test unit is a first test unit, wherein a plurality of partitions of the 3D IC (e.g., including a first partition and a second partition) each correspond to a different respective test unit of a plurality of test units. For example, the plurality of partitions include a first partition and a second partition, wherein, for each test unit of the plurality of test units, one or more PMC agents are coupled to provide the respective status information to the test unit.

[0053] In an illustrative scenario according to one embodiment, a first partition includes a first signal source circuitry (such as source circuitry 112) of a first IC die, and a second partition includes a first signal sink circuitry (such as sink circuitry 152) of a second IC die. In one such embodiment, a third partition of the 3D IC includes a second signal source circuitry of the second IC die, wherein a fourth partition of the 3D IC includes a second signal sink circuitry of the first IC die. The first condition is detected at 212, for example, when one or more other partitions (e.g., including the third and fourth partitions described above) are each in a respective active state, although some embodiments are not limited in this regard.

[0054] The method 200 further includes (at 214) detecting a second condition in which one or more communications by the first channel fail to meet a performance criterion. For example, in various embodiments, the method 200 includes: the test unit receiving test data from the PMC agent, performing communication of the test data from the first IC die via the first channel. In one such embodiment, the second IC die (e.g., its test unit) generates a value based on the communication, wherein at 214, the second condition is detected based on the second IC die detecting a mismatch between the value and a reference value.

[0055] In various other embodiments, method 200 includes the test unit receiving performance information from a sensor coupled to monitor or otherwise detect one or more characteristics of communications via the first channel. In one such embodiment, detecting the second condition at 214 includes identifying that a performance metric fails to satisfy a threshold condition based on the performance information, wherein the performance metric is based on the one or more communications via the first channel. For example, in some embodiments, the performance metric is a setup time (or a setup time margin).

[0056] The method 200 further includes an operation 202 performed based on the first condition and the second condition, for example, wherein the operation 202 is performed during the first condition based on a channel test failure or based on a sensor detecting that the first channel fails to meet a threshold of a performance metric. For example, the operation 202 includes disabling (at 216) a first conductive path between the first channel and the first partition. In addition, the operation 202 includes enabling (at 218) a second conductive path between a second channel (i.e., a repair channel) of the 3D IC and the first partition or the second partition. In an example embodiment, the operation 202 includes: the controller 138 and the controller 178 operate the mode circuit system 140 and the mode circuit system 180 in various ways to decouple one of the channels 102 from the source circuit system 112 and the sink circuit system 152 in a switching manner, and couple one of the repair channels 104 to the source circuit system 112 and the sink circuit system 152 in a switching manner.

[0057] Figure 3 Features of a die 300 for selectively replacing a 3D IC channel with a repair 3D IC channel according to an embodiment are shown. Die 300 illustrates an example of an embodiment in which a 3D IC includes a BIST unit (e.g., Rx BIST or TxBIST) that is configurable to perform a channel test operation and selectively perform a channel repair operation that replaces a channel with another channel that fails to meet a communication performance standard. In various embodiments, die 300 provides functionality such as functionality of system 100—e.g., in which one or more operations of method 200 are performed using die 300.

[0058] like Figure 3 As shown in , the hardware interface of die 300 facilitates coupling to another die (not shown). For example, conductive contacts 314 of the hardware interface facilitate inter-die communication with a respective one of functional channels 302 - for example, where other conductive contacts 316 of the hardware interface can be used to each alternately facilitate inter-die communication with a respective one of repair channels 304.

[0059] In various embodiments, die 300 provides functionality similar to one of dies 110, 150. For example, source / sink circuitry 312 of die 300 provides functionality of source circuitry 112 or sink circuitry 152—e.g., where mode circuitry 350 of die 300 provides functionality of mode circuitry 140 or mode circuitry 180, and where BIST unit 330 of die 300 provides functionality of Tx BIST unit 130 or Rx BIST unit 170. In one such embodiment, PMC agent 320 and interface circuitry 322 of die 300 correspond in functionality (respectively) to PMC agent 120 and interface circuitry 122. Although certain embodiments are not limited in this regard, interface circuitry 322 is coupled to BIST unit 330 via bus 306, which is compatible, for example, with a test bus standard such as that identified in the IEEE 1149.1 specification. In one such embodiment, interface circuitry 322 includes bridge circuitry 324 that facilitates selective coupling of BIST unit 330 to either PMC agent 320 or another bus 308, which, in an embodiment, is also compatible with the test standard. For example, bus 308 is used to communicate test information with an external test unit (not shown)—e.g., to facilitate channel testing during other stages of manufacturing die 300 and one or more other dies prior to packaging or field use in accordance with conventional techniques.

[0060] In the illustrated example embodiment, register space 331 of BIST unit 330 is configured to receive, update or otherwise provide information (e.g., including one or more test parameters) that at least partially determines the field test (and, e.g., repair) of a given functional channel. By way of illustration and not limitation, a "test pass / fail" register 332 serves as an information repository that specifies or otherwise indicates whether a given functional channel (or group of functional channels) being tested has passed the channel test under consideration. Alternatively or additionally, a "test complete" register 333 serves as an information repository that specifies or otherwise indicates (e.g., by indicating whether any one or more channel tests are currently pending) whether a given channel test has been completed. Alternatively or additionally, a "test clock cycle" register 334 serves as an information repository that specifies or otherwise indicates the length of time (e.g., in units of clock cycles) required to accommodate a channel test. In one such embodiment, the test clock cycle register 334 identifies the number of clock cycles required to accommodate the communication of signature data (or other suitable test information) as part of such a channel test.

[0061] In some embodiments, register space 331 additionally or alternatively includes at least one register (referred to herein as a "debug channel register") for identifying a functional channel that has been detected as failing to meet a performance standard. In one such embodiment, the identification at least partially determines whether the functional channel is to be replaced by a repair channel. As an illustration and not limitation, a debug channel register 335 of register space 331 serves as a repository for identifiers of functional channels (if any) that have been replaced by a first repair channel or are about to be replaced by a first repair channel. In various embodiments, the total number of debug registers in register space 331 is equal to the total number of conductive contacts that are each used to facilitate communication via a different corresponding repair channel 304 in the repair channels 304. For example, in one such embodiment, another debug channel register 336 of register space 331 serves as a repository for identifiers of another functional channel (if any) that has been replaced by a second repair channel or are about to be replaced by a second repair channel. In some embodiments, one or more registers of register space 331 are programmed or otherwise configured (e.g., by PMC agent 320 or other suitable logic) to facilitate channel testing and / or channel repair functions performed by other logic of BIST unit 330.

[0062] By way of illustration and not example, detector 340 of BIST unit 330 is operable to detect a condition, such as the first condition detected at 212 of method 200, in which a first partition and a second partition of a 3D IC (including circuitry of die 300) are each in a respective idle state. In an example embodiment, the first partition includes source / sink circuitry 312, for example, wherein the second partition includes corresponding signal source (or signal sink) circuitry of another die coupled to communicate with source / sink circuitry 312 via mode circuitry 350 and one or more of channels 302.

[0063] In one such embodiment, an evaluation unit 342 of the BIST unit 330 coupled to the detector 340 is operable to detect another condition (such as the second condition detected at 214 of the method 200) in which communication through a given functional channel fails to meet a performance standard. For example, the second condition is detected as a result of a channel test operation in which the evaluation unit 342 participated during the first condition. In an illustrative scenario according to one embodiment, the BIST unit 330 is a Tx BIST unit, wherein the register 344 of the evaluation unit 342 is a linear feedback shift register (LFSR) or other suitable circuit system for acting as a repository for one or more test patterns received from the PMC agent 320. In one such embodiment, during the channel test, some or all of the one or more test patterns are communicated from the evaluation unit 342 to a corresponding Rx BIST unit of another die (not shown) via the functional channel being tested.

[0064] In an alternative embodiment, the BIST unit 330 is an Rx BIST unit - for example, where the evaluation unit 342 is alternatively coupled to receive one or more test patterns during channel testing. In one such embodiment, the register 344 is a multiple input signature register (MISR) or other suitable circuitry that can be used to receive test information (if present) from a Tx BIST unit of another die (assuming that the link under test is able to communicate the test information to the die 300). In an embodiment where the BIST unit 330 is an Rx BIST unit, the evaluation unit 342 performs operations to generate a signature value based on the received test information (if present) and compares the signature value with a predetermined reference ("gold") signature value. Based on such a comparison, the evaluation unit 342 determines whether the tested channel is defective and, if so, how the channel repair operation is to replace the tested channel with a replacement channel in the repair channel 304.

[0065] By way of illustration and not limitation, the controller 346 of the BIST unit 330 is operable to selectively perform a channel repair operation based on a first condition and a second condition. The mode circuit system 350 includes one or more switches, multiplexers, and / or other suitable circuit structures that selectively enable or disable one or more conductive paths between the respective source / sink circuit system 312 and a respective one of the conductive contacts 314, 316 in response to the controller 346.

[0066] Figure 4Features of a system 400 for performing live channel repair in multiple partitioned clock domains according to an embodiment are shown. System 400 shows an example of an embodiment where live channel testing is performed based on respective idle states of multiple partitions of a 3D IC. In various embodiments, system 400 provides functionality such as functionality of system 100 or die 300—e.g., where one or more operations of method 200 are performed using system 400.

[0067] like Figure 4 As shown in , system 400 includes some or all of dies 410, 450 coupled to each other to form a 3D IC including functional channels (such as illustrative channels 402 and 406 shown) and repair channels (such as illustrative repair channels 404 and 408 shown). Die 410 includes a first hardware interface and a second hardware interface, through which signals are transmitted to die 450, and through which signals are received from die 450. For example, die 450 includes a third hardware interface and a fourth hardware interface, through which signals are received from the first hardware interface, and through which signals are transmitted to the second hardware interface.

[0068] In the example embodiment shown, the conductive contacts 414 of the first hardware interface are each coupled to a different corresponding one of the conductive contacts 454 of the third hardware interface via the channel 402 in various ways, for example, wherein the conductive contacts 416 of the first hardware interface are each coupled to a corresponding one of the conductive contacts 456 of the third hardware interface via the repair channel 404. Similarly, the conductive contacts 415 of the second hardware interface are each coupled to a different corresponding one of the conductive contacts 455 of the fourth hardware interface via the channel 406 in various ways, for example, wherein the conductive contacts 417 of the second hardware interface are each coupled to a corresponding one of the conductive contacts 457 of the fourth hardware interface via the repair channel 408 in various ways.

[0069] In various embodiments, dies 410, 450 provide similar functionality as dies 110, 150 in various ways—e.g., where channel 402 functionally corresponds to channel 102, and where repair channel 404 functionally corresponds to repair channel 104. In one such embodiment, partition 442, Tx mode circuitry 440, and Tx BIST unit 430 of die 410 (respectively) provide functionality such as functionality of source circuitry 112, mode circuitry 140, and Tx BIST unit 130—e.g., where partition 482, Rx mode circuitry 480, and Rx BIST unit 470 of die 450 (respectively) provide functionality such as functionality of sink circuitry 152, mode circuitry 180, and Rx BIST unit 170. Alternatively or additionally, partition 483, Tx mode circuitry 481, and Tx BIST unit 481 of die 450 (respectively) provide functionality such as the functionality of source circuitry 112, mode circuitry 140, and Tx BIST unit 130—for example, where partition 443, Rx mode circuitry 441, and Rx BIST unit 431 of die 410 (respectively) provide functionality such as the functionality of sink circuitry 152, mode circuitry 180, and Rx BIST unit 170.

[0070] In various embodiments, the partitions 442, 482 are configured to operate in a first clock domain, wherein the BIST units 430, 470 are operable to perform a first live channel test and / or a first channel repair (e.g., to replace one of the channels 402 with one of the repair channels 404) when the partitions 442, 482 are each in a respective idle state. In an illustrative scenario according to one embodiment, the partitions 443, 483 are also configured to operate in the same first clock domain, wherein the BIST units 430, 470 are configured to perform a first live channel test and / or a first channel repair when one or each of the partitions 443, 483 is in a respective active (non-idle) state. Additionally or alternatively, the BIST units 431, 471 are operable to perform a second live channel test and / or a second channel repair (e.g., to replace one of the channels 406 with one of the repair channels 408) when one or each of the partitions 442, 482 is in a respective active (non-idle) state. In an alternative embodiment, partitions 442, 482 are used to operate in a first clock domain, while partitions 443, 483 are used to operate in a second clock domain—for example, where channel testing and / or channel repair operations performed by BIST units 430, 470 are performed independently of channel testing and / or channel repair operations performed by BIST units 431, 471.

[0071] Figure 5Features of a die 500 for configuring a field channel repair function of a built-in self-test unit according to an embodiment are shown. Die 500 illustrates an example of an embodiment in which a BIST unit supports field channel testing and repair, and is further coupled to support circuit testing by an external test unit. In various embodiments, die 500 provides functionality such as functionality of die 110 or die 150 - for example, in which one or more operations of method 200 are performed using die 500.

[0072] like Figure 5 As shown in , die 500 includes a PMC agent 520, an interface circuit system 530, and a BIST unit 540, which correspond, for example, in functionality to the PMC agent 120, the interface circuit system 122, and the Tx BIST unit 130 (respectively). The interface circuit system 530 includes a converter 534 and a multiplexer (MUX) 536, wherein the converter 534 is coupled to receive status information, performance information, etc. from the PMC agent 520 via a bus 531. The converter 534 includes circuitry to reformat or otherwise convert such information for communication to the MUX 536 via another bus (e.g., the illustrative JTAG bus 533 shown) that is compatible with a test bus standard (such as the test bus standard identified in the IEEE 1149.1 specification).

[0073] In some embodiments, MUX 536 is coupled in a bridge circuit configuration to JTAG bus 533 and other JTAG buses 532, 535 that are also compatible with the same test bus standard. In one such embodiment, JTAG bus 532 is operable to communicate test information with an external test unit via a test access point (not shown) of die 500—e.g., to facilitate testing performed during manufacturing, packaging, or other stages prior to field use of die 500 according to conventional techniques. In contrast, in some embodiments, field operation of die 500—e.g., when die 500 is coupled with one or more other dies to form a 3DIC—occurs when the input of control signal 538 is tied to a fixed voltage, which sets MUX 536 to pass signals only between JTAG bus 533 and JTAG bus 535. In providing interface circuitry 530, some embodiments facilitate field testing functionality in various ways by extending the functionality of circuitry for conventional circuit testing with external test units or otherwise adapting such circuitry.

[0074] Fig. 6AFeatures of a system 600 for configuring an operating mode to facilitate field channel repair according to an embodiment are shown. System 600 illustrates one example of an embodiment in which any of a variety of operating modes may be configured to replace a functional channel of a 3D IC with a repair channel. In various embodiments, system 600 provides functionality such as functionality of system 100—e.g., where one or more operations of method 200 are performed using system 600.

[0075] like Fig. 6A As shown in , system 600 includes die 610, 650, which are coupled to each other in a 3D IC arrangement that includes functional channels 602, 604 and repair channels 606. The hardware interface of die 610 includes conductive contacts A1, A2, A3, wherein the hardware interface of die 650 similarly includes conductive contacts A1', A2', A3'. In the example embodiment shown, conductive contacts A1, A2, A3 are coupled to conductive contacts A1', A2', A3' (respectively) via channels 602, 604, 606. In various embodiments, die 610, 650 provide similar functionality as die 110, 150 in various ways - for example, wherein the Tx mode circuitry 640 of die 610 functionally corresponds to mode circuitry 140, and wherein the Rx mode circuitry 680 of die 650 functionally corresponds to mode circuitry 180.

[0076] Fig. 6A Modes of system 600 are shown, wherein Tx mode circuitry 640 and Rx mode circuitry 680 are configured in various ways in a first mode to enable respective communications via functional channels 602, 604. More specifically, Tx mode circuitry 640 includes multiplexers 642, 644, 646, and Rx mode circuitry 680 includes multiplexers 682, 684, 686. In the first mode, MUX 642 is configured to pass signal S1 to MUX 682 via channel 602, and MUX 644 is configured to pass signal S2 to MUX 684 via channel 604. Although MUX 646 is capable of passing signal S3 to MUX 686 via repair channel 606, in some embodiments, such signal S3 is not generated during the first mode. In another embodiment, channel 606 is a functional channel that transmits signal S3—eg, where some other channel (not shown) may be used as a replacement for channel 606 , and where channel 606 may be used as a repair channel for channel 604 .

[0077] In contrast, Figure 6B A second mode 601 of the device 600 is shown, wherein communication via the repair channel 606 replaces communication via the channel 604. Fig. 6A , Figure 6B In the figure, bold lines are used to represent signal paths selected by a MUX, while "X" symbols are used to indicate signal paths not selected by a given MUX. In the second mode, MUX 646 and MUX 684 are configured to pass signal S2 between die 610, 650 via channel 606, wherein communication via channel 604 is therefore disabled.

[0078] Figure 7 Features of a system 700 for facilitating predictive in-field channel repair functionality according to an embodiment are shown. System 700 shows an example of an embodiment in which a channel repair operation is performed based on a determination that a functional channel is expected to fail in the future according to certain predetermined criteria (even if, for example, the functional channel is currently able to successfully pass signals between some or all of the dies forming a 3D IC). In various embodiments, system 700 provides functionality such as that of system 100, die 300, system 400, die 500, or system 600—e.g., where one or more operations of method 200 are performed using system 700.

[0079] like Figure 7 As shown in , system 700 includes dies 710, 750 that are coupled to each other to at least partially form a 3D IC, the 3D IC arrangement including one or more functional channels (such as the illustrative channel 702 shown) and one or more repair channels (such as the illustrative repair channel 704 shown). The hardware interface of die 710 includes conductive contacts 714 and conductive contacts 716, wherein the hardware interface of die 750 similarly includes conductive contacts 754 and conductive contacts 756. In the example embodiment shown, the conductive contacts 714 are each coupled to a different corresponding conductive contact of the conductive contacts 754 of die 750 via the channel 702 in various ways, for example, wherein the conductive contacts 716 are each coupled to a corresponding one of the conductive contacts 756 via the repair channel 704 in various ways.

[0080] In various embodiments, die 710, 750 provide similar functionality as die 110, 150 in various ways—e.g., where channel 702 functionally corresponds to channel 102, and where repair channel 704 functionally corresponds to repair channel 104. In one such embodiment, source circuitry 712, mode circuitry 740, and Tx BIST unit 730 of die 710 functionally correspond to source circuitry 112, mode circuitry 140, and Tx BIST unit 130 (respectively)—e.g., where PMC agent 720 and interface circuitry 722 of die 710 functionally correspond to PMC agent 120 and interface circuitry 122 (respectively). Alternatively or additionally, the absorption circuit system 752, mode circuit system 780, and Rx BIST unit 770 of the tube core 750 (respectively) correspond functionally to the absorption circuit system 152, mode circuit system 180, and Rx BIST unit 170 - for example, where the PMC agent 760 and interface circuit system 762 of the tube core 750 (respectively) correspond functionally to the PMC agent 160 and interface circuit system 162.

[0081] In an embodiment, during field operation of system 700, one or more sensors (e.g., such as illustrative sensor 790 shown) are used to monitor the performance of one or more functional channels. For example, sensor 790 is coupled to monitor the sensitivity of a given functional channel. By way of illustration and not limitation, "sensitivity" in this context is indicated by one or more characteristics, including, but not limited to, relatively tight set timing margins - e.g., compared to threshold timing margins determined, for example, during the design / manufacturing phase or during field deployment. In some embodiments, sensor 790 provides smart sensor functionality that dynamically adjusts one or more channel performance thresholds, for example, using any of a variety of runtime analysis techniques.

[0082] In some embodiments, the functional channels are each assigned to a corresponding sensor - for example, where such assignment is performed dynamically in the field. A given one of the sensors (such as sensor 790) includes threshold information or otherwise has access to threshold information that is used as a reference for determining when communication via a given one of the channels 702 is outside of a performance margin. In addition, sensor 790 (e.g., via mode circuit system 740 and mode circuit system 780) is coupled to monitor or otherwise detect characteristics of signal communication performed using channel 702.

[0083] In an illustrative scenario according to one embodiment, the sensor 790 detects that a particular one of the channels 702 has reached or exceeded a threshold timing margin (or other) limit. Based on this detection, the sensor 790 programs or otherwise configures a microcontroller, firmware, or other suitable resource of the Tx BIST unit 730 (and similar resources of the Rx BIST unit 770, for example) (e.g., by setting a repair bit of a configuration register). In the example embodiment shown, the sensor 790 sends a signal to the Tx BIST unit 730 via the bus 792 and the interface circuit system 722, and / or sends a signal to the Rx BIST unit 770 via the bus 794 and the interface circuit system 762.

[0084] In one example embodiment, the size of the repair register is equal to (or otherwise corresponds to) the number of channels under control of a particular BIST unit. For example, in one embodiment, a controller of a BIST unit is coupled to selectively configure any one of ten channels, wherein the repair register of the BIST unit has a 10-bit width. In an example scenario of such an embodiment, the sensor 790 detects marginal performance of channel 2—for example, wherein the sensor 790 detects a hit of a threshold performance limit, and wherein the Tx BIST unit 730 reads, receives, or otherwise accesses an identifier of the same channel numbered 2 based on an interrupt sent by the sensor 790. Based on the detection of the threshold hit event, the Tx BIST unit 730 sets bit 2 corresponding to marginal channel 2 in the repair register. Subsequently, the controller of the Tx BIST unit 730 selectively asserts or deasserts corresponding select lines of various repair multiplexers in the mode circuit system 740. Similarly, the controller of the Rx BIST unit 770 selectively asserts or deasserts corresponding select lines of various repair multiplexers in the mode circuit system 780. This selective configuration of mode circuitry 740 and mode circuitry 780 enables channel repair by replacing marginal channel 2 with one of repair channels 704 .

[0085] In an illustrative scenario according to one embodiment, sensor 790 is a timing margin sensor (TMS) that monitors the setup margin of the corresponding timing path. As an illustration and not limitation, functional channels 702 are eight channels and repair channels 704 are two channels, wherein three of the functional channels are designed to operate with a relatively tight timing margin (e.g., +15 picoseconds) compared to the timing margins of the other five functional channels. In one such embodiment, sensor 790 performs monitoring on the three functional channels based on a threshold limit (e.g., 5 picoseconds), which is based on, for example, design-time modeling, runtime performance analysis, etc. In an example scenario, two of the three channels are each detected by sensor 790 (and / or other such sensors) as reaching or exceeding the threshold limit.

[0086] In response, the sensor 790 sends a corresponding interrupt to the Tx BIST unit 730 and the Rx BIST unit 770, which then reads the sensor information identifying the two marginal channels and / or other relevant information. Based on the detection of the marginal performance of the two channels, the Tx BIST unit 730 and the Rx BIST unit 770 each set the corresponding two bits of the corresponding repair register. Based on the setting of the bits, channel repair is performed by operating (e.g., asserting or deasserting) the repair multiplexers of the mode circuit system 740 and the mode circuit system 780 in various ways to replace each marginally performing functional channel with a corresponding one of the repair channels 704.

[0087] Figure 8 The figure shows a computer system or computing device 800 (also referred to as device 800) that supports field channel testing and repair for 3D ICs according to some embodiments. It should be noted that Figure 8 Those elements having the same reference numerals (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited thereto.

[0088] In some embodiments, device 800 represents a suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop computer, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, etc. It will be understood that certain components are shown generally, and not all components of such a device are shown in device 800.

[0089] In the example, the device 800 includes a SoC (System-on-Chip) 801. Figure 8Example boundaries of SOC 801 are illustrated in FIG. 8 using dashed lines, with some example components illustrated as being included within SOC 801 —however, SOC 801 may include any suitable components of device 800 .

[0090] In some embodiments, the device 800 includes a processor 804. The processor 804 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, a processing core, or other processing means. The processing operations performed by the processor 804 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other device, operations related to power management, operations related to connecting the computing device 800 to another device, and / or similar operations. The processing operations may also include operations related to audio I / O and / or display I / O.

[0091] In some embodiments, processor 804 includes multiple processing cores (also referred to as cores) 808a, 808b, 808c. Figure 8 Only three cores 808a, 808b, 808c are illustrated, but the processor 804 may include any other suitable number of processing cores, for example, dozens or even hundreds of processing cores. The processor cores 808a, 808b, 808c may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers, or other components.

[0092] In some embodiments, the processor 804 includes a cache 806. In an example, portions of the cache 806 may be dedicated to respective cores 808 (e.g., a first portion of the cache 806 is dedicated to core 808a, a second portion of the cache 806 is dedicated to core 808b, and so on). In an example, one or more portions of the cache 806 may be shared between two or more of the cores 808. The cache 806 may be divided into different levels, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, and the like.

[0093] In some embodiments, a given processor core (e.g., core 808a) may include a fetch unit for fetching instructions (including instructions with conditional branches) for execution by core 808a. The instructions may be fetched from any storage device such as memory 830. Processor core 808a may also include a decode unit for decoding the fetched instructions. For example, the decode unit may decode the fetched instructions into a plurality of micro-operations. Processor core 808a may include a dispatch unit for performing various operations associated with storing decoded instructions. For example, the dispatch unit may save data from the decode unit until the instruction is ready for dispatch, for example, until all source values ​​of the decoded instruction become available. In one embodiment, the dispatch unit may dispatch the decoded instructions to the execution unit for execution, and / or issue (or dispatch) the decoded instructions to the execution unit for execution.

[0094] The execution unit may execute the dispatched instruction after the instruction is decoded (e.g., by the decode unit) and dispatched (e.g., by the dispatch unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computing unit, a graphics computing unit, a general computing unit, etc.). The execution unit may also perform various arithmetic operations, such as addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In an embodiment, a coprocessor (not shown) may be combined with the execution unit to perform various arithmetic operations.

[0095] Further, the execution unit may execute instructions out of order. Therefore, in one embodiment, the processor core 808a (for example) may be an out-of-order processor core. The processor core 808a may also include a retirement unit. The retirement unit may retire the executed instructions after they are committed. In an embodiment, retiring the executed instructions may cause: the processor state is committed from the execution of these instructions, the physical registers used by these instructions are deallocated, and the like. The processor core 808a may also include a bus unit, which is used to implement communication between components of the processor core 808a and other components via one or more buses. The processor core 808a may also include one or more registers, which are used to store data accessed by various components of the core 808a (such as values ​​associated with the assigned application priority and / or subsystem state (mode)).

[0096] In some embodiments, device 800 includes connectivity circuitry 831. For example, connectivity circuitry 831 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks), for example, to enable device 800 to communicate with external devices. Device 800 can be separate from external devices (such as other computing devices, wireless access points or base stations, etc.).

[0097] In an example, the connectivity circuit system 831 may include a variety of different types of connectivity. In general, the connectivity circuit system 831 may include cellular connectivity circuit systems, wireless connectivity circuit systems, etc. The cellular connectivity circuit system of the connectivity circuit 831 generally refers to cellular network connectivity provided by a wireless operator, such as provided via the following: GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) system or variants or derivatives, 3GPP Long-Term Evolution (LTE) system or variants or derivatives, 3GPP LTE Advanced (LTE-Advanced, LTE-A) system or variants or derivatives, Fifth Generation (5G) wireless system or variants or derivatives, 5G mobile network system or variants or derivatives, 5G New Radio (NR) system or variants or derivatives, or other cellular service standards. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 831 refers to non-cellular wireless connectivity and may include personal area networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi) and / or wide area networks (such as WiMax) and / or other wireless communications. In an example, the connectivity circuitry 831 may include a network interface (such as a wired interface or a wireless interface), for example, so that the system embodiment can be incorporated into a wireless device, such as a cellular phone or a personal digital assistant.

[0098] In some embodiments, the device 800 includes a control hub 832, which represents hardware devices and / or software components related to interaction with one or more I / O devices. For example, the processor 804 can communicate with one or more of the display 822, one or more peripheral devices 824, a storage device 828, one or more other external devices 829, etc. via the control hub 832. The control hub 832 can be a chipset, a platform control hub (Platform Control Hub, PCH), etc.

[0099] For example, control hub 832 illustrates one or more connection points for additional devices connected to device 800, for example, through which a user can interact with the system. For example, devices that can be attached to device 800 (e.g., device 829) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboards or keypad devices, or other I / O devices for use with specific applications (such as card readers or other devices).

[0100] As described above, the control hub 832 can interact with audio devices, displays 822, and the like. For example, input or commands for one or more applications or functions of the device 800 can be provided through input from a microphone or other audio device. Additionally, audio output can be provided as a substitute or in addition to display output. In another example, if the display 822 includes a touch screen, the display 822 also acts as an input device, which can be at least partially managed by the control hub 832. Additional buttons or switches may also be present on the computing device 800 to provide I / O functions managed by the control hub 832. In one embodiment, the control hub 832 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in the device 800. The input can be part of the following: direct user interaction, and providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying the camera's flash, or other features).

[0101] In some embodiments, the control hub 832 can be coupled to various devices using any appropriate communication protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

[0102] In some embodiments, the display 822 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or tactile display for the user to interact with the device 800. The display 822 may include a display interface, a display screen, and / or a hardware device for providing a display to the user. In some embodiments, the display 822 includes a touch screen (or touchpad) device that provides both output and input to the user. In an example, the display 822 can communicate directly with the processor 804. The display 822 can be one or more of the following: an internal display device, such as in a mobile electronic device or a laptop device; or an external display device attached via a display interface (e.g., a display port (DisplayPort) or the like). In one embodiment, the display 822 can be a head mounted display (HMD), such as a stereoscopic display device used in a virtual reality (VR) application or an augmented reality (AR) application.

[0103] In some embodiments, and although not illustrated in the figure, in addition to the processor 804 (or in place of the processor 800), the device 822 may also include a graphics processing unit (GPU) including one or more graphics processing cores, which can control one or more aspects of the content displayed on the display 822.

[0104] The control hub 832 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (eg, drivers, protocol stacks) to make peripheral connections, such as to peripheral devices 824 .

[0105] It will be understood that device 800 can be a peripheral device that connects to other computing devices, or can have peripheral devices that connect to other computing devices. Device 800 can have a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on device 800. Additionally, the docking connector can allow device 800 to connect to certain peripheral devices that allow computing device 800 to control content output, such as to an audio-visual or other system.

[0106] In addition to a dedicated docking connector or other dedicated connection hardware, the device 800 may also be connected to peripherals via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of several different hardware interfaces), a display port including a Mini Display Port (MDP), a High Definition Multimedia Interface (HDMI), FireWire, or other types.

[0107] In some embodiments, for example, connectivity circuitry 831 may be coupled to control hub 832 in addition to or instead of being directly coupled to processor 804. In some embodiments, for example, display 822 may be coupled to control hub 832 in addition to or instead of being directly coupled to processor 804.

[0108] In some embodiments, the device 800 includes a memory 830 coupled to the processor 804 via a memory interface 834. The memory 830 includes a memory device for storing information in the device 800. The memory may include a non-volatile (the state does not change in the case of power interruption to the memory device) and / or a volatile (the state is uncertain in the case of power interruption to the memory device) memory device. The memory device 830 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to act as a process memory. In one embodiment, the memory 830 may operate as a system memory of the device 800 to store data and instructions for use when one or more processors 804 execute applications or processes. The memory 830 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the device 800.

[0109] The elements of various embodiments and examples are also provided as a machine-readable medium (e.g., memory 830) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 830) may include, but is not limited to, flash memory, optical disk, CD-ROM, DVD ROM, RAM, EPROM, EEPROM, magnetic or optical card, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic instructions or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted from a remote computer (e.g., server) to a requesting computer (e.g., client) via a communication link (e.g., modem or network connection) by means of a data signal.

[0110] In some embodiments, the device 800 includes a temperature measurement circuit system 840, which is used, for example, to measure the temperature of various components of the device 800. In an example, the temperature measurement circuit system 840 can be embedded, coupled or attached to various components whose temperatures are to be measured and monitored. For example, the temperature measurement circuit system 840 can measure the temperature of one or more of the cores 808a, 808b, 808c, the voltage regulator 814, the memory 830, the motherboard of the SOC 801, and / or any appropriate components of the device 800 (or can measure the temperature within one or more of these components).

[0111] In some embodiments, the device 800 includes a power measurement circuit system 842, which is used, for example, to measure the power consumed by one or more components of the device 800. In an example, in addition to measuring power, or instead of measuring power, the power measurement circuit system 842 can also measure voltage and / or current. In an example, the power measurement circuit system 842 can be embedded, coupled or attached to various components whose power, voltage and / or current consumption are to be measured and monitored. For example, the power measurement circuit system 842 can measure the following: power, current and / or voltage supplied by one or more voltage regulators 814; power supplied to the SOC 801; power supplied to the device 800; power consumed by the processor 804 (or any other component) of the device 800; and the like.

[0112] In some embodiments, the device 800 includes one or more voltage regulator circuit systems, generally referred to as voltage regulators (VRs) 814. VR 814 generates signals at appropriate voltage levels that can be supplied to operate any appropriate component of the device 800. By way of example only, VR 814 is illustrated as supplying signals to a processor 804 of the device 800. In some embodiments, VR 814 receives one or more voltage identification (VID) signals and generates voltage signals at appropriate levels based on the VID signals. Various types of VRs can be utilized for VR 814. For example, VR 814 can include a "buck" VR, a "boost" VR, a combination of a buck VR and a boost VR, a low dropout (LDO) regulator, a switching DC-DC regulator, and the like. Buck VRs are typically used in power delivery applications where an input voltage needs to be converted to an output voltage at a ratio less than 1. Boost VRs are typically used in power delivery applications where an input voltage needs to be converted to an output voltage at a ratio greater than 1. In some embodiments, each processor core has its own VR, which is controlled by PCU 810a / 810b and / or PMIC 812. In some embodiments, each core has a network of distributed LDOs to provide efficient control of power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs.

[0113] In some embodiments, the device 800 includes one or more clock generator circuitry, generally referred to as a clock generator 816. The clock generator 816 generates a clock signal at an appropriate frequency level, which can be supplied to any appropriate component of the device 800. By way of example only, the clock generator 816 is illustrated as supplying a clock signal to the processor 804 of the device 800. In some embodiments, the clock generator 816 receives one or more frequency identification (Frequency Identification, FID) signals and generates a clock signal at an appropriate frequency based on the FID signals.

[0114] In some embodiments, the device 800 includes a battery 818 that supplies power to various components of the device 800. By way of example only, the battery 818 is illustrated as supplying power to the processor 804. Although not illustrated in the drawings, the device 800 may include charging circuitry, for example, to recharge the battery based on an AC power supply received from an AC adapter.

[0115] In some embodiments, the device 800 includes a power control unit (PCU) 810 (also referred to as a power management unit (PMU), a power controller, etc.). In an example, some parts of the PCU 810 may be implemented by one or more processing cores 808, and these parts of the PCU 810 are symbolically shown using dashed boxes and are labeled as PCU 810a. In an example, some other parts of the PCU 810 may be implemented outside the processing core 808, and these parts of the PCU 810 are symbolically shown using dashed boxes and are labeled as PCU 810b. The PCU 810 may implement various power management operations for the device 800. The PCU 810 may include hardware interfaces, hardware circuit systems, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 800.

[0116] In some embodiments, the device 800 includes a power management integrated circuit (PMIC) 812, so as to implement various power management operations for the device 800. In some embodiments, the PMIC 812 is a reconfigurable power management IC (RPMIC) and / or an IMVP ( Shift voltage positioning). In an example, the PMIC is in an IC chip separate from the processor 804. The PMIC 812 can implement various power management operations for the device 800. The PMIC 812 can include hardware interfaces, hardware circuit systems, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), so as to implement various power management operations for the device 800, for example.

[0117] In an example, the device 800 includes one or both of the PCU 810 or the PMIC 812. In an example, either the PCU 810 or the PMIC 812 may not be present in the device 800, and thus, these components are illustrated using dashed lines.

[0118] Various power management operations of the device 800 may be performed by the PCU 810, by the PMIC 812, or by a combination of the PCU 810 and the PMIC 812. For example, the PCU 810 and / or the PMIC 812 may select a power state (e.g., a P-state) for various components of the device 800. For example, the PCU 810 and / or the PMIC 812 may select a power state (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification) for various components of the device 800. By way of example only, the PCU 810 and / or the PMIC 812 may cause various components of the device 800 to transition to a sleep state, to transition to an active state, to transition to an appropriate C-state (e.g., in accordance with the ACPI specification, a C0 state or another appropriate C-state), etc. In an example, the PCU 810 and / or the PMIC 812 may control a voltage output by the VR 814 and / or a frequency of a clock signal output by the clock generator, for example, by outputting a VID signal and / or a FID signal, respectively. For example, the PCU 810 and / or the PMIC 812 may control battery power usage, charging of the battery 818, and features related to power saving operations.

[0119] The clock generator 816 may include a phase locked loop (PLL), a frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 804 has its own clock source. Thus, each core can operate at a frequency independent of the operating frequency of other cores. In some embodiments, the PCU 810 and / or the PMIC 812 perform adaptive or dynamic frequency scaling or adjustment. For example, if the core is not operating at its maximum power consumption threshold or limit, the clock frequency of the processor core can be increased. In some embodiments, the PCU 810 and / or the PMIC 812 determine the operating status of each core of the processor, and when the PCU 810 and / or the PMIC 812 determine that the core is operating below the target performance level, the PCU 810 and / or the PMIC 812 opportunistically adjust the frequency and / or power supply voltage of the core without losing lock on the core clock source (e.g., the PLL of the core). For example, if a core is drawing less current from a power rail than the total current allocated for the core or processor 804, the PCU 810 and / or PMIC 812 may temporarily increase the power draw of the core or processor 804 (e.g., by increasing the clock frequency and / or power supply voltage level) so that the core or processor 804 may perform at a higher performance level. Thus, the voltage and / or frequency of the processor 804 may be temporarily increased without violating product reliability.

[0120] In an example, the PCU 810 and / or PMIC 812 may perform power management operations, for example, based at least in part on measurements received from the power measurement circuitry 842, the temperature measurement circuitry 840, based on the charge level of the battery 818, and / or based on any other appropriate information that may be used for power management. To this end, the PMIC 812 is communicatively coupled to one or more sensors to sense / detect various values / changes of one or more factors that have an impact on the power / thermal performance of the system / platform. Examples of the one or more factors include current, voltage drop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be arranged to be physically close to (and / or thermally contact / coupled with) one or more components or logic / IP blocks of the computing system. Additionally, in at least one embodiment, (one or more) sensors may be directly coupled to the PCU 810 and / or PMIC 812 to allow the PCU 810 and / or PMIC 812 to manage processor core energy based at least in part on (one or more) values ​​detected by one or more of these sensors.

[0121] An example software stack of the device 800 is also illustrated (although not all elements of the software stack are illustrated). By way of example only, the processor 804 may execute an application 850, an operating system 852, one or more power management (PM) specific applications (e.g., collectively referred to as PM applications 858), and the like. The PM application 858 may also be executed by the PCU 810 and / or the PMIC 812. The OS 852 may also include one or more PM applications 856a, 856b, 856c. The OS 852 may also include various drivers 854a, 854b, 854c, and the like, some of which may be specific to power management purposes. In some embodiments, the device 800 may further include a Basic Input / Output System (BIOS) 820. The BIOS 820 may communicate with the OS 852 (e.g., via one or more drivers 854), communicate with the processor 804, and the like.

[0122] For example, one or more of the PM applications 858, 856, the driver 854, the BIOS 820, etc. may be used to implement power management specific tasks, such as controlling the voltage and / or frequency of various components of the device 800, controlling the wake state, sleep state, and / or any other appropriate power state of various components of the device 800, controlling battery power usage, charging of the battery 818, features related to power saving operations, and the like.

[0123] In various embodiments, SoC 801 and / or other components of device 800 include or form at least a portion of a 3D IC that spans multiple IC dies. Given two such dies coupled to communicate with each other via one or more functional channels, one or more repair channels may each serve as a replacement for the one or more functional channels. In an embodiment, multiple dies provide functionality such as that of system 100 to perform field channel testing and, depending on the results of such testing, perform field channel repair. Exemplary Computer Architecture

[0124] Detailed below is a description of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktop computers, handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, separate servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, various systems or electronic devices that can contain processors and / or other execution logic as disclosed herein are generally suitable.

[0125] Fig. 9 The figure shows an exemplary system. The multiprocessor system 900 is a point-to-point interconnect system and includes multiple processors, including a first processor 970 and a second processor 980 coupled via a point-to-point interconnect 950. In some examples, the first processor 970 and the second processor 980 are isomorphic. In some examples, the first processor 970 and the second processor 980 are heterogeneous. Although the exemplary system 900 is shown as having two processors, the system can have three or more processors, or can be a single processor system.

[0126] Processors 970 and 980 are shown as including integrated memory controller (IMC) circuitry 972 and 982, respectively. Processor 970 also includes point-to-point (PP) interfaces 976 and 978 as part of its interconnect controller; similarly, second processor 980 includes PP interfaces 986 and 988. Processors 970, 980 can exchange information via a point-to-point (PP) interconnect 950 using point-to-point (PP) interface circuits 978, 988. IMCs 972 and 982 couple processors 970, 980 to respective memories, namely memory 932 and memory 934, which can be portions of main memory locally attached to the respective processors.

[0127] Processors 970, 980 may each exchange information with a chipset 990 via respective PP interconnects 952, 954 using point-to-point interface circuits 976, 994, 986, and 998. Chipset 990 may optionally exchange information with a coprocessor 938 via interface 992. In some examples, coprocessor 938 is a special-purpose processor such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and the like.

[0128] A shared cache (not shown) may be included in either processor 970, 980, or external to both processors but connected to these processors via the PP interconnect, so that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0129] Chipset 990 may be coupled to first interconnect 916 via interface 996. In some examples, first interconnect 916 may be a peripheral component interconnect (PCI) interconnect or an interconnect such as a PCI Express interconnect or another I / O interconnect. In some examples, one of the interconnects is coupled to a power control unit (PCU) 917, which may include circuitry, software, and / or firmware for performing power management operations related to processors 970, 980, and / or coprocessor 938. PCU 917 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. PCU 917 also provides control information to control the generated operating voltage. In various examples, PCU 917 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely controlled by the processor (e.g., by various processor hardware, and which may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0130] The PCU 917 is illustrated as existing as logic separate from the processor 970 and / or the processor 980. In other cases, the PCU 917 may be executed on a given one or more cores of the cores (not shown) of the processor 970 or 980. In some cases, the PCU 917 may be implemented as a (dedicated or general purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by the PCU 917 may be implemented outside the processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by the PCU 917 may be implemented within the BIOS or other system software.

[0131] Various I / O devices 914 may be coupled to the first interconnect 916 along with a bus bridge 918 that couples the first interconnect 916 to a second interconnect 920. In some examples, one or more additional processors 915 (such as a coprocessor, a high throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interconnect 916. In some examples, the second interconnect 920 may be a low pin count (LPC) interconnect. Various devices may be coupled to the second interconnect 920, including, for example, a keyboard and / or mouse 922, a communication device 927, and a storage circuit system 928. The storage circuit system 928 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device that may include instructions / code and data 930 in some examples. Further, audio I / O 924 may be coupled to second interconnect 920. Note that other architectures are possible in addition to the point-to-point architecture described above. For example, instead of a point-to-point architecture, a system such as multiprocessor system 900 may implement a multi-drop interconnect or other such architecture. Exemplary core architectures, processors, and computer architectures.

[0132] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors give rise to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip (SoC), which may be included on the same die with the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture.

[0133] Fig.10 The figure shows a block diagram of an example processor 1000 that may have more than one core and may have an integrated memory controller. The solid line box illustrates the processor 1000 having a single core 1002A, a system agent unit circuitry 1010, a set of one or more interconnected controller unit circuitry 1016, while the optional addition of dashed line boxes illustrates an alternative processor 1000 having multiple cores 1002A-1002N, a set of one or more integrated memory controller units 1014 in the system agent unit circuitry 1010, and dedicated logic 1008 and a set of one or more interconnected controller unit circuitry 1016. Note that the processor 1000 may be Fig. 9 one of the processors 970 or 980, or the coprocessors 938 or 915.

[0134] Thus, different implementations of processor 1000 may include: 1) a CPU, where the dedicated logic 1008 is an integrated graphics device and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 1002A-1002N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 1002A-1002N are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 1002A-1002N are a large number of general-purpose in-order cores. Thus, processor 1000 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit circuitry), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 1000 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0135] The memory hierarchy includes one or more levels of cache unit circuitry 1004A-1004N within the cores 1002A-1002N, a set of one or more shared cache unit circuitry 1006, and external memory (not shown) coupled to a set of (one or more) integrated memory controller unit circuitry 1014. The set of one or more shared cache unit circuitry 1006 may include one or more intermediate levels of cache (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)) and / or combinations thereof. Although in some examples, a ring-based interconnect network circuitry 1012 interconnects the dedicated logic 1008 (e.g., integrated graphics logic), the set of (one or more) shared cache unit circuitry 1006, and the system agent unit circuitry 1010, alternative examples use any number of well-known techniques for interconnecting such units. In some examples, coherency is maintained between the shared cache unit circuitry(s) 1006 and one or more of the cores 1002A- 1002N.

[0136] In some examples, one or more of the cores 1002A-1002N are capable of multi-threaded operation. System agent unit circuitry 1010 includes those components that coordinate and operate cores 1002A-1002N. System agent unit circuitry 1010 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, logic and components required to regulate the power state of cores 1002A-1002N and / or dedicated logic 1008 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0137] The cores 1002A-1002N may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 1002A-1002N may be heterogeneous in terms of ISA; that is, a subset of the cores 1002A-1002N may be able to execute an ISA, while other cores may only be able to execute a subset of that ISA or another ISA. Exemplary core architectures—in-order and out-of-order core block diagrams.

[0138] Fig.11A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to examples. Fig. 11Bis a block diagram illustrating both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example. Figure 11A-11B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optional addition of dashed line boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0139] exist Fig.11A , the processor pipeline 1100 includes a fetch stage 1102, an optional length decode stage 1104, a decode stage 1106, an optional allocation (Alloc) stage 1108, an optional rename stage 1110, a dispatch (also called a dispatch or issue) stage 1112, an optional register read / memory read stage 1114, an execute stage 1116, a write back / memory write stage 1118, an optional exception handling stage 1122, and an optional commit stage 1124. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 1102, one or more instructions are fetched from an instruction memory, and during the decode stage 1106, the fetched one or more instructions may be decoded, an address using a forwarded register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one example, the decode stage 1106 and the register read / memory read stage 1114 can be combined into one pipeline stage. In one example, during the execute stage 1116, decoded instructions can be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface can be performed, multiplication and addition operations can be performed, arithmetic operations with branch results can be performed, and the like.

[0140] As an example, Fig. 11BThe exemplary register renaming, out-of-order issue / execution architecture core of the present invention may implement pipeline 1100 as follows: 1) instruction fetch circuit system 1138 performs fetch stage 1102 and length decode stage 1104; 2) decode circuit system 1140 performs decode stage 1106; 3) rename / allocator unit circuit system 1152 performs allocate stage 1108 and rename stage 1110; 4) (one or more) scheduler circuit system 1156 performs schedule stage 1112; 5) (one or more) physical register file circuit system 111 58 and the memory unit circuit system 1170 perform a register read / memory read phase 1114; (one or more) execution clusters 1160 perform an execute phase 1116; 6) the memory unit circuit system 1170 and (one or more) physical register file circuit systems 1158 perform a write back / memory write phase 1118; 7) various circuit systems may be involved in the exception handling phase 1122; and 8) the retirement unit circuit system 1154 and (one or more) physical register file circuit systems 1158 perform a commit phase 1124.

[0141] Fig. 11B A processor core 1190 is shown, which includes a front end unit circuit system 1130 coupled to an execution engine unit circuit system 1150, and both are coupled to a memory unit circuit system 1170. The core 1190 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As a further option, the core 1190 can be a special purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0142] The front end unit circuit system 1130 may include a branch prediction circuit system 1132 coupled to an instruction cache circuit system 1134, the instruction cache circuit system 1134 is coupled to an instruction translation lookaside buffer (TLB) 1136, the instruction translation lookaside buffer 1136 is coupled to an instruction fetch circuit system 1138, and the instruction fetch circuit system 1138 is coupled to a decoding circuit system 1140. In one example, the instruction cache circuit system 1134 is included in the memory unit circuit system 1170 instead of in the front end circuit system 1130. The decoding circuit system 1140 (or decoder) can decode the instruction and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from the original instruction, or otherwise reflecting the original instruction, or derived from the original instruction as output. The decoding circuit system 1140 may further include an address generation unit (AGU, not shown) circuit system. In one example, the AGU generates an LSU address using the forwarded register port, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decoding circuit system 1140 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memories (ROM), etc. In one example, the core 1190 includes a microcode ROM (not shown) or other medium (e.g., in the decoding circuit system 1140, or otherwise within the front-end circuit system 1130) that stores microcode for certain macroinstructions. In one example, the decoding circuit system 1140 includes a micro-op or operation cache (not shown) to save / cache decoded operations, micro-tags, or micro-operations generated during the decoding stage or other stages of the processor pipeline 1100. The decoding circuit system 1140 may be coupled to the rename / allocator unit circuit system 1152 in the execution engine circuit system 1150.

[0143] Execution engine circuitry 1150 includes rename / allocator unit circuitry 1152, which is coupled to retirement unit circuitry 1154 and a set of one or more scheduler circuitry 1156. Scheduler circuitry(s) 1156 represent any number of different schedulers, including reservation stations, central instruction windows, etc. In some examples, scheduler circuitry(s) 1156 may include arithmetic logic unit (ALU) scheduler / scheduling circuitry, ALU queues, arithmetic generation unit (AGU) scheduler / scheduling circuitry, AGU queues, etc. Scheduler circuitry(s) 1156 are coupled to physical register file(s) circuitry 1158. Each physical register file circuitry in the physical register file(s) circuitry 1158 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., instruction pointer, which is the address of the next instruction to be executed), etc. In one example, the physical register file(s) circuitry 1158 includes vector register unit circuitry, write mask register unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general purpose registers, etc. The physical register file(s) circuitry 1158 is coupled to a retirement unit circuitry 1154 (also referred to as a retirement queue (“retire queue” or “retirement queue”) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using reorder buffer(s) (ROB) and retirement register file(s); using future file(s), history buffer(s) and retirement register file(s); using register maps and register pools, etc.). The retirement unit circuitry 1154 and the physical register file(s) circuitry 1158 are coupled to execution cluster(s) 1160. The execution cluster(s) 1160 includes a set of one or more execution unit circuitry 1162 and a set of one or more memory access circuitry 1164. The execution unit(s) circuit system 1162 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) and may be performed on various data types (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point).While some examples may include multiple execution units or execution unit circuitry dedicated to a particular function or set of functions, other examples may include only one execution unit circuitry or multiple execution units / execution unit circuitry that all perform all functions. Scheduler circuitry (one or more) 1156, physical register file circuitry (one or more) 1158, and execution cluster (one or more) 1160 are shown as potentially multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines each with its own scheduler circuitry, physical register file circuitry (one or more) and / or execution cluster - and in the case of separate memory access pipelines, certain examples are implemented where only the execution cluster of that pipeline has memory access circuitry (one or more) 1164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order issue / execution.

[0144] In some examples, the execution engine unit circuit system 1150 can perform load store unit (LSU) address / data pipelining to an Advanced Microcontroller Bus (AMB) interface (not shown), as well as address staging and writeback, data staging load, store, and branch.

[0145] The set of memory access circuitry 1164 is coupled to memory cell circuitry 1170, which includes data TLB circuitry 1172, which is coupled to data cache circuitry 1174, which is coupled to second level (L2) cache circuitry 1176. In one illustrative example, memory access circuitry 1164 may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to data TLB circuitry 1172 in memory cell circuitry 1170. Instruction cache circuitry 1134 is further coupled to second level (L2) cache circuitry 1176 in memory cell circuitry 1170. In one example, instruction cache 1134 and data cache 1174 are combined into L2 cache circuitry 1176, third level (L3) cache circuitry (not shown), and / or a single instruction and data cache in main memory (not shown). The L2 cache circuitry 1176 is coupled to one or more other levels of cache and ultimately to main memory.

[0146] Core 1190 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, core 1190 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data. Exemplary execution unit(s) circuitry.

[0147] Fig.12 The figure shows an example of execution unit circuitry (one or more) such as Fig. 11B (One or more) execution unit circuit systems 1162. As shown, (one or more) execution unit circuit systems 1162 may include one or more ALU circuits 1201, optional vector / single instruction multiple data (single instruction multiple data, SIMD) circuits 1203, load / store circuits 1205, branch / jump circuits 1207 and / or floating-point unit (FPU) circuits 1209. ALU circuits 1201 perform integer arithmetic and / or Boolean operations. Vector / SIMD circuits 1203 perform vector / SIMD operations on packed data (such as SIMD / vector registers). Load / store circuits 1205 execute load and store instructions to load data from memory into registers or store data from registers to memory. Load / store circuits 1205 may also generate addresses. Branch / jump circuits 1207 cause branches or jumps to memory addresses depending on the instructions. FPU circuits 1209 perform floating-point arithmetic. The width of execution unit circuitry 1162 varies depending on the example, and may range, for example, from 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit). Exemplary Register Architecture

[0148] Fig.131 is a block diagram of a register architecture 1300 according to some examples. As shown, the register architecture 1300 includes a vector / SIMD register 1310 whose width varies from 128 bits to 1024 bits. In some examples, the vector / SIMD register 1310 is physically 512 bits, and depending on the mapping, only some of the lower bits are used. For example, in some examples, the vector / SIMD register 1310 is a 512-bit ZMM register: the lower 256 bits are used for the YMM register, and the lower 128 bits are used for the XMM register. Thus, there is a superposition of registers. In some examples, the vector length field selects between the maximum length and one or more other shorter lengths, wherein each such shorter length is half the length of the previous length. Scalar operations are operations performed on the lowest order data element position in the ZMM / YMM / XMM register; depending on the example, the higher order data element position remains the same as before the instruction or is reset to zero.

[0149] In some examples, the register architecture 1300 includes write mask / predicate registers 1315. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate registers 1315 can allow merging (e.g., allowing any set of elements in the destination to be exempted from update during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 1315 corresponds to a data element position in the destination. In other examples, the write mask / predicate registers 1315 are scalable and consist of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0150] The register architecture 1300 includes a plurality of general purpose registers 1325. These registers may be 16 bits, 32 bits, 64 bits, etc., and may be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0151] In some examples, register architecture 1300 includes scalar floating point (FP) registers 1345 for scalar floating point operations on 32 / 64 / 80-bit floating point data using x87 instruction set architecture extensions, or as MMX registers to perform operations on 64-bit packed integer data, and for storing operands for some operations performed between MMX and XMM registers.

[0152] One or more flag registers 1340 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 1340 can store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 1340 are referred to as program status and control registers.

[0153] Segment registers 1320 contain segment points for use when accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

[0154] Machine specific registers (MSRs) 1335 control and report processor performance. Most MSRs 1335 handle system-related functions and are not accessible by applications. Machine check registers 1360 consist of control, status, and error reporting MSRs that are used to detect and report hardware errors.

[0155] One or more instruction pointer registers 1330 store instruction pointer values. Control register(s) 1355 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processor 970, 980, 938, 915, and / or 1000) and the characteristics of the currently executing task. Debug registers 1350 control and allow monitoring of debug operations of the processor or core.

[0156] Memory (mem) management registers 1365 specify the location of data structures used for protected mode memory management. These registers may include the GDTR, IDRT, task register, and LDTR registers.

[0157] Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, fewer, or different register files and registers. The register architecture 1300 may be used, for example, in the physical register file(s) circuitry 1158.

[0158] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

[0159] Note that in the corresponding figures of the embodiments, lines are used to represent signals. Some lines may be thicker to indicate a greater number of component signal paths, and / or have arrows at one or more ends to indicate the direction of information flow. Such indications are not intended to be restrictive. Instead, lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of circuits or logic units. As dictated by design needs or preferences, any represented signal may actually include one or more signals that may travel in either direction, and may be implemented using any suitable type of signal scheme.

[0160] Throughout the specification and in the claims, the term "connected" means a direct connection between connected objects, such as an electrical, mechanical, or magnetic connection, without any intermediary device. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected objects or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of "a / an" and "the" includes plural references. The meaning of "in" includes "in" and "on".

[0161] The term "device" can generally refer to an apparatus depending on the context in which that term is used. For example, a device can refer to a stack of layers or structures, a single structure or layer, a connection of various structures with active and / or passive elements, etc. Generally speaking, a device is a three-dimensional structure having a plane along the xy direction of an xyz Cartesian coordinate system and a height along the z direction. The plane of a device can also be the plane of an apparatus that includes the device.

[0162] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another and subsequently reducing it in layout area. The term "scaling" also generally refers to reducing the size of layouts and devices within the same technology node. The term "scaling" may also refer to the adjustment (e.g., slowing down or speeding up - i.e., shrinking or enlarging, respectively) of signal frequency relative to another parameter (e.g., power supply level).

[0163] The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within + / - 10% of a target value. For example, unless otherwise specified in the clear context of their use, the terms "substantially equal," "approximately equal," and "approximately equal" mean that only incidental variations exist between the objects so described. In the art, such variations are typically no greater than + / - 10% of a predetermined target value.

[0164] It is to be understood that the terms so used are interchangeable under appropriate circumstances such that, for example, the embodiments of the invention described herein are capable of operation in other orientations than those illustrated or otherwise described herein.

[0165] Unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are mentioned and is not intended to imply that the objects so described must be in a given order temporally, spatially, in ranking, or in any other manner.

[0166] The terms "left", "right", "front", "back", "top", "bottom", "above", "below", etc., if any, in the specification and claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. For example, the terms "above", "below", "front side", "back side", "top", "bottom", "above", "below", and "on" as used herein refer to the relative position of a component, structure, or material relative to other referenced components, structures, or materials within a device, where such physical relationships are significant. These terms are adopted herein for descriptive purposes only, and these terms are primarily within the context of the z-axis of the device, so these terms may be relative to the orientation of the device. Therefore, a first material that is "above" a second material in the context of the figures provided herein may also be "below" the second material when the device is oriented upside down relative to the context of the figures provided. In the context of materials, a material disposed above or below another material may be in direct contact, or may have one or more intervening materials. In addition, a material disposed between two materials may be in direct contact with both layers, or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material. A similar distinction is made in the context of component assemblies.

[0167] The term "between" may be employed in the context of a z-axis, x-axis, or y-axis of a device. A material between two other materials may be in contact with one or both of those two materials, or the material may be separated from both of the other two materials by one or more intervening materials. Thus, a material "between" two other materials may be in contact with either of the other two materials, or the material may be coupled to the other two materials by an intervening material. A device between two other devices may be directly connected to one or both of those two devices, or the device may be separated from both of the other two devices by one or more intervening devices.

[0168] As used throughout the specification and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. It should be noted that those elements of the drawings having the same reference numerals (or names) as elements of any other drawings may operate or function in any manner similar to that described, but are not limited thereto.

[0169] In addition, the various elements of the combinational logic and sequential logic discussed in the present disclosure may involve physical structures (such as AND gates, OR gates, or XOR gates), or involve a synthesized or otherwise optimized collection of devices that implement logic structures that are Boolean equivalents of the logic discussed.

[0170] This article describes techniques and architectures for supporting field channel testing and / or repair of 3D ICs. In the above description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of certain embodiments. However, it will be apparent to those skilled in the art that certain embodiments may be implemented without these specific details. In other examples, structures and devices are shown in block diagram form to avoid obscuring the description.

[0171] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase "in one embodiment" in different places in the specification does not necessarily all refer to the same embodiment.

[0172] Some parts of the detailed description herein are presented in terms of algorithms and symbolic representations of the operations on the data bits in the computer memory. These algorithmic descriptions and representations are techniques used by technicians in the computer field, and it is most effective to convey the essence of its work to other technicians in the field. Algorithms are generally conceived as self-consistent step sequences that reach the desired results. These steps are those steps that require physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. Mainly for common purposes, it has been proven to be convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0173] It should be borne in mind, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise, as will be apparent from the discussion herein, it is to be appreciated that throughout the specification, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms it into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0174] Certain embodiments also relate to an apparatus for performing the operations described herein. The apparatus may be specially constructed for the desired purpose, or it may include a general-purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM, a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM) (such as a dynamic RAM (DRAM)), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions and coupled to a computer system bus.

[0175] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems can be used together with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The required structure for various of these systems will be presented from the description herein. In addition, some embodiments are not described with reference to any particular programming language. It will be appreciated that various programming languages ​​can be used to implement the teachings of such embodiments described herein.

[0176] In one or more first embodiments, an integrated circuit (IC) die includes: a hardware interface for coupling the IC die to another IC die, wherein the IC die and the other IC die are used to at least partially form a three-dimensional (3D) IC; a test unit, the ...

[0177] In one or more second embodiments, further to the first embodiment, the test unit is a first test unit, and wherein the plurality of partitions of the 3D IC each corresponds to a different corresponding test unit in the plurality of test units, the plurality of partitions include a first partition and a second partition, and for each test unit in the plurality of test units: the PMC agent is used to be coupled to provide corresponding status information to the test unit, and the test unit is used to participate in corresponding channel testing based on the corresponding status information.

[0178] In one or more third embodiments, further to the second embodiment, each of the plurality of partitions is configured to operate in the first clock domain.

[0179] In one or more fourth embodiments, further to the third embodiment, the first condition occurs when one or more partitions of the plurality of partitions are each in a corresponding active state.

[0180] In one or more fifth embodiments, further to the second embodiment, the first partition includes a first signal source circuit, the second partition includes a first signal sink circuit, a third partition among the multiple partitions includes a second signal source circuit of another IC die, and a fourth partition among the multiple partitions includes a second signal sink circuit of the IC die.

[0181] In one or more sixth embodiments, further in the first embodiment or the second embodiment, the test unit is further used to: receive test data from the PMC agent, and perform communication of the test data from the IC die via the first channel, another IC die is used to generate a value based on the communication, and the test unit is used to detect a second condition based on a mismatch between the value and a reference value.

[0182] In one or more seventh embodiments, further to the first embodiment or the second embodiment, the test unit is further used to receive performance information from a sensor coupled to the first channel, and the test unit is used to detect the second condition including: the test unit is used to identify that the performance metric fails to meet the threshold condition based on the performance information, and the performance metric is based on one or more communications conducted via the first channel.

[0183] In one or more eighth embodiments, further to the seventh embodiment, the performance metric is a setup time metric.

[0184] In one or more ninth embodiments, further to the first embodiment or the second embodiment, the interface circuitry coupled between the PMC agent and the test unit provides the status information via a bus compatible with a test bus standard.

[0185] In one or more tenth embodiments, further to the ninth embodiment, the test bus standard is identified in the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 specification.

[0186] In one or more eleventh embodiments, a method includes: receiving status information from a power management control (PMC) agent at a test unit of a first integrated circuit (IC) die, wherein the first IC die and a second IC die are coupled to at least partially form a three-dimensional (3D) IC, wherein the test unit receives the status information during field operation of the 3D IC; detecting a first condition based on the status information, in which a first partition of the first IC die and a second partition of the second IC die are each in a corresponding idle state, wherein the 3D IC includes a first channel between the first partition and the second partition; detecting a second condition, in which one or more communications via the first channel fail to meet a performance criterion; based on the second condition and during the first condition: disabling a first conductive path between the first channel and the first partition; and enabling a second conductive path between a second channel and the first partition of the 3D IC.

[0187] In one or more twelfth embodiments, further to the eleventh embodiment, the test unit is a first test unit, and wherein the plurality of partitions of the 3D IC each corresponds to a different corresponding test unit in the plurality of test units, the plurality of partitions include a first partition and a second partition, and for each test unit in the plurality of test units: the PMC agent is coupled to provide corresponding status information to the test unit, and the test unit is used to participate in corresponding channel testing based on the corresponding status information.

[0188] In one or more thirteenth embodiments, further to the twelfth embodiment, the plurality of partitions are each configured to operate in a first clock domain.

[0189] In one or more fourteenth embodiments, further to the thirteenth embodiment, the first condition is when one or more partitions among the plurality of partitions are each in a corresponding active state.

[0190] In one or more fifteenth embodiments, further to the twelfth embodiment, the first partition includes a first signal source circuit, the second partition includes a first signal sink circuit, a third partition among the multiple partitions includes a second signal source circuit of a second IC die, and a fourth partition among the multiple partitions includes a second signal sink circuit of the first IC die.

[0191] In one or more sixteenth embodiments, further to the eleventh embodiment or the twelfth embodiment, the method further includes: at the test unit, receiving test data from the PMC agent, and performing communication of the test data from the first IC die via the first channel, wherein the second IC die generates a value based on the communication, and wherein the second condition is detected based on a mismatch between the value and a reference value.

[0192] In one or more seventeenth embodiments, further to the eleventh embodiment or the twelfth embodiment, the method further includes: at the test unit, receiving performance information from a sensor coupled to the first channel, wherein detecting the second condition includes: identifying, based on the performance information, that a performance metric fails to meet a threshold condition, wherein the performance metric is based on one or more communications conducted via the first channel.

[0193] In one or more eighteenth embodiments, further to the seventeenth embodiment, the performance metric is a setup time metric.

[0194] In one or more nineteenth embodiments, further in the eleventh embodiment or the twelfth embodiment, the interface circuit system coupled between the PMC agent and the test unit provides the status information via a bus compatible with a test bus standard.

[0195] In one or more twentieth embodiments, further to the nineteenth embodiment, the test bus standard is identified in the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 specification.

[0196] In one or more twenty-first embodiments, a system includes: a first integrated circuit (IC) die and a second IC die, the first IC die and the second IC die being coupled to each other to at least partially form a three-dimensional (3D) IC, wherein the first IC die includes: a test unit for receiving status information from a power management control (PMC) agent during field operation of the 3D IC, the test unit further for: detecting a first condition based on the status information, in which a first partition of the IC die and a second partition of another IC die are each in a corresponding idle state, wherein the 3D IC includes a first channel between the first partition and the second partition; and detecting a second condition, in which one or more communications via the first channel fail to meet a performance standard; and a mode circuit system coupled to the test unit; wherein, based on the second condition and during the first condition, the test unit is used to signal the mode circuit system to disable a first conductive path between the first channel and the first partition, and further enable a second conductive path between a second channel of the 3D IC and the first partition; and a memory interface for communicating signals between the 3D IC and a memory.

[0197] In one or more twenty-second embodiments, further to the twenty-first embodiment, the test unit is a first test unit, and wherein multiple partitions of the 3D IC each correspond to a different corresponding test unit in the multiple test units, the multiple partitions include a first partition and a second partition, and for each test unit in the multiple test units: the PMC agent is used to be coupled to provide corresponding status information to the test unit, and the test unit is used to participate in corresponding channel testing based on the corresponding status information.

[0198] In one or more twenty-third embodiments, further to the twenty-second embodiment, the plurality of partitions are each configured to operate in a first clock domain.

[0199] In one or more twenty-fourth embodiments, further to the twenty-third embodiment, the first condition is to occur when one or more of the plurality of partitions are each in a corresponding active state.

[0200] In one or more twenty-fifth embodiments, further to the twenty-second embodiment, the first partition includes a first signal source circuit, the second partition includes a first signal sink circuit, a third partition among the multiple partitions includes a second signal source circuit of another IC die, and a fourth partition among the multiple partitions includes a second signal sink circuit of the IC die.

[0201] In one or more twenty-sixth embodiments, further in the twenty-first embodiment or the twenty-second embodiment, the test unit is further used to: receive test data from the PMC agent, and perform communication of the test data from the IC die via the first channel, another IC die is used to generate a value based on the communication, and the test unit is used to detect a second condition based on a mismatch between the value and a reference value.

[0202] In one or more twenty-seventh embodiments, further in the twenty-first embodiment or the twenty-second embodiment, the test unit is further used to receive performance information from a sensor coupled to the first channel, and the test unit is used to detect the second condition including: the test unit is used to identify that the performance metric fails to meet the threshold condition based on the performance information, and the performance metric is based on one or more communications conducted via the first channel.

[0203] In one or more twenty-eighth embodiments, further to the twenty-seventh embodiment, the performance metric is a setup time metric.

[0204] In one or more twenty-ninth embodiments, further in the twenty-first embodiment or the twenty-second embodiment, the interface circuit system coupled between the PMC agent and the test unit provides status information via a bus compatible with a test bus standard.

[0205] In one or more thirtieth embodiments, further to the twenty-ninth embodiment, the test bus standard is identified in the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 specification.

[0206] In addition to what is described herein, various modifications may be made to the disclosed embodiments and implementations thereof without departing from their scope. Therefore, the descriptions and examples herein should be interpreted as illustrative rather than restrictive. The scope of the present invention should be defined only by reference to the appended claims.

Claims

1. An integrated circuit (IC) die for enabling communication via an alternative channel, the IC die comprising: a hardware interface for coupling the IC die to another IC die, wherein the IC die and the another IC die are used to at least partially form a three-dimensional 3D IC; A test unit, the test unit is used to receive status information from a power management control (PMC) agent during field operation of the 3D IC, the test unit is further used to: detecting a first condition based on the state information, in which a first partition of the IC die and a second partition of the another IC die are each in a corresponding idle state, wherein the 3D IC includes a first channel between the first partition and the second partition; as well as detecting a second condition in which one or more communications via the first channel fail to meet a performance criterion; as well as mode circuitry, the mode coupling circuitry coupled to the hardware interface and to the test unit; Wherein, based on the second condition and during the first condition, the test unit is used to signal the mode circuit system to disable a first conductive path between the first channel and the first partition, and further to enable a second conductive path between a second channel of the 3D IC and the first partition.

2. The IC die according to claim 1, characterized in that: The test unit is a first test unit, and wherein: The plurality of partitions of the 3D IC each correspond to a different respective test unit among the plurality of test units; The plurality of partitions include the first partition and the second partition; and For each test unit in the plurality of test units: The PMC agent is used to be coupled to provide corresponding status information to the test unit; and The testing unit is used to participate in the corresponding channel test based on the corresponding status information.

3. The IC die according to claim 2, characterized in that: The plurality of partitions are each configured to operate in a first clock domain.

4. The IC die according to claim 3, characterized in that: The first condition is to occur when one or more of the plurality of partitions are each in a corresponding active state.

5. The IC die according to claim 2, characterized in that: The first partition includes a first signal source circuit; The second partition includes a first signal absorbing circuit; A third partition of the plurality of partitions includes a second signal source circuit of the other IC die; and A fourth partition of the plurality of partitions includes a second signal sinking circuit of the IC die.

6. The IC die according to claim 1, characterized in that: The testing unit is further configured to: receiving test data from the PMC agent; and performing communication of the test data from the IC die via the first channel; the another IC die is for generating a value based on the communication; and The test unit is configured to detect the second condition based on a mismatch between the value and a reference value.

7. The IC die according to claim 1 or claim 6, characterized in that: The test unit is further configured to receive performance information from a sensor coupled to the first channel; The test unit is used to detect the second condition including: the test unit identifies, based on the performance information, that the performance metric fails to meet a threshold condition; and The performance metric is based on one or more communications conducted via the first channel.

8. The IC die according to claim 7, characterized in that: The performance metric is a setup time metric.

9. The IC die according to any one of claims 1, 6 or 7, characterized in that: Interface circuitry coupled between the PMC agent and the test unit is used to provide the status information via a bus compatible with a test bus standard.

10. The IC die according to claim 9, characterized in that: The test bus standard is identified in the Institute of Electrical and Electronics Engineers IEEE 1149.1 specification.

11. A method for enabling communication via an alternative channel, the method comprising: receiving status information from a power management control (PMC) agent at a test unit of a first integrated circuit (IC) die, wherein the first IC die and a second IC die are coupled to at least partially form a three-dimensional (3D) IC, wherein the test unit receives the status information during field operation of the 3D IC; detecting a first condition based on the state information, in which a first partition of the first IC die and a second partition of the second IC die are each in a respective idle state, wherein the 3D IC includes a first channel between the first partition and the second partition; detecting a second condition in which one or more communications via the first channel fail to meet a performance criterion; Based on the second condition and during the first condition: disabling a first conductive path between the first channel and the first partition; and A second conductive path between a second channel of the 3D IC and the first partition is enabled.

12. The method according to claim 11, characterized in that The test unit is a first test unit, and wherein: The plurality of partitions of the 3D IC each correspond to a different respective test unit among the plurality of test units; The plurality of partitions include the first partition and the second partition; and For each test unit in the plurality of test units: The PMC agent is coupled to provide corresponding status information to the test unit; and The testing unit is used to participate in the corresponding channel test based on the corresponding status information.

13. The method according to claim 12, characterized in that The plurality of partitions are each configured to operate in a first clock domain.

14. The method according to claim 12, characterized in that: The first partition includes a first signal source circuit; The second partition includes a first signal absorbing circuit; A third partition of the plurality of partitions includes a second signal source circuit of the second IC die; and A fourth partition of the plurality of partitions includes a second signal sinking circuit of the first IC die.

15. The method according to claim 11, further comprising: receiving, at the test unit, test data from the PMC agent; as well as performing communication of the test data from the first IC die via the first channel; Wherein the second IC die generates a value based on the communication, and wherein the second condition is detected based on a mismatch between the value and a reference value.

16. The method according to any one of claims 11 or 15, further comprising: receiving, at the test unit, performance information from a sensor coupled to the first channel; Wherein detecting the second condition includes: identifying, based on the performance information, that a performance metric fails to satisfy a threshold condition, wherein the performance metric is based on one or more communications via the first channel.

17. The method according to any one of claims 11, 15 or 16, characterized in that: Interface circuitry coupled between the PMC agent and the test unit provides the status information via a bus compatible with a test bus standard.

18. A system for enabling communication via an alternative channel, the system comprising: A first integrated circuit IC die and a second IC die, the first integrated circuit IC die and the second IC die being coupled to each other to at least partially form a three-dimensional 3D IC, wherein the first IC die comprises: A test unit, the test unit is used to receive status information from a power management control (PMC) agent during field operation of the 3D IC, the test unit is further used to: detecting a first condition based on the state information, in which a first partition of the IC die and a second partition of another IC die are each in a corresponding idle state, wherein the 3D IC includes a first channel between the first partition and the second partition; and detecting a second condition in which one or more communications via the first channel fail to meet a performance criterion; and mode circuitry coupled to the test unit; wherein, based on the second condition and during the first condition, the test unit is used to signal the mode circuit system to disable a first conductive path between the first channel and the first partition, and further enable a second conductive path between a second channel of the 3D IC and the first partition; and A memory interface is used to communicate signals between the 3D IC and a memory.

19. The system according to claim 18, characterized in that The test unit is a first test unit, and wherein: The plurality of partitions of the 3D IC each correspond to a different respective test unit among the plurality of test units; The plurality of partitions include the first partition and the second partition; and For each test unit in the plurality of test units: The PMC agent is used to be coupled to provide corresponding status information to the test unit; and The testing unit is used to participate in the corresponding channel test based on the corresponding status information.

20. The system according to claim 19, characterized in that The plurality of partitions are each configured to operate in a first clock domain.

21. The system according to claim 20, characterized in that The first condition is to occur when one or more of the plurality of partitions are each in a corresponding active state.

22. The system according to claim 19, characterized in that: The first partition includes a first signal source circuit; The second partition includes a first signal absorbing circuit; A third partition of the plurality of partitions includes a second signal source circuit of the other IC die; and A fourth partition of the plurality of partitions includes a second signal sinking circuit of the IC die.

23. The system according to claim 18, characterized in that: The testing unit is further configured to: receiving test data from the PMC agent; and performing communication of the test data from the IC die via the first channel; the another IC die is for generating a value based on the communication; and The test unit is configured to detect the second condition based on a mismatch between the value and a reference value.

24. The system according to any one of claims 18 or 23, characterized in that: The test unit is further configured to receive performance information from a sensor coupled to the first channel; The test unit is used to detect the second condition including: the test unit is used to identify that the performance metric fails to meet a threshold condition based on the performance information; and The performance metric is based on one or more communications conducted via the first channel.

25. The system of any one of claims 18, 23 or 24, wherein: Interface circuitry coupled between the PMC agent and the test unit provides the status information via a bus compatible with a test bus standard.

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